1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Common library for ADIS16XXX devices 4 * 5 * Copyright 2012 Analog Devices Inc. 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 */ 8 9 #ifndef __IIO_ADIS_H__ 10 #define __IIO_ADIS_H__ 11 12 #include <linux/cleanup.h> 13 #include <linux/spi/spi.h> 14 #include <linux/interrupt.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/types.h> 17 18 #define ADIS_WRITE_REG(reg) ((0x80 | (reg))) 19 #define ADIS_READ_REG(reg) ((reg) & 0x7f) 20 21 #define ADIS_PAGE_SIZE 0x80 22 #define ADIS_REG_PAGE_ID 0x00 23 24 struct adis; 25 struct iio_dev_attr; 26 27 /** 28 * struct adis_timeouts - ADIS chip variant timeouts 29 * @reset_ms - Wait time after rst pin goes inactive 30 * @sw_reset_ms - Wait time after sw reset command 31 * @self_test_ms - Wait time after self test command 32 */ 33 struct adis_timeout { 34 u16 reset_ms; 35 u16 sw_reset_ms; 36 u16 self_test_ms; 37 }; 38 39 /** 40 * struct adis_data - ADIS chip variant specific data 41 * @read_delay: SPI delay for read operations in us 42 * @write_delay: SPI delay for write operations in us 43 * @cs_change_delay: SPI delay between CS changes in us 44 * @glob_cmd_reg: Register address of the GLOB_CMD register 45 * @msc_ctrl_reg: Register address of the MSC_CTRL register 46 * @diag_stat_reg: Register address of the DIAG_STAT register 47 * @prod_id_reg: Register address of the PROD_ID register 48 * @prod_id: Product ID code that should be expected when reading @prod_id_reg 49 * @self_test_mask: Bitmask of supported self-test operations 50 * @self_test_reg: Register address to request self test command 51 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg 52 * @status_error_msgs: Array of error messages 53 * @status_error_mask: Bitmask of errors supported by the device 54 * @timeouts: Chip specific delays 55 * @enable_irq: Hook for ADIS devices that have a special IRQ enable/disable 56 * @unmasked_drdy: True for devices that cannot mask/unmask the data ready pin 57 * @has_paging: True if ADIS device has paged registers 58 * @burst_reg_cmd: Register command that triggers burst 59 * @burst_len: Burst size in the SPI RX buffer. If @burst_max_len is defined, 60 * this should be the minimum size supported by the device. 61 * @burst_max_len: Holds the maximum burst size when the device supports 62 * more than one burst mode with different sizes 63 * @burst_max_speed_hz: Maximum spi speed that can be used in burst mode 64 */ 65 struct adis_data { 66 unsigned int read_delay; 67 unsigned int write_delay; 68 unsigned int cs_change_delay; 69 70 unsigned int glob_cmd_reg; 71 unsigned int msc_ctrl_reg; 72 unsigned int diag_stat_reg; 73 unsigned int prod_id_reg; 74 75 unsigned int prod_id; 76 77 unsigned int self_test_mask; 78 unsigned int self_test_reg; 79 bool self_test_no_autoclear; 80 const struct adis_timeout *timeouts; 81 82 const char * const *status_error_msgs; 83 unsigned int status_error_mask; 84 85 int (*enable_irq)(struct adis *adis, bool enable); 86 bool unmasked_drdy; 87 88 bool has_paging; 89 bool has_fifo; 90 91 unsigned int burst_reg_cmd; 92 unsigned int burst_len; 93 unsigned int burst_max_len; 94 unsigned int burst_max_speed_hz; 95 }; 96 97 /** 98 * struct adis - ADIS device instance data 99 * @spi: Reference to SPI device which owns this ADIS IIO device 100 * @trig: IIO trigger object data 101 * @data: ADIS chip variant specific data 102 * @burst_extra_len: Burst extra length. Should only be used by devices that can 103 * dynamically change their burst mode length. 104 * @state_lock: Lock used by the device to protect state 105 * @msg: SPI message object 106 * @xfer: SPI transfer objects to be used for a @msg 107 * @current_page: Some ADIS devices have registers, this selects current page 108 * @irq_flag: IRQ handling flags as passed to request_irq() 109 * @buffer: Data buffer for information read from the device 110 * @tx: DMA safe TX buffer for SPI transfers 111 * @rx: DMA safe RX buffer for SPI transfers 112 */ 113 struct adis { 114 struct spi_device *spi; 115 struct iio_trigger *trig; 116 117 const struct adis_data *data; 118 unsigned int burst_extra_len; 119 /** 120 * The state_lock is meant to be used during operations that require 121 * a sequence of SPI R/W in order to protect the SPI transfer 122 * information (fields 'xfer', 'msg' & 'current_page') between 123 * potential concurrent accesses. 124 * This lock is used by all "adis_{functions}" that have to read/write 125 * registers. These functions also have unlocked variants 126 * (see "__adis_{functions}"), which don't hold this lock. 127 * This allows users of the ADIS library to group SPI R/W into 128 * the drivers, but they also must manage this lock themselves. 129 */ 130 struct mutex state_lock; 131 struct spi_message msg; 132 struct spi_transfer *xfer; 133 unsigned int current_page; 134 unsigned long irq_flag; 135 void *buffer; 136 137 u8 tx[10] __aligned(IIO_DMA_MINALIGN); 138 u8 rx[4]; 139 }; 140 141 int adis_init(struct adis *adis, struct iio_dev *indio_dev, 142 struct spi_device *spi, const struct adis_data *data); 143 int __adis_reset(struct adis *adis); 144 145 /** 146 * adis_reset() - Reset the device 147 * @adis: The adis device 148 * 149 * Returns 0 on success, a negative error code otherwise 150 */ 151 static inline int adis_reset(struct adis *adis) 152 { 153 guard(mutex)(&adis->state_lock); 154 return __adis_reset(adis); 155 } 156 157 int __adis_write_reg(struct adis *adis, unsigned int reg, 158 unsigned int val, unsigned int size); 159 int __adis_read_reg(struct adis *adis, unsigned int reg, 160 unsigned int *val, unsigned int size); 161 162 /** 163 * __adis_write_reg_8() - Write single byte to a register (unlocked) 164 * @adis: The adis device 165 * @reg: The address of the register to be written 166 * @value: The value to write 167 */ 168 static inline int __adis_write_reg_8(struct adis *adis, unsigned int reg, 169 u8 val) 170 { 171 return __adis_write_reg(adis, reg, val, 1); 172 } 173 174 /** 175 * __adis_write_reg_16() - Write 2 bytes to a pair of registers (unlocked) 176 * @adis: The adis device 177 * @reg: The address of the lower of the two registers 178 * @value: Value to be written 179 */ 180 static inline int __adis_write_reg_16(struct adis *adis, unsigned int reg, 181 u16 val) 182 { 183 return __adis_write_reg(adis, reg, val, 2); 184 } 185 186 /** 187 * __adis_write_reg_32() - write 4 bytes to four registers (unlocked) 188 * @adis: The adis device 189 * @reg: The address of the lower of the four register 190 * @value: Value to be written 191 */ 192 static inline int __adis_write_reg_32(struct adis *adis, unsigned int reg, 193 u32 val) 194 { 195 return __adis_write_reg(adis, reg, val, 4); 196 } 197 198 /** 199 * __adis_read_reg_16() - read 2 bytes from a 16-bit register (unlocked) 200 * @adis: The adis device 201 * @reg: The address of the lower of the two registers 202 * @val: The value read back from the device 203 */ 204 static inline int __adis_read_reg_16(struct adis *adis, unsigned int reg, 205 u16 *val) 206 { 207 unsigned int tmp; 208 int ret; 209 210 ret = __adis_read_reg(adis, reg, &tmp, 2); 211 if (ret == 0) 212 *val = tmp; 213 214 return ret; 215 } 216 217 /** 218 * __adis_read_reg_32() - read 4 bytes from a 32-bit register (unlocked) 219 * @adis: The adis device 220 * @reg: The address of the lower of the two registers 221 * @val: The value read back from the device 222 */ 223 static inline int __adis_read_reg_32(struct adis *adis, unsigned int reg, 224 u32 *val) 225 { 226 unsigned int tmp; 227 int ret; 228 229 ret = __adis_read_reg(adis, reg, &tmp, 4); 230 if (ret == 0) 231 *val = tmp; 232 233 return ret; 234 } 235 236 /** 237 * adis_write_reg() - write N bytes to register 238 * @adis: The adis device 239 * @reg: The address of the lower of the two registers 240 * @value: The value to write to device (up to 4 bytes) 241 * @size: The size of the @value (in bytes) 242 */ 243 static inline int adis_write_reg(struct adis *adis, unsigned int reg, 244 unsigned int val, unsigned int size) 245 { 246 guard(mutex)(&adis->state_lock); 247 return __adis_write_reg(adis, reg, val, size); 248 } 249 250 /** 251 * adis_read_reg() - read N bytes from register 252 * @adis: The adis device 253 * @reg: The address of the lower of the two registers 254 * @val: The value read back from the device 255 * @size: The size of the @val buffer 256 */ 257 static int adis_read_reg(struct adis *adis, unsigned int reg, 258 unsigned int *val, unsigned int size) 259 { 260 guard(mutex)(&adis->state_lock); 261 return __adis_read_reg(adis, reg, val, size); 262 } 263 264 /** 265 * adis_write_reg_8() - Write single byte to a register 266 * @adis: The adis device 267 * @reg: The address of the register to be written 268 * @value: The value to write 269 */ 270 static inline int adis_write_reg_8(struct adis *adis, unsigned int reg, 271 u8 val) 272 { 273 return adis_write_reg(adis, reg, val, 1); 274 } 275 276 /** 277 * adis_write_reg_16() - Write 2 bytes to a pair of registers 278 * @adis: The adis device 279 * @reg: The address of the lower of the two registers 280 * @value: Value to be written 281 */ 282 static inline int adis_write_reg_16(struct adis *adis, unsigned int reg, 283 u16 val) 284 { 285 return adis_write_reg(adis, reg, val, 2); 286 } 287 288 /** 289 * adis_write_reg_32() - write 4 bytes to four registers 290 * @adis: The adis device 291 * @reg: The address of the lower of the four register 292 * @value: Value to be written 293 */ 294 static inline int adis_write_reg_32(struct adis *adis, unsigned int reg, 295 u32 val) 296 { 297 return adis_write_reg(adis, reg, val, 4); 298 } 299 300 /** 301 * adis_read_reg_16() - read 2 bytes from a 16-bit register 302 * @adis: The adis device 303 * @reg: The address of the lower of the two registers 304 * @val: The value read back from the device 305 */ 306 static inline int adis_read_reg_16(struct adis *adis, unsigned int reg, 307 u16 *val) 308 { 309 unsigned int tmp; 310 int ret; 311 312 ret = adis_read_reg(adis, reg, &tmp, 2); 313 if (ret == 0) 314 *val = tmp; 315 316 return ret; 317 } 318 319 /** 320 * adis_read_reg_32() - read 4 bytes from a 32-bit register 321 * @adis: The adis device 322 * @reg: The address of the lower of the two registers 323 * @val: The value read back from the device 324 */ 325 static inline int adis_read_reg_32(struct adis *adis, unsigned int reg, 326 u32 *val) 327 { 328 unsigned int tmp; 329 int ret; 330 331 ret = adis_read_reg(adis, reg, &tmp, 4); 332 if (ret == 0) 333 *val = tmp; 334 335 return ret; 336 } 337 338 int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask, 339 const u32 val, u8 size); 340 /** 341 * adis_update_bits_base() - ADIS Update bits function - Locked version 342 * @adis: The adis device 343 * @reg: The address of the lower of the two registers 344 * @mask: Bitmask to change 345 * @val: Value to be written 346 * @size: Size of the register to update 347 * 348 * Updates the desired bits of @reg in accordance with @mask and @val. 349 */ 350 static inline int adis_update_bits_base(struct adis *adis, unsigned int reg, 351 const u32 mask, const u32 val, u8 size) 352 { 353 guard(mutex)(&adis->state_lock); 354 return __adis_update_bits_base(adis, reg, mask, val, size); 355 } 356 357 /** 358 * adis_update_bits() - Wrapper macro for adis_update_bits_base - Locked version 359 * @adis: The adis device 360 * @reg: The address of the lower of the two registers 361 * @mask: Bitmask to change 362 * @val: Value to be written 363 * 364 * This macro evaluates the sizeof of @val at compile time and calls 365 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for 366 * @val can lead to undesired behavior if the register to update is 16bit. 367 */ 368 #define adis_update_bits(adis, reg, mask, val) ({ \ 369 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \ 370 adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \ 371 }) 372 373 /** 374 * adis_update_bits() - Wrapper macro for adis_update_bits_base 375 * @adis: The adis device 376 * @reg: The address of the lower of the two registers 377 * @mask: Bitmask to change 378 * @val: Value to be written 379 * 380 * This macro evaluates the sizeof of @val at compile time and calls 381 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for 382 * @val can lead to undesired behavior if the register to update is 16bit. 383 */ 384 #define __adis_update_bits(adis, reg, mask, val) ({ \ 385 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \ 386 __adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \ 387 }) 388 389 int __adis_check_status(struct adis *adis); 390 int __adis_initial_startup(struct adis *adis); 391 int __adis_enable_irq(struct adis *adis, bool enable); 392 393 static inline int adis_enable_irq(struct adis *adis, bool enable) 394 { 395 guard(mutex)(&adis->state_lock); 396 return __adis_enable_irq(adis, enable); 397 } 398 399 static inline int adis_check_status(struct adis *adis) 400 { 401 guard(mutex)(&adis->state_lock); 402 return __adis_check_status(adis); 403 } 404 405 #define adis_dev_auto_lock(adis) guard(mutex)(&(adis)->state_lock) 406 #define adis_dev_auto_scoped_lock(adis) \ 407 scoped_guard(mutex, &(adis)->state_lock) 408 409 int adis_single_conversion(struct iio_dev *indio_dev, 410 const struct iio_chan_spec *chan, 411 unsigned int error_mask, int *val); 412 413 #define ADIS_VOLTAGE_CHAN(addr, si, chan, name, info_all, bits) { \ 414 .type = IIO_VOLTAGE, \ 415 .indexed = 1, \ 416 .channel = (chan), \ 417 .extend_name = name, \ 418 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 419 BIT(IIO_CHAN_INFO_SCALE), \ 420 .info_mask_shared_by_all = info_all, \ 421 .address = (addr), \ 422 .scan_index = (si), \ 423 .scan_type = { \ 424 .sign = 'u', \ 425 .realbits = (bits), \ 426 .storagebits = 16, \ 427 .endianness = IIO_BE, \ 428 }, \ 429 } 430 431 #define ADIS_SUPPLY_CHAN(addr, si, info_all, bits) \ 432 ADIS_VOLTAGE_CHAN(addr, si, 0, "supply", info_all, bits) 433 434 #define ADIS_AUX_ADC_CHAN(addr, si, info_all, bits) \ 435 ADIS_VOLTAGE_CHAN(addr, si, 1, NULL, info_all, bits) 436 437 #define ADIS_TEMP_CHAN(addr, si, info_all, bits) { \ 438 .type = IIO_TEMP, \ 439 .indexed = 1, \ 440 .channel = 0, \ 441 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 442 BIT(IIO_CHAN_INFO_SCALE) | \ 443 BIT(IIO_CHAN_INFO_OFFSET), \ 444 .info_mask_shared_by_all = info_all, \ 445 .address = (addr), \ 446 .scan_index = (si), \ 447 .scan_type = { \ 448 .sign = 'u', \ 449 .realbits = (bits), \ 450 .storagebits = 16, \ 451 .endianness = IIO_BE, \ 452 }, \ 453 } 454 455 #define ADIS_MOD_CHAN(_type, mod, addr, si, info_sep, info_all, bits) { \ 456 .type = (_type), \ 457 .modified = 1, \ 458 .channel2 = IIO_MOD_ ## mod, \ 459 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 460 (info_sep), \ 461 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 462 .info_mask_shared_by_all = info_all, \ 463 .address = (addr), \ 464 .scan_index = (si), \ 465 .scan_type = { \ 466 .sign = 's', \ 467 .realbits = (bits), \ 468 .storagebits = 16, \ 469 .endianness = IIO_BE, \ 470 }, \ 471 } 472 473 #define ADIS_ACCEL_CHAN(mod, addr, si, info_sep, info_all, bits) \ 474 ADIS_MOD_CHAN(IIO_ACCEL, mod, addr, si, info_sep, info_all, bits) 475 476 #define ADIS_GYRO_CHAN(mod, addr, si, info_sep, info_all, bits) \ 477 ADIS_MOD_CHAN(IIO_ANGL_VEL, mod, addr, si, info_sep, info_all, bits) 478 479 #define ADIS_INCLI_CHAN(mod, addr, si, info_sep, info_all, bits) \ 480 ADIS_MOD_CHAN(IIO_INCLI, mod, addr, si, info_sep, info_all, bits) 481 482 #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \ 483 ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits) 484 485 #define devm_adis_setup_buffer_and_trigger(adis, indio_dev, trigger_handler) \ 486 devm_adis_setup_buffer_and_trigger_with_attrs((adis), (indio_dev), \ 487 (trigger_handler), NULL, \ 488 NULL) 489 490 #ifdef CONFIG_IIO_ADIS_LIB_BUFFER 491 492 int 493 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, 494 struct iio_dev *indio_dev, 495 irq_handler_t trigger_handler, 496 const struct iio_buffer_setup_ops *ops, 497 const struct iio_dev_attr **buffer_attrs); 498 499 int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev); 500 501 int adis_update_scan_mode(struct iio_dev *indio_dev, 502 const unsigned long *scan_mask); 503 504 #else /* CONFIG_IIO_BUFFER */ 505 506 static inline int 507 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, 508 struct iio_dev *indio_dev, 509 irq_handler_t trigger_handler, 510 const struct iio_buffer_setup_ops *ops, 511 const struct iio_dev_attr **buffer_attrs) 512 { 513 return 0; 514 } 515 516 static inline int devm_adis_probe_trigger(struct adis *adis, 517 struct iio_dev *indio_dev) 518 { 519 return 0; 520 } 521 522 #define adis_update_scan_mode NULL 523 524 #endif /* CONFIG_IIO_BUFFER */ 525 526 #ifdef CONFIG_DEBUG_FS 527 528 int adis_debugfs_reg_access(struct iio_dev *indio_dev, 529 unsigned int reg, unsigned int writeval, 530 unsigned int *readval); 531 532 #else 533 534 #define adis_debugfs_reg_access NULL 535 536 #endif 537 538 #endif 539