xref: /linux/drivers/soc/mediatek/mtk-svs.c (revision 4232da23d75d173195c6766729e51947b64f83cd)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2022 MediaTek Inc.
4  * Copyright (C) 2022 Collabora Ltd.
5  *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/cpu.h>
13 #include <linux/cpuidle.h>
14 #include <linux/debugfs.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/nvmem-consumer.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_domain.h>
28 #include <linux/pm_opp.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/reset.h>
32 #include <linux/seq_file.h>
33 #include <linux/slab.h>
34 #include <linux/spinlock.h>
35 #include <linux/thermal.h>
36 
37 /* svs bank mode support */
38 #define SVSB_MODE_ALL_DISABLE		0
39 #define SVSB_MODE_INIT01		BIT(1)
40 #define SVSB_MODE_INIT02		BIT(2)
41 #define SVSB_MODE_MON			BIT(3)
42 
43 /* svs bank volt flags */
44 #define SVSB_INIT01_PD_REQ		BIT(0)
45 #define SVSB_INIT01_VOLT_IGNORE		BIT(1)
46 #define SVSB_INIT01_VOLT_INC_ONLY	BIT(2)
47 #define SVSB_MON_VOLT_IGNORE		BIT(16)
48 #define SVSB_REMOVE_DVTFIXED_VOLT	BIT(24)
49 
50 /* svs bank register fields and common configuration */
51 #define SVSB_PTPCONFIG_DETMAX		GENMASK(15, 0)
52 #define SVSB_DET_MAX			FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff)
53 #define SVSB_DET_WINDOW			0xa28
54 
55 /* DESCHAR */
56 #define SVSB_DESCHAR_FLD_MDES		GENMASK(7, 0)
57 #define SVSB_DESCHAR_FLD_BDES		GENMASK(15, 8)
58 
59 /* TEMPCHAR */
60 #define SVSB_TEMPCHAR_FLD_DVT_FIXED	GENMASK(7, 0)
61 #define SVSB_TEMPCHAR_FLD_MTDES		GENMASK(15, 8)
62 #define SVSB_TEMPCHAR_FLD_VCO		GENMASK(23, 16)
63 
64 /* DETCHAR */
65 #define SVSB_DETCHAR_FLD_DCMDET		GENMASK(7, 0)
66 #define SVSB_DETCHAR_FLD_DCBDET		GENMASK(15, 8)
67 
68 /* SVSEN (PTPEN) */
69 #define SVSB_PTPEN_INIT01		BIT(0)
70 #define SVSB_PTPEN_MON			BIT(1)
71 #define SVSB_PTPEN_INIT02		(SVSB_PTPEN_INIT01 | BIT(2))
72 #define SVSB_PTPEN_OFF			0x0
73 
74 /* FREQPCTS */
75 #define SVSB_FREQPCTS_FLD_PCT0_4	GENMASK(7, 0)
76 #define SVSB_FREQPCTS_FLD_PCT1_5	GENMASK(15, 8)
77 #define SVSB_FREQPCTS_FLD_PCT2_6	GENMASK(23, 16)
78 #define SVSB_FREQPCTS_FLD_PCT3_7	GENMASK(31, 24)
79 
80 /* INTSTS */
81 #define SVSB_INTSTS_VAL_CLEAN		0x00ffffff
82 #define SVSB_INTSTS_F0_COMPLETE		BIT(0)
83 #define SVSB_INTSTS_FLD_MONVOP		GENMASK(23, 16)
84 #define SVSB_RUNCONFIG_DEFAULT		0x80000000
85 
86 /* LIMITVALS */
87 #define SVSB_LIMITVALS_FLD_DTLO		GENMASK(7, 0)
88 #define SVSB_LIMITVALS_FLD_DTHI		GENMASK(15, 8)
89 #define SVSB_LIMITVALS_FLD_VMIN		GENMASK(23, 16)
90 #define SVSB_LIMITVALS_FLD_VMAX		GENMASK(31, 24)
91 #define SVSB_VAL_DTHI			0x1
92 #define SVSB_VAL_DTLO			0xfe
93 
94 /* INTEN */
95 #define SVSB_INTEN_F0EN			BIT(0)
96 #define SVSB_INTEN_DACK0UPEN		BIT(8)
97 #define SVSB_INTEN_DC0EN		BIT(9)
98 #define SVSB_INTEN_DC1EN		BIT(10)
99 #define SVSB_INTEN_DACK0LOEN		BIT(11)
100 #define SVSB_INTEN_INITPROD_OVF_EN	BIT(12)
101 #define SVSB_INTEN_INITSUM_OVF_EN	BIT(14)
102 #define SVSB_INTEN_MONVOPEN		GENMASK(23, 16)
103 #define SVSB_INTEN_INIT0x		(SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN |	\
104 					 SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN |		\
105 					 SVSB_INTEN_DACK0LOEN |				\
106 					 SVSB_INTEN_INITPROD_OVF_EN |			\
107 					 SVSB_INTEN_INITSUM_OVF_EN)
108 
109 /* TSCALCS */
110 #define SVSB_TSCALCS_FLD_MTS		GENMASK(11, 0)
111 #define SVSB_TSCALCS_FLD_BTS		GENMASK(23, 12)
112 
113 /* INIT2VALS */
114 #define SVSB_INIT2VALS_FLD_DCVOFFSETIN	GENMASK(15, 0)
115 #define SVSB_INIT2VALS_FLD_AGEVOFFSETIN	GENMASK(31, 16)
116 
117 /* VOPS */
118 #define SVSB_VOPS_FLD_VOP0_4		GENMASK(7, 0)
119 #define SVSB_VOPS_FLD_VOP1_5		GENMASK(15, 8)
120 #define SVSB_VOPS_FLD_VOP2_6		GENMASK(23, 16)
121 #define SVSB_VOPS_FLD_VOP3_7		GENMASK(31, 24)
122 
123 /* SVS Thermal Coefficients */
124 #define SVSB_TS_COEFF_MT8195		250460
125 #define SVSB_TS_COEFF_MT8186		204650
126 
127 /* Algo helpers */
128 #define FUSE_DATA_NOT_VALID		U32_MAX
129 
130 /* svs bank related setting */
131 #define BITS8				8
132 #define MAX_OPP_ENTRIES			16
133 #define REG_BYTES			4
134 #define SVSB_DC_SIGNED_BIT		BIT(15)
135 #define SVSB_DET_CLK_EN			BIT(31)
136 #define SVSB_TEMP_LOWER_BOUND		0xb2
137 #define SVSB_TEMP_UPPER_BOUND		0x64
138 
139 static DEFINE_SPINLOCK(svs_lock);
140 
141 #ifdef CONFIG_DEBUG_FS
142 #define debug_fops_ro(name)						\
143 	static int svs_##name##_debug_open(struct inode *inode,		\
144 					   struct file *filp)		\
145 	{								\
146 		return single_open(filp, svs_##name##_debug_show,	\
147 				   inode->i_private);			\
148 	}								\
149 	static const struct file_operations svs_##name##_debug_fops = {	\
150 		.owner = THIS_MODULE,					\
151 		.open = svs_##name##_debug_open,			\
152 		.read = seq_read,					\
153 		.llseek = seq_lseek,					\
154 		.release = single_release,				\
155 	}
156 
157 #define debug_fops_rw(name)						\
158 	static int svs_##name##_debug_open(struct inode *inode,		\
159 					   struct file *filp)		\
160 	{								\
161 		return single_open(filp, svs_##name##_debug_show,	\
162 				   inode->i_private);			\
163 	}								\
164 	static const struct file_operations svs_##name##_debug_fops = {	\
165 		.owner = THIS_MODULE,					\
166 		.open = svs_##name##_debug_open,			\
167 		.read = seq_read,					\
168 		.write = svs_##name##_debug_write,			\
169 		.llseek = seq_lseek,					\
170 		.release = single_release,				\
171 	}
172 
173 #define svs_dentry_data(name)	{__stringify(name), &svs_##name##_debug_fops}
174 #endif
175 
176 /**
177  * enum svsb_sw_id - SVS Bank Software ID
178  * @SVSB_SWID_CPU_LITTLE: CPU little cluster Bank
179  * @SVSB_SWID_CPU_BIG:    CPU big cluster Bank
180  * @SVSB_SWID_CCI:        Cache Coherent Interconnect Bank
181  * @SVSB_SWID_GPU:        GPU Bank
182  * @SVSB_SWID_MAX:        Total number of Banks
183  */
184 enum svsb_sw_id {
185 	SVSB_SWID_CPU_LITTLE,
186 	SVSB_SWID_CPU_BIG,
187 	SVSB_SWID_CCI,
188 	SVSB_SWID_GPU,
189 	SVSB_SWID_MAX
190 };
191 
192 /**
193  * enum svsb_type - SVS Bank 2-line: Type and Role
194  * @SVSB_TYPE_NONE: One-line type Bank - Global role
195  * @SVSB_TYPE_LOW:  Two-line type Bank - Low bank role
196  * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role
197  * @SVSB_TYPE_MAX:  Total number of bank types
198  */
199 enum svsb_type {
200 	SVSB_TYPE_NONE,
201 	SVSB_TYPE_LOW,
202 	SVSB_TYPE_HIGH,
203 	SVSB_TYPE_MAX
204 };
205 
206 /**
207  * enum svsb_phase - svs bank phase enumeration
208  * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
209  * @SVSB_PHASE_INIT01: svs bank basic init for data calibration
210  * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
211  * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
212  * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
213  *
214  * Each svs bank has its own independent phase and we enable each svs bank by
215  * running their phase orderly. However, when svs bank encounters unexpected
216  * condition, it will fire an irq (PHASE_ERROR) to inform svs software.
217  *
218  * svs bank general phase-enabled order:
219  * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
220  */
221 enum svsb_phase {
222 	SVSB_PHASE_ERROR = 0,
223 	SVSB_PHASE_INIT01,
224 	SVSB_PHASE_INIT02,
225 	SVSB_PHASE_MON,
226 	SVSB_PHASE_MAX,
227 };
228 
229 enum svs_reg_index {
230 	DESCHAR = 0,
231 	TEMPCHAR,
232 	DETCHAR,
233 	AGECHAR,
234 	DCCONFIG,
235 	AGECONFIG,
236 	FREQPCT30,
237 	FREQPCT74,
238 	LIMITVALS,
239 	VBOOT,
240 	DETWINDOW,
241 	CONFIG,
242 	TSCALCS,
243 	RUNCONFIG,
244 	SVSEN,
245 	INIT2VALS,
246 	DCVALUES,
247 	AGEVALUES,
248 	VOP30,
249 	VOP74,
250 	TEMP,
251 	INTSTS,
252 	INTSTSRAW,
253 	INTEN,
254 	CHKINT,
255 	CHKSHIFT,
256 	STATUS,
257 	VDESIGN30,
258 	VDESIGN74,
259 	DVT30,
260 	DVT74,
261 	AGECOUNT,
262 	SMSTATE0,
263 	SMSTATE1,
264 	CTL0,
265 	DESDETSEC,
266 	TEMPAGESEC,
267 	CTRLSPARE0,
268 	CTRLSPARE1,
269 	CTRLSPARE2,
270 	CTRLSPARE3,
271 	CORESEL,
272 	THERMINTST,
273 	INTST,
274 	THSTAGE0ST,
275 	THSTAGE1ST,
276 	THSTAGE2ST,
277 	THAHBST0,
278 	THAHBST1,
279 	SPARE0,
280 	SPARE1,
281 	SPARE2,
282 	SPARE3,
283 	THSLPEVEB,
284 	SVS_REG_MAX,
285 };
286 
287 static const u32 svs_regs_v2[] = {
288 	[DESCHAR]		= 0x00,
289 	[TEMPCHAR]		= 0x04,
290 	[DETCHAR]		= 0x08,
291 	[AGECHAR]		= 0x0c,
292 	[DCCONFIG]		= 0x10,
293 	[AGECONFIG]		= 0x14,
294 	[FREQPCT30]		= 0x18,
295 	[FREQPCT74]		= 0x1c,
296 	[LIMITVALS]		= 0x20,
297 	[VBOOT]			= 0x24,
298 	[DETWINDOW]		= 0x28,
299 	[CONFIG]		= 0x2c,
300 	[TSCALCS]		= 0x30,
301 	[RUNCONFIG]		= 0x34,
302 	[SVSEN]			= 0x38,
303 	[INIT2VALS]		= 0x3c,
304 	[DCVALUES]		= 0x40,
305 	[AGEVALUES]		= 0x44,
306 	[VOP30]			= 0x48,
307 	[VOP74]			= 0x4c,
308 	[TEMP]			= 0x50,
309 	[INTSTS]		= 0x54,
310 	[INTSTSRAW]		= 0x58,
311 	[INTEN]			= 0x5c,
312 	[CHKINT]		= 0x60,
313 	[CHKSHIFT]		= 0x64,
314 	[STATUS]		= 0x68,
315 	[VDESIGN30]		= 0x6c,
316 	[VDESIGN74]		= 0x70,
317 	[DVT30]			= 0x74,
318 	[DVT74]			= 0x78,
319 	[AGECOUNT]		= 0x7c,
320 	[SMSTATE0]		= 0x80,
321 	[SMSTATE1]		= 0x84,
322 	[CTL0]			= 0x88,
323 	[DESDETSEC]		= 0xe0,
324 	[TEMPAGESEC]		= 0xe4,
325 	[CTRLSPARE0]		= 0xf0,
326 	[CTRLSPARE1]		= 0xf4,
327 	[CTRLSPARE2]		= 0xf8,
328 	[CTRLSPARE3]		= 0xfc,
329 	[CORESEL]		= 0x300,
330 	[THERMINTST]		= 0x304,
331 	[INTST]			= 0x308,
332 	[THSTAGE0ST]		= 0x30c,
333 	[THSTAGE1ST]		= 0x310,
334 	[THSTAGE2ST]		= 0x314,
335 	[THAHBST0]		= 0x318,
336 	[THAHBST1]		= 0x31c,
337 	[SPARE0]		= 0x320,
338 	[SPARE1]		= 0x324,
339 	[SPARE2]		= 0x328,
340 	[SPARE3]		= 0x32c,
341 	[THSLPEVEB]		= 0x330,
342 };
343 
344 static const char * const svs_swid_names[SVSB_SWID_MAX] = {
345 	"SVSB_CPU_LITTLE", "SVSB_CPU_BIG", "SVSB_CCI", "SVSB_GPU"
346 };
347 
348 static const char * const svs_type_names[SVSB_TYPE_MAX] = {
349 	"", "_LOW", "_HIGH"
350 };
351 
352 enum svs_fusemap_dev {
353 	BDEV_BDES,
354 	BDEV_MDES,
355 	BDEV_MTDES,
356 	BDEV_DCBDET,
357 	BDEV_DCMDET,
358 	BDEV_MAX
359 };
360 
361 enum svs_fusemap_glb {
362 	GLB_FT_PGM,
363 	GLB_VMIN,
364 	GLB_MAX
365 };
366 
367 struct svs_fusemap {
368 	s8 index;
369 	u8 ofst;
370 };
371 
372 /**
373  * struct svs_platform - svs platform control
374  * @base: svs platform register base
375  * @dev: svs platform device
376  * @main_clk: main clock for svs bank
377  * @banks: svs banks that svs platform supports
378  * @rst: svs platform reset control
379  * @efuse_max: total number of svs efuse
380  * @tefuse_max: total number of thermal efuse
381  * @regs: svs platform registers map
382  * @efuse: svs efuse data received from NVMEM framework
383  * @tefuse: thermal efuse data received from NVMEM framework
384  * @ts_coeff: thermal sensors coefficient
385  * @bank_max: total number of svs banks
386  */
387 struct svs_platform {
388 	void __iomem *base;
389 	struct device *dev;
390 	struct clk *main_clk;
391 	struct svs_bank *banks;
392 	struct reset_control *rst;
393 	size_t efuse_max;
394 	size_t tefuse_max;
395 	const u32 *regs;
396 	u32 *efuse;
397 	u32 *tefuse;
398 	u32 ts_coeff;
399 	u16 bank_max;
400 };
401 
402 struct svs_platform_data {
403 	char *name;
404 	struct svs_bank *banks;
405 	bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata);
406 	int (*probe)(struct svs_platform *svsp);
407 	const struct svs_fusemap *glb_fuse_map;
408 	const u32 *regs;
409 	u32 ts_coeff;
410 	u16 bank_max;
411 };
412 
413 /**
414  * struct svs_bank_pdata - SVS Bank immutable config parameters
415  * @dev_fuse_map: Bank fuse map data
416  * @buck_name: Regulator name
417  * @tzone_name: Thermal zone name
418  * @age_config: Bank age configuration
419  * @ctl0: TS-x selection
420  * @dc_config: Bank dc configuration
421  * @int_st: Bank interrupt identification
422  * @turn_freq_base: Reference frequency for 2-line turn point
423  * @tzone_htemp: Thermal zone high temperature threshold
424  * @tzone_ltemp: Thermal zone low temperature threshold
425  * @volt_step: Bank voltage step
426  * @volt_base: Bank voltage base
427  * @tzone_htemp_voffset: Thermal zone high temperature voltage offset
428  * @tzone_ltemp_voffset: Thermal zone low temperature voltage offset
429  * @chk_shift: Bank chicken shift
430  * @cpu_id: CPU core ID for SVS CPU bank use only
431  * @opp_count: Bank opp count
432  * @vboot: Voltage request for bank init01 only
433  * @vco: Bank VCO value
434  * @sw_id: Bank software identification
435  * @type: SVS Bank Type (1 or 2-line) and Role (high/low)
436  * @set_freq_pct: function pointer to set bank frequency percent table
437  * @get_volts: function pointer to get bank voltages
438  */
439 struct svs_bank_pdata {
440 	const struct svs_fusemap *dev_fuse_map;
441 	char *buck_name;
442 	char *tzone_name;
443 	u32 age_config;
444 	u32 ctl0;
445 	u32 dc_config;
446 	u32 int_st;
447 	u32 turn_freq_base;
448 	u32 tzone_htemp;
449 	u32 tzone_ltemp;
450 	u32 volt_step;
451 	u32 volt_base;
452 	u16 tzone_htemp_voffset;
453 	u16 tzone_ltemp_voffset;
454 	u8 chk_shift;
455 	u8 cpu_id;
456 	u8 opp_count;
457 	u8 vboot;
458 	u8 vco;
459 	u8 sw_id;
460 	u8 type;
461 
462 	/* Callbacks */
463 	void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb);
464 	void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb);
465 };
466 
467 /**
468  * struct svs_bank - svs bank representation
469  * @pdata: SVS Bank immutable config parameters
470  * @dev: bank device
471  * @opp_dev: device for opp table/buck control
472  * @init_completion: the timeout completion for bank init
473  * @buck: regulator used by opp_dev
474  * @tzd: thermal zone device for getting temperature
475  * @lock: mutex lock to protect voltage update process
476  * @name: bank name
477  * @phase: bank current phase
478  * @volt_od: bank voltage overdrive
479  * @reg_data: bank register data in different phase for debug purpose
480  * @pm_runtime_enabled_count: bank pm runtime enabled count
481  * @mode_support: bank mode support
482  * @freq_base: reference frequency for bank init
483  * @opp_dfreq: default opp frequency table
484  * @opp_dvolt: default opp voltage table
485  * @freq_pct: frequency percent table for bank init
486  * @volt: bank voltage table
487  * @volt_flags: bank voltage flags
488  * @vmax: bank voltage maximum
489  * @vmin: bank voltage minimum
490  * @age_voffset_in: bank age voltage offset
491  * @dc_voffset_in: bank dc voltage offset
492  * @dvt_fixed: bank dvt fixed value
493  * @core_sel: bank selection
494  * @temp: bank temperature
495  * @bts: svs efuse data
496  * @mts: svs efuse data
497  * @bdes: svs efuse data
498  * @mdes: svs efuse data
499  * @mtdes: svs efuse data
500  * @dcbdet: svs efuse data
501  * @dcmdet: svs efuse data
502  * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
503  * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden
504  *
505  * Svs bank will generate suitable voltages by below general math equation
506  * and provide these voltages to opp voltage table.
507  *
508  * opp_volt[i] = (volt[i] * volt_step) + volt_base;
509  */
510 struct svs_bank {
511 	const struct svs_bank_pdata pdata;
512 	struct device *dev;
513 	struct device *opp_dev;
514 	struct completion init_completion;
515 	struct regulator *buck;
516 	struct thermal_zone_device *tzd;
517 	struct mutex lock;
518 	int pm_runtime_enabled_count;
519 	short int volt_od;
520 	char *name;
521 	enum svsb_phase phase;
522 	u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX];
523 	u8 mode_support;
524 	u32 opp_dfreq[MAX_OPP_ENTRIES];
525 	u32 opp_dvolt[MAX_OPP_ENTRIES];
526 	u32 freq_pct[MAX_OPP_ENTRIES];
527 	u32 volt[MAX_OPP_ENTRIES];
528 	u32 volt_flags;
529 	u32 freq_base;
530 	u32 turn_pt;
531 	u32 vbin_turn_pt;
532 	u32 core_sel;
533 	u32 temp;
534 	u16 age_voffset_in;
535 	u16 dc_voffset_in;
536 	u8 dvt_fixed;
537 	u8 vmax;
538 	u8 vmin;
539 	u16 bts;
540 	u16 mts;
541 	u16 bdes;
542 	u16 mdes;
543 	u8 mtdes;
544 	u8 dcbdet;
545 	u8 dcmdet;
546 };
547 
percent(u32 numerator,u32 denominator)548 static u32 percent(u32 numerator, u32 denominator)
549 {
550 	/* If not divide 1000, "numerator * 100" will have data overflow. */
551 	numerator /= 1000;
552 	denominator /= 1000;
553 
554 	return DIV_ROUND_UP(numerator * 100, denominator);
555 }
556 
svs_readl_relaxed(struct svs_platform * svsp,enum svs_reg_index rg_i)557 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i)
558 {
559 	return readl_relaxed(svsp->base + svsp->regs[rg_i]);
560 }
561 
svs_writel_relaxed(struct svs_platform * svsp,u32 val,enum svs_reg_index rg_i)562 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,
563 			       enum svs_reg_index rg_i)
564 {
565 	writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
566 }
567 
svs_switch_bank(struct svs_platform * svsp,struct svs_bank * svsb)568 static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb)
569 {
570 	svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
571 }
572 
svs_bank_volt_to_opp_volt(u32 svsb_volt,u32 svsb_volt_step,u32 svsb_volt_base)573 static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
574 				     u32 svsb_volt_base)
575 {
576 	return (svsb_volt * svsb_volt_step) + svsb_volt_base;
577 }
578 
svs_opp_volt_to_bank_volt(u32 opp_u_volt,u32 svsb_volt_step,u32 svsb_volt_base)579 static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step,
580 				     u32 svsb_volt_base)
581 {
582 	return (opp_u_volt - svsb_volt_base) / svsb_volt_step;
583 }
584 
svs_sync_bank_volts_from_opp(struct svs_bank * svsb)585 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb)
586 {
587 	const struct svs_bank_pdata *bdata = &svsb->pdata;
588 	struct dev_pm_opp *opp;
589 	u32 i, opp_u_volt;
590 
591 	for (i = 0; i < bdata->opp_count; i++) {
592 		opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
593 						 svsb->opp_dfreq[i],
594 						 true);
595 		if (IS_ERR(opp)) {
596 			dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
597 				svsb->opp_dfreq[i], PTR_ERR(opp));
598 			return PTR_ERR(opp);
599 		}
600 
601 		opp_u_volt = dev_pm_opp_get_voltage(opp);
602 		svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
603 							  bdata->volt_step,
604 							  bdata->volt_base);
605 		dev_pm_opp_put(opp);
606 	}
607 
608 	return 0;
609 }
610 
svs_adjust_pm_opp_volts(struct svs_bank * svsb)611 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
612 {
613 	int ret = -EPERM, tzone_temp = 0;
614 	const struct svs_bank_pdata *bdata = &svsb->pdata;
615 	u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop;
616 
617 	mutex_lock(&svsb->lock);
618 
619 	/*
620 	 * 2-line bank updates its corresponding opp volts.
621 	 * 1-line bank updates all opp volts.
622 	 */
623 	if (bdata->type == SVSB_TYPE_HIGH) {
624 		opp_start = 0;
625 		opp_stop = svsb->turn_pt;
626 	} else if (bdata->type == SVSB_TYPE_LOW) {
627 		opp_start = svsb->turn_pt;
628 		opp_stop = bdata->opp_count;
629 	} else {
630 		opp_start = 0;
631 		opp_stop = bdata->opp_count;
632 	}
633 
634 	/* Get thermal effect */
635 	if (!IS_ERR_OR_NULL(svsb->tzd)) {
636 		ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
637 		if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
638 			    svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
639 			dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
640 				bdata->tzone_name, ret, svsb->temp);
641 			svsb->phase = SVSB_PHASE_ERROR;
642 		}
643 
644 		if (tzone_temp >= bdata->tzone_htemp)
645 			temp_voffset += bdata->tzone_htemp_voffset;
646 		else if (tzone_temp <= bdata->tzone_ltemp)
647 			temp_voffset += bdata->tzone_ltemp_voffset;
648 
649 		/* 2-line bank update all opp volts when running mon mode */
650 		if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH ||
651 						      bdata->type == SVSB_TYPE_LOW)) {
652 			opp_start = 0;
653 			opp_stop = bdata->opp_count;
654 		}
655 	}
656 
657 	/* vmin <= svsb_volt (opp_volt) <= default opp voltage */
658 	for (i = opp_start; i < opp_stop; i++) {
659 		switch (svsb->phase) {
660 		case SVSB_PHASE_ERROR:
661 			opp_volt = svsb->opp_dvolt[i];
662 			break;
663 		case SVSB_PHASE_INIT01:
664 			/* do nothing */
665 			goto unlock_mutex;
666 		case SVSB_PHASE_INIT02:
667 		case SVSB_PHASE_MON:
668 			svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
669 			opp_volt = svs_bank_volt_to_opp_volt(svsb_volt,
670 							     bdata->volt_step,
671 							     bdata->volt_base);
672 			break;
673 		default:
674 			dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
675 			ret = -EINVAL;
676 			goto unlock_mutex;
677 		}
678 
679 		opp_volt = min(opp_volt, svsb->opp_dvolt[i]);
680 		ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
681 						svsb->opp_dfreq[i],
682 						opp_volt, opp_volt,
683 						svsb->opp_dvolt[i]);
684 		if (ret) {
685 			dev_err(svsb->dev, "set %uuV fail: %d\n",
686 				opp_volt, ret);
687 			goto unlock_mutex;
688 		}
689 	}
690 
691 unlock_mutex:
692 	mutex_unlock(&svsb->lock);
693 
694 	return ret;
695 }
696 
svs_bank_disable_and_restore_default_volts(struct svs_platform * svsp,struct svs_bank * svsb)697 static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp,
698 						       struct svs_bank *svsb)
699 {
700 	unsigned long flags;
701 
702 	if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
703 		return;
704 
705 	spin_lock_irqsave(&svs_lock, flags);
706 	svs_switch_bank(svsp, svsb);
707 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
708 	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
709 	spin_unlock_irqrestore(&svs_lock, flags);
710 
711 	svsb->phase = SVSB_PHASE_ERROR;
712 	svs_adjust_pm_opp_volts(svsb);
713 }
714 
715 #ifdef CONFIG_DEBUG_FS
svs_dump_debug_show(struct seq_file * m,void * p)716 static int svs_dump_debug_show(struct seq_file *m, void *p)
717 {
718 	struct svs_platform *svsp = (struct svs_platform *)m->private;
719 	struct svs_bank *svsb;
720 	unsigned long svs_reg_addr;
721 	u32 idx, i, j, bank_id;
722 
723 	for (i = 0; i < svsp->efuse_max; i++)
724 		if (svsp->efuse && svsp->efuse[i])
725 			seq_printf(m, "M_HW_RES%d = 0x%08x\n",
726 				   i, svsp->efuse[i]);
727 
728 	for (i = 0; i < svsp->tefuse_max; i++)
729 		if (svsp->tefuse)
730 			seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n",
731 				   i, svsp->tefuse[i]);
732 
733 	for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
734 		svsb = &svsp->banks[idx];
735 
736 		for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) {
737 			seq_printf(m, "Bank_number = %u\n", bank_id);
738 
739 			if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02)
740 				seq_printf(m, "mode = init%d\n", i);
741 			else if (i == SVSB_PHASE_MON)
742 				seq_puts(m, "mode = mon\n");
743 			else
744 				seq_puts(m, "mode = error\n");
745 
746 			for (j = DESCHAR; j < SVS_REG_MAX; j++) {
747 				svs_reg_addr = (unsigned long)(svsp->base +
748 							       svsp->regs[j]);
749 				seq_printf(m, "0x%08lx = 0x%08x\n",
750 					   svs_reg_addr, svsb->reg_data[i][j]);
751 			}
752 		}
753 	}
754 
755 	return 0;
756 }
757 
758 debug_fops_ro(dump);
759 
svs_enable_debug_show(struct seq_file * m,void * v)760 static int svs_enable_debug_show(struct seq_file *m, void *v)
761 {
762 	struct svs_bank *svsb = (struct svs_bank *)m->private;
763 
764 	switch (svsb->phase) {
765 	case SVSB_PHASE_ERROR:
766 		seq_puts(m, "disabled\n");
767 		break;
768 	case SVSB_PHASE_INIT01:
769 		seq_puts(m, "init1\n");
770 		break;
771 	case SVSB_PHASE_INIT02:
772 		seq_puts(m, "init2\n");
773 		break;
774 	case SVSB_PHASE_MON:
775 		seq_puts(m, "mon mode\n");
776 		break;
777 	default:
778 		seq_puts(m, "unknown\n");
779 		break;
780 	}
781 
782 	return 0;
783 }
784 
svs_enable_debug_write(struct file * filp,const char __user * buffer,size_t count,loff_t * pos)785 static ssize_t svs_enable_debug_write(struct file *filp,
786 				      const char __user *buffer,
787 				      size_t count, loff_t *pos)
788 {
789 	struct svs_bank *svsb = file_inode(filp)->i_private;
790 	struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
791 	int enabled, ret;
792 	char *buf = NULL;
793 
794 	if (count >= PAGE_SIZE)
795 		return -EINVAL;
796 
797 	buf = (char *)memdup_user_nul(buffer, count);
798 	if (IS_ERR(buf))
799 		return PTR_ERR(buf);
800 
801 	ret = kstrtoint(buf, 10, &enabled);
802 	if (ret)
803 		return ret;
804 
805 	if (!enabled) {
806 		svs_bank_disable_and_restore_default_volts(svsp, svsb);
807 		svsb->mode_support = SVSB_MODE_ALL_DISABLE;
808 	}
809 
810 	kfree(buf);
811 
812 	return count;
813 }
814 
815 debug_fops_rw(enable);
816 
svs_status_debug_show(struct seq_file * m,void * v)817 static int svs_status_debug_show(struct seq_file *m, void *v)
818 {
819 	struct svs_bank *svsb = (struct svs_bank *)m->private;
820 	struct dev_pm_opp *opp;
821 	int tzone_temp = 0, ret;
822 	u32 i;
823 
824 	ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
825 	if (ret)
826 		seq_printf(m, "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n",
827 			   svsb->name, svsb->vbin_turn_pt, svsb->turn_pt);
828 	else
829 		seq_printf(m, "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n",
830 			   svsb->name, tzone_temp, svsb->vbin_turn_pt,
831 			   svsb->turn_pt);
832 
833 	for (i = 0; i < svsb->pdata.opp_count; i++) {
834 		opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
835 						 svsb->opp_dfreq[i], true);
836 		if (IS_ERR(opp)) {
837 			seq_printf(m, "%s: cannot find freq = %u (%ld)\n",
838 				   svsb->name, svsb->opp_dfreq[i],
839 				   PTR_ERR(opp));
840 			return PTR_ERR(opp);
841 		}
842 
843 		seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ",
844 			   i, svsb->opp_dfreq[i], i,
845 			   dev_pm_opp_get_voltage(opp));
846 		seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n",
847 			   i, svsb->volt[i], i, svsb->freq_pct[i]);
848 		dev_pm_opp_put(opp);
849 	}
850 
851 	return 0;
852 }
853 
854 debug_fops_ro(status);
855 
svs_create_debug_cmds(struct svs_platform * svsp)856 static int svs_create_debug_cmds(struct svs_platform *svsp)
857 {
858 	struct svs_bank *svsb;
859 	struct dentry *svs_dir, *svsb_dir, *file_entry;
860 	const char *d = "/sys/kernel/debug/svs";
861 	u32 i, idx;
862 
863 	struct svs_dentry {
864 		const char *name;
865 		const struct file_operations *fops;
866 	};
867 
868 	struct svs_dentry svs_entries[] = {
869 		svs_dentry_data(dump),
870 	};
871 
872 	struct svs_dentry svsb_entries[] = {
873 		svs_dentry_data(enable),
874 		svs_dentry_data(status),
875 	};
876 
877 	svs_dir = debugfs_create_dir("svs", NULL);
878 	if (IS_ERR(svs_dir)) {
879 		dev_err(svsp->dev, "cannot create %s: %ld\n",
880 			d, PTR_ERR(svs_dir));
881 		return PTR_ERR(svs_dir);
882 	}
883 
884 	for (i = 0; i < ARRAY_SIZE(svs_entries); i++) {
885 		file_entry = debugfs_create_file(svs_entries[i].name, 0664,
886 						 svs_dir, svsp,
887 						 svs_entries[i].fops);
888 		if (IS_ERR(file_entry)) {
889 			dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
890 				d, svs_entries[i].name, PTR_ERR(file_entry));
891 			return PTR_ERR(file_entry);
892 		}
893 	}
894 
895 	for (idx = 0; idx < svsp->bank_max; idx++) {
896 		svsb = &svsp->banks[idx];
897 
898 		if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
899 			continue;
900 
901 		svsb_dir = debugfs_create_dir(svsb->name, svs_dir);
902 		if (IS_ERR(svsb_dir)) {
903 			dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
904 				d, svsb->name, PTR_ERR(svsb_dir));
905 			return PTR_ERR(svsb_dir);
906 		}
907 
908 		for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) {
909 			file_entry = debugfs_create_file(svsb_entries[i].name,
910 							 0664, svsb_dir, svsb,
911 							 svsb_entries[i].fops);
912 			if (IS_ERR(file_entry)) {
913 				dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
914 					d, svsb->name, svsb_entries[i].name,
915 					PTR_ERR(file_entry));
916 				return PTR_ERR(file_entry);
917 			}
918 		}
919 	}
920 
921 	return 0;
922 }
923 #endif /* CONFIG_DEBUG_FS */
924 
interpolate(u32 f0,u32 f1,u32 v0,u32 v1,u32 fx)925 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)
926 {
927 	u32 vx;
928 
929 	if (v0 == v1 || f0 == f1)
930 		return v0;
931 
932 	/* *100 to have decimal fraction factor */
933 	vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx));
934 
935 	return DIV_ROUND_UP(vx, 100);
936 }
937 
svs_get_bank_volts_v3(struct svs_platform * svsp,struct svs_bank * svsb)938 static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb)
939 {
940 	const struct svs_bank_pdata *bdata = &svsb->pdata;
941 	u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
942 	u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0;
943 	u32 middle_index = (bdata->opp_count / 2);
944 
945 	if (svsb->phase == SVSB_PHASE_MON &&
946 	    svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
947 		return;
948 
949 	vop74 = svs_readl_relaxed(svsp, VOP74);
950 	vop30 = svs_readl_relaxed(svsp, VOP30);
951 
952 	/* Target is to set svsb->volt[] by algorithm */
953 	if (turn_pt < middle_index) {
954 		if (bdata->type == SVSB_TYPE_HIGH) {
955 			/* volt[0] ~ volt[turn_pt - 1] */
956 			for (i = 0; i < turn_pt; i++) {
957 				b_sft = BITS8 * (shift_byte % REG_BYTES);
958 				vop = (shift_byte < REG_BYTES) ? &vop30 :
959 								 &vop74;
960 				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
961 				shift_byte++;
962 			}
963 		} else if (bdata->type == SVSB_TYPE_LOW) {
964 			/* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
965 			j = bdata->opp_count - 7;
966 			svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
967 			shift_byte++;
968 			for (i = j; i < bdata->opp_count; i++) {
969 				b_sft = BITS8 * (shift_byte % REG_BYTES);
970 				vop = (shift_byte < REG_BYTES) ? &vop30 :
971 								 &vop74;
972 				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
973 				shift_byte++;
974 			}
975 
976 			/* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */
977 			for (i = turn_pt + 1; i < j; i++)
978 				svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt],
979 							    svsb->freq_pct[j],
980 							    svsb->volt[turn_pt],
981 							    svsb->volt[j],
982 							    svsb->freq_pct[i]);
983 		}
984 	} else {
985 		if (bdata->type == SVSB_TYPE_HIGH) {
986 			/* volt[0] + volt[j] ~ volt[turn_pt - 1] */
987 			j = turn_pt - 7;
988 			svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
989 			shift_byte++;
990 			for (i = j; i < turn_pt; i++) {
991 				b_sft = BITS8 * (shift_byte % REG_BYTES);
992 				vop = (shift_byte < REG_BYTES) ? &vop30 :
993 								 &vop74;
994 				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
995 				shift_byte++;
996 			}
997 
998 			/* volt[1] ~ volt[j - 1] by interpolate */
999 			for (i = 1; i < j; i++)
1000 				svsb->volt[i] = interpolate(svsb->freq_pct[0],
1001 							    svsb->freq_pct[j],
1002 							    svsb->volt[0],
1003 							    svsb->volt[j],
1004 							    svsb->freq_pct[i]);
1005 		} else if (bdata->type == SVSB_TYPE_LOW) {
1006 			/* volt[turn_pt] ~ volt[opp_count - 1] */
1007 			for (i = turn_pt; i < bdata->opp_count; i++) {
1008 				b_sft = BITS8 * (shift_byte % REG_BYTES);
1009 				vop = (shift_byte < REG_BYTES) ? &vop30 :
1010 								 &vop74;
1011 				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
1012 				shift_byte++;
1013 			}
1014 		}
1015 	}
1016 
1017 	if (bdata->type == SVSB_TYPE_HIGH) {
1018 		opp_start = 0;
1019 		opp_stop = svsb->turn_pt;
1020 	} else if (bdata->type == SVSB_TYPE_LOW) {
1021 		opp_start = svsb->turn_pt;
1022 		opp_stop = bdata->opp_count;
1023 	}
1024 
1025 	for (i = opp_start; i < opp_stop; i++)
1026 		if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
1027 			svsb->volt[i] -= svsb->dvt_fixed;
1028 
1029 	/* For voltage bin support */
1030 	if (svsb->opp_dfreq[0] > svsb->freq_base) {
1031 		svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0],
1032 							  bdata->volt_step,
1033 							  bdata->volt_base);
1034 
1035 		/* Find voltage bin turn point */
1036 		for (i = 0; i < bdata->opp_count; i++) {
1037 			if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1038 				svsb->vbin_turn_pt = i;
1039 				break;
1040 			}
1041 		}
1042 
1043 		/* Override svs bank voltages */
1044 		for (i = 1; i < svsb->vbin_turn_pt; i++)
1045 			svsb->volt[i] = interpolate(svsb->freq_pct[0],
1046 						    svsb->freq_pct[svsb->vbin_turn_pt],
1047 						    svsb->volt[0],
1048 						    svsb->volt[svsb->vbin_turn_pt],
1049 						    svsb->freq_pct[i]);
1050 	}
1051 }
1052 
svs_set_bank_freq_pct_v3(struct svs_platform * svsp,struct svs_bank * svsb)1053 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb)
1054 {
1055 	const struct svs_bank_pdata *bdata = &svsb->pdata;
1056 	u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0;
1057 	u32 b_sft, shift_byte = 0, turn_pt;
1058 	u32 middle_index = (bdata->opp_count / 2);
1059 
1060 	for (i = 0; i < bdata->opp_count; i++) {
1061 		if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) {
1062 			svsb->turn_pt = i;
1063 			break;
1064 		}
1065 	}
1066 
1067 	turn_pt = svsb->turn_pt;
1068 
1069 	/* Target is to fill out freq_pct74 / freq_pct30 by algorithm */
1070 	if (turn_pt < middle_index) {
1071 		if (bdata->type == SVSB_TYPE_HIGH) {
1072 			/*
1073 			 * If we don't handle this situation,
1074 			 * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0"
1075 			 * and this leads SVSB_TYPE_LOW to work abnormally.
1076 			 */
1077 			if (turn_pt == 0)
1078 				freq_pct30 = svsb->freq_pct[0];
1079 
1080 			/* freq_pct[0] ~ freq_pct[turn_pt - 1] */
1081 			for (i = 0; i < turn_pt; i++) {
1082 				b_sft = BITS8 * (shift_byte % REG_BYTES);
1083 				freq_pct = (shift_byte < REG_BYTES) ?
1084 					   &freq_pct30 : &freq_pct74;
1085 				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1086 				shift_byte++;
1087 			}
1088 		} else if (bdata->type == SVSB_TYPE_LOW) {
1089 			/*
1090 			 * freq_pct[turn_pt] +
1091 			 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1]
1092 			 */
1093 			freq_pct30 = svsb->freq_pct[turn_pt];
1094 			shift_byte++;
1095 			j = bdata->opp_count - 7;
1096 			for (i = j; i < bdata->opp_count; i++) {
1097 				b_sft = BITS8 * (shift_byte % REG_BYTES);
1098 				freq_pct = (shift_byte < REG_BYTES) ?
1099 					   &freq_pct30 : &freq_pct74;
1100 				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1101 				shift_byte++;
1102 			}
1103 		}
1104 	} else {
1105 		if (bdata->type == SVSB_TYPE_HIGH) {
1106 			/*
1107 			 * freq_pct[0] +
1108 			 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1]
1109 			 */
1110 			freq_pct30 = svsb->freq_pct[0];
1111 			shift_byte++;
1112 			j = turn_pt - 7;
1113 			for (i = j; i < turn_pt; i++) {
1114 				b_sft = BITS8 * (shift_byte % REG_BYTES);
1115 				freq_pct = (shift_byte < REG_BYTES) ?
1116 					   &freq_pct30 : &freq_pct74;
1117 				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1118 				shift_byte++;
1119 			}
1120 		} else if (bdata->type == SVSB_TYPE_LOW) {
1121 			/* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */
1122 			for (i = turn_pt; i < bdata->opp_count; i++) {
1123 				b_sft = BITS8 * (shift_byte % REG_BYTES);
1124 				freq_pct = (shift_byte < REG_BYTES) ?
1125 					   &freq_pct30 : &freq_pct74;
1126 				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1127 				shift_byte++;
1128 			}
1129 		}
1130 	}
1131 
1132 	svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);
1133 	svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);
1134 }
1135 
svs_get_bank_volts_v2(struct svs_platform * svsp,struct svs_bank * svsb)1136 static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1137 {
1138 	const struct svs_bank_pdata *bdata = &svsb->pdata;
1139 	u32 temp, i;
1140 
1141 	temp = svs_readl_relaxed(svsp, VOP74);
1142 	svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1143 	svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1144 	svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1145 	svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1146 
1147 	temp = svs_readl_relaxed(svsp, VOP30);
1148 	svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1149 	svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1150 	svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1151 	svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1152 
1153 	for (i = 0; i <= 12; i += 2)
1154 		svsb->volt[i + 1] = interpolate(svsb->freq_pct[i],
1155 						svsb->freq_pct[i + 2],
1156 						svsb->volt[i],
1157 						svsb->volt[i + 2],
1158 						svsb->freq_pct[i + 1]);
1159 
1160 	svsb->volt[15] = interpolate(svsb->freq_pct[12],
1161 				     svsb->freq_pct[14],
1162 				     svsb->volt[12],
1163 				     svsb->volt[14],
1164 				     svsb->freq_pct[15]);
1165 
1166 	for (i = 0; i < bdata->opp_count; i++)
1167 		svsb->volt[i] += svsb->volt_od;
1168 
1169 	/* For voltage bin support */
1170 	if (svsb->opp_dfreq[0] > svsb->freq_base) {
1171 		svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0],
1172 							  bdata->volt_step,
1173 							  bdata->volt_base);
1174 
1175 		/* Find voltage bin turn point */
1176 		for (i = 0; i < bdata->opp_count; i++) {
1177 			if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1178 				svsb->vbin_turn_pt = i;
1179 				break;
1180 			}
1181 		}
1182 
1183 		/* Override svs bank voltages */
1184 		for (i = 1; i < svsb->vbin_turn_pt; i++)
1185 			svsb->volt[i] = interpolate(svsb->freq_pct[0],
1186 						    svsb->freq_pct[svsb->vbin_turn_pt],
1187 						    svsb->volt[0],
1188 						    svsb->volt[svsb->vbin_turn_pt],
1189 						    svsb->freq_pct[i]);
1190 	}
1191 }
1192 
svs_set_bank_freq_pct_v2(struct svs_platform * svsp,struct svs_bank * svsb)1193 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1194 {
1195 	u32 freqpct74_val, freqpct30_val;
1196 
1197 	freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
1198 			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
1199 			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
1200 			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
1201 
1202 	freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
1203 			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
1204 			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
1205 			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
1206 
1207 	svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);
1208 	svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);
1209 }
1210 
svs_set_bank_phase(struct svs_platform * svsp,unsigned int bank_idx,enum svsb_phase target_phase)1211 static void svs_set_bank_phase(struct svs_platform *svsp,
1212 			       unsigned int bank_idx,
1213 			       enum svsb_phase target_phase)
1214 {
1215 	struct svs_bank *svsb = &svsp->banks[bank_idx];
1216 	const struct svs_bank_pdata *bdata = &svsb->pdata;
1217 	u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs;
1218 
1219 	svs_switch_bank(svsp, svsb);
1220 
1221 	des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
1222 		   FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
1223 	svs_writel_relaxed(svsp, des_char, DESCHAR);
1224 
1225 	temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) |
1226 		    FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
1227 		    FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
1228 	svs_writel_relaxed(svsp, temp_char, TEMPCHAR);
1229 
1230 	det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
1231 		   FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
1232 	svs_writel_relaxed(svsp, det_char, DETCHAR);
1233 
1234 	svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG);
1235 	svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG);
1236 	svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG);
1237 
1238 	bdata->set_freq_pct(svsp, svsb);
1239 
1240 	limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) |
1241 		     FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) |
1242 		     FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
1243 		     FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
1244 	svs_writel_relaxed(svsp, limit_vals, LIMITVALS);
1245 
1246 	svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);
1247 	svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
1248 	svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT);
1249 	svs_writel_relaxed(svsp, bdata->ctl0, CTL0);
1250 	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1251 
1252 	switch (target_phase) {
1253 	case SVSB_PHASE_INIT01:
1254 		svs_writel_relaxed(svsp, bdata->vboot, VBOOT);
1255 		svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1256 		svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);
1257 		break;
1258 	case SVSB_PHASE_INIT02:
1259 		init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
1260 			    FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
1261 		svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1262 		svs_writel_relaxed(svsp, init2vals, INIT2VALS);
1263 		svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);
1264 		break;
1265 	case SVSB_PHASE_MON:
1266 		ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
1267 			   FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
1268 		svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
1269 		svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
1270 		svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);
1271 		break;
1272 	default:
1273 		dev_err(svsb->dev, "requested unknown target phase: %u\n",
1274 			target_phase);
1275 		break;
1276 	}
1277 }
1278 
svs_save_bank_register_data(struct svs_platform * svsp,unsigned short bank_idx,enum svsb_phase phase)1279 static inline void svs_save_bank_register_data(struct svs_platform *svsp,
1280 					       unsigned short bank_idx,
1281 					       enum svsb_phase phase)
1282 {
1283 	struct svs_bank *svsb = &svsp->banks[bank_idx];
1284 	enum svs_reg_index rg_i;
1285 
1286 	for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++)
1287 		svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1288 }
1289 
svs_error_isr_handler(struct svs_platform * svsp,unsigned short bank_idx)1290 static inline void svs_error_isr_handler(struct svs_platform *svsp,
1291 					 unsigned short bank_idx)
1292 {
1293 	struct svs_bank *svsb = &svsp->banks[bank_idx];
1294 
1295 	dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n",
1296 		__func__, svs_readl_relaxed(svsp, CORESEL));
1297 	dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n",
1298 		svs_readl_relaxed(svsp, SVSEN),
1299 		svs_readl_relaxed(svsp, INTSTS));
1300 	dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
1301 		svs_readl_relaxed(svsp, SMSTATE0),
1302 		svs_readl_relaxed(svsp, SMSTATE1));
1303 	dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1304 
1305 	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_ERROR);
1306 
1307 	svsb->phase = SVSB_PHASE_ERROR;
1308 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1309 	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1310 }
1311 
svs_init01_isr_handler(struct svs_platform * svsp,unsigned short bank_idx)1312 static inline void svs_init01_isr_handler(struct svs_platform *svsp,
1313 					  unsigned short bank_idx)
1314 {
1315 	struct svs_bank *svsb = &svsp->banks[bank_idx];
1316 	u32 val;
1317 
1318 	dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n",
1319 		 __func__, svs_readl_relaxed(svsp, VDESIGN74),
1320 		 svs_readl_relaxed(svsp, VDESIGN30),
1321 		 svs_readl_relaxed(svsp, DCVALUES));
1322 
1323 	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT01);
1324 
1325 	svsb->phase = SVSB_PHASE_INIT01;
1326 	val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1;
1327 	svsb->dc_voffset_in = val & GENMASK(15, 0);
1328 	if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE ||
1329 	    (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT &&
1330 	     svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY))
1331 		svsb->dc_voffset_in = 0;
1332 
1333 	svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1334 			       GENMASK(15, 0);
1335 
1336 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1337 	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1338 	svsb->core_sel &= ~SVSB_DET_CLK_EN;
1339 }
1340 
svs_init02_isr_handler(struct svs_platform * svsp,unsigned short bank_idx)1341 static inline void svs_init02_isr_handler(struct svs_platform *svsp,
1342 					  unsigned short bank_idx)
1343 {
1344 	struct svs_bank *svsb = &svsp->banks[bank_idx];
1345 	const struct svs_bank_pdata *bdata = &svsb->pdata;
1346 
1347 	dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n",
1348 		 __func__, svs_readl_relaxed(svsp, VOP74),
1349 		 svs_readl_relaxed(svsp, VOP30),
1350 		 svs_readl_relaxed(svsp, DCVALUES));
1351 
1352 	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02);
1353 
1354 	svsb->phase = SVSB_PHASE_INIT02;
1355 	bdata->get_volts(svsp, svsb);
1356 
1357 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1358 	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1359 }
1360 
svs_mon_mode_isr_handler(struct svs_platform * svsp,unsigned short bank_idx)1361 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp,
1362 					    unsigned short bank_idx)
1363 {
1364 	struct svs_bank *svsb = &svsp->banks[bank_idx];
1365 	const struct svs_bank_pdata *bdata = &svsb->pdata;
1366 
1367 	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON);
1368 
1369 	svsb->phase = SVSB_PHASE_MON;
1370 	bdata->get_volts(svsp, svsb);
1371 
1372 	svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1373 	svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);
1374 }
1375 
svs_isr(int irq,void * data)1376 static irqreturn_t svs_isr(int irq, void *data)
1377 {
1378 	struct svs_platform *svsp = data;
1379 	const struct svs_bank_pdata *bdata;
1380 	struct svs_bank *svsb = NULL;
1381 	unsigned long flags;
1382 	u32 idx, int_sts, svs_en;
1383 
1384 	for (idx = 0; idx < svsp->bank_max; idx++) {
1385 		svsb = &svsp->banks[idx];
1386 		bdata = &svsb->pdata;
1387 		WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name);
1388 
1389 		spin_lock_irqsave(&svs_lock, flags);
1390 
1391 		/* Find out which svs bank fires interrupt */
1392 		if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) {
1393 			spin_unlock_irqrestore(&svs_lock, flags);
1394 			continue;
1395 		}
1396 
1397 		svs_switch_bank(svsp, svsb);
1398 		int_sts = svs_readl_relaxed(svsp, INTSTS);
1399 		svs_en = svs_readl_relaxed(svsp, SVSEN);
1400 
1401 		if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1402 		    svs_en == SVSB_PTPEN_INIT01)
1403 			svs_init01_isr_handler(svsp, idx);
1404 		else if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1405 			 svs_en == SVSB_PTPEN_INIT02)
1406 			svs_init02_isr_handler(svsp, idx);
1407 		else if (int_sts & SVSB_INTSTS_FLD_MONVOP)
1408 			svs_mon_mode_isr_handler(svsp, idx);
1409 		else
1410 			svs_error_isr_handler(svsp, idx);
1411 
1412 		spin_unlock_irqrestore(&svs_lock, flags);
1413 		break;
1414 	}
1415 
1416 	svs_adjust_pm_opp_volts(svsb);
1417 
1418 	if (svsb->phase == SVSB_PHASE_INIT01 ||
1419 	    svsb->phase == SVSB_PHASE_INIT02)
1420 		complete(&svsb->init_completion);
1421 
1422 	return IRQ_HANDLED;
1423 }
1424 
svs_mode_available(struct svs_platform * svsp,u8 mode)1425 static bool svs_mode_available(struct svs_platform *svsp, u8 mode)
1426 {
1427 	int i;
1428 
1429 	for (i = 0; i < svsp->bank_max; i++)
1430 		if (svsp->banks[i].mode_support & mode)
1431 			return true;
1432 	return false;
1433 }
1434 
svs_init01(struct svs_platform * svsp)1435 static int svs_init01(struct svs_platform *svsp)
1436 {
1437 	const struct svs_bank_pdata *bdata;
1438 	struct svs_bank *svsb;
1439 	unsigned long flags, time_left;
1440 	bool search_done;
1441 	int ret = 0, r;
1442 	u32 opp_freq, opp_vboot, buck_volt, idx, i;
1443 
1444 	if (!svs_mode_available(svsp, SVSB_MODE_INIT01))
1445 		return 0;
1446 
1447 	/* Keep CPUs' core power on for svs_init01 initialization */
1448 	cpuidle_pause_and_lock();
1449 
1450 	 /* Svs bank init01 preparation - power enable */
1451 	for (idx = 0; idx < svsp->bank_max; idx++) {
1452 		svsb = &svsp->banks[idx];
1453 		bdata = &svsb->pdata;
1454 
1455 		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1456 			continue;
1457 
1458 		ret = regulator_enable(svsb->buck);
1459 		if (ret) {
1460 			dev_err(svsb->dev, "%s enable fail: %d\n",
1461 				bdata->buck_name, ret);
1462 			goto svs_init01_resume_cpuidle;
1463 		}
1464 
1465 		/* Some buck doesn't support mode change. Show fail msg only */
1466 		ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST);
1467 		if (ret)
1468 			dev_notice(svsb->dev, "set fast mode fail: %d\n", ret);
1469 
1470 		if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1471 			if (!pm_runtime_enabled(svsb->opp_dev)) {
1472 				pm_runtime_enable(svsb->opp_dev);
1473 				svsb->pm_runtime_enabled_count++;
1474 			}
1475 
1476 			ret = pm_runtime_resume_and_get(svsb->opp_dev);
1477 			if (ret < 0) {
1478 				dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
1479 				goto svs_init01_resume_cpuidle;
1480 			}
1481 		}
1482 	}
1483 
1484 	/*
1485 	 * Svs bank init01 preparation - vboot voltage adjustment
1486 	 * Sometimes two svs banks use the same buck. Therefore,
1487 	 * we have to set each svs bank to target voltage(vboot) first.
1488 	 */
1489 	for (idx = 0; idx < svsp->bank_max; idx++) {
1490 		svsb = &svsp->banks[idx];
1491 		bdata = &svsb->pdata;
1492 
1493 		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1494 			continue;
1495 
1496 		/*
1497 		 * Find the fastest freq that can be run at vboot and
1498 		 * fix to that freq until svs_init01 is done.
1499 		 */
1500 		search_done = false;
1501 		opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot,
1502 						      bdata->volt_step,
1503 						      bdata->volt_base);
1504 
1505 		for (i = 0; i < bdata->opp_count; i++) {
1506 			opp_freq = svsb->opp_dfreq[i];
1507 			if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) {
1508 				ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
1509 								opp_freq,
1510 								opp_vboot,
1511 								opp_vboot,
1512 								opp_vboot);
1513 				if (ret) {
1514 					dev_err(svsb->dev,
1515 						"set opp %uuV vboot fail: %d\n",
1516 						opp_vboot, ret);
1517 					goto svs_init01_finish;
1518 				}
1519 
1520 				search_done = true;
1521 			} else {
1522 				ret = dev_pm_opp_disable(svsb->opp_dev,
1523 							 svsb->opp_dfreq[i]);
1524 				if (ret) {
1525 					dev_err(svsb->dev,
1526 						"opp %uHz disable fail: %d\n",
1527 						svsb->opp_dfreq[i], ret);
1528 					goto svs_init01_finish;
1529 				}
1530 			}
1531 		}
1532 	}
1533 
1534 	/* Svs bank init01 begins */
1535 	for (idx = 0; idx < svsp->bank_max; idx++) {
1536 		svsb = &svsp->banks[idx];
1537 		bdata = &svsb->pdata;
1538 
1539 		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1540 			continue;
1541 
1542 		opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot,
1543 						      bdata->volt_step,
1544 						      bdata->volt_base);
1545 
1546 		buck_volt = regulator_get_voltage(svsb->buck);
1547 		if (buck_volt != opp_vboot) {
1548 			dev_err(svsb->dev,
1549 				"buck voltage: %uuV, expected vboot: %uuV\n",
1550 				buck_volt, opp_vboot);
1551 			ret = -EPERM;
1552 			goto svs_init01_finish;
1553 		}
1554 
1555 		spin_lock_irqsave(&svs_lock, flags);
1556 		svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT01);
1557 		spin_unlock_irqrestore(&svs_lock, flags);
1558 
1559 		time_left = wait_for_completion_timeout(&svsb->init_completion,
1560 							msecs_to_jiffies(5000));
1561 		if (!time_left) {
1562 			dev_err(svsb->dev, "init01 completion timeout\n");
1563 			ret = -EBUSY;
1564 			goto svs_init01_finish;
1565 		}
1566 	}
1567 
1568 svs_init01_finish:
1569 	for (idx = 0; idx < svsp->bank_max; idx++) {
1570 		svsb = &svsp->banks[idx];
1571 		bdata = &svsb->pdata;
1572 
1573 		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1574 			continue;
1575 
1576 		for (i = 0; i < bdata->opp_count; i++) {
1577 			r = dev_pm_opp_enable(svsb->opp_dev,
1578 					      svsb->opp_dfreq[i]);
1579 			if (r)
1580 				dev_err(svsb->dev, "opp %uHz enable fail: %d\n",
1581 					svsb->opp_dfreq[i], r);
1582 		}
1583 
1584 		if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1585 			r = pm_runtime_put_sync(svsb->opp_dev);
1586 			if (r)
1587 				dev_err(svsb->dev, "mtcmos off fail: %d\n", r);
1588 
1589 			if (svsb->pm_runtime_enabled_count > 0) {
1590 				pm_runtime_disable(svsb->opp_dev);
1591 				svsb->pm_runtime_enabled_count--;
1592 			}
1593 		}
1594 
1595 		r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL);
1596 		if (r)
1597 			dev_notice(svsb->dev, "set normal mode fail: %d\n", r);
1598 
1599 		r = regulator_disable(svsb->buck);
1600 		if (r)
1601 			dev_err(svsb->dev, "%s disable fail: %d\n",
1602 				bdata->buck_name, r);
1603 	}
1604 
1605 svs_init01_resume_cpuidle:
1606 	cpuidle_resume_and_unlock();
1607 
1608 	return ret;
1609 }
1610 
svs_init02(struct svs_platform * svsp)1611 static int svs_init02(struct svs_platform *svsp)
1612 {
1613 	const struct svs_bank_pdata *bdata;
1614 	struct svs_bank *svsb;
1615 	unsigned long flags, time_left;
1616 	int ret;
1617 	u32 idx;
1618 
1619 	if (!svs_mode_available(svsp, SVSB_MODE_INIT02))
1620 		return 0;
1621 
1622 	for (idx = 0; idx < svsp->bank_max; idx++) {
1623 		svsb = &svsp->banks[idx];
1624 
1625 		if (!(svsb->mode_support & SVSB_MODE_INIT02))
1626 			continue;
1627 
1628 		reinit_completion(&svsb->init_completion);
1629 		spin_lock_irqsave(&svs_lock, flags);
1630 		svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT02);
1631 		spin_unlock_irqrestore(&svs_lock, flags);
1632 
1633 		time_left = wait_for_completion_timeout(&svsb->init_completion,
1634 							msecs_to_jiffies(5000));
1635 		if (!time_left) {
1636 			dev_err(svsb->dev, "init02 completion timeout\n");
1637 			ret = -EBUSY;
1638 			goto out_of_init02;
1639 		}
1640 	}
1641 
1642 	/*
1643 	 * 2-line high/low bank update its corresponding opp voltages only.
1644 	 * Therefore, we sync voltages from opp for high/low bank voltages
1645 	 * consistency.
1646 	 */
1647 	for (idx = 0; idx < svsp->bank_max; idx++) {
1648 		svsb = &svsp->banks[idx];
1649 		bdata = &svsb->pdata;
1650 
1651 		if (!(svsb->mode_support & SVSB_MODE_INIT02))
1652 			continue;
1653 
1654 		if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) {
1655 			if (svs_sync_bank_volts_from_opp(svsb)) {
1656 				dev_err(svsb->dev, "sync volt fail\n");
1657 				ret = -EPERM;
1658 				goto out_of_init02;
1659 			}
1660 		}
1661 	}
1662 
1663 	return 0;
1664 
1665 out_of_init02:
1666 	for (idx = 0; idx < svsp->bank_max; idx++) {
1667 		svsb = &svsp->banks[idx];
1668 		svs_bank_disable_and_restore_default_volts(svsp, svsb);
1669 	}
1670 
1671 	return ret;
1672 }
1673 
svs_mon_mode(struct svs_platform * svsp)1674 static void svs_mon_mode(struct svs_platform *svsp)
1675 {
1676 	struct svs_bank *svsb;
1677 	unsigned long flags;
1678 	u32 idx;
1679 
1680 	for (idx = 0; idx < svsp->bank_max; idx++) {
1681 		svsb = &svsp->banks[idx];
1682 
1683 		if (!(svsb->mode_support & SVSB_MODE_MON))
1684 			continue;
1685 
1686 		spin_lock_irqsave(&svs_lock, flags);
1687 		svs_set_bank_phase(svsp, idx, SVSB_PHASE_MON);
1688 		spin_unlock_irqrestore(&svs_lock, flags);
1689 	}
1690 }
1691 
svs_start(struct svs_platform * svsp)1692 static int svs_start(struct svs_platform *svsp)
1693 {
1694 	int ret;
1695 
1696 	ret = svs_init01(svsp);
1697 	if (ret)
1698 		return ret;
1699 
1700 	ret = svs_init02(svsp);
1701 	if (ret)
1702 		return ret;
1703 
1704 	svs_mon_mode(svsp);
1705 
1706 	return 0;
1707 }
1708 
svs_suspend(struct device * dev)1709 static int svs_suspend(struct device *dev)
1710 {
1711 	struct svs_platform *svsp = dev_get_drvdata(dev);
1712 	int ret;
1713 	u32 idx;
1714 
1715 	for (idx = 0; idx < svsp->bank_max; idx++) {
1716 		struct svs_bank *svsb = &svsp->banks[idx];
1717 
1718 		svs_bank_disable_and_restore_default_volts(svsp, svsb);
1719 	}
1720 
1721 	ret = reset_control_assert(svsp->rst);
1722 	if (ret) {
1723 		dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1724 		return ret;
1725 	}
1726 
1727 	clk_disable_unprepare(svsp->main_clk);
1728 
1729 	return 0;
1730 }
1731 
svs_resume(struct device * dev)1732 static int svs_resume(struct device *dev)
1733 {
1734 	struct svs_platform *svsp = dev_get_drvdata(dev);
1735 	int ret;
1736 
1737 	ret = clk_prepare_enable(svsp->main_clk);
1738 	if (ret) {
1739 		dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1740 		return ret;
1741 	}
1742 
1743 	ret = reset_control_deassert(svsp->rst);
1744 	if (ret) {
1745 		dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1746 		goto out_of_resume;
1747 	}
1748 
1749 	ret = svs_init02(svsp);
1750 	if (ret)
1751 		goto svs_resume_reset_assert;
1752 
1753 	svs_mon_mode(svsp);
1754 
1755 	return 0;
1756 
1757 svs_resume_reset_assert:
1758 	dev_err(svsp->dev, "assert reset: %d\n",
1759 		reset_control_assert(svsp->rst));
1760 
1761 out_of_resume:
1762 	clk_disable_unprepare(svsp->main_clk);
1763 	return ret;
1764 }
1765 
svs_bank_resource_setup(struct svs_platform * svsp)1766 static int svs_bank_resource_setup(struct svs_platform *svsp)
1767 {
1768 	const struct svs_bank_pdata *bdata;
1769 	struct svs_bank *svsb;
1770 	struct dev_pm_opp *opp;
1771 	char tz_name_buf[20];
1772 	unsigned long freq;
1773 	int count, ret;
1774 	u32 idx, i;
1775 
1776 	dev_set_drvdata(svsp->dev, svsp);
1777 
1778 	for (idx = 0; idx < svsp->bank_max; idx++) {
1779 		svsb = &svsp->banks[idx];
1780 		bdata = &svsb->pdata;
1781 
1782 		if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) {
1783 			dev_err(svsb->dev, "unknown bank sw_id or type\n");
1784 			return -EINVAL;
1785 		}
1786 
1787 		svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL);
1788 		if (!svsb->dev)
1789 			return -ENOMEM;
1790 
1791 		svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s",
1792 					    svs_swid_names[bdata->sw_id],
1793 					    svs_type_names[bdata->type]);
1794 		if (!svsb->name)
1795 			return -ENOMEM;
1796 
1797 		ret = dev_set_name(svsb->dev, "%s", svsb->name);
1798 		if (ret)
1799 			return ret;
1800 
1801 		dev_set_drvdata(svsb->dev, svsp);
1802 
1803 		ret = devm_pm_opp_of_add_table(svsb->opp_dev);
1804 		if (ret) {
1805 			dev_err(svsb->dev, "add opp table fail: %d\n", ret);
1806 			return ret;
1807 		}
1808 
1809 		mutex_init(&svsb->lock);
1810 		init_completion(&svsb->init_completion);
1811 
1812 		if (svsb->mode_support & SVSB_MODE_INIT01) {
1813 			svsb->buck = devm_regulator_get_optional(svsb->opp_dev,
1814 								 bdata->buck_name);
1815 			if (IS_ERR(svsb->buck)) {
1816 				dev_err(svsb->dev, "cannot get \"%s-supply\"\n",
1817 					bdata->buck_name);
1818 				return PTR_ERR(svsb->buck);
1819 			}
1820 		}
1821 
1822 		if (!IS_ERR_OR_NULL(bdata->tzone_name)) {
1823 			snprintf(tz_name_buf, ARRAY_SIZE(tz_name_buf),
1824 				 "%s-thermal", bdata->tzone_name);
1825 			svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf);
1826 			if (IS_ERR(svsb->tzd)) {
1827 				dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1828 					tz_name_buf);
1829 				return PTR_ERR(svsb->tzd);
1830 			}
1831 		}
1832 
1833 		count = dev_pm_opp_get_opp_count(svsb->opp_dev);
1834 		if (bdata->opp_count != count) {
1835 			dev_err(svsb->dev,
1836 				"opp_count not \"%u\" but get \"%d\"?\n",
1837 				bdata->opp_count, count);
1838 			return count;
1839 		}
1840 
1841 		for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) {
1842 			opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq);
1843 			if (IS_ERR(opp)) {
1844 				dev_err(svsb->dev, "cannot find freq = %ld\n",
1845 					PTR_ERR(opp));
1846 				return PTR_ERR(opp);
1847 			}
1848 
1849 			svsb->opp_dfreq[i] = freq;
1850 			svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp);
1851 			svsb->freq_pct[i] = percent(svsb->opp_dfreq[i],
1852 						    svsb->freq_base);
1853 			dev_pm_opp_put(opp);
1854 		}
1855 	}
1856 
1857 	return 0;
1858 }
1859 
svs_get_efuse_data(struct svs_platform * svsp,const char * nvmem_cell_name,u32 ** svsp_efuse,size_t * svsp_efuse_max)1860 static int svs_get_efuse_data(struct svs_platform *svsp,
1861 			      const char *nvmem_cell_name,
1862 			      u32 **svsp_efuse, size_t *svsp_efuse_max)
1863 {
1864 	struct nvmem_cell *cell;
1865 
1866 	cell = nvmem_cell_get(svsp->dev, nvmem_cell_name);
1867 	if (IS_ERR(cell)) {
1868 		dev_err(svsp->dev, "no \"%s\"? %ld\n",
1869 			nvmem_cell_name, PTR_ERR(cell));
1870 		return PTR_ERR(cell);
1871 	}
1872 
1873 	*svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max);
1874 	if (IS_ERR(*svsp_efuse)) {
1875 		nvmem_cell_put(cell);
1876 		return PTR_ERR(*svsp_efuse);
1877 	}
1878 
1879 	*svsp_efuse_max /= sizeof(u32);
1880 	nvmem_cell_put(cell);
1881 
1882 	return 0;
1883 }
1884 
svs_get_fuse_val(u32 * fuse_array,const struct svs_fusemap * fmap,u8 nbits)1885 static u32 svs_get_fuse_val(u32 *fuse_array, const struct svs_fusemap *fmap, u8 nbits)
1886 {
1887 	u32 val;
1888 
1889 	if (fmap->index < 0)
1890 		return FUSE_DATA_NOT_VALID;
1891 
1892 	val = fuse_array[fmap->index] >> fmap->ofst;
1893 	val &= GENMASK(nbits - 1, 0);
1894 
1895 	return val;
1896 }
1897 
svs_is_available(struct svs_platform * svsp)1898 static bool svs_is_available(struct svs_platform *svsp)
1899 {
1900 	int i, num_populated = 0;
1901 
1902 	/* If at least two fuse arrays are populated, SVS is calibrated */
1903 	for (i = 0; i < svsp->efuse_max; i++) {
1904 		if (svsp->efuse[i])
1905 			num_populated++;
1906 
1907 		if (num_populated > 1)
1908 			return true;
1909 	}
1910 
1911 	return false;
1912 }
1913 
svs_common_parse_efuse(struct svs_platform * svsp,const struct svs_platform_data * pdata)1914 static bool svs_common_parse_efuse(struct svs_platform *svsp,
1915 				   const struct svs_platform_data *pdata)
1916 {
1917 	const struct svs_fusemap *gfmap = pdata->glb_fuse_map;
1918 	struct svs_fusemap tfm = { 0, 24 };
1919 	u32 golden_temp, val;
1920 	u8 ft_pgm, vmin;
1921 	int i;
1922 
1923 	if (!svs_is_available(svsp))
1924 		return false;
1925 
1926 	/* Get golden temperature from SVS-Thermal calibration */
1927 	val = svs_get_fuse_val(svsp->tefuse, &tfm, 8);
1928 
1929 	/* If golden temp is not programmed, use the default of 50 */
1930 	golden_temp = val ? val : 50;
1931 
1932 	/* Parse fused SVS calibration */
1933 	ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8);
1934 	vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2);
1935 
1936 	for (i = 0; i < svsp->bank_max; i++) {
1937 		struct svs_bank *svsb = &svsp->banks[i];
1938 		const struct svs_bank_pdata *bdata = &svsb->pdata;
1939 		const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1940 
1941 		if (vmin == 1)
1942 			svsb->vmin = 0x1e;
1943 
1944 		if (ft_pgm == 0)
1945 			svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1946 
1947 		svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1948 		svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1949 		svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1950 		svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1951 		svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1952 		svsb->vmax += svsb->dvt_fixed;
1953 
1954 		svsb->mts = (svsp->ts_coeff * 2) / 1000;
1955 		svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4;
1956 	}
1957 
1958 	return true;
1959 }
1960 
svs_mt8183_efuse_parsing(struct svs_platform * svsp,const struct svs_platform_data * pdata)1961 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp,
1962 				     const struct svs_platform_data *pdata)
1963 {
1964 	struct svs_bank *svsb;
1965 	const struct svs_bank_pdata *bdata;
1966 	int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0;
1967 	int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t;
1968 	int o_slope, o_slope_sign, ts_id;
1969 	u32 idx, i, ft_pgm, mts, temp0, temp1, temp2;
1970 
1971 	for (i = 0; i < svsp->efuse_max; i++)
1972 		if (svsp->efuse[i])
1973 			dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1974 				 i, svsp->efuse[i]);
1975 
1976 	if (!svsp->efuse[2]) {
1977 		dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1978 		return false;
1979 	}
1980 
1981 	/* Svs efuse parsing */
1982 	ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4);
1983 
1984 	for (idx = 0; idx < svsp->bank_max; idx++) {
1985 		svsb = &svsp->banks[idx];
1986 		bdata = &svsb->pdata;
1987 		const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1988 
1989 		if (ft_pgm <= 1)
1990 			svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1991 
1992 		svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1993 		svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1994 		svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1995 		svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1996 		svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1997 
1998 		switch (bdata->sw_id) {
1999 		case SVSB_SWID_CPU_LITTLE:
2000 		case SVSB_SWID_CCI:
2001 			if (ft_pgm <= 3)
2002 				svsb->volt_od += 10;
2003 			else
2004 				svsb->volt_od += 2;
2005 			break;
2006 		case SVSB_SWID_CPU_BIG:
2007 			if (ft_pgm <= 3)
2008 				svsb->volt_od += 15;
2009 			else
2010 				svsb->volt_od += 12;
2011 			break;
2012 		case SVSB_SWID_GPU:
2013 			if (ft_pgm != FUSE_DATA_NOT_VALID && ft_pgm >= 2) {
2014 				svsb->freq_base = 800000000; /* 800MHz */
2015 				svsb->dvt_fixed = 2;
2016 			}
2017 			break;
2018 		default:
2019 			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2020 			return false;
2021 		}
2022 	}
2023 
2024 	/* Thermal efuse parsing */
2025 	adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
2026 	adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
2027 
2028 	o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
2029 	o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
2030 	o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
2031 	o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
2032 	o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
2033 	o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
2034 
2035 	degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
2036 	adc_cali_en_t = svsp->tefuse[0] & BIT(0);
2037 	o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
2038 
2039 	ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
2040 	if (!ts_id) {
2041 		o_slope = 1534;
2042 	} else {
2043 		o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
2044 		if (!o_slope_sign)
2045 			o_slope = 1534 + o_slope * 10;
2046 		else
2047 			o_slope = 1534 - o_slope * 10;
2048 	}
2049 
2050 	if (adc_cali_en_t == 0 ||
2051 	    adc_ge_t < 265 || adc_ge_t > 758 ||
2052 	    adc_oe_t < 265 || adc_oe_t > 758 ||
2053 	    o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
2054 	    o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
2055 	    o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
2056 	    o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
2057 	    o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
2058 	    o_vtsabb < -8 || o_vtsabb > 484 ||
2059 	    degc_cali < 1 || degc_cali > 63) {
2060 		dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
2061 		goto remove_mt8183_svsb_mon_mode;
2062 	}
2063 
2064 	ge = ((adc_ge_t - 512) * 10000) / 4096;
2065 	oe = (adc_oe_t - 512);
2066 	gain = (10000 + ge);
2067 
2068 	format[0] = (o_vtsmcu[0] + 3350 - oe);
2069 	format[1] = (o_vtsmcu[1] + 3350 - oe);
2070 	format[2] = (o_vtsmcu[2] + 3350 - oe);
2071 	format[3] = (o_vtsmcu[3] + 3350 - oe);
2072 	format[4] = (o_vtsmcu[4] + 3350 - oe);
2073 	format[5] = (o_vtsabb + 3350 - oe);
2074 
2075 	for (i = 0; i < 6; i++)
2076 		x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain;
2077 
2078 	temp0 = (10000 * 100000 / gain) * 15 / 18;
2079 	mts = (temp0 * 10) / o_slope;
2080 
2081 	for (idx = 0; idx < svsp->bank_max; idx++) {
2082 		svsb = &svsp->banks[idx];
2083 		bdata = &svsb->pdata;
2084 		svsb->mts = mts;
2085 
2086 		switch (bdata->sw_id) {
2087 		case SVSB_SWID_CPU_LITTLE:
2088 			tb_roomt = x_roomt[3];
2089 			break;
2090 		case SVSB_SWID_CPU_BIG:
2091 			tb_roomt = x_roomt[4];
2092 			break;
2093 		case SVSB_SWID_CCI:
2094 			tb_roomt = x_roomt[3];
2095 			break;
2096 		case SVSB_SWID_GPU:
2097 			tb_roomt = x_roomt[1];
2098 			break;
2099 		default:
2100 			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2101 			goto remove_mt8183_svsb_mon_mode;
2102 		}
2103 
2104 		temp0 = (degc_cali * 10 / 2);
2105 		temp1 = ((10000 * 100000 / 4096 / gain) *
2106 			 oe + tb_roomt * 10) * 15 / 18;
2107 		temp2 = temp1 * 100 / o_slope;
2108 
2109 		svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
2110 	}
2111 
2112 	return true;
2113 
2114 remove_mt8183_svsb_mon_mode:
2115 	for (idx = 0; idx < svsp->bank_max; idx++) {
2116 		svsb = &svsp->banks[idx];
2117 		svsb->mode_support &= ~SVSB_MODE_MON;
2118 	}
2119 
2120 	return true;
2121 }
2122 
svs_get_subsys_device(struct svs_platform * svsp,const char * node_name)2123 static struct device *svs_get_subsys_device(struct svs_platform *svsp,
2124 					    const char *node_name)
2125 {
2126 	struct platform_device *pdev;
2127 	struct device_node *np;
2128 
2129 	np = of_find_node_by_name(NULL, node_name);
2130 	if (!np) {
2131 		dev_err(svsp->dev, "cannot find %s node\n", node_name);
2132 		return ERR_PTR(-ENODEV);
2133 	}
2134 
2135 	pdev = of_find_device_by_node(np);
2136 	if (!pdev) {
2137 		of_node_put(np);
2138 		dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2139 		return ERR_PTR(-ENXIO);
2140 	}
2141 
2142 	of_node_put(np);
2143 
2144 	return &pdev->dev;
2145 }
2146 
svs_add_device_link(struct svs_platform * svsp,const char * node_name)2147 static struct device *svs_add_device_link(struct svs_platform *svsp,
2148 					  const char *node_name)
2149 {
2150 	struct device *dev;
2151 	struct device_link *sup_link;
2152 
2153 	dev = svs_get_subsys_device(svsp, node_name);
2154 	if (IS_ERR(dev))
2155 		return dev;
2156 
2157 	sup_link = device_link_add(svsp->dev, dev,
2158 				   DL_FLAG_AUTOREMOVE_CONSUMER);
2159 	if (!sup_link) {
2160 		dev_err(svsp->dev, "sup_link is NULL\n");
2161 		return ERR_PTR(-EINVAL);
2162 	}
2163 
2164 	if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
2165 		return ERR_PTR(-EPROBE_DEFER);
2166 
2167 	return dev;
2168 }
2169 
svs_mt8192_platform_probe(struct svs_platform * svsp)2170 static int svs_mt8192_platform_probe(struct svs_platform *svsp)
2171 {
2172 	struct device *dev;
2173 	u32 idx;
2174 
2175 	svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
2176 	if (IS_ERR(svsp->rst))
2177 		return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
2178 				     "cannot get svs reset control\n");
2179 
2180 	dev = svs_add_device_link(svsp, "thermal-sensor");
2181 	if (IS_ERR(dev))
2182 		return dev_err_probe(svsp->dev, PTR_ERR(dev),
2183 				     "failed to get lvts device\n");
2184 
2185 	for (idx = 0; idx < svsp->bank_max; idx++) {
2186 		struct svs_bank *svsb = &svsp->banks[idx];
2187 		const struct svs_bank_pdata *bdata = &svsb->pdata;
2188 
2189 		switch (bdata->sw_id) {
2190 		case SVSB_SWID_CPU_LITTLE:
2191 		case SVSB_SWID_CPU_BIG:
2192 			svsb->opp_dev = get_cpu_device(bdata->cpu_id);
2193 			break;
2194 		case SVSB_SWID_CCI:
2195 			svsb->opp_dev = svs_add_device_link(svsp, "cci");
2196 			break;
2197 		case SVSB_SWID_GPU:
2198 			if (bdata->type == SVSB_TYPE_LOW)
2199 				svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
2200 			else
2201 				svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2202 			break;
2203 		default:
2204 			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2205 			return -EINVAL;
2206 		}
2207 
2208 		if (IS_ERR(svsb->opp_dev))
2209 			return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2210 					     "failed to get OPP device for bank %d\n",
2211 					     idx);
2212 	}
2213 
2214 	return 0;
2215 }
2216 
svs_mt8183_platform_probe(struct svs_platform * svsp)2217 static int svs_mt8183_platform_probe(struct svs_platform *svsp)
2218 {
2219 	struct device *dev;
2220 	u32 idx;
2221 
2222 	dev = svs_add_device_link(svsp, "thermal-sensor");
2223 	if (IS_ERR(dev))
2224 		return dev_err_probe(svsp->dev, PTR_ERR(dev),
2225 				     "failed to get thermal device\n");
2226 
2227 	for (idx = 0; idx < svsp->bank_max; idx++) {
2228 		struct svs_bank *svsb = &svsp->banks[idx];
2229 		const struct svs_bank_pdata *bdata = &svsb->pdata;
2230 
2231 		switch (bdata->sw_id) {
2232 		case SVSB_SWID_CPU_LITTLE:
2233 		case SVSB_SWID_CPU_BIG:
2234 			svsb->opp_dev = get_cpu_device(bdata->cpu_id);
2235 			break;
2236 		case SVSB_SWID_CCI:
2237 			svsb->opp_dev = svs_add_device_link(svsp, "cci");
2238 			break;
2239 		case SVSB_SWID_GPU:
2240 			svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2241 			break;
2242 		default:
2243 			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2244 			return -EINVAL;
2245 		}
2246 
2247 		if (IS_ERR(svsb->opp_dev))
2248 			return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2249 					     "failed to get OPP device for bank %d\n",
2250 					     idx);
2251 	}
2252 
2253 	return 0;
2254 }
2255 
2256 static struct svs_bank svs_mt8195_banks[] = {
2257 	{
2258 		.pdata = (const struct svs_bank_pdata) {
2259 			.sw_id			= SVSB_SWID_GPU,
2260 			.type			= SVSB_TYPE_LOW,
2261 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2262 			.get_volts		= svs_get_bank_volts_v3,
2263 			.opp_count		= MAX_OPP_ENTRIES,
2264 			.turn_freq_base		= 640000000,
2265 			.volt_step		= 6250,
2266 			.volt_base		= 400000,
2267 			.age_config		= 0x555555,
2268 			.dc_config		= 0x1,
2269 			.vco			= 0x18,
2270 			.chk_shift		= 0x87,
2271 			.int_st			= BIT(0),
2272 			.ctl0			= 0x00540003,
2273 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2274 				{ 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 }
2275 			}
2276 		},
2277 		.mode_support	= SVSB_MODE_INIT02,
2278 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2279 		.freq_base	= 640000000,
2280 		.core_sel	= 0x0fff0100,
2281 		.dvt_fixed	= 0x1,
2282 		.vmax		= 0x38,
2283 		.vmin		= 0x14,
2284 	},
2285 	{
2286 		.pdata = (const struct svs_bank_pdata) {
2287 			.sw_id			= SVSB_SWID_GPU,
2288 			.type			= SVSB_TYPE_HIGH,
2289 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2290 			.get_volts		= svs_get_bank_volts_v3,
2291 			.tzone_name		= "gpu",
2292 			.opp_count		= MAX_OPP_ENTRIES,
2293 			.turn_freq_base		= 640000000,
2294 			.volt_step		= 6250,
2295 			.volt_base		= 400000,
2296 			.age_config		= 0x555555,
2297 			.dc_config		= 0x1,
2298 			.vco			= 0x18,
2299 			.chk_shift		= 0x87,
2300 			.int_st			= BIT(1),
2301 			.ctl0			= 0x00540003,
2302 			.tzone_htemp		= 85000,
2303 			.tzone_htemp_voffset	= 0,
2304 			.tzone_ltemp		= 25000,
2305 			.tzone_ltemp_voffset	= 7,
2306 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2307 				{ 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 }
2308 			},
2309 		},
2310 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2311 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2312 		.freq_base	= 880000000,
2313 		.core_sel	= 0x0fff0101,
2314 		.dvt_fixed	= 0x6,
2315 		.vmax		= 0x38,
2316 		.vmin		= 0x14,
2317 	},
2318 };
2319 
2320 static struct svs_bank svs_mt8192_banks[] = {
2321 	{
2322 		.pdata = (const struct svs_bank_pdata) {
2323 			.sw_id			= SVSB_SWID_GPU,
2324 			.type			= SVSB_TYPE_LOW,
2325 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2326 			.get_volts		= svs_get_bank_volts_v3,
2327 			.tzone_name		= "gpu",
2328 			.opp_count		= MAX_OPP_ENTRIES,
2329 			.turn_freq_base		= 688000000,
2330 			.volt_step		= 6250,
2331 			.volt_base		= 400000,
2332 			.age_config		= 0x555555,
2333 			.dc_config		= 0x1,
2334 			.vco			= 0x18,
2335 			.chk_shift		= 0x87,
2336 			.int_st			= BIT(0),
2337 			.ctl0			= 0x00540003,
2338 			.tzone_htemp		= 85000,
2339 			.tzone_htemp_voffset	= 0,
2340 			.tzone_ltemp		= 25000,
2341 			.tzone_ltemp_voffset	= 7,
2342 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2343 				{ 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 }
2344 			}
2345 		},
2346 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2347 		.mode_support	= SVSB_MODE_INIT02,
2348 		.freq_base	= 688000000,
2349 		.core_sel	= 0x0fff0100,
2350 		.dvt_fixed	= 0x1,
2351 		.vmax		= 0x60,
2352 		.vmin		= 0x1a,
2353 	},
2354 	{
2355 		.pdata = (const struct svs_bank_pdata) {
2356 			.sw_id			= SVSB_SWID_GPU,
2357 			.type			= SVSB_TYPE_HIGH,
2358 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2359 			.get_volts		= svs_get_bank_volts_v3,
2360 			.tzone_name		= "gpu",
2361 			.opp_count		= MAX_OPP_ENTRIES,
2362 			.turn_freq_base		= 688000000,
2363 			.volt_step		= 6250,
2364 			.volt_base		= 400000,
2365 			.age_config		= 0x555555,
2366 			.dc_config		= 0x1,
2367 			.vco			= 0x18,
2368 			.chk_shift		= 0x87,
2369 			.int_st			= BIT(1),
2370 			.ctl0			= 0x00540003,
2371 			.tzone_htemp		= 85000,
2372 			.tzone_htemp_voffset	= 0,
2373 			.tzone_ltemp		= 25000,
2374 			.tzone_ltemp_voffset	= 7,
2375 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2376 				{ 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 }
2377 			}
2378 		},
2379 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2380 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2381 		.freq_base	= 902000000,
2382 		.core_sel	= 0x0fff0101,
2383 		.dvt_fixed	= 0x6,
2384 		.vmax		= 0x60,
2385 		.vmin		= 0x1a,
2386 	},
2387 };
2388 
2389 static struct svs_bank svs_mt8188_banks[] = {
2390 	{
2391 		.pdata = (const struct svs_bank_pdata) {
2392 			.sw_id			= SVSB_SWID_GPU,
2393 			.type			= SVSB_TYPE_LOW,
2394 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2395 			.get_volts		= svs_get_bank_volts_v3,
2396 			.opp_count		= MAX_OPP_ENTRIES,
2397 			.turn_freq_base		= 640000000,
2398 			.volt_step		= 6250,
2399 			.volt_base		= 400000,
2400 			.age_config		= 0x555555,
2401 			.dc_config		= 0x555555,
2402 			.vco			= 0x10,
2403 			.chk_shift		= 0x87,
2404 			.int_st			= BIT(0),
2405 			.ctl0			= 0x00100003,
2406 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2407 				{ 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 }
2408 			}
2409 		},
2410 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2411 		.mode_support	= SVSB_MODE_INIT02,
2412 		.freq_base	= 640000000,
2413 		.core_sel	= 0x0fff0000,
2414 		.dvt_fixed	= 0x1,
2415 		.vmax		= 0x38,
2416 		.vmin		= 0x1c,
2417 	},
2418 	{
2419 		.pdata = (const struct svs_bank_pdata) {
2420 			.sw_id			= SVSB_SWID_GPU,
2421 			.type			= SVSB_TYPE_HIGH,
2422 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2423 			.get_volts		= svs_get_bank_volts_v3,
2424 			.tzone_name		= "gpu",
2425 			.opp_count		= MAX_OPP_ENTRIES,
2426 			.turn_freq_base		= 640000000,
2427 			.volt_step		= 6250,
2428 			.volt_base		= 400000,
2429 			.age_config		= 0x555555,
2430 			.dc_config		= 0x555555,
2431 			.vco			= 0x10,
2432 			.chk_shift		= 0x87,
2433 			.int_st			= BIT(1),
2434 			.ctl0			= 0x00100003,
2435 			.tzone_htemp		= 85000,
2436 			.tzone_htemp_voffset	= 0,
2437 			.tzone_ltemp		= 25000,
2438 			.tzone_ltemp_voffset	= 7,
2439 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2440 				{ 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 }
2441 			}
2442 		},
2443 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2444 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2445 		.freq_base	= 880000000,
2446 		.core_sel	= 0x0fff0001,
2447 		.dvt_fixed	= 0x4,
2448 		.vmax		= 0x38,
2449 		.vmin		= 0x1c,
2450 	},
2451 };
2452 
2453 static struct svs_bank svs_mt8186_banks[] = {
2454 	{
2455 		.pdata = (const struct svs_bank_pdata) {
2456 			.sw_id			= SVSB_SWID_CPU_BIG,
2457 			.type			= SVSB_TYPE_LOW,
2458 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2459 			.get_volts		= svs_get_bank_volts_v3,
2460 			.cpu_id			= 6,
2461 			.opp_count		= MAX_OPP_ENTRIES,
2462 			.turn_freq_base		= 1670000000,
2463 			.volt_step		= 6250,
2464 			.volt_base		= 400000,
2465 			.age_config		= 0x1,
2466 			.dc_config		= 0x1,
2467 			.vco			= 0x10,
2468 			.chk_shift		= 0x87,
2469 			.int_st			= BIT(0),
2470 			.ctl0			= 0x00540003,
2471 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2472 				{ 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 }
2473 			}
2474 		},
2475 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2476 		.volt_od	= 4,
2477 		.mode_support	= SVSB_MODE_INIT02,
2478 		.freq_base	= 1670000000,
2479 		.core_sel	= 0x0fff0100,
2480 		.dvt_fixed	= 0x3,
2481 		.vmax		= 0x59,
2482 		.vmin		= 0x20,
2483 	},
2484 	{
2485 		.pdata = (const struct svs_bank_pdata) {
2486 			.sw_id			= SVSB_SWID_CPU_BIG,
2487 			.type			= SVSB_TYPE_HIGH,
2488 			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2489 			.get_volts		= svs_get_bank_volts_v3,
2490 			.cpu_id			= 6,
2491 			.tzone_name		= "cpu-big",
2492 			.opp_count		= MAX_OPP_ENTRIES,
2493 			.turn_freq_base		= 1670000000,
2494 			.volt_step		= 6250,
2495 			.volt_base		= 400000,
2496 			.age_config		= 0x1,
2497 			.dc_config		= 0x1,
2498 			.vco			= 0x10,
2499 			.chk_shift		= 0x87,
2500 			.int_st			= BIT(1),
2501 			.ctl0			= 0x00540003,
2502 			.tzone_htemp		= 85000,
2503 			.tzone_htemp_voffset	= 8,
2504 			.tzone_ltemp		= 25000,
2505 			.tzone_ltemp_voffset	= 8,
2506 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2507 				{ 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 }
2508 			}
2509 		},
2510 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2511 		.volt_od	= 4,
2512 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2513 		.freq_base	= 2050000000,
2514 		.core_sel	= 0x0fff0101,
2515 		.dvt_fixed	= 0x6,
2516 		.vmax		= 0x73,
2517 		.vmin		= 0x20,
2518 	},
2519 	{
2520 		.pdata = (const struct svs_bank_pdata) {
2521 			.sw_id			= SVSB_SWID_CPU_LITTLE,
2522 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2523 			.get_volts		= svs_get_bank_volts_v2,
2524 			.cpu_id			= 0,
2525 			.tzone_name		= "cpu-little",
2526 			.opp_count		= MAX_OPP_ENTRIES,
2527 			.volt_step		= 6250,
2528 			.volt_base		= 400000,
2529 			.age_config		= 0x1,
2530 			.dc_config		= 0x1,
2531 			.vco			= 0x10,
2532 			.chk_shift		= 0x87,
2533 			.int_st			= BIT(2),
2534 			.ctl0			= 0x3210000f,
2535 			.tzone_htemp		= 85000,
2536 			.tzone_htemp_voffset	= 8,
2537 			.tzone_ltemp		= 25000,
2538 			.tzone_ltemp_voffset	= 8,
2539 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2540 				{ 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 }
2541 			}
2542 		},
2543 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2544 		.volt_od	= 3,
2545 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2546 		.freq_base	= 2000000000,
2547 		.core_sel	= 0x0fff0102,
2548 		.dvt_fixed	= 0x6,
2549 		.vmax		= 0x65,
2550 		.vmin		= 0x20,
2551 	},
2552 	{
2553 		.pdata = (const struct svs_bank_pdata) {
2554 			.sw_id			= SVSB_SWID_CCI,
2555 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2556 			.get_volts		= svs_get_bank_volts_v2,
2557 			.tzone_name		= "cci",
2558 			.opp_count		= MAX_OPP_ENTRIES,
2559 			.volt_step		= 6250,
2560 			.volt_base		= 400000,
2561 			.age_config		= 0x1,
2562 			.dc_config		= 0x1,
2563 			.vco			= 0x10,
2564 			.chk_shift		= 0x87,
2565 			.int_st			= BIT(3),
2566 			.ctl0			= 0x3210000f,
2567 			.tzone_htemp		= 85000,
2568 			.tzone_htemp_voffset	= 8,
2569 			.tzone_ltemp		= 25000,
2570 			.tzone_ltemp_voffset	= 8,
2571 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2572 				{ 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 }
2573 			}
2574 		},
2575 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2576 		.volt_od	= 3,
2577 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2578 		.freq_base	= 1400000000,
2579 		.core_sel	= 0x0fff0103,
2580 		.dvt_fixed	= 0x6,
2581 		.vmax		= 0x65,
2582 		.vmin		= 0x20,
2583 	},
2584 	{
2585 		.pdata = (const struct svs_bank_pdata) {
2586 			.sw_id			= SVSB_SWID_GPU,
2587 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2588 			.get_volts		= svs_get_bank_volts_v2,
2589 			.tzone_name		= "gpu",
2590 			.opp_count		= MAX_OPP_ENTRIES,
2591 			.volt_step		= 6250,
2592 			.volt_base		= 400000,
2593 			.age_config		= 0x555555,
2594 			.dc_config		= 0x1,
2595 			.vco			= 0x10,
2596 			.chk_shift		= 0x87,
2597 			.int_st			= BIT(4),
2598 			.ctl0			= 0x00100003,
2599 			.tzone_htemp		= 85000,
2600 			.tzone_htemp_voffset	= 8,
2601 			.tzone_ltemp		= 25000,
2602 			.tzone_ltemp_voffset	= 7,
2603 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2604 				{ 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 }
2605 			}
2606 		},
2607 		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2608 		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2609 		.freq_base	= 850000000,
2610 		.core_sel	= 0x0fff0104,
2611 		.dvt_fixed	= 0x4,
2612 		.vmax		= 0x58,
2613 		.vmin		= 0x20,
2614 	},
2615 };
2616 
2617 static struct svs_bank svs_mt8183_banks[] = {
2618 	{
2619 		.pdata = (const struct svs_bank_pdata) {
2620 			.sw_id			= SVSB_SWID_CPU_LITTLE,
2621 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2622 			.get_volts		= svs_get_bank_volts_v2,
2623 			.cpu_id			= 0,
2624 			.buck_name		= "proc",
2625 			.opp_count		= MAX_OPP_ENTRIES,
2626 			.vboot			= 0x30,
2627 			.volt_step		= 6250,
2628 			.volt_base		= 500000,
2629 			.age_config		= 0x555555,
2630 			.dc_config		= 0x555555,
2631 			.vco			= 0x10,
2632 			.chk_shift		= 0x77,
2633 			.int_st			= BIT(0),
2634 			.ctl0			= 0x00010001,
2635 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2636 				{ 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 }
2637 			}
2638 		},
2639 		.volt_flags	= SVSB_INIT01_VOLT_INC_ONLY,
2640 		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2641 		.freq_base	= 1989000000,
2642 		.core_sel	= 0x8fff0000,
2643 		.dvt_fixed	= 0x7,
2644 		.vmax		= 0x64,
2645 		.vmin		= 0x18,
2646 
2647 	},
2648 	{
2649 		.pdata = (const struct svs_bank_pdata) {
2650 			.sw_id			= SVSB_SWID_CPU_BIG,
2651 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2652 			.get_volts		= svs_get_bank_volts_v2,
2653 			.cpu_id			= 4,
2654 			.buck_name		= "proc",
2655 			.opp_count		= MAX_OPP_ENTRIES,
2656 			.vboot			= 0x30,
2657 			.volt_step		= 6250,
2658 			.volt_base		= 500000,
2659 			.age_config		= 0x555555,
2660 			.dc_config		= 0x555555,
2661 			.vco			= 0x10,
2662 			.chk_shift		= 0x77,
2663 			.int_st			= BIT(1),
2664 			.ctl0			= 0x00000001,
2665 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2666 				{ 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 }
2667 			}
2668 		},
2669 		.volt_flags	= SVSB_INIT01_VOLT_INC_ONLY,
2670 		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2671 		.freq_base	= 1989000000,
2672 		.core_sel	= 0x8fff0001,
2673 		.dvt_fixed	= 0x7,
2674 		.vmax		= 0x58,
2675 		.vmin		= 0x10,
2676 
2677 	},
2678 	{
2679 		.pdata = (const struct svs_bank_pdata) {
2680 			.sw_id			= SVSB_SWID_CCI,
2681 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2682 			.get_volts		= svs_get_bank_volts_v2,
2683 			.buck_name		= "proc",
2684 			.opp_count		= MAX_OPP_ENTRIES,
2685 			.vboot			= 0x30,
2686 			.volt_step		= 6250,
2687 			.volt_base		= 500000,
2688 			.age_config		= 0x555555,
2689 			.dc_config		= 0x555555,
2690 			.vco			= 0x10,
2691 			.chk_shift		= 0x77,
2692 			.int_st			= BIT(2),
2693 			.ctl0			= 0x00100003,
2694 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2695 				{ 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 }
2696 			}
2697 		},
2698 		.volt_flags	= SVSB_INIT01_VOLT_INC_ONLY,
2699 		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2700 		.freq_base	= 1196000000,
2701 		.core_sel	= 0x8fff0002,
2702 		.dvt_fixed	= 0x7,
2703 		.vmax		= 0x64,
2704 		.vmin		= 0x18,
2705 	},
2706 	{
2707 		.pdata = (const struct svs_bank_pdata) {
2708 			.sw_id			= SVSB_SWID_GPU,
2709 			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2710 			.get_volts		= svs_get_bank_volts_v2,
2711 			.buck_name		= "mali",
2712 			.tzone_name		= "gpu",
2713 			.opp_count		= MAX_OPP_ENTRIES,
2714 			.vboot			= 0x30,
2715 			.volt_step		= 6250,
2716 			.volt_base		= 500000,
2717 			.age_config		= 0x555555,
2718 			.dc_config		= 0x555555,
2719 			.vco			= 0x10,
2720 			.chk_shift		= 0x77,
2721 			.int_st			= BIT(3),
2722 			.ctl0			= 0x00050001,
2723 			.tzone_htemp		= 85000,
2724 			.tzone_htemp_voffset	= 0,
2725 			.tzone_ltemp		= 25000,
2726 			.tzone_ltemp_voffset	= 3,
2727 			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2728 				{ 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 }
2729 			}
2730 		},
2731 		.volt_flags	= SVSB_INIT01_PD_REQ | SVSB_INIT01_VOLT_INC_ONLY,
2732 		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | SVSB_MODE_MON,
2733 		.freq_base	= 900000000,
2734 		.core_sel	= 0x8fff0003,
2735 		.dvt_fixed	= 0x3,
2736 		.vmax		= 0x40,
2737 		.vmin		= 0x14,
2738 	},
2739 };
2740 
2741 static const struct svs_platform_data svs_mt8195_platform_data = {
2742 	.name = "mt8195-svs",
2743 	.banks = svs_mt8195_banks,
2744 	.efuse_parsing = svs_common_parse_efuse,
2745 	.probe = svs_mt8192_platform_probe,
2746 	.regs = svs_regs_v2,
2747 	.bank_max = ARRAY_SIZE(svs_mt8195_banks),
2748 	.ts_coeff = SVSB_TS_COEFF_MT8195,
2749 	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2750 		{ 0, 0 }, { 19, 4 }
2751 	}
2752 };
2753 
2754 static const struct svs_platform_data svs_mt8192_platform_data = {
2755 	.name = "mt8192-svs",
2756 	.banks = svs_mt8192_banks,
2757 	.efuse_parsing = svs_common_parse_efuse,
2758 	.probe = svs_mt8192_platform_probe,
2759 	.regs = svs_regs_v2,
2760 	.bank_max = ARRAY_SIZE(svs_mt8192_banks),
2761 	.ts_coeff = SVSB_TS_COEFF_MT8195,
2762 	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2763 		/* FT_PGM not present */
2764 		{ -1, 0 }, { 19, 4 }
2765 	}
2766 };
2767 
2768 static const struct svs_platform_data svs_mt8188_platform_data = {
2769 	.name = "mt8188-svs",
2770 	.banks = svs_mt8188_banks,
2771 	.efuse_parsing = svs_common_parse_efuse,
2772 	.probe = svs_mt8192_platform_probe,
2773 	.regs = svs_regs_v2,
2774 	.bank_max = ARRAY_SIZE(svs_mt8188_banks),
2775 	.ts_coeff = SVSB_TS_COEFF_MT8195,
2776 	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2777 		/* FT_PGM and VMIN not present */
2778 		{ -1, 0 }, { -1, 0 }
2779 	}
2780 };
2781 
2782 static const struct svs_platform_data svs_mt8186_platform_data = {
2783 	.name = "mt8186-svs",
2784 	.banks = svs_mt8186_banks,
2785 	.efuse_parsing = svs_common_parse_efuse,
2786 	.probe = svs_mt8192_platform_probe,
2787 	.regs = svs_regs_v2,
2788 	.bank_max = ARRAY_SIZE(svs_mt8186_banks),
2789 	.ts_coeff = SVSB_TS_COEFF_MT8186,
2790 	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2791 		/* FT_PGM and VMIN not present */
2792 		{ -1, 0 }, { -1, 0 }
2793 	}
2794 };
2795 
2796 static const struct svs_platform_data svs_mt8183_platform_data = {
2797 	.name = "mt8183-svs",
2798 	.banks = svs_mt8183_banks,
2799 	.efuse_parsing = svs_mt8183_efuse_parsing,
2800 	.probe = svs_mt8183_platform_probe,
2801 	.regs = svs_regs_v2,
2802 	.bank_max = ARRAY_SIZE(svs_mt8183_banks),
2803 	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2804 		/* VMIN not present */
2805 		{ 0, 4 }, { -1, 0 }
2806 	}
2807 };
2808 
2809 static const struct of_device_id svs_of_match[] = {
2810 	{ .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data },
2811 	{ .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data },
2812 	{ .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data },
2813 	{ .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data },
2814 	{ .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data },
2815 	{ /* sentinel */ }
2816 };
2817 MODULE_DEVICE_TABLE(of, svs_of_match);
2818 
svs_probe(struct platform_device * pdev)2819 static int svs_probe(struct platform_device *pdev)
2820 {
2821 	struct svs_platform *svsp;
2822 	const struct svs_platform_data *svsp_data;
2823 	int ret, svsp_irq;
2824 
2825 	svsp_data = of_device_get_match_data(&pdev->dev);
2826 
2827 	svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
2828 	if (!svsp)
2829 		return -ENOMEM;
2830 
2831 	svsp->dev = &pdev->dev;
2832 	svsp->banks = svsp_data->banks;
2833 	svsp->regs = svsp_data->regs;
2834 	svsp->bank_max = svsp_data->bank_max;
2835 	svsp->ts_coeff = svsp_data->ts_coeff;
2836 
2837 	ret = svsp_data->probe(svsp);
2838 	if (ret)
2839 		return ret;
2840 
2841 	ret = svs_get_efuse_data(svsp, "svs-calibration-data",
2842 				 &svsp->efuse, &svsp->efuse_max);
2843 	if (ret)
2844 		return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n");
2845 
2846 	ret = svs_get_efuse_data(svsp, "t-calibration-data",
2847 				 &svsp->tefuse, &svsp->tefuse_max);
2848 	if (ret) {
2849 		dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n");
2850 		goto svs_probe_free_efuse;
2851 	}
2852 
2853 	if (!svsp_data->efuse_parsing(svsp, svsp_data)) {
2854 		ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n");
2855 		goto svs_probe_free_tefuse;
2856 	}
2857 
2858 	ret = svs_bank_resource_setup(svsp);
2859 	if (ret) {
2860 		dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n");
2861 		goto svs_probe_free_tefuse;
2862 	}
2863 
2864 	svsp_irq = platform_get_irq(pdev, 0);
2865 	if (svsp_irq < 0) {
2866 		ret = svsp_irq;
2867 		goto svs_probe_free_tefuse;
2868 	}
2869 
2870 	svsp->main_clk = devm_clk_get(svsp->dev, "main");
2871 	if (IS_ERR(svsp->main_clk)) {
2872 		ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk),
2873 				    "failed to get clock\n");
2874 		goto svs_probe_free_tefuse;
2875 	}
2876 
2877 	ret = clk_prepare_enable(svsp->main_clk);
2878 	if (ret) {
2879 		dev_err_probe(svsp->dev, ret, "cannot enable main clk\n");
2880 		goto svs_probe_free_tefuse;
2881 	}
2882 
2883 	svsp->base = of_iomap(svsp->dev->of_node, 0);
2884 	if (IS_ERR_OR_NULL(svsp->base)) {
2885 		ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n");
2886 		goto svs_probe_clk_disable;
2887 	}
2888 
2889 	ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
2890 					IRQF_ONESHOT, svsp_data->name, svsp);
2891 	if (ret) {
2892 		dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq);
2893 		goto svs_probe_iounmap;
2894 	}
2895 
2896 	ret = svs_start(svsp);
2897 	if (ret) {
2898 		dev_err_probe(svsp->dev, ret, "svs start fail\n");
2899 		goto svs_probe_iounmap;
2900 	}
2901 
2902 #ifdef CONFIG_DEBUG_FS
2903 	ret = svs_create_debug_cmds(svsp);
2904 	if (ret) {
2905 		dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n");
2906 		goto svs_probe_iounmap;
2907 	}
2908 #endif
2909 
2910 	return 0;
2911 
2912 svs_probe_iounmap:
2913 	iounmap(svsp->base);
2914 svs_probe_clk_disable:
2915 	clk_disable_unprepare(svsp->main_clk);
2916 svs_probe_free_tefuse:
2917 	kfree(svsp->tefuse);
2918 svs_probe_free_efuse:
2919 	kfree(svsp->efuse);
2920 	return ret;
2921 }
2922 
2923 static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume);
2924 
2925 static struct platform_driver svs_driver = {
2926 	.probe	= svs_probe,
2927 	.driver	= {
2928 		.name		= "mtk-svs",
2929 		.pm		= &svs_pm_ops,
2930 		.of_match_table	= svs_of_match,
2931 	},
2932 };
2933 
2934 module_platform_driver(svs_driver);
2935 
2936 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>");
2937 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
2938 MODULE_DESCRIPTION("MediaTek SVS driver");
2939 MODULE_LICENSE("GPL");
2940