xref: /freebsd/sys/dev/superio/superio.c (revision 2520675d3f0ef9039049fd67481f013b36f250ee)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2019 Andriy Gapon
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/conf.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/mutex.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/proc.h>
38 #include <sys/rman.h>
39 #include <sys/sbuf.h>
40 #include <sys/time.h>
41 
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <machine/stdarg.h>
45 
46 #include <isa/isavar.h>
47 
48 #include <dev/superio/superio.h>
49 #include <dev/superio/superio_io.h>
50 
51 #include "isa_if.h"
52 
53 typedef void (*sio_conf_enter_f)(struct resource*, uint16_t);
54 typedef void (*sio_conf_exit_f)(struct resource*, uint16_t);
55 
56 struct sio_conf_methods {
57 	sio_conf_enter_f	enter;
58 	sio_conf_exit_f		exit;
59 	superio_vendor_t	vendor;
60 };
61 
62 struct sio_device {
63 	uint8_t			ldn;
64 	superio_dev_type_t	type;
65 };
66 
67 struct superio_devinfo {
68 	STAILQ_ENTRY(superio_devinfo) link;
69 	struct resource_list	resources;
70 	device_t		dev;
71 	uint8_t			ldn;
72 	superio_dev_type_t	type;
73 	uint16_t		iobase;
74 	uint16_t		iobase2;
75 	uint8_t			irq;
76 	uint8_t			dma;
77 };
78 
79 struct siosc {
80 	struct mtx			conf_lock;
81 	STAILQ_HEAD(, superio_devinfo)	devlist;
82 	struct resource*		io_res;
83 	struct cdev			*chardev;
84 	int				io_rid;
85 	uint16_t			io_port;
86 	const struct sio_conf_methods	*methods;
87 	const struct sio_device		*known_devices;
88 	superio_vendor_t		vendor;
89 	uint16_t			devid;
90 	uint8_t				revid;
91 	int				extid;
92 	uint8_t				current_ldn;
93 	uint8_t				ldn_reg;
94 	uint8_t				enable_reg;
95 };
96 
97 static	d_ioctl_t	superio_ioctl;
98 
99 static struct cdevsw superio_cdevsw = {
100 	.d_version =	D_VERSION,
101 	.d_ioctl =	superio_ioctl,
102 	.d_name =	"superio",
103 };
104 
105 #define NUMPORTS	2
106 
107 static uint8_t
sio_read(struct resource * res,uint8_t reg)108 sio_read(struct resource* res, uint8_t reg)
109 {
110 	bus_write_1(res, 0, reg);
111 	return (bus_read_1(res, 1));
112 }
113 
114 /* Read a word from two one-byte registers, big endian. */
115 static uint16_t
sio_readw(struct resource * res,uint8_t reg)116 sio_readw(struct resource* res, uint8_t reg)
117 {
118 	uint16_t v;
119 
120 	v = sio_read(res, reg);
121 	v <<= 8;
122 	v |= sio_read(res, reg + 1);
123 	return (v);
124 }
125 
126 static void
sio_write(struct resource * res,uint8_t reg,uint8_t val)127 sio_write(struct resource* res, uint8_t reg, uint8_t val)
128 {
129 	bus_write_1(res, 0, reg);
130 	bus_write_1(res, 1, val);
131 }
132 
133 static void
sio_ldn_select(struct siosc * sc,uint8_t ldn)134 sio_ldn_select(struct siosc *sc, uint8_t ldn)
135 {
136 	mtx_assert(&sc->conf_lock, MA_OWNED);
137 	if (ldn == sc->current_ldn)
138 		return;
139 	sio_write(sc->io_res, sc->ldn_reg, ldn);
140 	sc->current_ldn = ldn;
141 }
142 
143 static uint8_t
sio_ldn_read(struct siosc * sc,uint8_t ldn,uint8_t reg)144 sio_ldn_read(struct siosc *sc, uint8_t ldn, uint8_t reg)
145 {
146 	mtx_assert(&sc->conf_lock, MA_OWNED);
147 	if (reg >= sc->enable_reg) {
148 		sio_ldn_select(sc, ldn);
149 		KASSERT(sc->current_ldn == ldn, ("sio_ldn_select failed"));
150 	}
151 	return (sio_read(sc->io_res, reg));
152 }
153 
154 static uint16_t
sio_ldn_readw(struct siosc * sc,uint8_t ldn,uint8_t reg)155 sio_ldn_readw(struct siosc *sc, uint8_t ldn, uint8_t reg)
156 {
157 	mtx_assert(&sc->conf_lock, MA_OWNED);
158 	if (reg >= sc->enable_reg) {
159 		sio_ldn_select(sc, ldn);
160 		KASSERT(sc->current_ldn == ldn, ("sio_ldn_select failed"));
161 	}
162 	return (sio_readw(sc->io_res, reg));
163 }
164 
165 static void
sio_ldn_write(struct siosc * sc,uint8_t ldn,uint8_t reg,uint8_t val)166 sio_ldn_write(struct siosc *sc, uint8_t ldn, uint8_t reg, uint8_t val)
167 {
168 	mtx_assert(&sc->conf_lock, MA_OWNED);
169 	if (reg <= sc->ldn_reg) {
170 		printf("ignored attempt to write special register 0x%x\n", reg);
171 		return;
172 	}
173 	sio_ldn_select(sc, ldn);
174 	KASSERT(sc->current_ldn == ldn, ("sio_ldn_select failed"));
175 	sio_write(sc->io_res, reg, val);
176 }
177 
178 static void
sio_conf_enter(struct siosc * sc)179 sio_conf_enter(struct siosc *sc)
180 {
181 	mtx_lock(&sc->conf_lock);
182 	sc->methods->enter(sc->io_res, sc->io_port);
183 }
184 
185 static void
sio_conf_exit(struct siosc * sc)186 sio_conf_exit(struct siosc *sc)
187 {
188 	sc->methods->exit(sc->io_res, sc->io_port);
189 	sc->current_ldn = 0xff;
190 	mtx_unlock(&sc->conf_lock);
191 }
192 
193 static void
ite_conf_enter(struct resource * res,uint16_t port)194 ite_conf_enter(struct resource* res, uint16_t port)
195 {
196 	bus_write_1(res, 0, 0x87);
197 	bus_write_1(res, 0, 0x01);
198 	bus_write_1(res, 0, 0x55);
199 	bus_write_1(res, 0, port == 0x2e ? 0x55 : 0xaa);
200 }
201 
202 static void
ite_conf_exit(struct resource * res,uint16_t port)203 ite_conf_exit(struct resource* res, uint16_t port)
204 {
205 	sio_write(res, 0x02, 0x02);
206 }
207 
208 static const struct sio_conf_methods ite_conf_methods = {
209 	.enter = ite_conf_enter,
210 	.exit = ite_conf_exit,
211 	.vendor = SUPERIO_VENDOR_ITE
212 };
213 
214 static void
nvt_conf_enter(struct resource * res,uint16_t port)215 nvt_conf_enter(struct resource* res, uint16_t port)
216 {
217 	bus_write_1(res, 0, 0x87);
218 	bus_write_1(res, 0, 0x87);
219 }
220 
221 static void
nvt_conf_exit(struct resource * res,uint16_t port)222 nvt_conf_exit(struct resource* res, uint16_t port)
223 {
224 	bus_write_1(res, 0, 0xaa);
225 }
226 
227 static const struct sio_conf_methods nvt_conf_methods = {
228 	.enter = nvt_conf_enter,
229 	.exit = nvt_conf_exit,
230 	.vendor = SUPERIO_VENDOR_NUVOTON
231 };
232 
233 static void
fintek_conf_enter(struct resource * res,uint16_t port)234 fintek_conf_enter(struct resource* res, uint16_t port)
235 {
236 	bus_write_1(res, 0, 0x87);
237 	bus_write_1(res, 0, 0x87);
238 }
239 
240 static void
fintek_conf_exit(struct resource * res,uint16_t port)241 fintek_conf_exit(struct resource* res, uint16_t port)
242 {
243 	bus_write_1(res, 0, 0xaa);
244 }
245 
246 static const struct sio_conf_methods fintek_conf_methods = {
247 	.enter = fintek_conf_enter,
248 	.exit = fintek_conf_exit,
249 	.vendor = SUPERIO_VENDOR_FINTEK
250 };
251 
252 static const struct sio_conf_methods * const methods_table[] = {
253 	&ite_conf_methods,
254 	&nvt_conf_methods,
255 	&fintek_conf_methods,
256 	NULL
257 };
258 
259 static const uint16_t ports_table[] = {
260 	0x2e, 0x4e, 0
261 };
262 
263 const struct sio_device ite_devices[] = {
264 	{ .ldn = 4, .type = SUPERIO_DEV_HWM },
265 	{ .ldn = 7, .type = SUPERIO_DEV_WDT },
266 	{ .type = SUPERIO_DEV_NONE },
267 };
268 
269 const struct sio_device w83627_devices[] = {
270 	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
271 	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },
272 	{ .type = SUPERIO_DEV_NONE },
273 };
274 
275 const struct sio_device nvt_devices[] = {
276 	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
277 	{ .type = SUPERIO_DEV_NONE },
278 };
279 
280 const struct sio_device nct5104_devices[] = {
281 	{ .ldn = 7, .type = SUPERIO_DEV_GPIO },
282 	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
283 	{ .ldn = 15, .type = SUPERIO_DEV_GPIO },
284 	{ .type = SUPERIO_DEV_NONE },
285 };
286 
287 const struct sio_device nct5585_devices[] = {
288 	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },
289 	{ .type = SUPERIO_DEV_NONE },
290 };
291 
292 const struct sio_device nct611x_devices[] = {
293 	{ .ldn = 0x7, .type = SUPERIO_DEV_GPIO },
294 	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
295 	{ .type = SUPERIO_DEV_NONE },
296 };
297 
298 const struct sio_device nct67xx_devices[] = {
299 	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
300 	{ .ldn = 0x9, .type = SUPERIO_DEV_GPIO },
301 	{ .ldn = 0xb, .type = SUPERIO_DEV_HWM },
302 	{ .type = SUPERIO_DEV_NONE },
303 };
304 
305 const struct sio_device fintek_devices[] = {
306 	{ .ldn = 6, .type = SUPERIO_DEV_GPIO },
307 	{ .ldn = 7, .type = SUPERIO_DEV_WDT },
308 	{ .type = SUPERIO_DEV_NONE },
309 };
310 
311 static const struct {
312 	superio_vendor_t	vendor;
313 	uint16_t		devid;
314 	uint16_t		mask;
315 	int			extid; /* Extra ID: used to handle conflicting devid. */
316 	const char		*descr;
317 	const struct sio_device	*devices;
318 } superio_table[] = {
319 	{
320 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8613,
321 		.devices = ite_devices,
322 	},
323 	{
324 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8712,
325 		.devices = ite_devices,
326 	},
327 	{
328 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8716,
329 		.devices = ite_devices,
330 	},
331 	{
332 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8718,
333 		.devices = ite_devices,
334 	},
335 	{
336 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8720,
337 		.devices = ite_devices,
338 	},
339 	{
340 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8721,
341 		.devices = ite_devices,
342 	},
343 	{
344 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8726,
345 		.devices = ite_devices,
346 	},
347 	{
348 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8728,
349 		.devices = ite_devices,
350 	},
351 	{
352 		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8771,
353 		.devices = ite_devices,
354 	},
355 	{
356 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x1061, .mask = 0x00,
357 		.descr	= "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. A)",
358 		.devices = nct5104_devices,
359 	},
360 	{
361 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5200, .mask = 0xff,
362 		.descr = "Winbond 83627HF/F/HG/G",
363 		.devices = nvt_devices,
364 	},
365 	{
366 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5900, .mask = 0xff,
367 		.descr = "Winbond 83627S",
368 		.devices = nvt_devices,
369 	},
370 	{
371 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6000, .mask = 0xff,
372 		.descr = "Winbond 83697HF",
373 		.devices = nvt_devices,
374 	},
375 	{
376 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6800, .mask = 0xff,
377 		.descr = "Winbond 83697UG",
378 		.devices = nvt_devices,
379 	},
380 	{
381 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x7000, .mask = 0xff,
382 		.descr = "Winbond 83637HF",
383 		.devices = nvt_devices,
384 	},
385 	{
386 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8200, .mask = 0xff,
387 		.descr = "Winbond 83627THF",
388 		.devices = nvt_devices,
389 	},
390 	{
391 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8500, .mask = 0xff,
392 		.descr = "Winbond 83687THF",
393 		.devices = nvt_devices,
394 	},
395 	{
396 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8800, .mask = 0xff,
397 		.descr = "Winbond 83627EHF",
398 		.devices = nvt_devices,
399 	},
400 	{
401 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa000, .mask = 0xff,
402 		.descr = "Winbond 83627DHG",
403 		.devices = w83627_devices,
404 	},
405 	{
406 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa200, .mask = 0xff,
407 		.descr = "Winbond 83627UHG",
408 		.devices = nvt_devices,
409 	},
410 	{
411 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa500, .mask = 0xff,
412 		.descr = "Winbond 83667HG",
413 		.devices = nvt_devices,
414 	},
415 	{
416 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb000, .mask = 0xff,
417 		.descr = "Winbond 83627DHG-P",
418 		.devices = nvt_devices,
419 	},
420 	{
421 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb300, .mask = 0xff,
422 		.descr = "Winbond 83667HG-B",
423 		.devices = nvt_devices,
424 	},
425 	{
426 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb400, .mask = 0xff,
427 		.descr = "Nuvoton NCT6775",
428 		.devices = nvt_devices,
429 	},
430 	{
431 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc300, .mask = 0xff,
432 		.descr = "Nuvoton NCT6776",
433 		.devices = nvt_devices,
434 	},
435 	{
436 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc400, .mask = 0xff,
437 		.descr = "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. B+)",
438 		.devices = nct5104_devices,
439 	},
440 	{
441 		.vendor  = SUPERIO_VENDOR_NUVOTON, .devid = 0xc500, .mask = 0xff,
442 		.descr   = "Nuvoton NCT6779D",
443 		.devices = nct67xx_devices,
444 	},
445 	{
446 		.vendor  = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 1,
447 		.descr   = "Nuvoton NCT6796D-E",
448 		.devices = nct67xx_devices,
449 	},
450 	{
451 		.vendor  = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 2,
452 		.descr   = "Nuvoton NCT5585D",
453 		.devices = nct5585_devices,
454 	},
455 	{
456 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc800, .mask = 0xff,
457 		.descr = "Nuvoton NCT6791",
458 		.devices = nvt_devices,
459 	},
460 	{
461 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc900, .mask = 0xff,
462 		.descr = "Nuvoton NCT6792",
463 		.devices = nvt_devices,
464 	},
465 	{
466 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd100, .mask = 0xff,
467 		.descr = "Nuvoton NCT6793",
468 		.devices = nvt_devices,
469 	},
470 	{
471 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd200, .mask = 0xff,
472 		.descr = "Nuvoton NCT6112D/NCT6114D/NCT6116D",
473 		.devices = nct611x_devices,
474 	},
475 	{
476 		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd300, .mask = 0xff,
477 		.descr = "Nuvoton NCT6795",
478 		.devices = nvt_devices,
479 	},
480 	{
481 		.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x1210, .mask = 0xff,
482 		.descr = "Fintek F81803",
483 		.devices = fintek_devices,
484 	},
485 	{
486 		.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x0704,
487 		.descr = "Fintek F81865",
488 		.devices = fintek_devices,
489 	},
490 	{ 0, 0 }
491 };
492 
493 static const char *
devtype_to_str(superio_dev_type_t type)494 devtype_to_str(superio_dev_type_t type)
495 {
496 	switch (type) {
497 	case SUPERIO_DEV_NONE:
498 		return ("none");
499 	case SUPERIO_DEV_HWM:
500 		return ("HWM");
501 	case SUPERIO_DEV_WDT:
502 		return ("WDT");
503 	case SUPERIO_DEV_GPIO:
504 		return ("GPIO");
505 	case SUPERIO_DEV_MAX:
506 		return ("invalid");
507 	}
508 	return ("invalid");
509 }
510 
511 static int
superio_detect(device_t dev,bool claim,struct siosc * sc)512 superio_detect(device_t dev, bool claim, struct siosc *sc)
513 {
514 	struct resource *res;
515 	rman_res_t port;
516 	rman_res_t count;
517 	uint16_t devid;
518 	uint8_t revid;
519 	int error;
520 	int rid;
521 	int i, m;
522 	int prefer;
523 
524 	error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, &count);
525 	if (error != 0)
526 		return (error);
527 	if (port > UINT16_MAX || count < NUMPORTS) {
528 		device_printf(dev, "unexpected I/O range size\n");
529 		return (ENXIO);
530 	}
531 
532 	/*
533 	 * Make a temporary resource reservation for hardware probing.
534 	 * If we can't get the resources we need then
535 	 * we need to abort.  Possibly this indicates
536 	 * the resources were used by another device
537 	 * in which case the probe would have failed anyhow.
538 	 */
539 	rid = 0;
540 	res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
541 	if (res == NULL) {
542 		if (claim)
543 			device_printf(dev, "failed to allocate I/O resource\n");
544 		return (ENXIO);
545 	}
546 
547 	prefer = 0;
548 	resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer", &prefer);
549 	if (bootverbose && prefer > 0)
550 		device_printf(dev, "prefer extid %d\n", prefer);
551 
552 	for (m = 0; methods_table[m] != NULL; m++) {
553 		methods_table[m]->enter(res, port);
554 		if (methods_table[m]->vendor == SUPERIO_VENDOR_ITE) {
555 			devid = sio_readw(res, 0x20);
556 			revid = sio_read(res, 0x22);
557 		} else if (methods_table[m]->vendor == SUPERIO_VENDOR_NUVOTON) {
558 			devid = sio_read(res, 0x20);
559 			revid = sio_read(res, 0x21);
560 			devid = (devid << 8) | revid;
561 		} else if (methods_table[m]->vendor == SUPERIO_VENDOR_FINTEK) {
562 			devid = sio_read(res, 0x20);
563 			revid = sio_read(res, 0x21);
564 			devid = (devid << 8) | revid;
565 		} else {
566 			continue;
567 		}
568 		methods_table[m]->exit(res, port);
569 		for (i = 0; superio_table[i].vendor != 0; i++) {
570 			uint16_t mask;
571 
572 			mask = superio_table[i].mask;
573 			if (superio_table[i].vendor !=
574 			    methods_table[m]->vendor)
575 				continue;
576 			if ((superio_table[i].devid & ~mask) != (devid & ~mask))
577 				continue;
578 			if (prefer > 0 && prefer != superio_table[i].extid)
579 				continue;
580 			break;
581 		}
582 
583 		/* Found a matching SuperIO entry. */
584 		if (superio_table[i].vendor != 0)
585 			break;
586 	}
587 
588 	if (methods_table[m] == NULL)
589 		error = ENXIO;
590 	else
591 		error = 0;
592 	if (!claim || error != 0) {
593 		bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
594 		return (error);
595 	}
596 
597 	sc->methods = methods_table[m];
598 	sc->vendor = sc->methods->vendor;
599 	sc->known_devices = superio_table[i].devices;
600 	sc->io_res = res;
601 	sc->io_rid = rid;
602 	sc->io_port = port;
603 	sc->devid = devid;
604 	sc->revid = revid;
605 	sc->extid = superio_table[i].extid;
606 
607 	KASSERT(sc->vendor == SUPERIO_VENDOR_ITE ||
608 	    sc->vendor == SUPERIO_VENDOR_NUVOTON ||
609 	    sc->vendor == SUPERIO_VENDOR_FINTEK,
610 	    ("Only ITE, Nuvoton and Fintek SuperIO-s are supported"));
611 	sc->ldn_reg = 0x07;
612 	sc->enable_reg = 0x30;	/* FIXME enable_reg not used by nctgpio(4). */
613 	sc->current_ldn = 0xff;	/* no device should have this */
614 
615 	if (superio_table[i].descr != NULL) {
616 		device_set_desc(dev, superio_table[i].descr);
617 	} else if (sc->vendor == SUPERIO_VENDOR_ITE) {
618 		device_set_descf(dev,
619 		    "ITE IT%4x SuperIO (revision 0x%02x)",
620 		    sc->devid, sc->revid);
621 	}
622 	return (0);
623 }
624 
625 static void
superio_identify(driver_t * driver,device_t parent)626 superio_identify(driver_t *driver, device_t parent)
627 {
628 	device_t	child;
629 	int i;
630 
631 	/*
632 	 * Don't create child devices if any already exist.
633 	 * Those could be created via isa hints or if this
634 	 * driver is loaded, unloaded and then loaded again.
635 	 */
636 	if (device_find_child(parent, "superio", -1)) {
637 		if (bootverbose)
638 			printf("superio: device(s) already created\n");
639 		return;
640 	}
641 
642 	/*
643 	 * Create a child for each candidate port.
644 	 * It would be nice if we could somehow clean up those
645 	 * that this driver fails to probe.
646 	 */
647 	for (i = 0; ports_table[i] != 0; i++) {
648 		child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE,
649 		    "superio", -1);
650 		if (child == NULL) {
651 			device_printf(parent, "failed to add superio child\n");
652 			continue;
653 		}
654 		bus_set_resource(child, SYS_RES_IOPORT,	0, ports_table[i], 2);
655 		if (superio_detect(child, false, NULL) != 0)
656 			device_delete_child(parent, child);
657 	}
658 }
659 
660 static int
superio_probe(device_t dev)661 superio_probe(device_t dev)
662 {
663 	struct siosc *sc;
664 	int error;
665 
666 	/* Make sure we do not claim some ISA PNP device. */
667 	if (isa_get_logicalid(dev) != 0)
668 		return (ENXIO);
669 
670 	/*
671 	 * XXX We can populate the softc now only because we return
672 	 * BUS_PROBE_SPECIFIC
673 	 */
674 	sc = device_get_softc(dev);
675 	error = superio_detect(dev, true, sc);
676 	if (error != 0)
677 		return (error);
678 	return (BUS_PROBE_SPECIFIC);
679 }
680 
681 static void
superio_add_known_child(device_t dev,superio_dev_type_t type,uint8_t ldn)682 superio_add_known_child(device_t dev, superio_dev_type_t type, uint8_t ldn)
683 {
684 	struct siosc *sc = device_get_softc(dev);
685 	struct superio_devinfo *dinfo;
686 	device_t child;
687 
688 	child = BUS_ADD_CHILD(dev, 0, NULL, DEVICE_UNIT_ANY);
689 	if (child == NULL) {
690 		device_printf(dev, "failed to add child for ldn %d, type %s\n",
691 		    ldn, devtype_to_str(type));
692 		return;
693 	}
694 	dinfo = device_get_ivars(child);
695 	dinfo->ldn = ldn;
696 	dinfo->type = type;
697 	sio_conf_enter(sc);
698 	dinfo->iobase = sio_ldn_readw(sc, ldn, 0x60);
699 	dinfo->iobase2 = sio_ldn_readw(sc, ldn, 0x62);
700 	dinfo->irq = sio_ldn_readw(sc, ldn, 0x70);
701 	dinfo->dma = sio_ldn_readw(sc, ldn, 0x74);
702 	sio_conf_exit(sc);
703 	STAILQ_INSERT_TAIL(&sc->devlist, dinfo, link);
704 }
705 
706 static int
superio_attach(device_t dev)707 superio_attach(device_t dev)
708 {
709 	struct siosc *sc = device_get_softc(dev);
710 	int i;
711 
712 	mtx_init(&sc->conf_lock, device_get_nameunit(dev), "superio", MTX_DEF);
713 	STAILQ_INIT(&sc->devlist);
714 
715 	for (i = 0; sc->known_devices[i].type != SUPERIO_DEV_NONE; i++) {
716 		superio_add_known_child(dev, sc->known_devices[i].type,
717 		    sc->known_devices[i].ldn);
718 	}
719 
720 	bus_generic_probe(dev);
721 	bus_generic_attach(dev);
722 
723 	sc->chardev = make_dev(&superio_cdevsw, device_get_unit(dev),
724 	    UID_ROOT, GID_WHEEL, 0600, "superio%d", device_get_unit(dev));
725 	if (sc->chardev == NULL)
726 		device_printf(dev, "failed to create character device\n");
727 	else
728 		sc->chardev->si_drv1 = sc;
729 	return (0);
730 }
731 
732 static int
superio_detach(device_t dev)733 superio_detach(device_t dev)
734 {
735 	struct siosc *sc = device_get_softc(dev);
736 	int error;
737 
738 	error = bus_generic_detach(dev);
739 	if (error != 0)
740 		return (error);
741 	if (sc->chardev != NULL)
742 		destroy_dev(sc->chardev);
743 	device_delete_children(dev);
744 	bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, sc->io_res);
745 	mtx_destroy(&sc->conf_lock);
746 	return (0);
747 }
748 
749 static device_t
superio_add_child(device_t dev,u_int order,const char * name,int unit)750 superio_add_child(device_t dev, u_int order, const char *name, int unit)
751 {
752 	struct superio_devinfo *dinfo;
753 	device_t child;
754 
755 	child = device_add_child_ordered(dev, order, name, unit);
756 	if (child == NULL)
757 		return (NULL);
758 	dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_NOWAIT | M_ZERO);
759 	if (dinfo == NULL) {
760 		device_delete_child(dev, child);
761 		return (NULL);
762 	}
763 	dinfo->ldn = 0xff;
764 	dinfo->type = SUPERIO_DEV_NONE;
765 	dinfo->dev = child;
766 	resource_list_init(&dinfo->resources);
767 	device_set_ivars(child, dinfo);
768 	return (child);
769 }
770 
771 static void
superio_child_deleted(device_t dev,device_t child)772 superio_child_deleted(device_t dev, device_t child)
773 {
774 	struct superio_devinfo *dinfo;
775 
776 	dinfo = device_get_ivars(child);
777 	if (dinfo == NULL)
778 		return;
779 	resource_list_free(&dinfo->resources);
780 	free(dinfo, M_DEVBUF);
781 }
782 
783 static int
superio_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)784 superio_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
785 {
786 	struct superio_devinfo *dinfo;
787 
788 	dinfo = device_get_ivars(child);
789 	switch (which) {
790 	case SUPERIO_IVAR_LDN:
791 		*result = dinfo->ldn;
792 		break;
793 	case SUPERIO_IVAR_TYPE:
794 		*result = dinfo->type;
795 		break;
796 	case SUPERIO_IVAR_IOBASE:
797 		*result = dinfo->iobase;
798 		break;
799 	case SUPERIO_IVAR_IOBASE2:
800 		*result = dinfo->iobase2;
801 		break;
802 	case SUPERIO_IVAR_IRQ:
803 		*result = dinfo->irq;
804 		break;
805 	case SUPERIO_IVAR_DMA:
806 		*result = dinfo->dma;
807 		break;
808 	default:
809 		return (ENOENT);
810 	}
811 	return (0);
812 }
813 
814 static int
superio_write_ivar(device_t dev,device_t child,int which,uintptr_t value)815 superio_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
816 {
817 
818 	switch (which) {
819 	case SUPERIO_IVAR_LDN:
820 	case SUPERIO_IVAR_TYPE:
821 	case SUPERIO_IVAR_IOBASE:
822 	case SUPERIO_IVAR_IOBASE2:
823 	case SUPERIO_IVAR_IRQ:
824 	case SUPERIO_IVAR_DMA:
825 		return (EINVAL);
826 	default:
827 		return (ENOENT);
828 	}
829 }
830 
831 static struct resource_list *
superio_get_resource_list(device_t dev,device_t child)832 superio_get_resource_list(device_t dev, device_t child)
833 {
834 	struct superio_devinfo *dinfo = device_get_ivars(child);
835 
836 	return (&dinfo->resources);
837 }
838 
839 static int
superio_printf(struct superio_devinfo * dinfo,const char * fmt,...)840 superio_printf(struct superio_devinfo *dinfo, const char *fmt, ...)
841 {
842 	va_list ap;
843 	int retval;
844 
845 	retval = printf("superio:%s@ldn%0x2x: ",
846 	    devtype_to_str(dinfo->type), dinfo->ldn);
847 	va_start(ap, fmt);
848 	retval += vprintf(fmt, ap);
849 	va_end(ap);
850 	return (retval);
851 }
852 
853 static void
superio_child_detached(device_t dev,device_t child)854 superio_child_detached(device_t dev, device_t child)
855 {
856 	struct superio_devinfo *dinfo;
857 	struct resource_list *rl;
858 
859 	dinfo = device_get_ivars(child);
860 	rl = &dinfo->resources;
861 
862 	if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
863 		superio_printf(dinfo, "Device leaked IRQ resources\n");
864 	if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
865 		superio_printf(dinfo, "Device leaked memory resources\n");
866 	if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
867 		superio_printf(dinfo, "Device leaked I/O resources\n");
868 }
869 
870 static int
superio_child_location(device_t parent,device_t child,struct sbuf * sb)871 superio_child_location(device_t parent, device_t child, struct sbuf *sb)
872 {
873 	uint8_t ldn;
874 
875 	ldn = superio_get_ldn(child);
876 	sbuf_printf(sb, "ldn=0x%02x", ldn);
877 	return (0);
878 }
879 
880 static int
superio_child_pnp(device_t parent,device_t child,struct sbuf * sb)881 superio_child_pnp(device_t parent, device_t child, struct sbuf *sb)
882 {
883 	superio_dev_type_t type;
884 
885 	type = superio_get_type(child);
886 	sbuf_printf(sb, "type=%s", devtype_to_str(type));
887 	return (0);
888 }
889 
890 static int
superio_print_child(device_t parent,device_t child)891 superio_print_child(device_t parent, device_t child)
892 {
893 	superio_dev_type_t type;
894 	uint8_t ldn;
895 	int retval;
896 
897 	ldn = superio_get_ldn(child);
898 	type = superio_get_type(child);
899 
900 	retval = bus_print_child_header(parent, child);
901 	retval += printf(" at %s ldn 0x%02x", devtype_to_str(type), ldn);
902 	retval += bus_print_child_footer(parent, child);
903 
904 	return (retval);
905 }
906 
907 superio_vendor_t
superio_vendor(device_t dev)908 superio_vendor(device_t dev)
909 {
910 	device_t sio_dev = device_get_parent(dev);
911 	struct siosc *sc = device_get_softc(sio_dev);
912 
913 	return (sc->vendor);
914 }
915 
916 uint16_t
superio_devid(device_t dev)917 superio_devid(device_t dev)
918 {
919 	device_t sio_dev = device_get_parent(dev);
920 	struct siosc *sc = device_get_softc(sio_dev);
921 
922 	return (sc->devid);
923 }
924 
925 uint8_t
superio_revid(device_t dev)926 superio_revid(device_t dev)
927 {
928 	device_t sio_dev = device_get_parent(dev);
929 	struct siosc *sc = device_get_softc(sio_dev);
930 
931 	return (sc->revid);
932 }
933 
934 int
superio_extid(device_t dev)935 superio_extid(device_t dev)
936 {
937 	device_t sio_dev = device_get_parent(dev);
938 	struct siosc *sc = device_get_softc(sio_dev);
939 
940 	return (sc->extid);
941 }
942 
943 uint8_t
superio_ldn_read(device_t dev,uint8_t ldn,uint8_t reg)944 superio_ldn_read(device_t dev, uint8_t ldn, uint8_t reg)
945 {
946 	device_t      sio_dev = device_get_parent(dev);
947 	struct siosc *sc      = device_get_softc(sio_dev);
948 	uint8_t       v;
949 
950 	sio_conf_enter(sc);
951 	v = sio_ldn_read(sc, ldn, reg);
952 	sio_conf_exit(sc);
953 	return (v);
954 }
955 
956 uint8_t
superio_read(device_t dev,uint8_t reg)957 superio_read(device_t dev, uint8_t reg)
958 {
959 	struct superio_devinfo *dinfo = device_get_ivars(dev);
960 
961 	return (superio_ldn_read(dev, dinfo->ldn, reg));
962 }
963 
964 void
superio_ldn_write(device_t dev,uint8_t ldn,uint8_t reg,uint8_t val)965 superio_ldn_write(device_t dev, uint8_t ldn, uint8_t reg, uint8_t val)
966 {
967 	device_t      sio_dev = device_get_parent(dev);
968 	struct siosc *sc      = device_get_softc(sio_dev);
969 
970 	sio_conf_enter(sc);
971 	sio_ldn_write(sc, ldn, reg, val);
972 	sio_conf_exit(sc);
973 }
974 
975 void
superio_write(device_t dev,uint8_t reg,uint8_t val)976 superio_write(device_t dev, uint8_t reg, uint8_t val)
977 {
978 	struct superio_devinfo *dinfo = device_get_ivars(dev);
979 
980 	return (superio_ldn_write(dev, dinfo->ldn, reg, val));
981 }
982 
983 bool
superio_dev_enabled(device_t dev,uint8_t mask)984 superio_dev_enabled(device_t dev, uint8_t mask)
985 {
986 	device_t sio_dev = device_get_parent(dev);
987 	struct siosc *sc = device_get_softc(sio_dev);
988 	struct superio_devinfo *dinfo = device_get_ivars(dev);
989 	uint8_t v;
990 
991 	/* GPIO device is always active in ITE chips. */
992 	if (sc->vendor == SUPERIO_VENDOR_ITE && dinfo->ldn == 7)
993 		return (true);
994 
995 	v = superio_read(dev, sc->enable_reg); /* FIXME enable_reg not used by nctgpio(4). */
996 	return ((v & mask) != 0);
997 }
998 
999 void
superio_dev_enable(device_t dev,uint8_t mask)1000 superio_dev_enable(device_t dev, uint8_t mask)
1001 {
1002 	device_t sio_dev = device_get_parent(dev);
1003 	struct siosc *sc = device_get_softc(sio_dev);
1004 	struct superio_devinfo *dinfo = device_get_ivars(dev);
1005 	uint8_t v;
1006 
1007 	/* GPIO device is always active in ITE chips. */
1008 	if (sc->vendor == SUPERIO_VENDOR_ITE && dinfo->ldn == 7)
1009 		return;
1010 
1011 	sio_conf_enter(sc);
1012 	v = sio_ldn_read(sc, dinfo->ldn, sc->enable_reg);
1013 	v |= mask;
1014 	sio_ldn_write(sc, dinfo->ldn, sc->enable_reg, v);
1015 	sio_conf_exit(sc);
1016 }
1017 
1018 void
superio_dev_disable(device_t dev,uint8_t mask)1019 superio_dev_disable(device_t dev, uint8_t mask)
1020 {
1021 	device_t sio_dev = device_get_parent(dev);
1022 	struct siosc *sc = device_get_softc(sio_dev);
1023 	struct superio_devinfo *dinfo = device_get_ivars(dev);
1024 	uint8_t v;
1025 
1026 	/* GPIO device is always active in ITE chips. */
1027 	if (sc->vendor == SUPERIO_VENDOR_ITE && dinfo->ldn == 7)
1028 		return;
1029 
1030 	sio_conf_enter(sc);
1031 	v = sio_ldn_read(sc, dinfo->ldn, sc->enable_reg);
1032 	v &= ~mask;
1033 	sio_ldn_write(sc, dinfo->ldn, sc->enable_reg, v);
1034 	sio_conf_exit(sc);
1035 }
1036 
1037 device_t
superio_find_dev(device_t superio,superio_dev_type_t type,int ldn)1038 superio_find_dev(device_t superio, superio_dev_type_t type, int ldn)
1039 {
1040 	struct siosc *sc = device_get_softc(superio);
1041 	struct superio_devinfo *dinfo;
1042 
1043 	if (ldn < -1 || ldn > UINT8_MAX)
1044 		return (NULL);		/* ERANGE */
1045 	if (type == SUPERIO_DEV_NONE && ldn == -1)
1046 		return (NULL);		/* EINVAL */
1047 
1048 	STAILQ_FOREACH(dinfo, &sc->devlist, link) {
1049 		if (ldn != -1 && dinfo->ldn != ldn)
1050 			continue;
1051 		if (type != SUPERIO_DEV_NONE && dinfo->type != type)
1052 			continue;
1053 		return (dinfo->dev);
1054 	}
1055 	return (NULL);
1056 }
1057 
1058 static int
superio_ioctl(struct cdev * dev,u_long cmd,caddr_t data,int flags,struct thread * td)1059 superio_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flags,
1060     struct thread *td)
1061 {
1062 	struct siosc *sc;
1063 	struct superiocmd *s;
1064 
1065 	sc = dev->si_drv1;
1066 	s = (struct superiocmd *)data;
1067 	switch (cmd) {
1068 	case SUPERIO_CR_READ:
1069 		sio_conf_enter(sc);
1070 		s->val = sio_ldn_read(sc, s->ldn, s->cr);
1071 		sio_conf_exit(sc);
1072 		return (0);
1073 	case SUPERIO_CR_WRITE:
1074 		sio_conf_enter(sc);
1075 		sio_ldn_write(sc, s->ldn, s->cr, s->val);
1076 		sio_conf_exit(sc);
1077 		return (0);
1078 	default:
1079 		return (ENOTTY);
1080 	}
1081 }
1082 
1083 static device_method_t superio_methods[] = {
1084 	DEVMETHOD(device_identify,	superio_identify),
1085 	DEVMETHOD(device_probe,		superio_probe),
1086 	DEVMETHOD(device_attach,	superio_attach),
1087 	DEVMETHOD(device_detach,	superio_detach),
1088 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
1089 	DEVMETHOD(device_suspend,	bus_generic_suspend),
1090 	DEVMETHOD(device_resume,	bus_generic_resume),
1091 
1092 	DEVMETHOD(bus_add_child,	superio_add_child),
1093 	DEVMETHOD(bus_child_deleted,	superio_child_deleted),
1094 	DEVMETHOD(bus_child_detached,	superio_child_detached),
1095 	DEVMETHOD(bus_child_location,	superio_child_location),
1096 	DEVMETHOD(bus_child_pnpinfo,	superio_child_pnp),
1097 	DEVMETHOD(bus_print_child,	superio_print_child),
1098 	DEVMETHOD(bus_read_ivar,	superio_read_ivar),
1099 	DEVMETHOD(bus_write_ivar,	superio_write_ivar),
1100 	DEVMETHOD(bus_get_resource_list, superio_get_resource_list),
1101 	DEVMETHOD(bus_alloc_resource,	bus_generic_rl_alloc_resource),
1102 	DEVMETHOD(bus_release_resource,	bus_generic_rl_release_resource),
1103 	DEVMETHOD(bus_set_resource,	bus_generic_rl_set_resource),
1104 	DEVMETHOD(bus_get_resource,	bus_generic_rl_get_resource),
1105 	DEVMETHOD(bus_delete_resource,	bus_generic_rl_delete_resource),
1106 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1107 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1108 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
1109 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
1110 
1111 	DEVMETHOD_END
1112 };
1113 
1114 static driver_t superio_driver = {
1115 	"superio",
1116 	superio_methods,
1117 	sizeof(struct siosc)
1118 };
1119 
1120 DRIVER_MODULE(superio, isa, superio_driver, 0, 0);
1121 MODULE_VERSION(superio, 1);
1122