1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /* 82571EB Gigabit Ethernet Controller
36 * 82571EB Gigabit Ethernet Controller (Copper)
37 * 82571EB Gigabit Ethernet Controller (Fiber)
38 * 82571EB Dual Port Gigabit Mezzanine Adapter
39 * 82571EB Quad Port Gigabit Mezzanine Adapter
40 * 82571PT Gigabit PT Quad Port Server ExpressModule
41 * 82572EI Gigabit Ethernet Controller (Copper)
42 * 82572EI Gigabit Ethernet Controller (Fiber)
43 * 82572EI Gigabit Ethernet Controller
44 * 82573V Gigabit Ethernet Controller (Copper)
45 * 82573E Gigabit Ethernet Controller (Copper)
46 * 82573L Gigabit Ethernet Controller
47 * 82574L Gigabit Network Connection
48 * 82583V Gigabit Network Connection
49 */
50
51 #include "e1000_api.h"
52
53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
54 static void e1000_release_nvm_82571(struct e1000_hw *hw);
55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
61 bool active);
62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
63 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
64 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
66 static s32 e1000_led_on_82574(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
74 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
75 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
77 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
78 bool active);
79 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
80 bool active);
81 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
82 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
83 u16 words, u16 *data);
84 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
85 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
86
87 /**
88 * e1000_init_phy_params_82571 - Init PHY func ptrs.
89 * @hw: pointer to the HW structure
90 **/
e1000_init_phy_params_82571(struct e1000_hw * hw)91 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
92 {
93 struct e1000_phy_info *phy = &hw->phy;
94 s32 ret_val;
95
96 DEBUGFUNC("e1000_init_phy_params_82571");
97
98 if (hw->phy.media_type != e1000_media_type_copper) {
99 phy->type = e1000_phy_none;
100 return E1000_SUCCESS;
101 }
102
103 phy->addr = 1;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
106
107 phy->ops.check_reset_block = e1000_check_reset_block_generic;
108 phy->ops.reset = e1000_phy_hw_reset_generic;
109 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
110 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
111 phy->ops.power_up = e1000_power_up_phy_copper;
112 phy->ops.power_down = e1000_power_down_phy_copper_82571;
113
114 switch (hw->mac.type) {
115 case e1000_82571:
116 case e1000_82572:
117 phy->type = e1000_phy_igp_2;
118 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
119 phy->ops.get_info = e1000_get_phy_info_igp;
120 phy->ops.check_polarity = e1000_check_polarity_igp;
121 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
122 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
123 phy->ops.read_reg = e1000_read_phy_reg_igp;
124 phy->ops.write_reg = e1000_write_phy_reg_igp;
125 phy->ops.acquire = e1000_get_hw_semaphore;
126 phy->ops.release = e1000_put_hw_semaphore;
127 break;
128 case e1000_82573:
129 phy->type = e1000_phy_m88;
130 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
131 phy->ops.get_info = e1000_get_phy_info_m88;
132 phy->ops.check_polarity = e1000_check_polarity_m88;
133 phy->ops.commit = e1000_phy_sw_reset_generic;
134 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
135 phy->ops.get_cable_length = e1000_get_cable_length_m88;
136 phy->ops.read_reg = e1000_read_phy_reg_m88;
137 phy->ops.write_reg = e1000_write_phy_reg_m88;
138 phy->ops.acquire = e1000_get_hw_semaphore;
139 phy->ops.release = e1000_put_hw_semaphore;
140 break;
141 case e1000_82574:
142 case e1000_82583:
143
144 phy->type = e1000_phy_bm;
145 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
146 phy->ops.get_info = e1000_get_phy_info_m88;
147 phy->ops.check_polarity = e1000_check_polarity_m88;
148 phy->ops.commit = e1000_phy_sw_reset_generic;
149 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
150 phy->ops.get_cable_length = e1000_get_cable_length_m88;
151 phy->ops.read_reg = e1000_read_phy_reg_bm2;
152 phy->ops.write_reg = e1000_write_phy_reg_bm2;
153 phy->ops.acquire = e1000_get_hw_semaphore_82574;
154 phy->ops.release = e1000_put_hw_semaphore_82574;
155 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
156 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
157 break;
158 default:
159 return -E1000_ERR_PHY;
160 break;
161 }
162
163 /* This can only be done after all function pointers are setup. */
164 ret_val = e1000_get_phy_id_82571(hw);
165 if (ret_val) {
166 DEBUGOUT("Error getting PHY ID\n");
167 return ret_val;
168 }
169
170 /* Verify phy id */
171 switch (hw->mac.type) {
172 case e1000_82571:
173 case e1000_82572:
174 if (phy->id != IGP01E1000_I_PHY_ID)
175 ret_val = -E1000_ERR_PHY;
176 break;
177 case e1000_82573:
178 if (phy->id != M88E1111_I_PHY_ID)
179 ret_val = -E1000_ERR_PHY;
180 break;
181 case e1000_82574:
182 case e1000_82583:
183 if (phy->id != BME1000_E_PHY_ID_R2)
184 ret_val = -E1000_ERR_PHY;
185 break;
186 default:
187 ret_val = -E1000_ERR_PHY;
188 break;
189 }
190
191 if (ret_val)
192 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
193
194 return ret_val;
195 }
196
197 /**
198 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
199 * @hw: pointer to the HW structure
200 **/
e1000_init_nvm_params_82571(struct e1000_hw * hw)201 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
202 {
203 struct e1000_nvm_info *nvm = &hw->nvm;
204 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
205 u16 size;
206
207 DEBUGFUNC("e1000_init_nvm_params_82571");
208
209 nvm->opcode_bits = 8;
210 nvm->delay_usec = 1;
211 switch (nvm->override) {
212 case e1000_nvm_override_spi_large:
213 nvm->page_size = 32;
214 nvm->address_bits = 16;
215 break;
216 case e1000_nvm_override_spi_small:
217 nvm->page_size = 8;
218 nvm->address_bits = 8;
219 break;
220 default:
221 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
222 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
223 break;
224 }
225
226 switch (hw->mac.type) {
227 case e1000_82573:
228 case e1000_82574:
229 case e1000_82583:
230 if (((eecd >> 15) & 0x3) == 0x3) {
231 nvm->type = e1000_nvm_flash_hw;
232 nvm->word_size = 2048;
233 /* Autonomous Flash update bit must be cleared due
234 * to Flash update issue.
235 */
236 eecd &= ~E1000_EECD_AUPDEN;
237 E1000_WRITE_REG(hw, E1000_EECD, eecd);
238 break;
239 }
240 /* FALLTHROUGH */
241 default:
242 nvm->type = e1000_nvm_eeprom_spi;
243 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
244 E1000_EECD_SIZE_EX_SHIFT);
245 /* Added to a constant, "size" becomes the left-shift value
246 * for setting word_size.
247 */
248 size += NVM_WORD_SIZE_BASE_SHIFT;
249
250 /* EEPROM access above 16k is unsupported */
251 if (size > 14)
252 size = 14;
253 nvm->word_size = 1 << size;
254 break;
255 }
256
257 /* Function Pointers */
258 switch (hw->mac.type) {
259 case e1000_82574:
260 case e1000_82583:
261 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
262 nvm->ops.release = e1000_put_hw_semaphore_82574;
263 break;
264 default:
265 nvm->ops.acquire = e1000_acquire_nvm_82571;
266 nvm->ops.release = e1000_release_nvm_82571;
267 break;
268 }
269 nvm->ops.read = e1000_read_nvm_eerd;
270 nvm->ops.update = e1000_update_nvm_checksum_82571;
271 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
272 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
273 nvm->ops.write = e1000_write_nvm_82571;
274
275 return E1000_SUCCESS;
276 }
277
278 /**
279 * e1000_init_mac_params_82571 - Init MAC func ptrs.
280 * @hw: pointer to the HW structure
281 **/
e1000_init_mac_params_82571(struct e1000_hw * hw)282 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
283 {
284 struct e1000_mac_info *mac = &hw->mac;
285 u32 swsm = 0;
286 u32 swsm2 = 0;
287 bool force_clear_smbi = false;
288
289 DEBUGFUNC("e1000_init_mac_params_82571");
290
291 /* Set media type and media-dependent function pointers */
292 switch (hw->device_id) {
293 case E1000_DEV_ID_82571EB_FIBER:
294 case E1000_DEV_ID_82572EI_FIBER:
295 case E1000_DEV_ID_82571EB_QUAD_FIBER:
296 hw->phy.media_type = e1000_media_type_fiber;
297 mac->ops.setup_physical_interface =
298 e1000_setup_fiber_serdes_link_82571;
299 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
300 mac->ops.get_link_up_info =
301 e1000_get_speed_and_duplex_fiber_serdes_generic;
302 break;
303 case E1000_DEV_ID_82571EB_SERDES:
304 case E1000_DEV_ID_82571EB_SERDES_DUAL:
305 case E1000_DEV_ID_82571EB_SERDES_QUAD:
306 case E1000_DEV_ID_82572EI_SERDES:
307 hw->phy.media_type = e1000_media_type_internal_serdes;
308 mac->ops.setup_physical_interface =
309 e1000_setup_fiber_serdes_link_82571;
310 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
311 mac->ops.get_link_up_info =
312 e1000_get_speed_and_duplex_fiber_serdes_generic;
313 break;
314 default:
315 hw->phy.media_type = e1000_media_type_copper;
316 mac->ops.setup_physical_interface =
317 e1000_setup_copper_link_82571;
318 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
319 mac->ops.get_link_up_info =
320 e1000_get_speed_and_duplex_copper_generic;
321 break;
322 }
323
324 /* Set mta register count */
325 mac->mta_reg_count = 128;
326 /* Set rar entry count */
327 mac->rar_entry_count = E1000_RAR_ENTRIES;
328 /* Set if part includes ASF firmware */
329 mac->asf_firmware_present = true;
330 /* Adaptive IFS supported */
331 mac->adaptive_ifs = true;
332
333 /* Function pointers */
334
335 /* bus type/speed/width */
336 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
337 /* reset */
338 mac->ops.reset_hw = e1000_reset_hw_82571;
339 /* hw initialization */
340 mac->ops.init_hw = e1000_init_hw_82571;
341 /* link setup */
342 mac->ops.setup_link = e1000_setup_link_82571;
343 /* multicast address update */
344 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
345 /* writing VFTA */
346 mac->ops.write_vfta = e1000_write_vfta_generic;
347 /* clearing VFTA */
348 mac->ops.clear_vfta = e1000_clear_vfta_82571;
349 /* read mac address */
350 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
351 /* ID LED init */
352 mac->ops.id_led_init = e1000_id_led_init_generic;
353 /* setup LED */
354 mac->ops.setup_led = e1000_setup_led_generic;
355 /* cleanup LED */
356 mac->ops.cleanup_led = e1000_cleanup_led_generic;
357 /* turn off LED */
358 mac->ops.led_off = e1000_led_off_generic;
359 /* clear hardware counters */
360 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
361
362 /* MAC-specific function pointers */
363 switch (hw->mac.type) {
364 case e1000_82573:
365 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
366 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
367 mac->ops.led_on = e1000_led_on_generic;
368 mac->ops.blink_led = e1000_blink_led_generic;
369
370 /* FWSM register */
371 mac->has_fwsm = true;
372 /* ARC supported; valid only if manageability features are
373 * enabled.
374 */
375 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
376 E1000_FWSM_MODE_MASK);
377 break;
378 case e1000_82574:
379 case e1000_82583:
380 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
381 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
382 mac->ops.led_on = e1000_led_on_82574;
383 break;
384 default:
385 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
386 mac->ops.led_on = e1000_led_on_generic;
387 mac->ops.blink_led = e1000_blink_led_generic;
388
389 /* FWSM register */
390 mac->has_fwsm = true;
391 break;
392 }
393
394 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
395 * first NVM or PHY access. This should be done for single-port
396 * devices, and for one port only on dual-port devices so that
397 * for those devices we can still use the SMBI lock to synchronize
398 * inter-port accesses to the PHY & NVM.
399 */
400 switch (hw->mac.type) {
401 case e1000_82571:
402 case e1000_82572:
403 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
404
405 if (!(swsm2 & E1000_SWSM2_LOCK)) {
406 /* Only do this for the first interface on this card */
407 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
408 E1000_SWSM2_LOCK);
409 force_clear_smbi = true;
410 } else {
411 force_clear_smbi = false;
412 }
413 break;
414 default:
415 force_clear_smbi = true;
416 break;
417 }
418
419 if (force_clear_smbi) {
420 /* Make sure SWSM.SMBI is clear */
421 swsm = E1000_READ_REG(hw, E1000_SWSM);
422 if (swsm & E1000_SWSM_SMBI) {
423 /* This bit should not be set on a first interface, and
424 * indicates that the bootagent or EFI code has
425 * improperly left this bit enabled
426 */
427 DEBUGOUT("Please update your 82571 Bootagent\n");
428 }
429 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
430 }
431
432 /* Initialze device specific counter of SMBI acquisition timeouts. */
433 hw->dev_spec._82571.smb_counter = 0;
434
435 return E1000_SUCCESS;
436 }
437
438 /**
439 * e1000_init_function_pointers_82571 - Init func ptrs.
440 * @hw: pointer to the HW structure
441 *
442 * Called to initialize all function pointers and parameters.
443 **/
e1000_init_function_pointers_82571(struct e1000_hw * hw)444 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
445 {
446 DEBUGFUNC("e1000_init_function_pointers_82571");
447
448 hw->mac.ops.init_params = e1000_init_mac_params_82571;
449 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
450 hw->phy.ops.init_params = e1000_init_phy_params_82571;
451 }
452
453 /**
454 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
455 * @hw: pointer to the HW structure
456 *
457 * Reads the PHY registers and stores the PHY ID and possibly the PHY
458 * revision in the hardware structure.
459 **/
e1000_get_phy_id_82571(struct e1000_hw * hw)460 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
461 {
462 struct e1000_phy_info *phy = &hw->phy;
463 s32 ret_val;
464 u16 phy_id = 0;
465
466 DEBUGFUNC("e1000_get_phy_id_82571");
467
468 switch (hw->mac.type) {
469 case e1000_82571:
470 case e1000_82572:
471 /* The 82571 firmware may still be configuring the PHY.
472 * In this case, we cannot access the PHY until the
473 * configuration is done. So we explicitly set the
474 * PHY ID.
475 */
476 phy->id = IGP01E1000_I_PHY_ID;
477 break;
478 case e1000_82573:
479 return e1000_get_phy_id(hw);
480 break;
481 case e1000_82574:
482 case e1000_82583:
483 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
484 if (ret_val)
485 return ret_val;
486
487 phy->id = (u32)(phy_id << 16);
488 usec_delay(20);
489 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
490 if (ret_val)
491 return ret_val;
492
493 phy->id |= (u32)(phy_id);
494 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
495 break;
496 default:
497 return -E1000_ERR_PHY;
498 break;
499 }
500
501 return E1000_SUCCESS;
502 }
503
504 /**
505 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
506 * @hw: pointer to the HW structure
507 *
508 * Acquire the HW semaphore during reset.
509 *
510 **/
511 static s32
e1000_get_hw_semaphore_82574(struct e1000_hw * hw)512 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
513 {
514 u32 extcnf_ctrl;
515 s32 i = 0;
516 /* XXX assert that mutex is held */
517 DEBUGFUNC("e1000_get_hw_semaphore_82574");
518
519 ASSERT_CTX_LOCK_HELD(hw);
520 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
521 do {
522 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
523 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
524 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
525
526 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
527 break;
528
529 msec_delay(2);
530 i++;
531 } while (i < MDIO_OWNERSHIP_TIMEOUT);
532
533 if (i == MDIO_OWNERSHIP_TIMEOUT) {
534 /* Release semaphores */
535 e1000_put_hw_semaphore_82574(hw);
536 DEBUGOUT("Driver can't access the PHY\n");
537 return -E1000_ERR_PHY;
538 }
539
540 return E1000_SUCCESS;
541 }
542
543 /**
544 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
545 * @hw: pointer to the HW structure
546 *
547 * Release hardware semaphore used during reset.
548 *
549 **/
550 static void
e1000_put_hw_semaphore_82574(struct e1000_hw * hw)551 e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
552 {
553 u32 extcnf_ctrl;
554
555 DEBUGFUNC("e1000_put_hw_semaphore_82574");
556
557 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
558 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
559 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
560 }
561
562 /**
563 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
564 * @hw: pointer to the HW structure
565 * @active: true to enable LPLU, false to disable
566 *
567 * Sets the LPLU D0 state according to the active flag.
568 * LPLU will not be activated unless the
569 * device autonegotiation advertisement meets standards of
570 * either 10 or 10/100 or 10/100/1000 at all duplexes.
571 * This is a function pointer entry point only called by
572 * PHY setup routines.
573 **/
e1000_set_d0_lplu_state_82574(struct e1000_hw * hw,bool active)574 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
575 {
576 u32 data = E1000_READ_REG(hw, E1000_POEMB);
577
578 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
579
580 if (active)
581 data |= E1000_PHY_CTRL_D0A_LPLU;
582 else
583 data &= ~E1000_PHY_CTRL_D0A_LPLU;
584
585 E1000_WRITE_REG(hw, E1000_POEMB, data);
586 return E1000_SUCCESS;
587 }
588
589 /**
590 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
591 * @hw: pointer to the HW structure
592 * @active: boolean used to enable/disable lplu
593 *
594 * The low power link up (lplu) state is set to the power management level D3
595 * when active is true, else clear lplu for D3. LPLU
596 * is used during Dx states where the power conservation is most important.
597 * During driver activity, SmartSpeed should be enabled so performance is
598 * maintained.
599 **/
e1000_set_d3_lplu_state_82574(struct e1000_hw * hw,bool active)600 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
601 {
602 u32 data = E1000_READ_REG(hw, E1000_POEMB);
603
604 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
605
606 if (!active) {
607 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
608 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
609 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
610 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
611 data |= E1000_PHY_CTRL_NOND0A_LPLU;
612 }
613
614 E1000_WRITE_REG(hw, E1000_POEMB, data);
615 return E1000_SUCCESS;
616 }
617
618 /**
619 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
620 * @hw: pointer to the HW structure
621 *
622 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
623 * Then for non-82573 hardware, set the EEPROM access request bit and wait
624 * for EEPROM access grant bit. If the access grant bit is not set, release
625 * hardware semaphore.
626 **/
e1000_acquire_nvm_82571(struct e1000_hw * hw)627 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
628 {
629 s32 ret_val;
630
631 DEBUGFUNC("e1000_acquire_nvm_82571");
632
633 ret_val = e1000_get_hw_semaphore(hw);
634 if (ret_val)
635 return ret_val;
636
637 switch (hw->mac.type) {
638 case e1000_82573:
639 break;
640 default:
641 ret_val = e1000_acquire_nvm_generic(hw);
642 break;
643 }
644
645 if (ret_val)
646 e1000_put_hw_semaphore(hw);
647
648 return ret_val;
649 }
650
651 /**
652 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
653 * @hw: pointer to the HW structure
654 *
655 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
656 **/
e1000_release_nvm_82571(struct e1000_hw * hw)657 static void e1000_release_nvm_82571(struct e1000_hw *hw)
658 {
659 DEBUGFUNC("e1000_release_nvm_82571");
660
661 e1000_release_nvm_generic(hw);
662 e1000_put_hw_semaphore(hw);
663 }
664
665 /**
666 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
667 * @hw: pointer to the HW structure
668 * @offset: offset within the EEPROM to be written to
669 * @words: number of words to write
670 * @data: 16 bit word(s) to be written to the EEPROM
671 *
672 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
673 *
674 * If e1000_update_nvm_checksum is not called after this function, the
675 * EEPROM will most likely contain an invalid checksum.
676 **/
e1000_write_nvm_82571(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)677 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
678 u16 *data)
679 {
680 s32 ret_val;
681
682 DEBUGFUNC("e1000_write_nvm_82571");
683
684 switch (hw->mac.type) {
685 case e1000_82573:
686 case e1000_82574:
687 case e1000_82583:
688 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
689 break;
690 case e1000_82571:
691 case e1000_82572:
692 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
693 break;
694 default:
695 ret_val = -E1000_ERR_NVM;
696 break;
697 }
698
699 return ret_val;
700 }
701
702 /**
703 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
704 * @hw: pointer to the HW structure
705 *
706 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
707 * up to the checksum. Then calculates the EEPROM checksum and writes the
708 * value to the EEPROM.
709 **/
e1000_update_nvm_checksum_82571(struct e1000_hw * hw)710 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
711 {
712 u32 eecd;
713 s32 ret_val;
714 u16 i;
715
716 DEBUGFUNC("e1000_update_nvm_checksum_82571");
717
718 ret_val = e1000_update_nvm_checksum_generic(hw);
719 if (ret_val)
720 return ret_val;
721
722 /* If our nvm is an EEPROM, then we're done
723 * otherwise, commit the checksum to the flash NVM.
724 */
725 if (hw->nvm.type != e1000_nvm_flash_hw)
726 return E1000_SUCCESS;
727
728 /* Check for pending operations. */
729 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
730 msec_delay(1);
731 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
732 break;
733 }
734
735 if (i == E1000_FLASH_UPDATES)
736 return -E1000_ERR_NVM;
737
738 /* Reset the firmware if using STM opcode. */
739 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
740 /* The enabling of and the actual reset must be done
741 * in two write cycles.
742 */
743 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
744 E1000_WRITE_FLUSH(hw);
745 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
746 }
747
748 /* Commit the write to flash */
749 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
750 E1000_WRITE_REG(hw, E1000_EECD, eecd);
751
752 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
753 msec_delay(1);
754 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
755 break;
756 }
757
758 if (i == E1000_FLASH_UPDATES)
759 return -E1000_ERR_NVM;
760
761 return E1000_SUCCESS;
762 }
763
764 /**
765 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
766 * @hw: pointer to the HW structure
767 *
768 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
769 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
770 **/
e1000_validate_nvm_checksum_82571(struct e1000_hw * hw)771 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
772 {
773 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
774
775 if (hw->nvm.type == e1000_nvm_flash_hw)
776 e1000_fix_nvm_checksum_82571(hw);
777
778 return e1000_validate_nvm_checksum_generic(hw);
779 }
780
781 /**
782 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
783 * @hw: pointer to the HW structure
784 * @offset: offset within the EEPROM to be written to
785 * @words: number of words to write
786 * @data: 16 bit word(s) to be written to the EEPROM
787 *
788 * After checking for invalid values, poll the EEPROM to ensure the previous
789 * command has completed before trying to write the next word. After write
790 * poll for completion.
791 *
792 * If e1000_update_nvm_checksum is not called after this function, the
793 * EEPROM will most likely contain an invalid checksum.
794 **/
e1000_write_nvm_eewr_82571(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)795 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
796 u16 words, u16 *data)
797 {
798 struct e1000_nvm_info *nvm = &hw->nvm;
799 u32 i, eewr = 0;
800 s32 ret_val = E1000_SUCCESS;
801
802 DEBUGFUNC("e1000_write_nvm_eewr_82571");
803
804 /* A check for invalid values: offset too large, too many words,
805 * and not enough words.
806 */
807 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
808 (words == 0)) {
809 DEBUGOUT("nvm parameter(s) out of bounds\n");
810 return -E1000_ERR_NVM;
811 }
812
813 for (i = 0; i < words; i++) {
814 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
815 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
816 E1000_NVM_RW_REG_START);
817
818 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
819 if (ret_val)
820 break;
821
822 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
823
824 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
825 if (ret_val)
826 break;
827 }
828
829 return ret_val;
830 }
831
832 /**
833 * e1000_get_cfg_done_82571 - Poll for configuration done
834 * @hw: pointer to the HW structure
835 *
836 * Reads the management control register for the config done bit to be set.
837 **/
e1000_get_cfg_done_82571(struct e1000_hw * hw)838 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
839 {
840 s32 timeout = PHY_CFG_TIMEOUT;
841
842 DEBUGFUNC("e1000_get_cfg_done_82571");
843
844 while (timeout) {
845 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
846 E1000_NVM_CFG_DONE_PORT_0)
847 break;
848 msec_delay(1);
849 timeout--;
850 }
851 if (!timeout) {
852 DEBUGOUT("MNG configuration cycle has not completed.\n");
853 return -E1000_ERR_RESET;
854 }
855
856 return E1000_SUCCESS;
857 }
858
859 /**
860 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
861 * @hw: pointer to the HW structure
862 * @active: true to enable LPLU, false to disable
863 *
864 * Sets the LPLU D0 state according to the active flag. When activating LPLU
865 * this function also disables smart speed and vice versa. LPLU will not be
866 * activated unless the device autonegotiation advertisement meets standards
867 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
868 * pointer entry point only called by PHY setup routines.
869 **/
e1000_set_d0_lplu_state_82571(struct e1000_hw * hw,bool active)870 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
871 {
872 struct e1000_phy_info *phy = &hw->phy;
873 s32 ret_val;
874 u16 data;
875
876 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
877
878 if (!(phy->ops.read_reg))
879 return E1000_SUCCESS;
880
881 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
882 if (ret_val)
883 return ret_val;
884
885 if (active) {
886 data |= IGP02E1000_PM_D0_LPLU;
887 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
888 data);
889 if (ret_val)
890 return ret_val;
891
892 /* When LPLU is enabled, we should disable SmartSpeed */
893 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
894 &data);
895 if (ret_val)
896 return ret_val;
897 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
898 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
899 data);
900 if (ret_val)
901 return ret_val;
902 } else {
903 data &= ~IGP02E1000_PM_D0_LPLU;
904 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
905 data);
906 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
907 * during Dx states where the power conservation is most
908 * important. During driver activity we should enable
909 * SmartSpeed, so performance is maintained.
910 */
911 if (phy->smart_speed == e1000_smart_speed_on) {
912 ret_val = phy->ops.read_reg(hw,
913 IGP01E1000_PHY_PORT_CONFIG,
914 &data);
915 if (ret_val)
916 return ret_val;
917
918 data |= IGP01E1000_PSCFR_SMART_SPEED;
919 ret_val = phy->ops.write_reg(hw,
920 IGP01E1000_PHY_PORT_CONFIG,
921 data);
922 if (ret_val)
923 return ret_val;
924 } else if (phy->smart_speed == e1000_smart_speed_off) {
925 ret_val = phy->ops.read_reg(hw,
926 IGP01E1000_PHY_PORT_CONFIG,
927 &data);
928 if (ret_val)
929 return ret_val;
930
931 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
932 ret_val = phy->ops.write_reg(hw,
933 IGP01E1000_PHY_PORT_CONFIG,
934 data);
935 if (ret_val)
936 return ret_val;
937 }
938 }
939
940 return E1000_SUCCESS;
941 }
942
943 /**
944 * e1000_reset_hw_82571 - Reset hardware
945 * @hw: pointer to the HW structure
946 *
947 * This resets the hardware into a known state.
948 **/
e1000_reset_hw_82571(struct e1000_hw * hw)949 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
950 {
951 u32 ctrl, ctrl_ext, eecd, tctl;
952 s32 ret_val;
953
954 DEBUGFUNC("e1000_reset_hw_82571");
955
956 /* Prevent the PCI-E bus from sticking if there is no TLP connection
957 * on the last TLP read/write transaction when MAC is reset.
958 */
959 ret_val = e1000_disable_pcie_master_generic(hw);
960 if (ret_val)
961 DEBUGOUT("PCI-E Master disable polling has failed.\n");
962
963 DEBUGOUT("Masking off all interrupts\n");
964 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
965
966 E1000_WRITE_REG(hw, E1000_RCTL, 0);
967 tctl = E1000_READ_REG(hw, E1000_TCTL);
968 tctl &= ~E1000_TCTL_EN;
969 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
970 E1000_WRITE_FLUSH(hw);
971
972 msec_delay(10);
973
974 /* Must acquire the MDIO ownership before MAC reset.
975 * Ownership defaults to firmware after a reset.
976 */
977 switch (hw->mac.type) {
978 case e1000_82573:
979 case e1000_82574:
980 case e1000_82583:
981 ret_val = e1000_get_hw_semaphore_82574(hw);
982 break;
983 default:
984 break;
985 }
986
987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
988
989 DEBUGOUT("Issuing a global reset to MAC\n");
990 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
991
992 /* Must release MDIO ownership and mutex after MAC reset. */
993 switch (hw->mac.type) {
994 case e1000_82573:
995 case e1000_82574:
996 case e1000_82583:
997 /* Release mutex only if the hw semaphore is acquired */
998 if (!ret_val)
999 e1000_put_hw_semaphore_82574(hw);
1000 break;
1001 default:
1002 /* we didn't get the semaphore no need to put it */
1003 break;
1004 }
1005
1006 if (hw->nvm.type == e1000_nvm_flash_hw) {
1007 usec_delay(10);
1008 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1009 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1010 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1011 E1000_WRITE_FLUSH(hw);
1012 }
1013
1014 ret_val = e1000_get_auto_rd_done_generic(hw);
1015 if (ret_val)
1016 /* We don't want to continue accessing MAC registers. */
1017 return ret_val;
1018
1019 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1020 * Need to wait for Phy configuration completion before accessing
1021 * NVM and Phy.
1022 */
1023
1024 switch (hw->mac.type) {
1025 case e1000_82571:
1026 case e1000_82572:
1027 /* REQ and GNT bits need to be cleared when using AUTO_RD
1028 * to access the EEPROM.
1029 */
1030 eecd = E1000_READ_REG(hw, E1000_EECD);
1031 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1032 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1033 break;
1034 case e1000_82573:
1035 case e1000_82574:
1036 case e1000_82583:
1037 msec_delay(25);
1038 break;
1039 default:
1040 break;
1041 }
1042
1043 /* Clear any pending interrupt events. */
1044 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1045 E1000_READ_REG(hw, E1000_ICR);
1046
1047 if (hw->mac.type == e1000_82571) {
1048 /* Install any alternate MAC address into RAR0 */
1049 ret_val = e1000_check_alt_mac_addr_generic(hw);
1050 if (ret_val)
1051 return ret_val;
1052
1053 e1000_set_laa_state_82571(hw, true);
1054 }
1055
1056 /* Reinitialize the 82571 serdes link state machine */
1057 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1058 hw->mac.serdes_link_state = e1000_serdes_link_down;
1059
1060 return E1000_SUCCESS;
1061 }
1062
1063 /**
1064 * e1000_init_hw_82571 - Initialize hardware
1065 * @hw: pointer to the HW structure
1066 *
1067 * This inits the hardware readying it for operation.
1068 **/
e1000_init_hw_82571(struct e1000_hw * hw)1069 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1070 {
1071 struct e1000_mac_info *mac = &hw->mac;
1072 u32 reg_data;
1073 s32 ret_val;
1074 u16 i, rar_count = mac->rar_entry_count;
1075
1076 DEBUGFUNC("e1000_init_hw_82571");
1077
1078 e1000_initialize_hw_bits_82571(hw);
1079
1080 /* Initialize identification LED */
1081 ret_val = mac->ops.id_led_init(hw);
1082 /* An error is not fatal and we should not stop init due to this */
1083 if (ret_val)
1084 DEBUGOUT("Error initializing identification LED\n");
1085
1086 /* Disabling VLAN filtering */
1087 DEBUGOUT("Initializing the IEEE VLAN\n");
1088 mac->ops.clear_vfta(hw);
1089
1090 /* Setup the receive address.
1091 * If, however, a locally administered address was assigned to the
1092 * 82571, we must reserve a RAR for it to work around an issue where
1093 * resetting one port will reload the MAC on the other port.
1094 */
1095 if (e1000_get_laa_state_82571(hw))
1096 rar_count--;
1097 e1000_init_rx_addrs_generic(hw, rar_count);
1098
1099 /* Zero out the Multicast HASH table */
1100 DEBUGOUT("Zeroing the MTA\n");
1101 for (i = 0; i < mac->mta_reg_count; i++)
1102 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1103
1104 /* Setup link and flow control */
1105 ret_val = mac->ops.setup_link(hw);
1106
1107 /* Set the transmit descriptor write-back policy */
1108 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1109 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1110 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1111 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1112
1113 /* ...for both queues. */
1114 switch (mac->type) {
1115 case e1000_82573:
1116 e1000_enable_tx_pkt_filtering_generic(hw);
1117 /* FALLTHROUGH */
1118 case e1000_82574:
1119 case e1000_82583:
1120 reg_data = E1000_READ_REG(hw, E1000_GCR);
1121 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1122 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1123 break;
1124 default:
1125 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1126 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1127 E1000_TXDCTL_FULL_TX_DESC_WB |
1128 E1000_TXDCTL_COUNT_DESC);
1129 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1130 break;
1131 }
1132
1133 /* Clear all of the statistics registers (clear on read). It is
1134 * important that we do this after we have tried to establish link
1135 * because the symbol error count will increment wildly if there
1136 * is no link.
1137 */
1138 e1000_clear_hw_cntrs_82571(hw);
1139
1140 return ret_val;
1141 }
1142
1143 /**
1144 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1145 * @hw: pointer to the HW structure
1146 *
1147 * Initializes required hardware-dependent bits needed for normal operation.
1148 **/
e1000_initialize_hw_bits_82571(struct e1000_hw * hw)1149 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1150 {
1151 u32 reg;
1152
1153 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1154
1155 /* Transmit Descriptor Control 0 */
1156 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1157 reg |= (1 << 22);
1158 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1159
1160 /* Transmit Descriptor Control 1 */
1161 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1162 reg |= (1 << 22);
1163 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1164
1165 /* Transmit Arbitration Control 0 */
1166 reg = E1000_READ_REG(hw, E1000_TARC(0));
1167 reg &= ~(0xF << 27); /* 30:27 */
1168 switch (hw->mac.type) {
1169 case e1000_82571:
1170 case e1000_82572:
1171 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1172 break;
1173 case e1000_82574:
1174 case e1000_82583:
1175 reg |= (1 << 26);
1176 break;
1177 default:
1178 break;
1179 }
1180 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1181
1182 /* Transmit Arbitration Control 1 */
1183 reg = E1000_READ_REG(hw, E1000_TARC(1));
1184 switch (hw->mac.type) {
1185 case e1000_82571:
1186 case e1000_82572:
1187 reg &= ~((1 << 29) | (1 << 30));
1188 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1189 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1190 reg &= ~(1 << 28);
1191 else
1192 reg |= (1 << 28);
1193 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1194 break;
1195 default:
1196 break;
1197 }
1198
1199 /* Device Control */
1200 switch (hw->mac.type) {
1201 case e1000_82573:
1202 case e1000_82574:
1203 case e1000_82583:
1204 reg = E1000_READ_REG(hw, E1000_CTRL);
1205 reg &= ~(1 << 29);
1206 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1207 break;
1208 default:
1209 break;
1210 }
1211
1212 /* Extended Device Control */
1213 switch (hw->mac.type) {
1214 case e1000_82573:
1215 case e1000_82574:
1216 case e1000_82583:
1217 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1218 reg &= ~(1 << 23);
1219 reg |= (1 << 22);
1220 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1221 break;
1222 default:
1223 break;
1224 }
1225
1226 if (hw->mac.type == e1000_82571) {
1227 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1228 reg |= E1000_PBA_ECC_CORR_EN;
1229 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1230 }
1231
1232 /* Workaround for hardware errata.
1233 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1234 */
1235 if ((hw->mac.type == e1000_82571) ||
1236 (hw->mac.type == e1000_82572)) {
1237 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1238 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1239 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1240 }
1241
1242 /* Disable IPv6 extension header parsing because some malformed
1243 * IPv6 headers can hang the Rx.
1244 */
1245 if (hw->mac.type <= e1000_82573) {
1246 reg = E1000_READ_REG(hw, E1000_RFCTL);
1247 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1248 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1249 }
1250
1251 /* PCI-Ex Control Registers */
1252 switch (hw->mac.type) {
1253 case e1000_82574:
1254 case e1000_82583:
1255 reg = E1000_READ_REG(hw, E1000_GCR);
1256 reg |= (1 << 22);
1257 E1000_WRITE_REG(hw, E1000_GCR, reg);
1258
1259 /* Workaround for hardware errata.
1260 * apply workaround for hardware errata documented in errata
1261 * docs Fixes issue where some error prone or unreliable PCIe
1262 * completions are occurring, particularly with ASPM enabled.
1263 * Without fix, issue can cause Tx timeouts.
1264 */
1265 reg = E1000_READ_REG(hw, E1000_GCR2);
1266 reg |= 1;
1267 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1268 break;
1269 default:
1270 break;
1271 }
1272
1273 return;
1274 }
1275
1276 /**
1277 * e1000_clear_vfta_82571 - Clear VLAN filter table
1278 * @hw: pointer to the HW structure
1279 *
1280 * Clears the register array which contains the VLAN filter table by
1281 * setting all the values to 0.
1282 **/
e1000_clear_vfta_82571(struct e1000_hw * hw)1283 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1284 {
1285 u32 offset;
1286 u32 vfta_value = 0;
1287 u32 vfta_offset = 0;
1288 u32 vfta_bit_in_reg = 0;
1289
1290 DEBUGFUNC("e1000_clear_vfta_82571");
1291
1292 switch (hw->mac.type) {
1293 case e1000_82573:
1294 case e1000_82574:
1295 case e1000_82583:
1296 if (hw->mng_cookie.vlan_id != 0) {
1297 /* The VFTA is a 4096b bit-field, each identifying
1298 * a single VLAN ID. The following operations
1299 * determine which 32b entry (i.e. offset) into the
1300 * array we want to set the VLAN ID (i.e. bit) of
1301 * the manageability unit.
1302 */
1303 vfta_offset = (hw->mng_cookie.vlan_id >>
1304 E1000_VFTA_ENTRY_SHIFT) &
1305 E1000_VFTA_ENTRY_MASK;
1306 vfta_bit_in_reg =
1307 1 << (hw->mng_cookie.vlan_id &
1308 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1309 }
1310 break;
1311 default:
1312 break;
1313 }
1314 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1315 /* If the offset we want to clear is the same offset of the
1316 * manageability VLAN ID, then clear all bits except that of
1317 * the manageability unit.
1318 */
1319 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1320 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1321 E1000_WRITE_FLUSH(hw);
1322 }
1323 }
1324
1325 /**
1326 * e1000_check_mng_mode_82574 - Check manageability is enabled
1327 * @hw: pointer to the HW structure
1328 *
1329 * Reads the NVM Initialization Control Word 2 and returns true
1330 * (>0) if any manageability is enabled, else false (0).
1331 **/
e1000_check_mng_mode_82574(struct e1000_hw * hw)1332 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1333 {
1334 u16 data;
1335 s32 ret_val;
1336
1337 DEBUGFUNC("e1000_check_mng_mode_82574");
1338
1339 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1340 if (ret_val)
1341 return false;
1342
1343 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1344 }
1345
1346 /**
1347 * e1000_led_on_82574 - Turn LED on
1348 * @hw: pointer to the HW structure
1349 *
1350 * Turn LED on.
1351 **/
e1000_led_on_82574(struct e1000_hw * hw)1352 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1353 {
1354 u32 ctrl;
1355 u32 i;
1356
1357 DEBUGFUNC("e1000_led_on_82574");
1358
1359 ctrl = hw->mac.ledctl_mode2;
1360 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1361 /* If no link, then turn LED on by setting the invert bit
1362 * for each LED that's "on" (0x0E) in ledctl_mode2.
1363 */
1364 for (i = 0; i < 4; i++)
1365 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1366 E1000_LEDCTL_MODE_LED_ON)
1367 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1368 }
1369 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1370
1371 return E1000_SUCCESS;
1372 }
1373
1374 /**
1375 * e1000_check_phy_82574 - check 82574 phy hung state
1376 * @hw: pointer to the HW structure
1377 *
1378 * Returns whether phy is hung or not
1379 **/
e1000_check_phy_82574(struct e1000_hw * hw)1380 bool e1000_check_phy_82574(struct e1000_hw *hw)
1381 {
1382 u16 status_1kbt = 0;
1383 u16 receive_errors = 0;
1384 s32 ret_val;
1385
1386 DEBUGFUNC("e1000_check_phy_82574");
1387
1388 /* Read PHY Receive Error counter first, if its is max - all F's then
1389 * read the Base1000T status register If both are max then PHY is hung.
1390 */
1391 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1392 &receive_errors);
1393 if (ret_val)
1394 return false;
1395 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1396 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1397 &status_1kbt);
1398 if (ret_val)
1399 return false;
1400 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1401 E1000_IDLE_ERROR_COUNT_MASK)
1402 return true;
1403 }
1404
1405 return false;
1406 }
1407
1408
1409 /**
1410 * e1000_setup_link_82571 - Setup flow control and link settings
1411 * @hw: pointer to the HW structure
1412 *
1413 * Determines which flow control settings to use, then configures flow
1414 * control. Calls the appropriate media-specific link configuration
1415 * function. Assuming the adapter has a valid link partner, a valid link
1416 * should be established. Assumes the hardware has previously been reset
1417 * and the transmitter and receiver are not enabled.
1418 **/
e1000_setup_link_82571(struct e1000_hw * hw)1419 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1420 {
1421 DEBUGFUNC("e1000_setup_link_82571");
1422
1423 /* 82573 does not have a word in the NVM to determine
1424 * the default flow control setting, so we explicitly
1425 * set it to full.
1426 */
1427 switch (hw->mac.type) {
1428 case e1000_82573:
1429 case e1000_82574:
1430 case e1000_82583:
1431 if (hw->fc.requested_mode == e1000_fc_default)
1432 hw->fc.requested_mode = e1000_fc_full;
1433 break;
1434 default:
1435 break;
1436 }
1437
1438 return e1000_setup_link_generic(hw);
1439 }
1440
1441 /**
1442 * e1000_setup_copper_link_82571 - Configure copper link settings
1443 * @hw: pointer to the HW structure
1444 *
1445 * Configures the link for auto-neg or forced speed and duplex. Then we check
1446 * for link, once link is established calls to configure collision distance
1447 * and flow control are called.
1448 **/
e1000_setup_copper_link_82571(struct e1000_hw * hw)1449 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1450 {
1451 u32 ctrl;
1452 s32 ret_val;
1453
1454 DEBUGFUNC("e1000_setup_copper_link_82571");
1455
1456 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1457 ctrl |= E1000_CTRL_SLU;
1458 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1459 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1460
1461 switch (hw->phy.type) {
1462 case e1000_phy_m88:
1463 case e1000_phy_bm:
1464 ret_val = e1000_copper_link_setup_m88(hw);
1465 break;
1466 case e1000_phy_igp_2:
1467 ret_val = e1000_copper_link_setup_igp(hw);
1468 break;
1469 default:
1470 return -E1000_ERR_PHY;
1471 break;
1472 }
1473
1474 if (ret_val)
1475 return ret_val;
1476
1477 return e1000_setup_copper_link_generic(hw);
1478 }
1479
1480 /**
1481 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1482 * @hw: pointer to the HW structure
1483 *
1484 * Configures collision distance and flow control for fiber and serdes links.
1485 * Upon successful setup, poll for link.
1486 **/
e1000_setup_fiber_serdes_link_82571(struct e1000_hw * hw)1487 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1488 {
1489 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1490
1491 switch (hw->mac.type) {
1492 case e1000_82571:
1493 case e1000_82572:
1494 /* If SerDes loopback mode is entered, there is no form
1495 * of reset to take the adapter out of that mode. So we
1496 * have to explicitly take the adapter out of loopback
1497 * mode. This prevents drivers from twiddling their thumbs
1498 * if another tool failed to take it out of loopback mode.
1499 */
1500 E1000_WRITE_REG(hw, E1000_SCTL,
1501 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1502 break;
1503 default:
1504 break;
1505 }
1506
1507 return e1000_setup_fiber_serdes_link_generic(hw);
1508 }
1509
1510 /**
1511 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1512 * @hw: pointer to the HW structure
1513 *
1514 * Reports the link state as up or down.
1515 *
1516 * If autonegotiation is supported by the link partner, the link state is
1517 * determined by the result of autonegotiation. This is the most likely case.
1518 * If autonegotiation is not supported by the link partner, and the link
1519 * has a valid signal, force the link up.
1520 *
1521 * The link state is represented internally here by 4 states:
1522 *
1523 * 1) down
1524 * 2) autoneg_progress
1525 * 3) autoneg_complete (the link successfully autonegotiated)
1526 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1527 *
1528 **/
e1000_check_for_serdes_link_82571(struct e1000_hw * hw)1529 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1530 {
1531 struct e1000_mac_info *mac = &hw->mac;
1532 u32 rxcw;
1533 u32 ctrl;
1534 u32 status;
1535 u32 txcw;
1536 u32 i;
1537 s32 ret_val = E1000_SUCCESS;
1538
1539 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1540
1541 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1542 status = E1000_READ_REG(hw, E1000_STATUS);
1543 E1000_READ_REG(hw, E1000_RXCW);
1544 /* SYNCH bit and IV bit are sticky */
1545 usec_delay(10);
1546 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1547
1548 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1549 /* Receiver is synchronized with no invalid bits. */
1550 switch (mac->serdes_link_state) {
1551 case e1000_serdes_link_autoneg_complete:
1552 if (!(status & E1000_STATUS_LU)) {
1553 /* We have lost link, retry autoneg before
1554 * reporting link failure
1555 */
1556 mac->serdes_link_state =
1557 e1000_serdes_link_autoneg_progress;
1558 mac->serdes_has_link = false;
1559 DEBUGOUT("AN_UP -> AN_PROG\n");
1560 } else {
1561 mac->serdes_has_link = true;
1562 }
1563 break;
1564
1565 case e1000_serdes_link_forced_up:
1566 /* If we are receiving /C/ ordered sets, re-enable
1567 * auto-negotiation in the TXCW register and disable
1568 * forced link in the Device Control register in an
1569 * attempt to auto-negotiate with our link partner.
1570 */
1571 if (rxcw & E1000_RXCW_C) {
1572 /* Enable autoneg, and unforce link up */
1573 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1574 E1000_WRITE_REG(hw, E1000_CTRL,
1575 (ctrl & ~E1000_CTRL_SLU));
1576 mac->serdes_link_state =
1577 e1000_serdes_link_autoneg_progress;
1578 mac->serdes_has_link = false;
1579 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1580 } else {
1581 mac->serdes_has_link = true;
1582 }
1583 break;
1584
1585 case e1000_serdes_link_autoneg_progress:
1586 if (rxcw & E1000_RXCW_C) {
1587 /* We received /C/ ordered sets, meaning the
1588 * link partner has autonegotiated, and we can
1589 * trust the Link Up (LU) status bit.
1590 */
1591 if (status & E1000_STATUS_LU) {
1592 mac->serdes_link_state =
1593 e1000_serdes_link_autoneg_complete;
1594 DEBUGOUT("AN_PROG -> AN_UP\n");
1595 mac->serdes_has_link = true;
1596 } else {
1597 /* Autoneg completed, but failed. */
1598 mac->serdes_link_state =
1599 e1000_serdes_link_down;
1600 DEBUGOUT("AN_PROG -> DOWN\n");
1601 }
1602 } else {
1603 /* The link partner did not autoneg.
1604 * Force link up and full duplex, and change
1605 * state to forced.
1606 */
1607 E1000_WRITE_REG(hw, E1000_TXCW,
1608 (mac->txcw & ~E1000_TXCW_ANE));
1609 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1610 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1611
1612 /* Configure Flow Control after link up. */
1613 ret_val =
1614 e1000_config_fc_after_link_up_generic(hw);
1615 if (ret_val) {
1616 DEBUGOUT("Error config flow control\n");
1617 break;
1618 }
1619 mac->serdes_link_state =
1620 e1000_serdes_link_forced_up;
1621 mac->serdes_has_link = true;
1622 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1623 }
1624 break;
1625
1626 case e1000_serdes_link_down:
1627 default:
1628 /* The link was down but the receiver has now gained
1629 * valid sync, so lets see if we can bring the link
1630 * up.
1631 */
1632 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1633 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1634 ~E1000_CTRL_SLU));
1635 mac->serdes_link_state =
1636 e1000_serdes_link_autoneg_progress;
1637 mac->serdes_has_link = false;
1638 DEBUGOUT("DOWN -> AN_PROG\n");
1639 break;
1640 }
1641 } else {
1642 if (!(rxcw & E1000_RXCW_SYNCH)) {
1643 mac->serdes_has_link = false;
1644 mac->serdes_link_state = e1000_serdes_link_down;
1645 DEBUGOUT("ANYSTATE -> DOWN\n");
1646 } else {
1647 /* Check several times, if SYNCH bit and CONFIG
1648 * bit both are consistently 1 then simply ignore
1649 * the IV bit and restart Autoneg
1650 */
1651 for (i = 0; i < AN_RETRY_COUNT; i++) {
1652 usec_delay(10);
1653 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1654 if ((rxcw & E1000_RXCW_SYNCH) &&
1655 (rxcw & E1000_RXCW_C))
1656 continue;
1657
1658 if (rxcw & E1000_RXCW_IV) {
1659 mac->serdes_has_link = false;
1660 mac->serdes_link_state =
1661 e1000_serdes_link_down;
1662 DEBUGOUT("ANYSTATE -> DOWN\n");
1663 break;
1664 }
1665 }
1666
1667 if (i == AN_RETRY_COUNT) {
1668 txcw = E1000_READ_REG(hw, E1000_TXCW);
1669 txcw |= E1000_TXCW_ANE;
1670 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1671 mac->serdes_link_state =
1672 e1000_serdes_link_autoneg_progress;
1673 mac->serdes_has_link = false;
1674 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1675 }
1676 }
1677 }
1678
1679 return ret_val;
1680 }
1681
1682 /**
1683 * e1000_valid_led_default_82571 - Verify a valid default LED config
1684 * @hw: pointer to the HW structure
1685 * @data: pointer to the NVM (EEPROM)
1686 *
1687 * Read the EEPROM for the current default LED configuration. If the
1688 * LED configuration is not valid, set to a valid LED configuration.
1689 **/
e1000_valid_led_default_82571(struct e1000_hw * hw,u16 * data)1690 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1691 {
1692 s32 ret_val;
1693
1694 DEBUGFUNC("e1000_valid_led_default_82571");
1695
1696 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1697 if (ret_val) {
1698 DEBUGOUT("NVM Read Error\n");
1699 return ret_val;
1700 }
1701
1702 switch (hw->mac.type) {
1703 case e1000_82573:
1704 case e1000_82574:
1705 case e1000_82583:
1706 if (*data == ID_LED_RESERVED_F746)
1707 *data = ID_LED_DEFAULT_82573;
1708 break;
1709 default:
1710 if (*data == ID_LED_RESERVED_0000 ||
1711 *data == ID_LED_RESERVED_FFFF)
1712 *data = ID_LED_DEFAULT;
1713 break;
1714 }
1715
1716 return E1000_SUCCESS;
1717 }
1718
1719 /**
1720 * e1000_get_laa_state_82571 - Get locally administered address state
1721 * @hw: pointer to the HW structure
1722 *
1723 * Retrieve and return the current locally administered address state.
1724 **/
e1000_get_laa_state_82571(struct e1000_hw * hw)1725 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1726 {
1727 DEBUGFUNC("e1000_get_laa_state_82571");
1728
1729 if (hw->mac.type != e1000_82571)
1730 return false;
1731
1732 return hw->dev_spec._82571.laa_is_present;
1733 }
1734
1735 /**
1736 * e1000_set_laa_state_82571 - Set locally administered address state
1737 * @hw: pointer to the HW structure
1738 * @state: enable/disable locally administered address
1739 *
1740 * Enable/Disable the current locally administered address state.
1741 **/
e1000_set_laa_state_82571(struct e1000_hw * hw,bool state)1742 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1743 {
1744 DEBUGFUNC("e1000_set_laa_state_82571");
1745
1746 if (hw->mac.type != e1000_82571)
1747 return;
1748
1749 hw->dev_spec._82571.laa_is_present = state;
1750
1751 /* If workaround is activated... */
1752 if (state)
1753 /* Hold a copy of the LAA in RAR[14] This is done so that
1754 * between the time RAR[0] gets clobbered and the time it
1755 * gets fixed, the actual LAA is in one of the RARs and no
1756 * incoming packets directed to this port are dropped.
1757 * Eventually the LAA will be in RAR[0] and RAR[14].
1758 */
1759 hw->mac.ops.rar_set(hw, hw->mac.addr,
1760 hw->mac.rar_entry_count - 1);
1761 return;
1762 }
1763
1764 /**
1765 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1766 * @hw: pointer to the HW structure
1767 *
1768 * Verifies that the EEPROM has completed the update. After updating the
1769 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1770 * the checksum fix is not implemented, we need to set the bit and update
1771 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1772 * we need to return bad checksum.
1773 **/
e1000_fix_nvm_checksum_82571(struct e1000_hw * hw)1774 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1775 {
1776 struct e1000_nvm_info *nvm = &hw->nvm;
1777 s32 ret_val;
1778 u16 data;
1779
1780 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1781
1782 if (nvm->type != e1000_nvm_flash_hw)
1783 return E1000_SUCCESS;
1784
1785 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1786 * 10h-12h. Checksum may need to be fixed.
1787 */
1788 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1789 if (ret_val)
1790 return ret_val;
1791
1792 if (!(data & 0x10)) {
1793 /* Read 0x23 and check bit 15. This bit is a 1
1794 * when the checksum has already been fixed. If
1795 * the checksum is still wrong and this bit is a
1796 * 1, we need to return bad checksum. Otherwise,
1797 * we need to set this bit to a 1 and update the
1798 * checksum.
1799 */
1800 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1801 if (ret_val)
1802 return ret_val;
1803
1804 if (!(data & 0x8000)) {
1805 data |= 0x8000;
1806 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1807 if (ret_val)
1808 return ret_val;
1809 ret_val = nvm->ops.update(hw);
1810 if (ret_val)
1811 return ret_val;
1812 }
1813 }
1814
1815 return E1000_SUCCESS;
1816 }
1817
1818
1819 /**
1820 * e1000_read_mac_addr_82571 - Read device MAC address
1821 * @hw: pointer to the HW structure
1822 **/
e1000_read_mac_addr_82571(struct e1000_hw * hw)1823 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1824 {
1825 DEBUGFUNC("e1000_read_mac_addr_82571");
1826
1827 if (hw->mac.type == e1000_82571) {
1828 s32 ret_val;
1829
1830 /* If there's an alternate MAC address place it in RAR0
1831 * so that it will override the Si installed default perm
1832 * address.
1833 */
1834 ret_val = e1000_check_alt_mac_addr_generic(hw);
1835 if (ret_val)
1836 return ret_val;
1837 }
1838
1839 return e1000_read_mac_addr_generic(hw);
1840 }
1841
1842 /**
1843 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1844 * @hw: pointer to the HW structure
1845 *
1846 * In the case of a PHY power down to save power, or to turn off link during a
1847 * driver unload, or wake on lan is not enabled, remove the link.
1848 **/
e1000_power_down_phy_copper_82571(struct e1000_hw * hw)1849 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1850 {
1851 struct e1000_phy_info *phy = &hw->phy;
1852 struct e1000_mac_info *mac = &hw->mac;
1853
1854 if (!phy->ops.check_reset_block)
1855 return;
1856
1857 /* If the management interface is not enabled, then power down */
1858 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1859 e1000_power_down_phy_copper(hw);
1860
1861 return;
1862 }
1863
1864 /**
1865 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1866 * @hw: pointer to the HW structure
1867 *
1868 * Clears the hardware counters by reading the counter registers.
1869 **/
e1000_clear_hw_cntrs_82571(struct e1000_hw * hw)1870 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1871 {
1872 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1873
1874 e1000_clear_hw_cntrs_base_generic(hw);
1875
1876 E1000_READ_REG(hw, E1000_PRC64);
1877 E1000_READ_REG(hw, E1000_PRC127);
1878 E1000_READ_REG(hw, E1000_PRC255);
1879 E1000_READ_REG(hw, E1000_PRC511);
1880 E1000_READ_REG(hw, E1000_PRC1023);
1881 E1000_READ_REG(hw, E1000_PRC1522);
1882 E1000_READ_REG(hw, E1000_PTC64);
1883 E1000_READ_REG(hw, E1000_PTC127);
1884 E1000_READ_REG(hw, E1000_PTC255);
1885 E1000_READ_REG(hw, E1000_PTC511);
1886 E1000_READ_REG(hw, E1000_PTC1023);
1887 E1000_READ_REG(hw, E1000_PTC1522);
1888
1889 E1000_READ_REG(hw, E1000_ALGNERRC);
1890 E1000_READ_REG(hw, E1000_RXERRC);
1891 E1000_READ_REG(hw, E1000_TNCRS);
1892 E1000_READ_REG(hw, E1000_CEXTERR);
1893 E1000_READ_REG(hw, E1000_TSCTC);
1894 E1000_READ_REG(hw, E1000_TSCTFC);
1895
1896 E1000_READ_REG(hw, E1000_MGTPRC);
1897 E1000_READ_REG(hw, E1000_MGTPDC);
1898 E1000_READ_REG(hw, E1000_MGTPTC);
1899
1900 E1000_READ_REG(hw, E1000_IAC);
1901 E1000_READ_REG(hw, E1000_ICRXOC);
1902
1903 E1000_READ_REG(hw, E1000_ICRXPTC);
1904 E1000_READ_REG(hw, E1000_ICRXATC);
1905 E1000_READ_REG(hw, E1000_ICTXPTC);
1906 E1000_READ_REG(hw, E1000_ICTXATC);
1907 E1000_READ_REG(hw, E1000_ICTXQEC);
1908 E1000_READ_REG(hw, E1000_ICTXQMTC);
1909 E1000_READ_REG(hw, E1000_ICRXDMTC);
1910 }
1911