xref: /linux/drivers/gpu/drm/i915/display/intel_crt.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Eric Anholt <eric@anholt.net>
25  */
26 
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35 
36 #include "i915_drv.h"
37 #include "i915_irq.h"
38 #include "i915_reg.h"
39 #include "intel_connector.h"
40 #include "intel_crt.h"
41 #include "intel_crt_regs.h"
42 #include "intel_crtc.h"
43 #include "intel_ddi.h"
44 #include "intel_ddi_buf_trans.h"
45 #include "intel_de.h"
46 #include "intel_display_driver.h"
47 #include "intel_display_types.h"
48 #include "intel_fdi.h"
49 #include "intel_fdi_regs.h"
50 #include "intel_fifo_underrun.h"
51 #include "intel_gmbus.h"
52 #include "intel_hotplug.h"
53 #include "intel_hotplug_irq.h"
54 #include "intel_load_detect.h"
55 #include "intel_pch_display.h"
56 #include "intel_pch_refclk.h"
57 
58 /* Here's the desired hotplug mode */
59 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE |			\
60 			   ADPA_CRT_HOTPLUG_PERIOD_128 |		\
61 			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
62 			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
63 			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
64 			   ADPA_CRT_HOTPLUG_VOLREF_325MV)
65 #define ADPA_HOTPLUG_MASK (ADPA_CRT_HOTPLUG_MONITOR_MASK |		\
66 			   ADPA_CRT_HOTPLUG_ENABLE |			\
67 			   ADPA_CRT_HOTPLUG_PERIOD_MASK |		\
68 			   ADPA_CRT_HOTPLUG_WARMUP_MASK |		\
69 			   ADPA_CRT_HOTPLUG_SAMPLE_MASK |		\
70 			   ADPA_CRT_HOTPLUG_VOLTAGE_MASK |		\
71 			   ADPA_CRT_HOTPLUG_VOLREF_MASK |		\
72 			   ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
73 
74 struct intel_crt {
75 	struct intel_encoder base;
76 	bool force_hotplug_required;
77 	i915_reg_t adpa_reg;
78 };
79 
intel_encoder_to_crt(struct intel_encoder * encoder)80 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
81 {
82 	return container_of(encoder, struct intel_crt, base);
83 }
84 
intel_attached_crt(struct intel_connector * connector)85 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
86 {
87 	return intel_encoder_to_crt(intel_attached_encoder(connector));
88 }
89 
intel_crt_port_enabled(struct intel_display * display,i915_reg_t adpa_reg,enum pipe * pipe)90 bool intel_crt_port_enabled(struct intel_display *display,
91 			    i915_reg_t adpa_reg, enum pipe *pipe)
92 {
93 	struct drm_i915_private *dev_priv = to_i915(display->drm);
94 	u32 val;
95 
96 	val = intel_de_read(display, adpa_reg);
97 
98 	/* asserts want to know the pipe even if the port is disabled */
99 	if (HAS_PCH_CPT(dev_priv))
100 		*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val);
101 	else
102 		*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val);
103 
104 	return val & ADPA_DAC_ENABLE;
105 }
106 
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)107 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
108 				   enum pipe *pipe)
109 {
110 	struct intel_display *display = to_intel_display(encoder);
111 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
112 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
113 	intel_wakeref_t wakeref;
114 	bool ret;
115 
116 	wakeref = intel_display_power_get_if_enabled(dev_priv,
117 						     encoder->power_domain);
118 	if (!wakeref)
119 		return false;
120 
121 	ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
122 
123 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
124 
125 	return ret;
126 }
127 
intel_crt_get_flags(struct intel_encoder * encoder)128 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
129 {
130 	struct intel_display *display = to_intel_display(encoder);
131 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
132 	u32 tmp, flags = 0;
133 
134 	tmp = intel_de_read(display, crt->adpa_reg);
135 
136 	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
137 		flags |= DRM_MODE_FLAG_PHSYNC;
138 	else
139 		flags |= DRM_MODE_FLAG_NHSYNC;
140 
141 	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
142 		flags |= DRM_MODE_FLAG_PVSYNC;
143 	else
144 		flags |= DRM_MODE_FLAG_NVSYNC;
145 
146 	return flags;
147 }
148 
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)149 static void intel_crt_get_config(struct intel_encoder *encoder,
150 				 struct intel_crtc_state *crtc_state)
151 {
152 	crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
153 
154 	crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
155 
156 	crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
157 }
158 
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)159 static void hsw_crt_get_config(struct intel_encoder *encoder,
160 			       struct intel_crtc_state *crtc_state)
161 {
162 	lpt_pch_get_config(crtc_state);
163 
164 	hsw_ddi_get_config(encoder, crtc_state);
165 
166 	crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
167 						DRM_MODE_FLAG_NHSYNC |
168 						DRM_MODE_FLAG_PVSYNC |
169 						DRM_MODE_FLAG_NVSYNC);
170 	crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
171 }
172 
173 /* Note: The caller is required to filter out dpms modes not supported by the
174  * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)175 static void intel_crt_set_dpms(struct intel_encoder *encoder,
176 			       const struct intel_crtc_state *crtc_state,
177 			       int mode)
178 {
179 	struct intel_display *display = to_intel_display(encoder);
180 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
181 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
182 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
183 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
184 	u32 adpa;
185 
186 	if (DISPLAY_VER(display) >= 5)
187 		adpa = ADPA_HOTPLUG_BITS;
188 	else
189 		adpa = 0;
190 
191 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
192 		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
193 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
194 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
195 
196 	/* For CPT allow 3 pipe config, for others just use A or B */
197 	if (HAS_PCH_LPT(dev_priv))
198 		; /* Those bits don't exist here */
199 	else if (HAS_PCH_CPT(dev_priv))
200 		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
201 	else
202 		adpa |= ADPA_PIPE_SEL(crtc->pipe);
203 
204 	if (!HAS_PCH_SPLIT(dev_priv))
205 		intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
206 
207 	switch (mode) {
208 	case DRM_MODE_DPMS_ON:
209 		adpa |= ADPA_DAC_ENABLE;
210 		break;
211 	case DRM_MODE_DPMS_STANDBY:
212 		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
213 		break;
214 	case DRM_MODE_DPMS_SUSPEND:
215 		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
216 		break;
217 	case DRM_MODE_DPMS_OFF:
218 		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
219 		break;
220 	}
221 
222 	intel_de_write(display, crt->adpa_reg, adpa);
223 }
224 
intel_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)225 static void intel_disable_crt(struct intel_atomic_state *state,
226 			      struct intel_encoder *encoder,
227 			      const struct intel_crtc_state *old_crtc_state,
228 			      const struct drm_connector_state *old_conn_state)
229 {
230 	intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
231 }
232 
pch_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)233 static void pch_disable_crt(struct intel_atomic_state *state,
234 			    struct intel_encoder *encoder,
235 			    const struct intel_crtc_state *old_crtc_state,
236 			    const struct drm_connector_state *old_conn_state)
237 {
238 }
239 
pch_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)240 static void pch_post_disable_crt(struct intel_atomic_state *state,
241 				 struct intel_encoder *encoder,
242 				 const struct intel_crtc_state *old_crtc_state,
243 				 const struct drm_connector_state *old_conn_state)
244 {
245 	intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
246 }
247 
hsw_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)248 static void hsw_disable_crt(struct intel_atomic_state *state,
249 			    struct intel_encoder *encoder,
250 			    const struct intel_crtc_state *old_crtc_state,
251 			    const struct drm_connector_state *old_conn_state)
252 {
253 	struct intel_display *display = to_intel_display(encoder);
254 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
255 
256 	drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
257 
258 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
259 }
260 
hsw_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)261 static void hsw_post_disable_crt(struct intel_atomic_state *state,
262 				 struct intel_encoder *encoder,
263 				 const struct intel_crtc_state *old_crtc_state,
264 				 const struct drm_connector_state *old_conn_state)
265 {
266 	struct intel_display *display = to_intel_display(encoder);
267 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
268 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
269 
270 	intel_crtc_vblank_off(old_crtc_state);
271 
272 	intel_disable_transcoder(old_crtc_state);
273 
274 	intel_ddi_disable_transcoder_func(old_crtc_state);
275 
276 	ilk_pfit_disable(old_crtc_state);
277 
278 	intel_ddi_disable_transcoder_clock(old_crtc_state);
279 
280 	pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
281 
282 	lpt_pch_disable(state, crtc);
283 
284 	hsw_fdi_disable(encoder);
285 
286 	drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
287 
288 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
289 }
290 
hsw_pre_pll_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)291 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
292 				   struct intel_encoder *encoder,
293 				   const struct intel_crtc_state *crtc_state,
294 				   const struct drm_connector_state *conn_state)
295 {
296 	struct intel_display *display = to_intel_display(encoder);
297 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
298 
299 	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
300 
301 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
302 }
303 
hsw_pre_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)304 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
305 			       struct intel_encoder *encoder,
306 			       const struct intel_crtc_state *crtc_state,
307 			       const struct drm_connector_state *conn_state)
308 {
309 	struct intel_display *display = to_intel_display(encoder);
310 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
311 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
312 	enum pipe pipe = crtc->pipe;
313 
314 	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
315 
316 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
317 
318 	hsw_fdi_link_train(encoder, crtc_state);
319 
320 	intel_ddi_enable_transcoder_clock(encoder, crtc_state);
321 }
322 
hsw_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)323 static void hsw_enable_crt(struct intel_atomic_state *state,
324 			   struct intel_encoder *encoder,
325 			   const struct intel_crtc_state *crtc_state,
326 			   const struct drm_connector_state *conn_state)
327 {
328 	struct intel_display *display = to_intel_display(encoder);
329 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
331 	enum pipe pipe = crtc->pipe;
332 
333 	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
334 
335 	intel_ddi_enable_transcoder_func(encoder, crtc_state);
336 
337 	intel_enable_transcoder(crtc_state);
338 
339 	lpt_pch_enable(state, crtc);
340 
341 	intel_crtc_vblank_on(crtc_state);
342 
343 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
344 
345 	intel_crtc_wait_for_next_vblank(crtc);
346 	intel_crtc_wait_for_next_vblank(crtc);
347 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
348 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
349 }
350 
intel_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)351 static void intel_enable_crt(struct intel_atomic_state *state,
352 			     struct intel_encoder *encoder,
353 			     const struct intel_crtc_state *crtc_state,
354 			     const struct drm_connector_state *conn_state)
355 {
356 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
357 }
358 
359 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)360 intel_crt_mode_valid(struct drm_connector *connector,
361 		     struct drm_display_mode *mode)
362 {
363 	struct intel_display *display = to_intel_display(connector->dev);
364 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
365 	int max_dotclk = display->cdclk.max_dotclk_freq;
366 	enum drm_mode_status status;
367 	int max_clock;
368 
369 	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
370 	if (status != MODE_OK)
371 		return status;
372 
373 	if (mode->clock < 25000)
374 		return MODE_CLOCK_LOW;
375 
376 	if (HAS_PCH_LPT(dev_priv))
377 		max_clock = 180000;
378 	else if (IS_VALLEYVIEW(dev_priv))
379 		/*
380 		 * 270 MHz due to current DPLL limits,
381 		 * DAC limit supposedly 355 MHz.
382 		 */
383 		max_clock = 270000;
384 	else if (IS_DISPLAY_VER(display, 3, 4))
385 		max_clock = 400000;
386 	else
387 		max_clock = 350000;
388 	if (mode->clock > max_clock)
389 		return MODE_CLOCK_HIGH;
390 
391 	if (mode->clock > max_dotclk)
392 		return MODE_CLOCK_HIGH;
393 
394 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
395 	if (HAS_PCH_LPT(dev_priv) &&
396 	    ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
397 		return MODE_CLOCK_HIGH;
398 
399 	/* HSW/BDW FDI limited to 4k */
400 	if (mode->hdisplay > 4096)
401 		return MODE_H_ILLEGAL;
402 
403 	return MODE_OK;
404 }
405 
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)406 static int intel_crt_compute_config(struct intel_encoder *encoder,
407 				    struct intel_crtc_state *crtc_state,
408 				    struct drm_connector_state *conn_state)
409 {
410 	struct drm_display_mode *adjusted_mode =
411 		&crtc_state->hw.adjusted_mode;
412 
413 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
414 		return -EINVAL;
415 
416 	crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
417 	crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
418 
419 	return 0;
420 }
421 
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)422 static int pch_crt_compute_config(struct intel_encoder *encoder,
423 				  struct intel_crtc_state *crtc_state,
424 				  struct drm_connector_state *conn_state)
425 {
426 	struct drm_display_mode *adjusted_mode =
427 		&crtc_state->hw.adjusted_mode;
428 
429 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
430 		return -EINVAL;
431 
432 	crtc_state->has_pch_encoder = true;
433 	if (!intel_fdi_compute_pipe_bpp(crtc_state))
434 		return -EINVAL;
435 
436 	crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
437 
438 	return 0;
439 }
440 
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)441 static int hsw_crt_compute_config(struct intel_encoder *encoder,
442 				  struct intel_crtc_state *crtc_state,
443 				  struct drm_connector_state *conn_state)
444 {
445 	struct intel_display *display = to_intel_display(encoder);
446 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
447 	struct drm_display_mode *adjusted_mode =
448 		&crtc_state->hw.adjusted_mode;
449 
450 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
451 		return -EINVAL;
452 
453 	/* HSW/BDW FDI limited to 4k */
454 	if (adjusted_mode->crtc_hdisplay > 4096 ||
455 	    adjusted_mode->crtc_hblank_start > 4096)
456 		return -EINVAL;
457 
458 	crtc_state->has_pch_encoder = true;
459 	if (!intel_fdi_compute_pipe_bpp(crtc_state))
460 		return -EINVAL;
461 
462 	crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
463 
464 	/* LPT FDI RX only supports 8bpc. */
465 	if (HAS_PCH_LPT(dev_priv)) {
466 		/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
467 		if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) {
468 			drm_dbg_kms(display->drm,
469 				    "LPT only supports 24bpp\n");
470 			return -EINVAL;
471 		}
472 
473 		crtc_state->pipe_bpp = 24;
474 	}
475 
476 	/* FDI must always be 2.7 GHz */
477 	crtc_state->port_clock = 135000 * 2;
478 
479 	crtc_state->enhanced_framing = true;
480 
481 	adjusted_mode->crtc_clock = lpt_iclkip(crtc_state);
482 
483 	return 0;
484 }
485 
ilk_crt_detect_hotplug(struct drm_connector * connector)486 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
487 {
488 	struct intel_display *display = to_intel_display(connector->dev);
489 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
490 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
491 	u32 adpa;
492 	bool ret;
493 
494 	/* The first time through, trigger an explicit detection cycle */
495 	if (crt->force_hotplug_required) {
496 		bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
497 		u32 save_adpa;
498 
499 		crt->force_hotplug_required = false;
500 
501 		save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
502 		drm_dbg_kms(display->drm,
503 			    "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
504 
505 		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
506 		if (turn_off_dac)
507 			adpa &= ~ADPA_DAC_ENABLE;
508 
509 		intel_de_write(display, crt->adpa_reg, adpa);
510 
511 		if (intel_de_wait_for_clear(display,
512 					    crt->adpa_reg,
513 					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
514 					    1000))
515 			drm_dbg_kms(display->drm,
516 				    "timed out waiting for FORCE_TRIGGER");
517 
518 		if (turn_off_dac) {
519 			intel_de_write(display, crt->adpa_reg, save_adpa);
520 			intel_de_posting_read(display, crt->adpa_reg);
521 		}
522 	}
523 
524 	/* Check the status to see if both blue and green are on now */
525 	adpa = intel_de_read(display, crt->adpa_reg);
526 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
527 		ret = true;
528 	else
529 		ret = false;
530 	drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
531 		    adpa, ret);
532 
533 	return ret;
534 }
535 
valleyview_crt_detect_hotplug(struct drm_connector * connector)536 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
537 {
538 	struct intel_display *display = to_intel_display(connector->dev);
539 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
540 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
541 	bool reenable_hpd;
542 	u32 adpa;
543 	bool ret;
544 	u32 save_adpa;
545 
546 	/*
547 	 * Doing a force trigger causes a hpd interrupt to get sent, which can
548 	 * get us stuck in a loop if we're polling:
549 	 *  - We enable power wells and reset the ADPA
550 	 *  - output_poll_exec does force probe on VGA, triggering a hpd
551 	 *  - HPD handler waits for poll to unlock dev->mode_config.mutex
552 	 *  - output_poll_exec shuts off the ADPA, unlocks
553 	 *    dev->mode_config.mutex
554 	 *  - HPD handler runs, resets ADPA and brings us back to the start
555 	 *
556 	 * Just disable HPD interrupts here to prevent this
557 	 */
558 	reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
559 
560 	save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
561 	drm_dbg_kms(display->drm,
562 		    "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
563 
564 	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
565 
566 	intel_de_write(display, crt->adpa_reg, adpa);
567 
568 	if (intel_de_wait_for_clear(display, crt->adpa_reg,
569 				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
570 		drm_dbg_kms(display->drm,
571 			    "timed out waiting for FORCE_TRIGGER");
572 		intel_de_write(display, crt->adpa_reg, save_adpa);
573 	}
574 
575 	/* Check the status to see if both blue and green are on now */
576 	adpa = intel_de_read(display, crt->adpa_reg);
577 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
578 		ret = true;
579 	else
580 		ret = false;
581 
582 	drm_dbg_kms(display->drm,
583 		    "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
584 
585 	if (reenable_hpd)
586 		intel_hpd_enable(dev_priv, crt->base.hpd_pin);
587 
588 	return ret;
589 }
590 
intel_crt_detect_hotplug(struct drm_connector * connector)591 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
592 {
593 	struct intel_display *display = to_intel_display(connector->dev);
594 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
595 	u32 stat;
596 	bool ret = false;
597 	int i, tries = 0;
598 
599 	if (HAS_PCH_SPLIT(dev_priv))
600 		return ilk_crt_detect_hotplug(connector);
601 
602 	if (IS_VALLEYVIEW(dev_priv))
603 		return valleyview_crt_detect_hotplug(connector);
604 
605 	/*
606 	 * On 4 series desktop, CRT detect sequence need to be done twice
607 	 * to get a reliable result.
608 	 */
609 
610 	if (IS_G45(dev_priv))
611 		tries = 2;
612 	else
613 		tries = 1;
614 
615 	for (i = 0; i < tries ; i++) {
616 		/* turn on the FORCE_DETECT */
617 		i915_hotplug_interrupt_update(dev_priv,
618 					      CRT_HOTPLUG_FORCE_DETECT,
619 					      CRT_HOTPLUG_FORCE_DETECT);
620 		/* wait for FORCE_DETECT to go off */
621 		if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
622 					    CRT_HOTPLUG_FORCE_DETECT, 1000))
623 			drm_dbg_kms(display->drm,
624 				    "timed out waiting for FORCE_DETECT to go off");
625 	}
626 
627 	stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
628 	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
629 		ret = true;
630 
631 	/* clear the interrupt we just generated, if any */
632 	intel_de_write(display, PORT_HOTPLUG_STAT(display),
633 		       CRT_HOTPLUG_INT_STATUS);
634 
635 	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
636 
637 	return ret;
638 }
639 
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * ddc)640 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
641 						 struct i2c_adapter *ddc)
642 {
643 	const struct drm_edid *drm_edid;
644 
645 	drm_edid = drm_edid_read_ddc(connector, ddc);
646 
647 	if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
648 		drm_dbg_kms(connector->dev,
649 			    "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
650 		intel_gmbus_force_bit(ddc, true);
651 		drm_edid = drm_edid_read_ddc(connector, ddc);
652 		intel_gmbus_force_bit(ddc, false);
653 	}
654 
655 	return drm_edid;
656 }
657 
658 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * ddc)659 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
660 				   struct i2c_adapter *ddc)
661 {
662 	const struct drm_edid *drm_edid;
663 	int ret;
664 
665 	drm_edid = intel_crt_get_edid(connector, ddc);
666 	if (!drm_edid)
667 		return 0;
668 
669 	ret = intel_connector_update_modes(connector, drm_edid);
670 
671 	drm_edid_free(drm_edid);
672 
673 	return ret;
674 }
675 
intel_crt_detect_ddc(struct drm_connector * connector)676 static bool intel_crt_detect_ddc(struct drm_connector *connector)
677 {
678 	struct intel_display *display = to_intel_display(connector->dev);
679 	const struct drm_edid *drm_edid;
680 	bool ret = false;
681 
682 	drm_edid = intel_crt_get_edid(connector, connector->ddc);
683 
684 	if (drm_edid) {
685 		/*
686 		 * This may be a DVI-I connector with a shared DDC
687 		 * link between analog and digital outputs, so we
688 		 * have to check the EDID input spec of the attached device.
689 		 */
690 		if (drm_edid_is_digital(drm_edid)) {
691 			drm_dbg_kms(display->drm,
692 				    "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
693 		} else {
694 			drm_dbg_kms(display->drm,
695 				    "CRT detected via DDC:0x50 [EDID]\n");
696 			ret = true;
697 		}
698 	} else {
699 		drm_dbg_kms(display->drm,
700 			    "CRT not detected via DDC:0x50 [no valid EDID found]\n");
701 	}
702 
703 	drm_edid_free(drm_edid);
704 
705 	return ret;
706 }
707 
708 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,enum pipe pipe)709 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
710 {
711 	struct intel_display *display = to_intel_display(&crt->base);
712 	enum transcoder cpu_transcoder = (enum transcoder)pipe;
713 	u32 save_bclrpat;
714 	u32 save_vtotal;
715 	u32 vtotal, vactive;
716 	u32 vsample;
717 	u32 vblank, vblank_start, vblank_end;
718 	u32 dsl;
719 	u8 st00;
720 	enum drm_connector_status status;
721 
722 	drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
723 
724 	save_bclrpat = intel_de_read(display,
725 				     BCLRPAT(display, cpu_transcoder));
726 	save_vtotal = intel_de_read(display,
727 				    TRANS_VTOTAL(display, cpu_transcoder));
728 	vblank = intel_de_read(display,
729 			       TRANS_VBLANK(display, cpu_transcoder));
730 
731 	vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
732 	vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
733 
734 	vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
735 	vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
736 
737 	/* Set the border color to purple. */
738 	intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
739 
740 	if (DISPLAY_VER(display) != 2) {
741 		u32 transconf = intel_de_read(display,
742 					      TRANSCONF(display, cpu_transcoder));
743 
744 		intel_de_write(display, TRANSCONF(display, cpu_transcoder),
745 			       transconf | TRANSCONF_FORCE_BORDER);
746 		intel_de_posting_read(display,
747 				      TRANSCONF(display, cpu_transcoder));
748 		/* Wait for next Vblank to substitue
749 		 * border color for Color info */
750 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
751 		st00 = intel_de_read8(display, _VGA_MSR_WRITE);
752 		status = ((st00 & (1 << 4)) != 0) ?
753 			connector_status_connected :
754 			connector_status_disconnected;
755 
756 		intel_de_write(display, TRANSCONF(display, cpu_transcoder),
757 			       transconf);
758 	} else {
759 		bool restore_vblank = false;
760 		int count, detect;
761 
762 		/*
763 		* If there isn't any border, add some.
764 		* Yes, this will flicker
765 		*/
766 		if (vblank_start <= vactive && vblank_end >= vtotal) {
767 			u32 vsync = intel_de_read(display,
768 						  TRANS_VSYNC(display, cpu_transcoder));
769 			u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
770 
771 			vblank_start = vsync_start;
772 			intel_de_write(display,
773 				       TRANS_VBLANK(display, cpu_transcoder),
774 				       VBLANK_START(vblank_start - 1) |
775 				       VBLANK_END(vblank_end - 1));
776 			restore_vblank = true;
777 		}
778 		/* sample in the vertical border, selecting the larger one */
779 		if (vblank_start - vactive >= vtotal - vblank_end)
780 			vsample = (vblank_start + vactive) >> 1;
781 		else
782 			vsample = (vtotal + vblank_end) >> 1;
783 
784 		/*
785 		 * Wait for the border to be displayed
786 		 */
787 		while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
788 			;
789 		while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
790 			;
791 		/*
792 		 * Watch ST00 for an entire scanline
793 		 */
794 		detect = 0;
795 		count = 0;
796 		do {
797 			count++;
798 			/* Read the ST00 VGA status register */
799 			st00 = intel_de_read8(display, _VGA_MSR_WRITE);
800 			if (st00 & (1 << 4))
801 				detect++;
802 		} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
803 
804 		/* restore vblank if necessary */
805 		if (restore_vblank)
806 			intel_de_write(display,
807 				       TRANS_VBLANK(display, cpu_transcoder),
808 				       vblank);
809 		/*
810 		 * If more than 3/4 of the scanline detected a monitor,
811 		 * then it is assumed to be present. This works even on i830,
812 		 * where there isn't any way to force the border color across
813 		 * the screen
814 		 */
815 		status = detect * 4 > count * 3 ?
816 			 connector_status_connected :
817 			 connector_status_disconnected;
818 	}
819 
820 	/* Restore previous settings */
821 	intel_de_write(display, BCLRPAT(display, cpu_transcoder),
822 		       save_bclrpat);
823 
824 	return status;
825 }
826 
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)827 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
828 {
829 	DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
830 	return 1;
831 }
832 
833 static const struct dmi_system_id intel_spurious_crt_detect[] = {
834 	{
835 		.callback = intel_spurious_crt_detect_dmi_callback,
836 		.ident = "ACER ZGB",
837 		.matches = {
838 			DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
839 			DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
840 		},
841 	},
842 	{
843 		.callback = intel_spurious_crt_detect_dmi_callback,
844 		.ident = "Intel DZ77BH-55K",
845 		.matches = {
846 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
847 			DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
848 		},
849 	},
850 	{ }
851 };
852 
853 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)854 intel_crt_detect(struct drm_connector *connector,
855 		 struct drm_modeset_acquire_ctx *ctx,
856 		 bool force)
857 {
858 	struct intel_display *display = to_intel_display(connector->dev);
859 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
860 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
861 	struct intel_encoder *encoder = &crt->base;
862 	struct drm_atomic_state *state;
863 	intel_wakeref_t wakeref;
864 	int status;
865 
866 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
867 		    connector->base.id, connector->name,
868 		    force);
869 
870 	if (!intel_display_device_enabled(display))
871 		return connector_status_disconnected;
872 
873 	if (!intel_display_driver_check_access(display))
874 		return connector->status;
875 
876 	if (display->params.load_detect_test) {
877 		wakeref = intel_display_power_get(dev_priv, encoder->power_domain);
878 		goto load_detect;
879 	}
880 
881 	/* Skip machines without VGA that falsely report hotplug events */
882 	if (dmi_check_system(intel_spurious_crt_detect))
883 		return connector_status_disconnected;
884 
885 	wakeref = intel_display_power_get(dev_priv, encoder->power_domain);
886 
887 	if (I915_HAS_HOTPLUG(display)) {
888 		/* We can not rely on the HPD pin always being correctly wired
889 		 * up, for example many KVM do not pass it through, and so
890 		 * only trust an assertion that the monitor is connected.
891 		 */
892 		if (intel_crt_detect_hotplug(connector)) {
893 			drm_dbg_kms(display->drm,
894 				    "CRT detected via hotplug\n");
895 			status = connector_status_connected;
896 			goto out;
897 		} else
898 			drm_dbg_kms(display->drm,
899 				    "CRT not detected via hotplug\n");
900 	}
901 
902 	if (intel_crt_detect_ddc(connector)) {
903 		status = connector_status_connected;
904 		goto out;
905 	}
906 
907 	/* Load detection is broken on HPD capable machines. Whoever wants a
908 	 * broken monitor (without edid) to work behind a broken kvm (that fails
909 	 * to have the right resistors for HP detection) needs to fix this up.
910 	 * For now just bail out. */
911 	if (I915_HAS_HOTPLUG(display)) {
912 		status = connector_status_disconnected;
913 		goto out;
914 	}
915 
916 load_detect:
917 	if (!force) {
918 		status = connector->status;
919 		goto out;
920 	}
921 
922 	/* for pre-945g platforms use load detect */
923 	state = intel_load_detect_get_pipe(connector, ctx);
924 	if (IS_ERR(state)) {
925 		status = PTR_ERR(state);
926 	} else if (!state) {
927 		status = connector_status_unknown;
928 	} else {
929 		if (intel_crt_detect_ddc(connector))
930 			status = connector_status_connected;
931 		else if (DISPLAY_VER(display) < 4)
932 			status = intel_crt_load_detect(crt,
933 				to_intel_crtc(connector->state->crtc)->pipe);
934 		else if (display->params.load_detect_test)
935 			status = connector_status_disconnected;
936 		else
937 			status = connector_status_unknown;
938 		intel_load_detect_release_pipe(connector, state, ctx);
939 	}
940 
941 out:
942 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
943 
944 	return status;
945 }
946 
intel_crt_get_modes(struct drm_connector * connector)947 static int intel_crt_get_modes(struct drm_connector *connector)
948 {
949 	struct intel_display *display = to_intel_display(connector->dev);
950 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
951 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
952 	struct intel_encoder *encoder = &crt->base;
953 	intel_wakeref_t wakeref;
954 	struct i2c_adapter *ddc;
955 	int ret;
956 
957 	if (!intel_display_driver_check_access(display))
958 		return drm_edid_connector_add_modes(connector);
959 
960 	wakeref = intel_display_power_get(dev_priv, encoder->power_domain);
961 
962 	ret = intel_crt_ddc_get_modes(connector, connector->ddc);
963 	if (ret || !IS_G4X(dev_priv))
964 		goto out;
965 
966 	/* Try to probe digital port for output in DVI-I -> VGA mode. */
967 	ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
968 	ret = intel_crt_ddc_get_modes(connector, ddc);
969 
970 out:
971 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
972 
973 	return ret;
974 }
975 
intel_crt_reset(struct drm_encoder * encoder)976 void intel_crt_reset(struct drm_encoder *encoder)
977 {
978 	struct intel_display *display = to_intel_display(encoder->dev);
979 	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
980 
981 	if (DISPLAY_VER(display) >= 5) {
982 		u32 adpa;
983 
984 		adpa = intel_de_read(display, crt->adpa_reg);
985 		adpa &= ~ADPA_HOTPLUG_MASK;
986 		adpa |= ADPA_HOTPLUG_BITS;
987 		intel_de_write(display, crt->adpa_reg, adpa);
988 		intel_de_posting_read(display, crt->adpa_reg);
989 
990 		drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
991 		crt->force_hotplug_required = true;
992 	}
993 
994 }
995 
996 /*
997  * Routines for controlling stuff on the analog port
998  */
999 
1000 static const struct drm_connector_funcs intel_crt_connector_funcs = {
1001 	.fill_modes = drm_helper_probe_single_connector_modes,
1002 	.late_register = intel_connector_register,
1003 	.early_unregister = intel_connector_unregister,
1004 	.destroy = intel_connector_destroy,
1005 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1006 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1007 };
1008 
1009 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
1010 	.detect_ctx = intel_crt_detect,
1011 	.mode_valid = intel_crt_mode_valid,
1012 	.get_modes = intel_crt_get_modes,
1013 };
1014 
1015 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
1016 	.reset = intel_crt_reset,
1017 	.destroy = intel_encoder_destroy,
1018 };
1019 
intel_crt_init(struct intel_display * display)1020 void intel_crt_init(struct intel_display *display)
1021 {
1022 	struct drm_i915_private *dev_priv = to_i915(display->drm);
1023 	struct intel_connector *connector;
1024 	struct intel_crt *crt;
1025 	i915_reg_t adpa_reg;
1026 	u8 ddc_pin;
1027 	u32 adpa;
1028 
1029 	if (HAS_PCH_SPLIT(dev_priv))
1030 		adpa_reg = PCH_ADPA;
1031 	else if (IS_VALLEYVIEW(dev_priv))
1032 		adpa_reg = VLV_ADPA;
1033 	else
1034 		adpa_reg = ADPA;
1035 
1036 	adpa = intel_de_read(display, adpa_reg);
1037 	if ((adpa & ADPA_DAC_ENABLE) == 0) {
1038 		/*
1039 		 * On some machines (some IVB at least) CRT can be
1040 		 * fused off, but there's no known fuse bit to
1041 		 * indicate that. On these machine the ADPA register
1042 		 * works normally, except the DAC enable bit won't
1043 		 * take. So the only way to tell is attempt to enable
1044 		 * it and see what happens.
1045 		 */
1046 		intel_de_write(display, adpa_reg,
1047 			       adpa | ADPA_DAC_ENABLE |
1048 			       ADPA_HSYNC_CNTL_DISABLE |
1049 			       ADPA_VSYNC_CNTL_DISABLE);
1050 		if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1051 			return;
1052 		intel_de_write(display, adpa_reg, adpa);
1053 	}
1054 
1055 	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1056 	if (!crt)
1057 		return;
1058 
1059 	connector = intel_connector_alloc();
1060 	if (!connector) {
1061 		kfree(crt);
1062 		return;
1063 	}
1064 
1065 	ddc_pin = display->vbt.crt_ddc_pin;
1066 
1067 	drm_connector_init_with_ddc(display->drm, &connector->base,
1068 				    &intel_crt_connector_funcs,
1069 				    DRM_MODE_CONNECTOR_VGA,
1070 				    intel_gmbus_get_adapter(display, ddc_pin));
1071 
1072 	drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
1073 			 DRM_MODE_ENCODER_DAC, "CRT");
1074 
1075 	intel_connector_attach_encoder(connector, &crt->base);
1076 
1077 	crt->base.type = INTEL_OUTPUT_ANALOG;
1078 	crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1079 	if (IS_I830(dev_priv))
1080 		crt->base.pipe_mask = BIT(PIPE_A);
1081 	else
1082 		crt->base.pipe_mask = ~0;
1083 
1084 	if (DISPLAY_VER(display) != 2)
1085 		connector->base.interlace_allowed = true;
1086 
1087 	crt->adpa_reg = adpa_reg;
1088 
1089 	crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1090 
1091 	if (I915_HAS_HOTPLUG(display) &&
1092 	    !dmi_check_system(intel_spurious_crt_detect)) {
1093 		crt->base.hpd_pin = HPD_CRT;
1094 		crt->base.hotplug = intel_encoder_hotplug;
1095 		connector->polled = DRM_CONNECTOR_POLL_HPD;
1096 	} else {
1097 		connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1098 	}
1099 	connector->base.polled = connector->polled;
1100 
1101 	if (HAS_DDI(display)) {
1102 		assert_port_valid(dev_priv, PORT_E);
1103 
1104 		crt->base.port = PORT_E;
1105 		crt->base.get_config = hsw_crt_get_config;
1106 		crt->base.get_hw_state = intel_ddi_get_hw_state;
1107 		crt->base.compute_config = hsw_crt_compute_config;
1108 		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1109 		crt->base.pre_enable = hsw_pre_enable_crt;
1110 		crt->base.enable = hsw_enable_crt;
1111 		crt->base.disable = hsw_disable_crt;
1112 		crt->base.post_disable = hsw_post_disable_crt;
1113 		crt->base.enable_clock = hsw_ddi_enable_clock;
1114 		crt->base.disable_clock = hsw_ddi_disable_clock;
1115 		crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1116 
1117 		intel_ddi_buf_trans_init(&crt->base);
1118 	} else {
1119 		if (HAS_PCH_SPLIT(dev_priv)) {
1120 			crt->base.compute_config = pch_crt_compute_config;
1121 			crt->base.disable = pch_disable_crt;
1122 			crt->base.post_disable = pch_post_disable_crt;
1123 		} else {
1124 			crt->base.compute_config = intel_crt_compute_config;
1125 			crt->base.disable = intel_disable_crt;
1126 		}
1127 		crt->base.port = PORT_NONE;
1128 		crt->base.get_config = intel_crt_get_config;
1129 		crt->base.get_hw_state = intel_crt_get_hw_state;
1130 		crt->base.enable = intel_enable_crt;
1131 	}
1132 	connector->get_hw_state = intel_connector_get_hw_state;
1133 
1134 	drm_connector_helper_add(&connector->base, &intel_crt_connector_helper_funcs);
1135 
1136 	/*
1137 	 * TODO: find a proper way to discover whether we need to set the the
1138 	 * polarity and link reversal bits or not, instead of relying on the
1139 	 * BIOS.
1140 	 */
1141 	if (HAS_PCH_LPT(dev_priv)) {
1142 		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1143 				 FDI_RX_LINK_REVERSAL_OVERRIDE;
1144 
1145 		display->fdi.rx_config = intel_de_read(display,
1146 						       FDI_RX_CTL(PIPE_A)) & fdi_config;
1147 	}
1148 
1149 	intel_crt_reset(&crt->base.base);
1150 }
1151