1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/devfreq.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interconnect.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
18
19 #include <soc/qcom/ice.h>
20
21 #include <ufs/ufshcd.h>
22 #include <ufs/ufshci.h>
23 #include <ufs/ufs_quirks.h>
24 #include <ufs/unipro.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
27
28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
29 #define MCQ_QCFGPTR_UNIT 0x200
30 #define MCQ_SQATTR_OFFSET(c) \
31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
32 #define MCQ_QCFG_SIZE 0x40
33
34 enum {
35 TSTBUS_UAWM,
36 TSTBUS_UARM,
37 TSTBUS_TXUC,
38 TSTBUS_RXUC,
39 TSTBUS_DFC,
40 TSTBUS_TRLUT,
41 TSTBUS_TMRLUT,
42 TSTBUS_OCSC,
43 TSTBUS_UTP_HCI,
44 TSTBUS_COMBINED,
45 TSTBUS_WRAPPER,
46 TSTBUS_UNIPRO,
47 TSTBUS_MAX,
48 };
49
50 #define QCOM_UFS_MAX_GEAR 5
51 #define QCOM_UFS_MAX_LANE 2
52
53 enum {
54 MODE_MIN,
55 MODE_PWM,
56 MODE_HS_RA,
57 MODE_HS_RB,
58 MODE_MAX,
59 };
60
61 static const struct __ufs_qcom_bw_table {
62 u32 mem_bw;
63 u32 cfg_bw;
64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
70 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 },
71 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
72 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
73 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
74 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
75 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 },
76 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
77 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
78 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
79 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
80 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
81 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
82 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
83 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
84 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
85 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
90 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
91 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
92 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
93 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
94 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
95 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
96 [MODE_MAX][0][0] = { 7643136, 819200 },
97 };
98
99 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
100 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
101
rcdev_to_ufs_host(struct reset_controller_dev * rcd)102 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
103 {
104 return container_of(rcd, struct ufs_qcom_host, rcdev);
105 }
106
107 #ifdef CONFIG_SCSI_UFS_CRYPTO
108
ufs_qcom_ice_enable(struct ufs_qcom_host * host)109 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
110 {
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
112 qcom_ice_enable(host->ice);
113 }
114
ufs_qcom_ice_init(struct ufs_qcom_host * host)115 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
116 {
117 struct ufs_hba *hba = host->hba;
118 struct device *dev = hba->dev;
119 struct qcom_ice *ice;
120
121 ice = of_qcom_ice_get(dev);
122 if (ice == ERR_PTR(-EOPNOTSUPP)) {
123 dev_warn(dev, "Disabling inline encryption support\n");
124 ice = NULL;
125 }
126
127 if (IS_ERR_OR_NULL(ice))
128 return PTR_ERR_OR_ZERO(ice);
129
130 host->ice = ice;
131 hba->caps |= UFSHCD_CAP_CRYPTO;
132
133 return 0;
134 }
135
ufs_qcom_ice_resume(struct ufs_qcom_host * host)136 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
137 {
138 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
139 return qcom_ice_resume(host->ice);
140
141 return 0;
142 }
143
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)144 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
145 {
146 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
147 return qcom_ice_suspend(host->ice);
148
149 return 0;
150 }
151
ufs_qcom_ice_program_key(struct ufs_hba * hba,const union ufs_crypto_cfg_entry * cfg,int slot)152 static int ufs_qcom_ice_program_key(struct ufs_hba *hba,
153 const union ufs_crypto_cfg_entry *cfg,
154 int slot)
155 {
156 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
157 union ufs_crypto_cap_entry cap;
158 bool config_enable =
159 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE;
160
161 /* Only AES-256-XTS has been tested so far. */
162 cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
163 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
164 cap.key_size != UFS_CRYPTO_KEY_SIZE_256)
165 return -EOPNOTSUPP;
166
167 if (config_enable)
168 return qcom_ice_program_key(host->ice,
169 QCOM_ICE_CRYPTO_ALG_AES_XTS,
170 QCOM_ICE_CRYPTO_KEY_SIZE_256,
171 cfg->crypto_key,
172 cfg->data_unit_size, slot);
173 else
174 return qcom_ice_evict_key(host->ice, slot);
175 }
176
177 #else
178
179 #define ufs_qcom_ice_program_key NULL
180
ufs_qcom_ice_enable(struct ufs_qcom_host * host)181 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
182 {
183 }
184
ufs_qcom_ice_init(struct ufs_qcom_host * host)185 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
186 {
187 return 0;
188 }
189
ufs_qcom_ice_resume(struct ufs_qcom_host * host)190 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
191 {
192 return 0;
193 }
194
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)195 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
196 {
197 return 0;
198 }
199 #endif
200
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)201 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
202 {
203 if (!host->is_lane_clks_enabled)
204 return;
205
206 clk_bulk_disable_unprepare(host->num_clks, host->clks);
207
208 host->is_lane_clks_enabled = false;
209 }
210
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)211 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
212 {
213 int err;
214
215 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
216 if (err)
217 return err;
218
219 host->is_lane_clks_enabled = true;
220
221 return 0;
222 }
223
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)224 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
225 {
226 int err;
227 struct device *dev = host->hba->dev;
228
229 if (has_acpi_companion(dev))
230 return 0;
231
232 err = devm_clk_bulk_get_all(dev, &host->clks);
233 if (err <= 0)
234 return err;
235
236 host->num_clks = err;
237
238 return 0;
239 }
240
ufs_qcom_check_hibern8(struct ufs_hba * hba)241 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
242 {
243 int err;
244 u32 tx_fsm_val;
245 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
246
247 do {
248 err = ufshcd_dme_get(hba,
249 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
250 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
251 &tx_fsm_val);
252 if (err || tx_fsm_val == TX_FSM_HIBERN8)
253 break;
254
255 /* sleep for max. 200us */
256 usleep_range(100, 200);
257 } while (time_before(jiffies, timeout));
258
259 /*
260 * we might have scheduled out for long during polling so
261 * check the state again.
262 */
263 if (time_after(jiffies, timeout))
264 err = ufshcd_dme_get(hba,
265 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
266 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
267 &tx_fsm_val);
268
269 if (err) {
270 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
271 __func__, err);
272 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
273 err = tx_fsm_val;
274 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
275 __func__, err);
276 }
277
278 return err;
279 }
280
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)281 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
282 {
283 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
284
285 if (host->hw_ver.major >= 0x05)
286 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
287 }
288
289 /*
290 * ufs_qcom_host_reset - reset host controller and PHY
291 */
ufs_qcom_host_reset(struct ufs_hba * hba)292 static int ufs_qcom_host_reset(struct ufs_hba *hba)
293 {
294 int ret;
295 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
296 bool reenable_intr;
297
298 if (!host->core_reset)
299 return 0;
300
301 reenable_intr = hba->is_irq_enabled;
302 ufshcd_disable_irq(hba);
303
304 ret = reset_control_assert(host->core_reset);
305 if (ret) {
306 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
307 __func__, ret);
308 return ret;
309 }
310
311 /*
312 * The hardware requirement for delay between assert/deassert
313 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
314 * ~125us (4/32768). To be on the safe side add 200us delay.
315 */
316 usleep_range(200, 210);
317
318 ret = reset_control_deassert(host->core_reset);
319 if (ret) {
320 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
321 __func__, ret);
322 return ret;
323 }
324
325 usleep_range(1000, 1100);
326
327 if (reenable_intr)
328 ufshcd_enable_irq(hba);
329
330 return 0;
331 }
332
ufs_qcom_get_hs_gear(struct ufs_hba * hba)333 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
334 {
335 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
336
337 if (host->hw_ver.major >= 0x4)
338 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
339
340 /* Default is HS-G3 */
341 return UFS_HS_G3;
342 }
343
ufs_qcom_power_up_sequence(struct ufs_hba * hba)344 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
345 {
346 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
347 struct ufs_host_params *host_params = &host->host_params;
348 struct phy *phy = host->generic_phy;
349 enum phy_mode mode;
350 int ret;
351
352 /*
353 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
354 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
355 * so that the subsequent power mode change shall stick to Rate-A.
356 */
357 if (host->hw_ver.major == 0x5) {
358 if (host->phy_gear == UFS_HS_G5)
359 host_params->hs_rate = PA_HS_MODE_A;
360 else
361 host_params->hs_rate = PA_HS_MODE_B;
362 }
363
364 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
365
366 /* Reset UFS Host Controller and PHY */
367 ret = ufs_qcom_host_reset(hba);
368 if (ret)
369 return ret;
370
371 /* phy initialization - calibrate the phy */
372 ret = phy_init(phy);
373 if (ret) {
374 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
375 __func__, ret);
376 return ret;
377 }
378
379 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
380 if (ret)
381 goto out_disable_phy;
382
383 /* power on phy - start serdes and phy's power and clocks */
384 ret = phy_power_on(phy);
385 if (ret) {
386 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
387 __func__, ret);
388 goto out_disable_phy;
389 }
390
391 ufs_qcom_select_unipro_mode(host);
392
393 return 0;
394
395 out_disable_phy:
396 phy_exit(phy);
397
398 return ret;
399 }
400
401 /*
402 * The UTP controller has a number of internal clock gating cells (CGCs).
403 * Internal hardware sub-modules within the UTP controller control the CGCs.
404 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
405 * in a specific operation, UTP controller CGCs are by default disabled and
406 * this function enables them (after every UFS link startup) to save some power
407 * leakage.
408 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)409 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
410 {
411 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
412 REG_UFS_CFG2);
413
414 /* Ensure that HW clock gating is enabled before next operations */
415 ufshcd_readl(hba, REG_UFS_CFG2);
416 }
417
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)418 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
419 enum ufs_notify_change_status status)
420 {
421 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
422 int err;
423
424 switch (status) {
425 case PRE_CHANGE:
426 err = ufs_qcom_power_up_sequence(hba);
427 if (err)
428 return err;
429
430 /*
431 * The PHY PLL output is the source of tx/rx lane symbol
432 * clocks, hence, enable the lane clocks only after PHY
433 * is initialized.
434 */
435 err = ufs_qcom_enable_lane_clks(host);
436 break;
437 case POST_CHANGE:
438 /* check if UFS PHY moved from DISABLED to HIBERN8 */
439 err = ufs_qcom_check_hibern8(hba);
440 ufs_qcom_enable_hw_clk_gating(hba);
441 ufs_qcom_ice_enable(host);
442 break;
443 default:
444 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
445 err = -EINVAL;
446 break;
447 }
448 return err;
449 }
450
451 /**
452 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
453 *
454 * @hba: host controller instance
455 * @gear: Current operating gear
456 * @hs: current power mode
457 * @rate: current operating rate (A or B)
458 * @update_link_startup_timer: indicate if link_start ongoing
459 * @is_pre_scale_up: flag to check if pre scale up condition.
460 * Return: zero for success and non-zero in case of a failure.
461 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,u32 gear,u32 hs,u32 rate,bool update_link_startup_timer,bool is_pre_scale_up)462 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
463 u32 hs, u32 rate, bool update_link_startup_timer,
464 bool is_pre_scale_up)
465 {
466 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
467 struct ufs_clk_info *clki;
468 unsigned long core_clk_rate = 0;
469 u32 core_clk_cycles_per_us;
470
471 /*
472 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
473 * Aggregation logic.
474 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
475 * controller V4.0.0 onwards.
476 */
477 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
478 return 0;
479
480 if (gear == 0) {
481 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
482 return -EINVAL;
483 }
484
485 list_for_each_entry(clki, &hba->clk_list_head, list) {
486 if (!strcmp(clki->name, "core_clk")) {
487 if (is_pre_scale_up)
488 core_clk_rate = clki->max_freq;
489 else
490 core_clk_rate = clk_get_rate(clki->clk);
491 break;
492 }
493
494 }
495
496 /* If frequency is smaller than 1MHz, set to 1MHz */
497 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
498 core_clk_rate = DEFAULT_CLK_RATE_HZ;
499
500 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
501 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
502 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
503 /*
504 * make sure above write gets applied before we return from
505 * this function.
506 */
507 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
508 }
509
510 return 0;
511 }
512
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)513 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
514 enum ufs_notify_change_status status)
515 {
516 int err = 0;
517
518 switch (status) {
519 case PRE_CHANGE:
520 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
521 0, true, false)) {
522 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
523 __func__);
524 return -EINVAL;
525 }
526
527 err = ufs_qcom_set_core_clk_ctrl(hba, true);
528 if (err)
529 dev_err(hba->dev, "cfg core clk ctrl failed\n");
530 /*
531 * Some UFS devices (and may be host) have issues if LCC is
532 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
533 * before link startup which will make sure that both host
534 * and device TX LCC are disabled once link startup is
535 * completed.
536 */
537 err = ufshcd_disable_host_tx_lcc(hba);
538
539 break;
540 default:
541 break;
542 }
543
544 return err;
545 }
546
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)547 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
548 {
549 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
550
551 /* reset gpio is optional */
552 if (!host->device_reset)
553 return;
554
555 gpiod_set_value_cansleep(host->device_reset, asserted);
556 }
557
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)558 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
559 enum ufs_notify_change_status status)
560 {
561 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
562 struct phy *phy = host->generic_phy;
563
564 if (status == PRE_CHANGE)
565 return 0;
566
567 if (ufs_qcom_is_link_off(hba)) {
568 /*
569 * Disable the tx/rx lane symbol clocks before PHY is
570 * powered down as the PLL source should be disabled
571 * after downstream clocks are disabled.
572 */
573 ufs_qcom_disable_lane_clks(host);
574 phy_power_off(phy);
575
576 /* reset the connected UFS device during power down */
577 ufs_qcom_device_reset_ctrl(hba, true);
578
579 } else if (!ufs_qcom_is_link_active(hba)) {
580 ufs_qcom_disable_lane_clks(host);
581 }
582
583 return ufs_qcom_ice_suspend(host);
584 }
585
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)586 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
587 {
588 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
589 struct phy *phy = host->generic_phy;
590 int err;
591
592 if (ufs_qcom_is_link_off(hba)) {
593 err = phy_power_on(phy);
594 if (err) {
595 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
596 __func__, err);
597 return err;
598 }
599
600 err = ufs_qcom_enable_lane_clks(host);
601 if (err)
602 return err;
603
604 } else if (!ufs_qcom_is_link_active(hba)) {
605 err = ufs_qcom_enable_lane_clks(host);
606 if (err)
607 return err;
608 }
609
610 return ufs_qcom_ice_resume(host);
611 }
612
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)613 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
614 {
615 if (host->dev_ref_clk_ctrl_mmio &&
616 (enable ^ host->is_dev_ref_clk_enabled)) {
617 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
618
619 if (enable)
620 temp |= host->dev_ref_clk_en_mask;
621 else
622 temp &= ~host->dev_ref_clk_en_mask;
623
624 /*
625 * If we are here to disable this clock it might be immediately
626 * after entering into hibern8 in which case we need to make
627 * sure that device ref_clk is active for specific time after
628 * hibern8 enter.
629 */
630 if (!enable) {
631 unsigned long gating_wait;
632
633 gating_wait = host->hba->dev_info.clk_gating_wait_us;
634 if (!gating_wait) {
635 udelay(1);
636 } else {
637 /*
638 * bRefClkGatingWaitTime defines the minimum
639 * time for which the reference clock is
640 * required by device during transition from
641 * HS-MODE to LS-MODE or HIBERN8 state. Give it
642 * more delay to be on the safe side.
643 */
644 gating_wait += 10;
645 usleep_range(gating_wait, gating_wait + 10);
646 }
647 }
648
649 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
650
651 /*
652 * Make sure the write to ref_clk reaches the destination and
653 * not stored in a Write Buffer (WB).
654 */
655 readl(host->dev_ref_clk_ctrl_mmio);
656
657 /*
658 * If we call hibern8 exit after this, we need to make sure that
659 * device ref_clk is stable for at least 1us before the hibern8
660 * exit command.
661 */
662 if (enable)
663 udelay(1);
664
665 host->is_dev_ref_clk_enabled = enable;
666 }
667 }
668
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)669 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
670 {
671 struct device *dev = host->hba->dev;
672 int ret;
673
674 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
675 if (ret < 0) {
676 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
677 return ret;
678 }
679
680 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
681 if (ret < 0) {
682 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
683 return ret;
684 }
685
686 return 0;
687 }
688
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)689 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
690 {
691 struct ufs_pa_layer_attr *p = &host->dev_req_params;
692 int gear = max_t(u32, p->gear_rx, p->gear_tx);
693 int lane = max_t(u32, p->lane_rx, p->lane_tx);
694
695 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR,
696 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n",
697 gear, QCOM_UFS_MAX_GEAR))
698 gear = QCOM_UFS_MAX_GEAR;
699
700 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE,
701 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n",
702 lane, QCOM_UFS_MAX_LANE))
703 lane = QCOM_UFS_MAX_LANE;
704
705 if (ufshcd_is_hs_mode(p)) {
706 if (p->hs_rate == PA_HS_MODE_B)
707 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
708 else
709 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
710 } else {
711 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
712 }
713 }
714
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)715 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
716 {
717 struct __ufs_qcom_bw_table bw_table;
718
719 bw_table = ufs_qcom_get_bw_table(host);
720
721 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
722 }
723
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)724 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
725 enum ufs_notify_change_status status,
726 struct ufs_pa_layer_attr *dev_max_params,
727 struct ufs_pa_layer_attr *dev_req_params)
728 {
729 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
730 struct ufs_host_params *host_params = &host->host_params;
731 int ret = 0;
732
733 if (!dev_req_params) {
734 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
735 return -EINVAL;
736 }
737
738 switch (status) {
739 case PRE_CHANGE:
740 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
741 if (ret) {
742 dev_err(hba->dev, "%s: failed to determine capabilities\n",
743 __func__);
744 return ret;
745 }
746
747 /*
748 * During UFS driver probe, always update the PHY gear to match the negotiated
749 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
750 * the second init can program the optimal PHY settings. This allows one to start
751 * the first init with either the minimum or the maximum support gear.
752 */
753 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
754 /*
755 * Skip REINIT if the negotiated gear matches with the
756 * initial phy_gear. Otherwise, update the phy_gear to
757 * program the optimal gear setting during REINIT.
758 */
759 if (host->phy_gear == dev_req_params->gear_tx)
760 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
761 else
762 host->phy_gear = dev_req_params->gear_tx;
763 }
764
765 /* enable the device ref clock before changing to HS mode */
766 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
767 ufshcd_is_hs_mode(dev_req_params))
768 ufs_qcom_dev_ref_clk_ctrl(host, true);
769
770 if (host->hw_ver.major >= 0x4) {
771 ufshcd_dme_configure_adapt(hba,
772 dev_req_params->gear_tx,
773 PA_INITIAL_ADAPT);
774 }
775 break;
776 case POST_CHANGE:
777 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
778 dev_req_params->pwr_rx,
779 dev_req_params->hs_rate, false, false)) {
780 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
781 __func__);
782 /*
783 * we return error code at the end of the routine,
784 * but continue to configure UFS_PHY_TX_LANE_ENABLE
785 * and bus voting as usual
786 */
787 ret = -EINVAL;
788 }
789
790 /* cache the power mode parameters to use internally */
791 memcpy(&host->dev_req_params,
792 dev_req_params, sizeof(*dev_req_params));
793
794 ufs_qcom_icc_update_bw(host);
795
796 /* disable the device ref clock if entered PWM mode */
797 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
798 !ufshcd_is_hs_mode(dev_req_params))
799 ufs_qcom_dev_ref_clk_ctrl(host, false);
800 break;
801 default:
802 ret = -EINVAL;
803 break;
804 }
805
806 return ret;
807 }
808
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)809 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
810 {
811 int err;
812 u32 pa_vs_config_reg1;
813
814 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
815 &pa_vs_config_reg1);
816 if (err)
817 return err;
818
819 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
820 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
821 (pa_vs_config_reg1 | (1 << 12)));
822 }
823
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)824 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
825 {
826 int err = 0;
827
828 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
829 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
830
831 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
832 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
833
834 return err;
835 }
836
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)837 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
838 {
839 return ufshci_version(2, 0);
840 }
841
842 /**
843 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
844 * @hba: host controller instance
845 *
846 * QCOM UFS host controller might have some non standard behaviours (quirks)
847 * than what is specified by UFSHCI specification. Advertise all such
848 * quirks to standard UFS host controller driver so standard takes them into
849 * account.
850 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)851 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
852 {
853 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
854
855 if (host->hw_ver.major == 0x2)
856 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
857
858 if (host->hw_ver.major > 0x3)
859 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
860
861 if (of_device_is_compatible(hba->dev->of_node, "qcom,sm8550-ufshc"))
862 hba->quirks |= UFSHCD_QUIRK_BROKEN_LSDBS_CAP;
863 }
864
ufs_qcom_set_phy_gear(struct ufs_qcom_host * host)865 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
866 {
867 struct ufs_host_params *host_params = &host->host_params;
868 u32 val, dev_major;
869
870 /*
871 * Default to powering up the PHY to the max gear possible, which is
872 * backwards compatible with lower gears but not optimal from
873 * a power usage point of view. After device negotiation, if the
874 * gear is lower a reinit will be performed to program the PHY
875 * to the ideal gear for this combo of controller and device.
876 */
877 host->phy_gear = host_params->hs_tx_gear;
878
879 if (host->hw_ver.major < 0x4) {
880 /*
881 * These controllers only have one PHY init sequence,
882 * let's power up the PHY using that (the minimum supported
883 * gear, UFS_HS_G2).
884 */
885 host->phy_gear = UFS_HS_G2;
886 } else if (host->hw_ver.major >= 0x5) {
887 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
888 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
889
890 /*
891 * Since the UFS device version is populated, let's remove the
892 * REINIT quirk as the negotiated gear won't change during boot.
893 * So there is no need to do reinit.
894 */
895 if (dev_major != 0x0)
896 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
897
898 /*
899 * For UFS 3.1 device and older, power up the PHY using HS-G4
900 * PHY gear to save power.
901 */
902 if (dev_major > 0x0 && dev_major < 0x4)
903 host->phy_gear = UFS_HS_G4;
904 }
905 }
906
ufs_qcom_set_host_params(struct ufs_hba * hba)907 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
908 {
909 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
910 struct ufs_host_params *host_params = &host->host_params;
911
912 ufshcd_init_host_params(host_params);
913
914 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
915 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
916 }
917
ufs_qcom_set_caps(struct ufs_hba * hba)918 static void ufs_qcom_set_caps(struct ufs_hba *hba)
919 {
920 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
921 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
922 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
923 hba->caps |= UFSHCD_CAP_WB_EN;
924 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
925 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
926 }
927
928 /**
929 * ufs_qcom_setup_clocks - enables/disable clocks
930 * @hba: host controller instance
931 * @on: If true, enable clocks else disable them.
932 * @status: PRE_CHANGE or POST_CHANGE notify
933 *
934 * Return: 0 on success, non-zero on failure.
935 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)936 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
937 enum ufs_notify_change_status status)
938 {
939 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
940
941 /*
942 * In case ufs_qcom_init() is not yet done, simply ignore.
943 * This ufs_qcom_setup_clocks() shall be called from
944 * ufs_qcom_init() after init is done.
945 */
946 if (!host)
947 return 0;
948
949 switch (status) {
950 case PRE_CHANGE:
951 if (on) {
952 ufs_qcom_icc_update_bw(host);
953 } else {
954 if (!ufs_qcom_is_link_active(hba)) {
955 /* disable device ref_clk */
956 ufs_qcom_dev_ref_clk_ctrl(host, false);
957 }
958 }
959 break;
960 case POST_CHANGE:
961 if (on) {
962 /* enable the device ref clock for HS mode*/
963 if (ufshcd_is_hs_mode(&hba->pwr_info))
964 ufs_qcom_dev_ref_clk_ctrl(host, true);
965 } else {
966 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
967 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
968 }
969 break;
970 }
971
972 return 0;
973 }
974
975 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)976 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
977 {
978 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
979
980 ufs_qcom_assert_reset(host->hba);
981 /* provide 1ms delay to let the reset pulse propagate. */
982 usleep_range(1000, 1100);
983 return 0;
984 }
985
986 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)987 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
988 {
989 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
990
991 ufs_qcom_deassert_reset(host->hba);
992
993 /*
994 * after reset deassertion, phy will need all ref clocks,
995 * voltage, current to settle down before starting serdes.
996 */
997 usleep_range(1000, 1100);
998 return 0;
999 }
1000
1001 static const struct reset_control_ops ufs_qcom_reset_ops = {
1002 .assert = ufs_qcom_reset_assert,
1003 .deassert = ufs_qcom_reset_deassert,
1004 };
1005
ufs_qcom_icc_init(struct ufs_qcom_host * host)1006 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1007 {
1008 struct device *dev = host->hba->dev;
1009 int ret;
1010
1011 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1012 if (IS_ERR(host->icc_ddr))
1013 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1014 "failed to acquire interconnect path\n");
1015
1016 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1017 if (IS_ERR(host->icc_cpu))
1018 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1019 "failed to acquire interconnect path\n");
1020
1021 /*
1022 * Set Maximum bandwidth vote before initializing the UFS controller and
1023 * device. Ideally, a minimal interconnect vote would suffice for the
1024 * initialization, but a max vote would allow faster initialization.
1025 */
1026 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1027 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1028 if (ret < 0)
1029 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1030
1031 return 0;
1032 }
1033
1034 /**
1035 * ufs_qcom_init - bind phy with controller
1036 * @hba: host controller instance
1037 *
1038 * Binds PHY with controller and powers up PHY enabling clocks
1039 * and regulators.
1040 *
1041 * Return: -EPROBE_DEFER if binding fails, returns negative error
1042 * on phy power up failure and returns zero on success.
1043 */
ufs_qcom_init(struct ufs_hba * hba)1044 static int ufs_qcom_init(struct ufs_hba *hba)
1045 {
1046 int err;
1047 struct device *dev = hba->dev;
1048 struct ufs_qcom_host *host;
1049 struct ufs_clk_info *clki;
1050
1051 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1052 if (!host)
1053 return -ENOMEM;
1054
1055 /* Make a two way bind between the qcom host and the hba */
1056 host->hba = hba;
1057 ufshcd_set_variant(hba, host);
1058
1059 /* Setup the optional reset control of HCI */
1060 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1061 if (IS_ERR(host->core_reset)) {
1062 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1063 "Failed to get reset control\n");
1064 goto out_variant_clear;
1065 }
1066
1067 /* Fire up the reset controller. Failure here is non-fatal. */
1068 host->rcdev.of_node = dev->of_node;
1069 host->rcdev.ops = &ufs_qcom_reset_ops;
1070 host->rcdev.owner = dev->driver->owner;
1071 host->rcdev.nr_resets = 1;
1072 err = devm_reset_controller_register(dev, &host->rcdev);
1073 if (err)
1074 dev_warn(dev, "Failed to register reset controller\n");
1075
1076 if (!has_acpi_companion(dev)) {
1077 host->generic_phy = devm_phy_get(dev, "ufsphy");
1078 if (IS_ERR(host->generic_phy)) {
1079 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1080 goto out_variant_clear;
1081 }
1082 }
1083
1084 err = ufs_qcom_icc_init(host);
1085 if (err)
1086 goto out_variant_clear;
1087
1088 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1089 GPIOD_OUT_HIGH);
1090 if (IS_ERR(host->device_reset)) {
1091 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1092 "Failed to acquire device reset gpio\n");
1093 goto out_variant_clear;
1094 }
1095
1096 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1097 &host->hw_ver.minor, &host->hw_ver.step);
1098
1099 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1100 host->dev_ref_clk_en_mask = BIT(26);
1101
1102 list_for_each_entry(clki, &hba->clk_list_head, list) {
1103 if (!strcmp(clki->name, "core_clk_unipro"))
1104 clki->keep_link_active = true;
1105 }
1106
1107 err = ufs_qcom_init_lane_clks(host);
1108 if (err)
1109 goto out_variant_clear;
1110
1111 ufs_qcom_set_caps(hba);
1112 ufs_qcom_advertise_quirks(hba);
1113 ufs_qcom_set_host_params(hba);
1114 ufs_qcom_set_phy_gear(host);
1115
1116 err = ufs_qcom_ice_init(host);
1117 if (err)
1118 goto out_variant_clear;
1119
1120 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1121
1122 ufs_qcom_get_default_testbus_cfg(host);
1123 err = ufs_qcom_testbus_config(host);
1124 if (err)
1125 /* Failure is non-fatal */
1126 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1127 __func__, err);
1128
1129 return 0;
1130
1131 out_variant_clear:
1132 ufshcd_set_variant(hba, NULL);
1133
1134 return err;
1135 }
1136
ufs_qcom_exit(struct ufs_hba * hba)1137 static void ufs_qcom_exit(struct ufs_hba *hba)
1138 {
1139 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1140
1141 ufs_qcom_disable_lane_clks(host);
1142 phy_power_off(host->generic_phy);
1143 phy_exit(host->generic_phy);
1144 }
1145
1146 /**
1147 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1148 *
1149 * @hba: host controller instance
1150 * @cycles_in_1us: No of cycles in 1us to be configured
1151 *
1152 * Returns error if dme get/set configuration for 40ns fails
1153 * and returns zero on success.
1154 */
ufs_qcom_set_clk_40ns_cycles(struct ufs_hba * hba,u32 cycles_in_1us)1155 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1156 u32 cycles_in_1us)
1157 {
1158 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1159 u32 cycles_in_40ns;
1160 u32 reg;
1161 int err;
1162
1163 /*
1164 * UFS host controller V4.0.0 onwards needs to program
1165 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1166 * frequency of unipro core clk of UFS host controller.
1167 */
1168 if (host->hw_ver.major < 4)
1169 return 0;
1170
1171 /*
1172 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1173 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1174 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1175 * specification expect to be 16. Hence use exact hardware spec
1176 * mandated value for cycles_in_40ns instead of calculating using
1177 * generic formulae.
1178 */
1179 switch (cycles_in_1us) {
1180 case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1181 cycles_in_40ns = 16;
1182 break;
1183 case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1184 cycles_in_40ns = 12;
1185 break;
1186 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1187 cycles_in_40ns = 8;
1188 break;
1189 case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1190 cycles_in_40ns = 6;
1191 break;
1192 case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1193 cycles_in_40ns = 4;
1194 break;
1195 case UNIPRO_CORE_CLK_FREQ_75_MHZ:
1196 cycles_in_40ns = 3;
1197 break;
1198 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1199 cycles_in_40ns = 2;
1200 break;
1201 default:
1202 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1203 cycles_in_1us);
1204 return -EINVAL;
1205 }
1206
1207 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®);
1208 if (err)
1209 return err;
1210
1211 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1212 reg |= cycles_in_40ns;
1213
1214 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1215 }
1216
ufs_qcom_set_core_clk_ctrl(struct ufs_hba * hba,bool is_scale_up)1217 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up)
1218 {
1219 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1220 struct list_head *head = &hba->clk_list_head;
1221 struct ufs_clk_info *clki;
1222 u32 cycles_in_1us = 0;
1223 u32 core_clk_ctrl_reg;
1224 int err;
1225
1226 list_for_each_entry(clki, head, list) {
1227 if (!IS_ERR_OR_NULL(clki->clk) &&
1228 !strcmp(clki->name, "core_clk_unipro")) {
1229 if (!clki->max_freq)
1230 cycles_in_1us = 150; /* default for backwards compatibility */
1231 else if (is_scale_up)
1232 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000));
1233 else
1234 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000));
1235 break;
1236 }
1237 }
1238
1239 err = ufshcd_dme_get(hba,
1240 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1241 &core_clk_ctrl_reg);
1242 if (err)
1243 return err;
1244
1245 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1246 if (host->hw_ver.major >= 4) {
1247 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1248 return -ERANGE;
1249 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1250 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1251 } else {
1252 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1253 return -ERANGE;
1254 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1255 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1256 }
1257
1258 /* Clear CORE_CLK_DIV_EN */
1259 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1260
1261 err = ufshcd_dme_set(hba,
1262 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1263 core_clk_ctrl_reg);
1264 if (err)
1265 return err;
1266
1267 /* Configure unipro core clk 40ns attribute */
1268 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1269 }
1270
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba)1271 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1272 {
1273 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1274 struct ufs_pa_layer_attr *attr = &host->dev_req_params;
1275 int ret;
1276
1277 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,
1278 attr->hs_rate, false, true);
1279 if (ret) {
1280 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1281 return ret;
1282 }
1283 /* set unipro core clock attributes and clear clock divider */
1284 return ufs_qcom_set_core_clk_ctrl(hba, true);
1285 }
1286
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1287 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1288 {
1289 return 0;
1290 }
1291
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1292 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1293 {
1294 int err;
1295 u32 core_clk_ctrl_reg;
1296
1297 err = ufshcd_dme_get(hba,
1298 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1299 &core_clk_ctrl_reg);
1300
1301 /* make sure CORE_CLK_DIV_EN is cleared */
1302 if (!err &&
1303 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1304 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1305 err = ufshcd_dme_set(hba,
1306 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1307 core_clk_ctrl_reg);
1308 }
1309
1310 return err;
1311 }
1312
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba)1313 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1314 {
1315 /* set unipro core clock attributes and clear clock divider */
1316 return ufs_qcom_set_core_clk_ctrl(hba, false);
1317 }
1318
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,enum ufs_notify_change_status status)1319 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1320 bool scale_up, enum ufs_notify_change_status status)
1321 {
1322 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1323 int err;
1324
1325 /* check the host controller state before sending hibern8 cmd */
1326 if (!ufshcd_is_hba_active(hba))
1327 return 0;
1328
1329 if (status == PRE_CHANGE) {
1330 err = ufshcd_uic_hibern8_enter(hba);
1331 if (err)
1332 return err;
1333 if (scale_up)
1334 err = ufs_qcom_clk_scale_up_pre_change(hba);
1335 else
1336 err = ufs_qcom_clk_scale_down_pre_change(hba);
1337
1338 if (err) {
1339 ufshcd_uic_hibern8_exit(hba);
1340 return err;
1341 }
1342 } else {
1343 if (scale_up)
1344 err = ufs_qcom_clk_scale_up_post_change(hba);
1345 else
1346 err = ufs_qcom_clk_scale_down_post_change(hba);
1347
1348
1349 if (err) {
1350 ufshcd_uic_hibern8_exit(hba);
1351 return err;
1352 }
1353
1354 ufs_qcom_icc_update_bw(host);
1355 ufshcd_uic_hibern8_exit(hba);
1356 }
1357
1358 return 0;
1359 }
1360
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1361 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1362 {
1363 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1364 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1365 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1366 }
1367
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1368 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1369 {
1370 /* provide a legal default configuration */
1371 host->testbus.select_major = TSTBUS_UNIPRO;
1372 host->testbus.select_minor = 37;
1373 }
1374
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1375 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1376 {
1377 if (host->testbus.select_major >= TSTBUS_MAX) {
1378 dev_err(host->hba->dev,
1379 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1380 __func__, host->testbus.select_major);
1381 return false;
1382 }
1383
1384 return true;
1385 }
1386
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1387 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1388 {
1389 int reg;
1390 int offset;
1391 u32 mask = TEST_BUS_SUB_SEL_MASK;
1392
1393 if (!host)
1394 return -EINVAL;
1395
1396 if (!ufs_qcom_testbus_cfg_is_ok(host))
1397 return -EPERM;
1398
1399 switch (host->testbus.select_major) {
1400 case TSTBUS_UAWM:
1401 reg = UFS_TEST_BUS_CTRL_0;
1402 offset = 24;
1403 break;
1404 case TSTBUS_UARM:
1405 reg = UFS_TEST_BUS_CTRL_0;
1406 offset = 16;
1407 break;
1408 case TSTBUS_TXUC:
1409 reg = UFS_TEST_BUS_CTRL_0;
1410 offset = 8;
1411 break;
1412 case TSTBUS_RXUC:
1413 reg = UFS_TEST_BUS_CTRL_0;
1414 offset = 0;
1415 break;
1416 case TSTBUS_DFC:
1417 reg = UFS_TEST_BUS_CTRL_1;
1418 offset = 24;
1419 break;
1420 case TSTBUS_TRLUT:
1421 reg = UFS_TEST_BUS_CTRL_1;
1422 offset = 16;
1423 break;
1424 case TSTBUS_TMRLUT:
1425 reg = UFS_TEST_BUS_CTRL_1;
1426 offset = 8;
1427 break;
1428 case TSTBUS_OCSC:
1429 reg = UFS_TEST_BUS_CTRL_1;
1430 offset = 0;
1431 break;
1432 case TSTBUS_WRAPPER:
1433 reg = UFS_TEST_BUS_CTRL_2;
1434 offset = 16;
1435 break;
1436 case TSTBUS_COMBINED:
1437 reg = UFS_TEST_BUS_CTRL_2;
1438 offset = 8;
1439 break;
1440 case TSTBUS_UTP_HCI:
1441 reg = UFS_TEST_BUS_CTRL_2;
1442 offset = 0;
1443 break;
1444 case TSTBUS_UNIPRO:
1445 reg = UFS_UNIPRO_CFG;
1446 offset = 20;
1447 mask = 0xFFF;
1448 break;
1449 /*
1450 * No need for a default case, since
1451 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1452 * is legal
1453 */
1454 }
1455 mask <<= offset;
1456 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1457 (u32)host->testbus.select_major << 19,
1458 REG_UFS_CFG1);
1459 ufshcd_rmwl(host->hba, mask,
1460 (u32)host->testbus.select_minor << offset,
1461 reg);
1462 ufs_qcom_enable_test_bus(host);
1463
1464 return 0;
1465 }
1466
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1467 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1468 {
1469 u32 reg;
1470 struct ufs_qcom_host *host;
1471
1472 host = ufshcd_get_variant(hba);
1473
1474 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1475 "HCI Vendor Specific Registers ");
1476
1477 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1478 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1479
1480 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1481 reg |= UTP_DBG_RAMS_EN;
1482 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1483
1484 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1485 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1486
1487 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1488 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1489
1490 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1491 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1492
1493 /* clear bit 17 - UTP_DBG_RAMS_EN */
1494 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1495
1496 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1497 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1498
1499 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1500 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1501
1502 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1503 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1504
1505 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1506 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1507
1508 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1509 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1510
1511 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1512 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1513
1514 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1515 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1516 }
1517
1518 /**
1519 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1520 * @hba: per-adapter instance
1521 *
1522 * Toggles the (optional) reset line to reset the attached device.
1523 */
ufs_qcom_device_reset(struct ufs_hba * hba)1524 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1525 {
1526 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1527
1528 /* reset gpio is optional */
1529 if (!host->device_reset)
1530 return -EOPNOTSUPP;
1531
1532 /*
1533 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1534 * be on the safe side.
1535 */
1536 ufs_qcom_device_reset_ctrl(hba, true);
1537 usleep_range(10, 15);
1538
1539 ufs_qcom_device_reset_ctrl(hba, false);
1540 usleep_range(10, 15);
1541
1542 return 0;
1543 }
1544
1545 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1546 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1547 struct devfreq_dev_profile *p,
1548 struct devfreq_simple_ondemand_data *d)
1549 {
1550 p->polling_ms = 60;
1551 p->timer = DEVFREQ_TIMER_DELAYED;
1552 d->upthreshold = 70;
1553 d->downdifferential = 5;
1554
1555 hba->clk_scaling.suspend_on_no_request = true;
1556 }
1557 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * data)1558 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1559 struct devfreq_dev_profile *p,
1560 struct devfreq_simple_ondemand_data *data)
1561 {
1562 }
1563 #endif
1564
ufs_qcom_reinit_notify(struct ufs_hba * hba)1565 static void ufs_qcom_reinit_notify(struct ufs_hba *hba)
1566 {
1567 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1568
1569 phy_power_off(host->generic_phy);
1570 }
1571
1572 /* Resources */
1573 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1574 {.name = "ufs_mem",},
1575 {.name = "mcq",},
1576 /* Submission Queue DAO */
1577 {.name = "mcq_sqd",},
1578 /* Submission Queue Interrupt Status */
1579 {.name = "mcq_sqis",},
1580 /* Completion Queue DAO */
1581 {.name = "mcq_cqd",},
1582 /* Completion Queue Interrupt Status */
1583 {.name = "mcq_cqis",},
1584 /* MCQ vendor specific */
1585 {.name = "mcq_vs",},
1586 };
1587
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1588 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1589 {
1590 struct platform_device *pdev = to_platform_device(hba->dev);
1591 struct ufshcd_res_info *res;
1592 struct resource *res_mem, *res_mcq;
1593 int i, ret;
1594
1595 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1596
1597 for (i = 0; i < RES_MAX; i++) {
1598 res = &hba->res[i];
1599 res->resource = platform_get_resource_byname(pdev,
1600 IORESOURCE_MEM,
1601 res->name);
1602 if (!res->resource) {
1603 dev_info(hba->dev, "Resource %s not provided\n", res->name);
1604 if (i == RES_UFS)
1605 return -ENODEV;
1606 continue;
1607 } else if (i == RES_UFS) {
1608 res_mem = res->resource;
1609 res->base = hba->mmio_base;
1610 continue;
1611 }
1612
1613 res->base = devm_ioremap_resource(hba->dev, res->resource);
1614 if (IS_ERR(res->base)) {
1615 dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1616 res->name, (int)PTR_ERR(res->base));
1617 ret = PTR_ERR(res->base);
1618 res->base = NULL;
1619 return ret;
1620 }
1621 }
1622
1623 /* MCQ resource provided in DT */
1624 res = &hba->res[RES_MCQ];
1625 /* Bail if MCQ resource is provided */
1626 if (res->base)
1627 goto out;
1628
1629 /* Explicitly allocate MCQ resource from ufs_mem */
1630 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1631 if (!res_mcq)
1632 return -ENOMEM;
1633
1634 res_mcq->start = res_mem->start +
1635 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1636 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1637 res_mcq->flags = res_mem->flags;
1638 res_mcq->name = "mcq";
1639
1640 ret = insert_resource(&iomem_resource, res_mcq);
1641 if (ret) {
1642 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1643 ret);
1644 return ret;
1645 }
1646
1647 res->base = devm_ioremap_resource(hba->dev, res_mcq);
1648 if (IS_ERR(res->base)) {
1649 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1650 (int)PTR_ERR(res->base));
1651 ret = PTR_ERR(res->base);
1652 goto ioremap_err;
1653 }
1654
1655 out:
1656 hba->mcq_base = res->base;
1657 return 0;
1658 ioremap_err:
1659 res->base = NULL;
1660 remove_resource(res_mcq);
1661 return ret;
1662 }
1663
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1664 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1665 {
1666 struct ufshcd_res_info *mem_res, *sqdao_res;
1667 struct ufshcd_mcq_opr_info_t *opr;
1668 int i;
1669
1670 mem_res = &hba->res[RES_UFS];
1671 sqdao_res = &hba->res[RES_MCQ_SQD];
1672
1673 if (!mem_res->base || !sqdao_res->base)
1674 return -EINVAL;
1675
1676 for (i = 0; i < OPR_MAX; i++) {
1677 opr = &hba->mcq_opr[i];
1678 opr->offset = sqdao_res->resource->start -
1679 mem_res->resource->start + 0x40 * i;
1680 opr->stride = 0x100;
1681 opr->base = sqdao_res->base + 0x40 * i;
1682 }
1683
1684 return 0;
1685 }
1686
ufs_qcom_get_hba_mac(struct ufs_hba * hba)1687 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1688 {
1689 /* Qualcomm HC supports up to 64 */
1690 return MAX_SUPP_MAC;
1691 }
1692
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)1693 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1694 unsigned long *ocqs)
1695 {
1696 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1697
1698 if (!mcq_vs_res->base)
1699 return -EINVAL;
1700
1701 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1702
1703 return 0;
1704 }
1705
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)1706 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1707 {
1708 struct device *dev = msi_desc_to_dev(desc);
1709 struct ufs_hba *hba = dev_get_drvdata(dev);
1710
1711 ufshcd_mcq_config_esi(hba, msg);
1712 }
1713
ufs_qcom_mcq_esi_handler(int irq,void * data)1714 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1715 {
1716 struct msi_desc *desc = data;
1717 struct device *dev = msi_desc_to_dev(desc);
1718 struct ufs_hba *hba = dev_get_drvdata(dev);
1719 u32 id = desc->msi_index;
1720 struct ufs_hw_queue *hwq = &hba->uhq[id];
1721
1722 ufshcd_mcq_write_cqis(hba, 0x1, id);
1723 ufshcd_mcq_poll_cqe_lock(hba, hwq);
1724
1725 return IRQ_HANDLED;
1726 }
1727
ufs_qcom_config_esi(struct ufs_hba * hba)1728 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1729 {
1730 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1731 struct msi_desc *desc;
1732 struct msi_desc *failed_desc = NULL;
1733 int nr_irqs, ret;
1734
1735 if (host->esi_enabled)
1736 return 0;
1737
1738 /*
1739 * 1. We only handle CQs as of now.
1740 * 2. Poll queues do not need ESI.
1741 */
1742 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1743 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
1744 ufs_qcom_write_msi_msg);
1745 if (ret) {
1746 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1747 return ret;
1748 }
1749
1750 msi_lock_descs(hba->dev);
1751 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1752 ret = devm_request_irq(hba->dev, desc->irq,
1753 ufs_qcom_mcq_esi_handler,
1754 IRQF_SHARED, "qcom-mcq-esi", desc);
1755 if (ret) {
1756 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1757 __func__, desc->irq, ret);
1758 failed_desc = desc;
1759 break;
1760 }
1761 }
1762 msi_unlock_descs(hba->dev);
1763
1764 if (ret) {
1765 /* Rewind */
1766 msi_lock_descs(hba->dev);
1767 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1768 if (desc == failed_desc)
1769 break;
1770 devm_free_irq(hba->dev, desc->irq, hba);
1771 }
1772 msi_unlock_descs(hba->dev);
1773 platform_device_msi_free_irqs_all(hba->dev);
1774 } else {
1775 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1776 host->hw_ver.step == 0)
1777 ufshcd_rmwl(hba, ESI_VEC_MASK,
1778 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
1779 REG_UFS_CFG3);
1780 ufshcd_mcq_enable_esi(hba);
1781 host->esi_enabled = true;
1782 }
1783
1784 return ret;
1785 }
1786
1787 /*
1788 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1789 *
1790 * The variant operations configure the necessary controller and PHY
1791 * handshake during initialization.
1792 */
1793 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1794 .name = "qcom",
1795 .init = ufs_qcom_init,
1796 .exit = ufs_qcom_exit,
1797 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1798 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1799 .setup_clocks = ufs_qcom_setup_clocks,
1800 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1801 .link_startup_notify = ufs_qcom_link_startup_notify,
1802 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1803 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1804 .suspend = ufs_qcom_suspend,
1805 .resume = ufs_qcom_resume,
1806 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1807 .device_reset = ufs_qcom_device_reset,
1808 .config_scaling_param = ufs_qcom_config_scaling_param,
1809 .program_key = ufs_qcom_ice_program_key,
1810 .reinit_notify = ufs_qcom_reinit_notify,
1811 .mcq_config_resource = ufs_qcom_mcq_config_resource,
1812 .get_hba_mac = ufs_qcom_get_hba_mac,
1813 .op_runtime_config = ufs_qcom_op_runtime_config,
1814 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
1815 .config_esi = ufs_qcom_config_esi,
1816 };
1817
1818 /**
1819 * ufs_qcom_probe - probe routine of the driver
1820 * @pdev: pointer to Platform device handle
1821 *
1822 * Return: zero for success and non-zero for failure.
1823 */
ufs_qcom_probe(struct platform_device * pdev)1824 static int ufs_qcom_probe(struct platform_device *pdev)
1825 {
1826 int err;
1827 struct device *dev = &pdev->dev;
1828
1829 /* Perform generic probe */
1830 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1831 if (err)
1832 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
1833
1834 return 0;
1835 }
1836
1837 /**
1838 * ufs_qcom_remove - set driver_data of the device to NULL
1839 * @pdev: pointer to platform device handle
1840 *
1841 * Always returns 0
1842 */
ufs_qcom_remove(struct platform_device * pdev)1843 static void ufs_qcom_remove(struct platform_device *pdev)
1844 {
1845 struct ufs_hba *hba = platform_get_drvdata(pdev);
1846
1847 pm_runtime_get_sync(&(pdev)->dev);
1848 ufshcd_remove(hba);
1849 platform_device_msi_free_irqs_all(hba->dev);
1850 }
1851
1852 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
1853 { .compatible = "qcom,ufshc" },
1854 { .compatible = "qcom,sm8550-ufshc" },
1855 {},
1856 };
1857 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1858
1859 #ifdef CONFIG_ACPI
1860 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1861 { "QCOM24A5" },
1862 { },
1863 };
1864 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1865 #endif
1866
1867 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1868 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1869 .prepare = ufshcd_suspend_prepare,
1870 .complete = ufshcd_resume_complete,
1871 #ifdef CONFIG_PM_SLEEP
1872 .suspend = ufshcd_system_suspend,
1873 .resume = ufshcd_system_resume,
1874 .freeze = ufshcd_system_freeze,
1875 .restore = ufshcd_system_restore,
1876 .thaw = ufshcd_system_thaw,
1877 #endif
1878 };
1879
1880 static struct platform_driver ufs_qcom_pltform = {
1881 .probe = ufs_qcom_probe,
1882 .remove_new = ufs_qcom_remove,
1883 .driver = {
1884 .name = "ufshcd-qcom",
1885 .pm = &ufs_qcom_pm_ops,
1886 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1887 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1888 },
1889 };
1890 module_platform_driver(ufs_qcom_pltform);
1891
1892 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");
1893 MODULE_LICENSE("GPL v2");
1894