xref: /linux/sound/soc/codecs/wm8995.c (revision 33e02dc69afbd8f1b85a51d74d72f139ba4ca623)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * wm8995.c  --  WM8995 ALSA SoC Audio driver
4  *
5  * Copyright 2010 Wolfson Microelectronics plc
6  *
7  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8  *
9  * Based on wm8994.c and wm_hubs.c by Mark Brown
10  */
11 
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/regmap.h>
19 #include <linux/spi/spi.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 
30 #include "wm8995.h"
31 
32 #define WM8995_NUM_SUPPLIES 8
33 static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
34 	"DCVDD",
35 	"DBVDD1",
36 	"DBVDD2",
37 	"DBVDD3",
38 	"AVDD1",
39 	"AVDD2",
40 	"CPVDD",
41 	"MICVDD"
42 };
43 
44 static const struct reg_default wm8995_reg_defaults[] = {
45 	{ 0, 0x8995 },
46 	{ 5, 0x0100 },
47 	{ 16, 0x000b },
48 	{ 17, 0x000b },
49 	{ 24, 0x02c0 },
50 	{ 25, 0x02c0 },
51 	{ 26, 0x02c0 },
52 	{ 27, 0x02c0 },
53 	{ 28, 0x000f },
54 	{ 32, 0x0005 },
55 	{ 33, 0x0005 },
56 	{ 40, 0x0003 },
57 	{ 41, 0x0013 },
58 	{ 48, 0x0004 },
59 	{ 56, 0x09f8 },
60 	{ 64, 0x1f25 },
61 	{ 69, 0x0004 },
62 	{ 82, 0xaaaa },
63 	{ 84, 0x2a2a },
64 	{ 146, 0x0060 },
65 	{ 256, 0x0002 },
66 	{ 257, 0x8004 },
67 	{ 520, 0x0010 },
68 	{ 528, 0x0083 },
69 	{ 529, 0x0083 },
70 	{ 548, 0x0c80 },
71 	{ 580, 0x0c80 },
72 	{ 768, 0x4050 },
73 	{ 769, 0x4000 },
74 	{ 771, 0x0040 },
75 	{ 772, 0x0040 },
76 	{ 773, 0x0040 },
77 	{ 774, 0x0004 },
78 	{ 775, 0x0100 },
79 	{ 784, 0x4050 },
80 	{ 785, 0x4000 },
81 	{ 787, 0x0040 },
82 	{ 788, 0x0040 },
83 	{ 789, 0x0040 },
84 	{ 1024, 0x00c0 },
85 	{ 1025, 0x00c0 },
86 	{ 1026, 0x00c0 },
87 	{ 1027, 0x00c0 },
88 	{ 1028, 0x00c0 },
89 	{ 1029, 0x00c0 },
90 	{ 1030, 0x00c0 },
91 	{ 1031, 0x00c0 },
92 	{ 1056, 0x0200 },
93 	{ 1057, 0x0010 },
94 	{ 1058, 0x0200 },
95 	{ 1059, 0x0010 },
96 	{ 1088, 0x0098 },
97 	{ 1089, 0x0845 },
98 	{ 1104, 0x0098 },
99 	{ 1105, 0x0845 },
100 	{ 1152, 0x6318 },
101 	{ 1153, 0x6300 },
102 	{ 1154, 0x0fca },
103 	{ 1155, 0x0400 },
104 	{ 1156, 0x00d8 },
105 	{ 1157, 0x1eb5 },
106 	{ 1158, 0xf145 },
107 	{ 1159, 0x0b75 },
108 	{ 1160, 0x01c5 },
109 	{ 1161, 0x1c58 },
110 	{ 1162, 0xf373 },
111 	{ 1163, 0x0a54 },
112 	{ 1164, 0x0558 },
113 	{ 1165, 0x168e },
114 	{ 1166, 0xf829 },
115 	{ 1167, 0x07ad },
116 	{ 1168, 0x1103 },
117 	{ 1169, 0x0564 },
118 	{ 1170, 0x0559 },
119 	{ 1171, 0x4000 },
120 	{ 1184, 0x6318 },
121 	{ 1185, 0x6300 },
122 	{ 1186, 0x0fca },
123 	{ 1187, 0x0400 },
124 	{ 1188, 0x00d8 },
125 	{ 1189, 0x1eb5 },
126 	{ 1190, 0xf145 },
127 	{ 1191, 0x0b75 },
128 	{ 1192, 0x01c5 },
129 	{ 1193, 0x1c58 },
130 	{ 1194, 0xf373 },
131 	{ 1195, 0x0a54 },
132 	{ 1196, 0x0558 },
133 	{ 1197, 0x168e },
134 	{ 1198, 0xf829 },
135 	{ 1199, 0x07ad },
136 	{ 1200, 0x1103 },
137 	{ 1201, 0x0564 },
138 	{ 1202, 0x0559 },
139 	{ 1203, 0x4000 },
140 	{ 1280, 0x00c0 },
141 	{ 1281, 0x00c0 },
142 	{ 1282, 0x00c0 },
143 	{ 1283, 0x00c0 },
144 	{ 1312, 0x0200 },
145 	{ 1313, 0x0010 },
146 	{ 1344, 0x0098 },
147 	{ 1345, 0x0845 },
148 	{ 1408, 0x6318 },
149 	{ 1409, 0x6300 },
150 	{ 1410, 0x0fca },
151 	{ 1411, 0x0400 },
152 	{ 1412, 0x00d8 },
153 	{ 1413, 0x1eb5 },
154 	{ 1414, 0xf145 },
155 	{ 1415, 0x0b75 },
156 	{ 1416, 0x01c5 },
157 	{ 1417, 0x1c58 },
158 	{ 1418, 0xf373 },
159 	{ 1419, 0x0a54 },
160 	{ 1420, 0x0558 },
161 	{ 1421, 0x168e },
162 	{ 1422, 0xf829 },
163 	{ 1423, 0x07ad },
164 	{ 1424, 0x1103 },
165 	{ 1425, 0x0564 },
166 	{ 1426, 0x0559 },
167 	{ 1427, 0x4000 },
168 	{ 1568, 0x0002 },
169 	{ 1792, 0xa100 },
170 	{ 1793, 0xa101 },
171 	{ 1794, 0xa101 },
172 	{ 1795, 0xa101 },
173 	{ 1796, 0xa101 },
174 	{ 1797, 0xa101 },
175 	{ 1798, 0xa101 },
176 	{ 1799, 0xa101 },
177 	{ 1800, 0xa101 },
178 	{ 1801, 0xa101 },
179 	{ 1802, 0xa101 },
180 	{ 1803, 0xa101 },
181 	{ 1804, 0xa101 },
182 	{ 1805, 0xa101 },
183 	{ 1825, 0x0055 },
184 	{ 1848, 0x3fff },
185 	{ 1849, 0x1fff },
186 	{ 2049, 0x0001 },
187 	{ 2050, 0x0069 },
188 	{ 2056, 0x0002 },
189 	{ 2057, 0x0003 },
190 	{ 2058, 0x0069 },
191 	{ 12288, 0x0001 },
192 	{ 12289, 0x0001 },
193 	{ 12291, 0x0006 },
194 	{ 12292, 0x0040 },
195 	{ 12293, 0x0001 },
196 	{ 12294, 0x000f },
197 	{ 12295, 0x0006 },
198 	{ 12296, 0x0001 },
199 	{ 12297, 0x0003 },
200 	{ 12298, 0x0104 },
201 	{ 12300, 0x0060 },
202 	{ 12301, 0x0011 },
203 	{ 12302, 0x0401 },
204 	{ 12304, 0x0050 },
205 	{ 12305, 0x0003 },
206 	{ 12306, 0x0100 },
207 	{ 12308, 0x0051 },
208 	{ 12309, 0x0003 },
209 	{ 12310, 0x0104 },
210 	{ 12311, 0x000a },
211 	{ 12312, 0x0060 },
212 	{ 12313, 0x003b },
213 	{ 12314, 0x0502 },
214 	{ 12315, 0x0100 },
215 	{ 12316, 0x2fff },
216 	{ 12320, 0x2fff },
217 	{ 12324, 0x2fff },
218 	{ 12328, 0x2fff },
219 	{ 12332, 0x2fff },
220 	{ 12336, 0x2fff },
221 	{ 12340, 0x2fff },
222 	{ 12344, 0x2fff },
223 	{ 12348, 0x2fff },
224 	{ 12352, 0x0001 },
225 	{ 12353, 0x0001 },
226 	{ 12355, 0x0006 },
227 	{ 12356, 0x0040 },
228 	{ 12357, 0x0001 },
229 	{ 12358, 0x000f },
230 	{ 12359, 0x0006 },
231 	{ 12360, 0x0001 },
232 	{ 12361, 0x0003 },
233 	{ 12362, 0x0104 },
234 	{ 12364, 0x0060 },
235 	{ 12365, 0x0011 },
236 	{ 12366, 0x0401 },
237 	{ 12368, 0x0050 },
238 	{ 12369, 0x0003 },
239 	{ 12370, 0x0100 },
240 	{ 12372, 0x0060 },
241 	{ 12373, 0x003b },
242 	{ 12374, 0x0502 },
243 	{ 12375, 0x0100 },
244 	{ 12376, 0x2fff },
245 	{ 12380, 0x2fff },
246 	{ 12384, 0x2fff },
247 	{ 12388, 0x2fff },
248 	{ 12392, 0x2fff },
249 	{ 12396, 0x2fff },
250 	{ 12400, 0x2fff },
251 	{ 12404, 0x2fff },
252 	{ 12408, 0x2fff },
253 	{ 12412, 0x2fff },
254 	{ 12416, 0x0001 },
255 	{ 12417, 0x0001 },
256 	{ 12419, 0x0006 },
257 	{ 12420, 0x0040 },
258 	{ 12421, 0x0001 },
259 	{ 12422, 0x000f },
260 	{ 12423, 0x0006 },
261 	{ 12424, 0x0001 },
262 	{ 12425, 0x0003 },
263 	{ 12426, 0x0106 },
264 	{ 12428, 0x0061 },
265 	{ 12429, 0x0011 },
266 	{ 12430, 0x0401 },
267 	{ 12432, 0x0050 },
268 	{ 12433, 0x0003 },
269 	{ 12434, 0x0102 },
270 	{ 12436, 0x0051 },
271 	{ 12437, 0x0003 },
272 	{ 12438, 0x0106 },
273 	{ 12439, 0x000a },
274 	{ 12440, 0x0061 },
275 	{ 12441, 0x003b },
276 	{ 12442, 0x0502 },
277 	{ 12443, 0x0100 },
278 	{ 12444, 0x2fff },
279 	{ 12448, 0x2fff },
280 	{ 12452, 0x2fff },
281 	{ 12456, 0x2fff },
282 	{ 12460, 0x2fff },
283 	{ 12464, 0x2fff },
284 	{ 12468, 0x2fff },
285 	{ 12472, 0x2fff },
286 	{ 12476, 0x2fff },
287 	{ 12480, 0x0001 },
288 	{ 12481, 0x0001 },
289 	{ 12483, 0x0006 },
290 	{ 12484, 0x0040 },
291 	{ 12485, 0x0001 },
292 	{ 12486, 0x000f },
293 	{ 12487, 0x0006 },
294 	{ 12488, 0x0001 },
295 	{ 12489, 0x0003 },
296 	{ 12490, 0x0106 },
297 	{ 12492, 0x0061 },
298 	{ 12493, 0x0011 },
299 	{ 12494, 0x0401 },
300 	{ 12496, 0x0050 },
301 	{ 12497, 0x0003 },
302 	{ 12498, 0x0102 },
303 	{ 12500, 0x0061 },
304 	{ 12501, 0x003b },
305 	{ 12502, 0x0502 },
306 	{ 12503, 0x0100 },
307 	{ 12504, 0x2fff },
308 	{ 12508, 0x2fff },
309 	{ 12512, 0x2fff },
310 	{ 12516, 0x2fff },
311 	{ 12520, 0x2fff },
312 	{ 12524, 0x2fff },
313 	{ 12528, 0x2fff },
314 	{ 12532, 0x2fff },
315 	{ 12536, 0x2fff },
316 	{ 12540, 0x2fff },
317 	{ 12544, 0x0060 },
318 	{ 12546, 0x0601 },
319 	{ 12548, 0x0050 },
320 	{ 12550, 0x0100 },
321 	{ 12552, 0x0001 },
322 	{ 12554, 0x0104 },
323 	{ 12555, 0x0100 },
324 	{ 12556, 0x2fff },
325 	{ 12560, 0x2fff },
326 	{ 12564, 0x2fff },
327 	{ 12568, 0x2fff },
328 	{ 12572, 0x2fff },
329 	{ 12576, 0x2fff },
330 	{ 12580, 0x2fff },
331 	{ 12584, 0x2fff },
332 	{ 12588, 0x2fff },
333 	{ 12592, 0x2fff },
334 	{ 12596, 0x2fff },
335 	{ 12600, 0x2fff },
336 	{ 12604, 0x2fff },
337 	{ 12608, 0x0061 },
338 	{ 12610, 0x0601 },
339 	{ 12612, 0x0050 },
340 	{ 12614, 0x0102 },
341 	{ 12616, 0x0001 },
342 	{ 12618, 0x0106 },
343 	{ 12619, 0x0100 },
344 	{ 12620, 0x2fff },
345 	{ 12624, 0x2fff },
346 	{ 12628, 0x2fff },
347 	{ 12632, 0x2fff },
348 	{ 12636, 0x2fff },
349 	{ 12640, 0x2fff },
350 	{ 12644, 0x2fff },
351 	{ 12648, 0x2fff },
352 	{ 12652, 0x2fff },
353 	{ 12656, 0x2fff },
354 	{ 12660, 0x2fff },
355 	{ 12664, 0x2fff },
356 	{ 12668, 0x2fff },
357 	{ 12672, 0x0060 },
358 	{ 12674, 0x0601 },
359 	{ 12676, 0x0061 },
360 	{ 12678, 0x0601 },
361 	{ 12680, 0x0050 },
362 	{ 12682, 0x0300 },
363 	{ 12684, 0x0001 },
364 	{ 12686, 0x0304 },
365 	{ 12688, 0x0040 },
366 	{ 12690, 0x000f },
367 	{ 12692, 0x0001 },
368 	{ 12695, 0x0100 },
369 };
370 
371 struct fll_config {
372 	int src;
373 	int in;
374 	int out;
375 };
376 
377 struct wm8995_priv {
378 	struct regmap *regmap;
379 	int sysclk[2];
380 	int mclk[2];
381 	int aifclk[2];
382 	struct fll_config fll[2], fll_suspend[2];
383 	struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
384 	struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
385 	struct snd_soc_component *component;
386 };
387 
388 /*
389  * We can't use the same notifier block for more than one supply and
390  * there's no way I can see to get from a callback to the caller
391  * except container_of().
392  */
393 #define WM8995_REGULATOR_EVENT(n) \
394 static int wm8995_regulator_event_##n(struct notifier_block *nb, \
395 				      unsigned long event, void *data)    \
396 { \
397 	struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
398 				     disable_nb[n]); \
399 	if (event & REGULATOR_EVENT_DISABLE) { \
400 		regcache_mark_dirty(wm8995->regmap);	\
401 	} \
402 	return 0; \
403 }
404 
405 WM8995_REGULATOR_EVENT(0)
406 WM8995_REGULATOR_EVENT(1)
407 WM8995_REGULATOR_EVENT(2)
408 WM8995_REGULATOR_EVENT(3)
409 WM8995_REGULATOR_EVENT(4)
410 WM8995_REGULATOR_EVENT(5)
411 WM8995_REGULATOR_EVENT(6)
412 WM8995_REGULATOR_EVENT(7)
413 
414 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
415 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
416 static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
417 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
418 
419 static const char *in1l_text[] = {
420 	"Differential", "Single-ended IN1LN", "Single-ended IN1LP"
421 };
422 
423 static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
424 			    2, in1l_text);
425 
426 static const char *in1r_text[] = {
427 	"Differential", "Single-ended IN1RN", "Single-ended IN1RP"
428 };
429 
430 static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
431 			    0, in1r_text);
432 
433 static const char *dmic_src_text[] = {
434 	"DMICDAT1", "DMICDAT2", "DMICDAT3"
435 };
436 
437 static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
438 			    8, dmic_src_text);
439 static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
440 			    6, dmic_src_text);
441 
442 static const struct snd_kcontrol_new wm8995_snd_controls[] = {
443 	SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
444 		WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
445 	SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
446 		WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
447 
448 	SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
449 		WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
450 	SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
451 		WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
452 
453 	SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
454 		WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
455 	SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
456 		WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
457 	SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
458 		WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
459 
460 	SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
461 		WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
462 
463 	SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
464 		4, 3, 0, in1l_boost_tlv),
465 
466 	SOC_ENUM("IN1L Mode", in1l_enum),
467 	SOC_ENUM("IN1R Mode", in1r_enum),
468 
469 	SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
470 	SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
471 
472 	SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
473 		24, 0, sidetone_tlv),
474 	SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
475 		24, 0, sidetone_tlv),
476 
477 	SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
478 		WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
479 	SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
480 		WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
481 	SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
482 		WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
483 };
484 
wm8995_update_class_w(struct snd_soc_component * component)485 static void wm8995_update_class_w(struct snd_soc_component *component)
486 {
487 	int enable = 1;
488 	int source = 0;  /* GCC flow analysis can't track enable */
489 	int reg, reg_r;
490 
491 	/* We also need the same setting for L/R and only one path */
492 	reg = snd_soc_component_read(component, WM8995_DAC1_LEFT_MIXER_ROUTING);
493 	switch (reg) {
494 	case WM8995_AIF2DACL_TO_DAC1L:
495 		dev_dbg(component->dev, "Class W source AIF2DAC\n");
496 		source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
497 		break;
498 	case WM8995_AIF1DAC2L_TO_DAC1L:
499 		dev_dbg(component->dev, "Class W source AIF1DAC2\n");
500 		source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
501 		break;
502 	case WM8995_AIF1DAC1L_TO_DAC1L:
503 		dev_dbg(component->dev, "Class W source AIF1DAC1\n");
504 		source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
505 		break;
506 	default:
507 		dev_dbg(component->dev, "DAC mixer setting: %x\n", reg);
508 		enable = 0;
509 		break;
510 	}
511 
512 	reg_r = snd_soc_component_read(component, WM8995_DAC1_RIGHT_MIXER_ROUTING);
513 	if (reg_r != reg) {
514 		dev_dbg(component->dev, "Left and right DAC mixers different\n");
515 		enable = 0;
516 	}
517 
518 	if (enable) {
519 		dev_dbg(component->dev, "Class W enabled\n");
520 		snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
521 				    WM8995_CP_DYN_PWR_MASK |
522 				    WM8995_CP_DYN_SRC_SEL_MASK,
523 				    source | WM8995_CP_DYN_PWR);
524 	} else {
525 		dev_dbg(component->dev, "Class W disabled\n");
526 		snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
527 				    WM8995_CP_DYN_PWR_MASK, 0);
528 	}
529 }
530 
check_clk_sys(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)531 static int check_clk_sys(struct snd_soc_dapm_widget *source,
532 			 struct snd_soc_dapm_widget *sink)
533 {
534 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
535 	unsigned int reg;
536 	const char *clk;
537 
538 	reg = snd_soc_component_read(component, WM8995_CLOCKING_1);
539 	/* Check what we're currently using for CLK_SYS */
540 	if (reg & WM8995_SYSCLK_SRC)
541 		clk = "AIF2CLK";
542 	else
543 		clk = "AIF1CLK";
544 	return !snd_soc_dapm_widget_name_cmp(source, clk);
545 }
546 
wm8995_put_class_w(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)547 static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
548 			      struct snd_ctl_elem_value *ucontrol)
549 {
550 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
551 	int ret;
552 
553 	ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
554 	wm8995_update_class_w(component);
555 	return ret;
556 }
557 
hp_supply_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)558 static int hp_supply_event(struct snd_soc_dapm_widget *w,
559 			   struct snd_kcontrol *kcontrol, int event)
560 {
561 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
562 
563 	switch (event) {
564 	case SND_SOC_DAPM_PRE_PMU:
565 		/* Enable the headphone amp */
566 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
567 				    WM8995_HPOUT1L_ENA_MASK |
568 				    WM8995_HPOUT1R_ENA_MASK,
569 				    WM8995_HPOUT1L_ENA |
570 				    WM8995_HPOUT1R_ENA);
571 
572 		/* Enable the second stage */
573 		snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
574 				    WM8995_HPOUT1L_DLY_MASK |
575 				    WM8995_HPOUT1R_DLY_MASK,
576 				    WM8995_HPOUT1L_DLY |
577 				    WM8995_HPOUT1R_DLY);
578 		break;
579 	case SND_SOC_DAPM_PRE_PMD:
580 		snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
581 				    WM8995_CP_ENA_MASK, 0);
582 		break;
583 	}
584 
585 	return 0;
586 }
587 
dc_servo_cmd(struct snd_soc_component * component,unsigned int reg,unsigned int val,unsigned int mask)588 static void dc_servo_cmd(struct snd_soc_component *component,
589 			 unsigned int reg, unsigned int val, unsigned int mask)
590 {
591 	int timeout = 10;
592 
593 	dev_dbg(component->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
594 		__func__, reg, val, mask);
595 
596 	snd_soc_component_write(component, reg, val);
597 	while (timeout--) {
598 		msleep(10);
599 		val = snd_soc_component_read(component, WM8995_DC_SERVO_READBACK_0);
600 		if ((val & mask) == mask)
601 			return;
602 	}
603 
604 	dev_err(component->dev, "Timed out waiting for DC Servo\n");
605 }
606 
hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)607 static int hp_event(struct snd_soc_dapm_widget *w,
608 		    struct snd_kcontrol *kcontrol, int event)
609 {
610 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
611 	unsigned int reg;
612 
613 	reg = snd_soc_component_read(component, WM8995_ANALOGUE_HP_1);
614 
615 	switch (event) {
616 	case SND_SOC_DAPM_POST_PMU:
617 		snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
618 				    WM8995_CP_ENA_MASK, WM8995_CP_ENA);
619 
620 		msleep(5);
621 
622 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
623 				    WM8995_HPOUT1L_ENA_MASK |
624 				    WM8995_HPOUT1R_ENA_MASK,
625 				    WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
626 
627 		udelay(20);
628 
629 		reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
630 		snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
631 
632 		snd_soc_component_write(component, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
633 			      WM8995_DCS_ENA_CHAN_1);
634 
635 		dc_servo_cmd(component, WM8995_DC_SERVO_2,
636 			     WM8995_DCS_TRIG_STARTUP_0 |
637 			     WM8995_DCS_TRIG_STARTUP_1,
638 			     WM8995_DCS_TRIG_DAC_WR_0 |
639 			     WM8995_DCS_TRIG_DAC_WR_1);
640 
641 		reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
642 		       WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
643 		snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
644 
645 		break;
646 	case SND_SOC_DAPM_PRE_PMD:
647 		snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
648 				    WM8995_HPOUT1L_OUTP_MASK |
649 				    WM8995_HPOUT1R_OUTP_MASK |
650 				    WM8995_HPOUT1L_RMV_SHORT_MASK |
651 				    WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
652 
653 		snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
654 				    WM8995_HPOUT1L_DLY_MASK |
655 				    WM8995_HPOUT1R_DLY_MASK, 0);
656 
657 		snd_soc_component_write(component, WM8995_DC_SERVO_1, 0);
658 
659 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
660 				    WM8995_HPOUT1L_ENA_MASK |
661 				    WM8995_HPOUT1R_ENA_MASK,
662 				    0);
663 		break;
664 	}
665 
666 	return 0;
667 }
668 
configure_aif_clock(struct snd_soc_component * component,int aif)669 static int configure_aif_clock(struct snd_soc_component *component, int aif)
670 {
671 	struct wm8995_priv *wm8995;
672 	int rate;
673 	int reg1 = 0;
674 	int offset;
675 
676 	wm8995 = snd_soc_component_get_drvdata(component);
677 
678 	if (aif)
679 		offset = 4;
680 	else
681 		offset = 0;
682 
683 	switch (wm8995->sysclk[aif]) {
684 	case WM8995_SYSCLK_MCLK1:
685 		rate = wm8995->mclk[0];
686 		break;
687 	case WM8995_SYSCLK_MCLK2:
688 		reg1 |= 0x8;
689 		rate = wm8995->mclk[1];
690 		break;
691 	case WM8995_SYSCLK_FLL1:
692 		reg1 |= 0x10;
693 		rate = wm8995->fll[0].out;
694 		break;
695 	case WM8995_SYSCLK_FLL2:
696 		reg1 |= 0x18;
697 		rate = wm8995->fll[1].out;
698 		break;
699 	default:
700 		return -EINVAL;
701 	}
702 
703 	if (rate >= 13500000) {
704 		rate /= 2;
705 		reg1 |= WM8995_AIF1CLK_DIV;
706 
707 		dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
708 			aif + 1, rate);
709 	}
710 
711 	wm8995->aifclk[aif] = rate;
712 
713 	snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1 + offset,
714 			    WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
715 			    reg1);
716 	return 0;
717 }
718 
configure_clock(struct snd_soc_component * component)719 static int configure_clock(struct snd_soc_component *component)
720 {
721 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
722 	struct wm8995_priv *wm8995;
723 	int change, new;
724 
725 	wm8995 = snd_soc_component_get_drvdata(component);
726 
727 	/* Bring up the AIF clocks first */
728 	configure_aif_clock(component, 0);
729 	configure_aif_clock(component, 1);
730 
731 	/*
732 	 * Then switch CLK_SYS over to the higher of them; a change
733 	 * can only happen as a result of a clocking change which can
734 	 * only be made outside of DAPM so we can safely redo the
735 	 * clocking.
736 	 */
737 
738 	/* If they're equal it doesn't matter which is used */
739 	if (wm8995->aifclk[0] == wm8995->aifclk[1])
740 		return 0;
741 
742 	if (wm8995->aifclk[0] < wm8995->aifclk[1])
743 		new = WM8995_SYSCLK_SRC;
744 	else
745 		new = 0;
746 
747 	change = snd_soc_component_update_bits(component, WM8995_CLOCKING_1,
748 				     WM8995_SYSCLK_SRC_MASK, new);
749 	if (!change)
750 		return 0;
751 
752 	snd_soc_dapm_sync(dapm);
753 
754 	return 0;
755 }
756 
clk_sys_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)757 static int clk_sys_event(struct snd_soc_dapm_widget *w,
758 			 struct snd_kcontrol *kcontrol, int event)
759 {
760 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
761 
762 	switch (event) {
763 	case SND_SOC_DAPM_PRE_PMU:
764 		return configure_clock(component);
765 
766 	case SND_SOC_DAPM_POST_PMD:
767 		configure_clock(component);
768 		break;
769 	}
770 
771 	return 0;
772 }
773 
774 static const char *sidetone_text[] = {
775 	"ADC/DMIC1", "DMIC2",
776 };
777 
778 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text);
779 
780 static const struct snd_kcontrol_new sidetone1_mux =
781 	SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
782 
783 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text);
784 
785 static const struct snd_kcontrol_new sidetone2_mux =
786 	SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
787 
788 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
789 	SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
790 		1, 1, 0),
791 	SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
792 		0, 1, 0),
793 };
794 
795 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
796 	SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
797 		1, 1, 0),
798 	SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
799 		0, 1, 0),
800 };
801 
802 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
803 	SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
804 		1, 1, 0),
805 	SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
806 		0, 1, 0),
807 };
808 
809 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
810 	SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
811 		1, 1, 0),
812 	SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
813 		0, 1, 0),
814 };
815 
816 static const struct snd_kcontrol_new dac1l_mix[] = {
817 	WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
818 		5, 1, 0),
819 	WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
820 		4, 1, 0),
821 	WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
822 		2, 1, 0),
823 	WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
824 		1, 1, 0),
825 	WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
826 		0, 1, 0),
827 };
828 
829 static const struct snd_kcontrol_new dac1r_mix[] = {
830 	WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
831 		5, 1, 0),
832 	WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
833 		4, 1, 0),
834 	WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
835 		2, 1, 0),
836 	WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
837 		1, 1, 0),
838 	WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
839 		0, 1, 0),
840 };
841 
842 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
843 	SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
844 		5, 1, 0),
845 	SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
846 		4, 1, 0),
847 	SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
848 		2, 1, 0),
849 	SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
850 		1, 1, 0),
851 	SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
852 		0, 1, 0),
853 };
854 
855 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
856 	SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
857 		5, 1, 0),
858 	SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
859 		4, 1, 0),
860 	SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
861 		2, 1, 0),
862 	SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
863 		1, 1, 0),
864 	SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
865 		0, 1, 0),
866 };
867 
868 static const struct snd_kcontrol_new in1l_pga =
869 	SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
870 
871 static const struct snd_kcontrol_new in1r_pga =
872 	SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
873 
874 static const char *adc_mux_text[] = {
875 	"ADC",
876 	"DMIC",
877 };
878 
879 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
880 
881 static const struct snd_kcontrol_new adcl_mux =
882 	SOC_DAPM_ENUM("ADCL Mux", adc_enum);
883 
884 static const struct snd_kcontrol_new adcr_mux =
885 	SOC_DAPM_ENUM("ADCR Mux", adc_enum);
886 
887 static const char *spk_src_text[] = {
888 	"DAC1L", "DAC1R", "DAC2L", "DAC2R"
889 };
890 
891 static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
892 			    0, spk_src_text);
893 static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
894 			    0, spk_src_text);
895 static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
896 			    0, spk_src_text);
897 static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
898 			    0, spk_src_text);
899 
900 static const struct snd_kcontrol_new spk1l_mux =
901 	SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
902 static const struct snd_kcontrol_new spk1r_mux =
903 	SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
904 static const struct snd_kcontrol_new spk2l_mux =
905 	SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
906 static const struct snd_kcontrol_new spk2r_mux =
907 	SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
908 
909 static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
910 	SND_SOC_DAPM_INPUT("DMIC1DAT"),
911 	SND_SOC_DAPM_INPUT("DMIC2DAT"),
912 
913 	SND_SOC_DAPM_INPUT("IN1L"),
914 	SND_SOC_DAPM_INPUT("IN1R"),
915 
916 	SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
917 		&in1l_pga, 1),
918 	SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
919 		&in1r_pga, 1),
920 
921 	SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0,
922 			    NULL, 0),
923 	SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0,
924 			    NULL, 0),
925 
926 	SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
927 	SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
928 	SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
929 	SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
930 	SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
931 	SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
932 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
933 
934 	SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
935 		WM8995_POWER_MANAGEMENT_3, 9, 0),
936 	SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
937 		WM8995_POWER_MANAGEMENT_3, 8, 0),
938 	SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
939 	SND_SOC_NOPM, 0, 0),
940 	SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
941 		0, WM8995_POWER_MANAGEMENT_3, 11, 0),
942 	SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
943 		0, WM8995_POWER_MANAGEMENT_3, 10, 0),
944 
945 	SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux),
946 	SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
947 
948 	SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
949 	SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
950 	SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
951 	SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
952 
953 	SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
954 	SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
955 
956 	SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
957 		aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
958 	SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
959 		aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
960 	SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
961 		aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
962 	SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
963 		aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
964 
965 	SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
966 		9, 0),
967 	SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
968 		8, 0),
969 	SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
970 		0, 0),
971 
972 	SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
973 		11, 0),
974 	SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
975 		10, 0),
976 
977 	SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
978 		aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
979 	SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
980 		aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
981 
982 	SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
983 	SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
984 	SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
985 	SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
986 
987 	SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
988 		ARRAY_SIZE(dac1l_mix)),
989 	SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
990 		ARRAY_SIZE(dac1r_mix)),
991 
992 	SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
993 	SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
994 
995 	SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
996 		hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
997 
998 	SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
999 		hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1000 
1001 	SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
1002 		4, 0, &spk1l_mux),
1003 	SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
1004 		4, 0, &spk1r_mux),
1005 	SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
1006 		4, 0, &spk2l_mux),
1007 	SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
1008 		4, 0, &spk2r_mux),
1009 
1010 	SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1011 
1012 	SND_SOC_DAPM_OUTPUT("HP1L"),
1013 	SND_SOC_DAPM_OUTPUT("HP1R"),
1014 	SND_SOC_DAPM_OUTPUT("SPK1L"),
1015 	SND_SOC_DAPM_OUTPUT("SPK1R"),
1016 	SND_SOC_DAPM_OUTPUT("SPK2L"),
1017 	SND_SOC_DAPM_OUTPUT("SPK2R")
1018 };
1019 
1020 static const struct snd_soc_dapm_route wm8995_intercon[] = {
1021 	{ "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1022 	{ "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1023 
1024 	{ "DSP1CLK", NULL, "CLK_SYS" },
1025 	{ "DSP2CLK", NULL, "CLK_SYS" },
1026 	{ "SYSDSPCLK", NULL, "CLK_SYS" },
1027 
1028 	{ "AIF1ADC1L", NULL, "AIF1CLK" },
1029 	{ "AIF1ADC1L", NULL, "DSP1CLK" },
1030 	{ "AIF1ADC1R", NULL, "AIF1CLK" },
1031 	{ "AIF1ADC1R", NULL, "DSP1CLK" },
1032 	{ "AIF1ADC1R", NULL, "SYSDSPCLK" },
1033 
1034 	{ "AIF1ADC2L", NULL, "AIF1CLK" },
1035 	{ "AIF1ADC2L", NULL, "DSP1CLK" },
1036 	{ "AIF1ADC2R", NULL, "AIF1CLK" },
1037 	{ "AIF1ADC2R", NULL, "DSP1CLK" },
1038 	{ "AIF1ADC2R", NULL, "SYSDSPCLK" },
1039 
1040 	{ "DMIC1L", NULL, "DMIC1DAT" },
1041 	{ "DMIC1L", NULL, "CLK_SYS" },
1042 	{ "DMIC1R", NULL, "DMIC1DAT" },
1043 	{ "DMIC1R", NULL, "CLK_SYS" },
1044 	{ "DMIC2L", NULL, "DMIC2DAT" },
1045 	{ "DMIC2L", NULL, "CLK_SYS" },
1046 	{ "DMIC2R", NULL, "DMIC2DAT" },
1047 	{ "DMIC2R", NULL, "CLK_SYS" },
1048 
1049 	{ "ADCL", NULL, "AIF1CLK" },
1050 	{ "ADCL", NULL, "DSP1CLK" },
1051 	{ "ADCL", NULL, "SYSDSPCLK" },
1052 
1053 	{ "ADCR", NULL, "AIF1CLK" },
1054 	{ "ADCR", NULL, "DSP1CLK" },
1055 	{ "ADCR", NULL, "SYSDSPCLK" },
1056 
1057 	{ "IN1L PGA", "IN1L Switch", "IN1L" },
1058 	{ "IN1R PGA", "IN1R Switch", "IN1R" },
1059 	{ "IN1L PGA", NULL, "LDO2" },
1060 	{ "IN1R PGA", NULL, "LDO2" },
1061 
1062 	{ "ADCL", NULL, "IN1L PGA" },
1063 	{ "ADCR", NULL, "IN1R PGA" },
1064 
1065 	{ "ADCL Mux", "ADC", "ADCL" },
1066 	{ "ADCL Mux", "DMIC", "DMIC1L" },
1067 	{ "ADCR Mux", "ADC", "ADCR" },
1068 	{ "ADCR Mux", "DMIC", "DMIC1R" },
1069 
1070 	/* AIF1 outputs */
1071 	{ "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1072 	{ "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1073 
1074 	{ "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1075 	{ "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1076 
1077 	{ "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1078 	{ "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1079 
1080 	{ "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1081 	{ "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1082 
1083 	/* Sidetone */
1084 	{ "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
1085 	{ "Left Sidetone", "DMIC2", "AIF1ADC2L" },
1086 	{ "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
1087 	{ "Right Sidetone", "DMIC2", "AIF1ADC2R" },
1088 
1089 	{ "AIF1DAC1L", NULL, "AIF1CLK" },
1090 	{ "AIF1DAC1L", NULL, "DSP1CLK" },
1091 	{ "AIF1DAC1R", NULL, "AIF1CLK" },
1092 	{ "AIF1DAC1R", NULL, "DSP1CLK" },
1093 	{ "AIF1DAC1R", NULL, "SYSDSPCLK" },
1094 
1095 	{ "AIF1DAC2L", NULL, "AIF1CLK" },
1096 	{ "AIF1DAC2L", NULL, "DSP1CLK" },
1097 	{ "AIF1DAC2R", NULL, "AIF1CLK" },
1098 	{ "AIF1DAC2R", NULL, "DSP1CLK" },
1099 	{ "AIF1DAC2R", NULL, "SYSDSPCLK" },
1100 
1101 	{ "DAC1L", NULL, "AIF1CLK" },
1102 	{ "DAC1L", NULL, "DSP1CLK" },
1103 	{ "DAC1L", NULL, "SYSDSPCLK" },
1104 
1105 	{ "DAC1R", NULL, "AIF1CLK" },
1106 	{ "DAC1R", NULL, "DSP1CLK" },
1107 	{ "DAC1R", NULL, "SYSDSPCLK" },
1108 
1109 	{ "AIF1DAC1L", NULL, "AIF1DACDAT" },
1110 	{ "AIF1DAC1R", NULL, "AIF1DACDAT" },
1111 	{ "AIF1DAC2L", NULL, "AIF1DACDAT" },
1112 	{ "AIF1DAC2R", NULL, "AIF1DACDAT" },
1113 
1114 	/* DAC1 inputs */
1115 	{ "DAC1L", NULL, "DAC1L Mixer" },
1116 	{ "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1117 	{ "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1118 	{ "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1119 	{ "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1120 
1121 	{ "DAC1R", NULL, "DAC1R Mixer" },
1122 	{ "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1123 	{ "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1124 	{ "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1125 	{ "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1126 
1127 	/* DAC2/AIF2 outputs */
1128 	{ "DAC2L", NULL, "AIF2DAC2L Mixer" },
1129 	{ "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1130 	{ "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1131 
1132 	{ "DAC2R", NULL, "AIF2DAC2R Mixer" },
1133 	{ "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1134 	{ "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1135 
1136 	/* Output stages */
1137 	{ "Headphone PGA", NULL, "DAC1L" },
1138 	{ "Headphone PGA", NULL, "DAC1R" },
1139 
1140 	{ "Headphone PGA", NULL, "DAC2L" },
1141 	{ "Headphone PGA", NULL, "DAC2R" },
1142 
1143 	{ "Headphone PGA", NULL, "Headphone Supply" },
1144 	{ "Headphone PGA", NULL, "CLK_SYS" },
1145 	{ "Headphone PGA", NULL, "LDO2" },
1146 
1147 	{ "HP1L", NULL, "Headphone PGA" },
1148 	{ "HP1R", NULL, "Headphone PGA" },
1149 
1150 	{ "SPK1L Driver", "DAC1L", "DAC1L" },
1151 	{ "SPK1L Driver", "DAC1R", "DAC1R" },
1152 	{ "SPK1L Driver", "DAC2L", "DAC2L" },
1153 	{ "SPK1L Driver", "DAC2R", "DAC2R" },
1154 	{ "SPK1L Driver", NULL, "CLK_SYS" },
1155 
1156 	{ "SPK1R Driver", "DAC1L", "DAC1L" },
1157 	{ "SPK1R Driver", "DAC1R", "DAC1R" },
1158 	{ "SPK1R Driver", "DAC2L", "DAC2L" },
1159 	{ "SPK1R Driver", "DAC2R", "DAC2R" },
1160 	{ "SPK1R Driver", NULL, "CLK_SYS" },
1161 
1162 	{ "SPK2L Driver", "DAC1L", "DAC1L" },
1163 	{ "SPK2L Driver", "DAC1R", "DAC1R" },
1164 	{ "SPK2L Driver", "DAC2L", "DAC2L" },
1165 	{ "SPK2L Driver", "DAC2R", "DAC2R" },
1166 	{ "SPK2L Driver", NULL, "CLK_SYS" },
1167 
1168 	{ "SPK2R Driver", "DAC1L", "DAC1L" },
1169 	{ "SPK2R Driver", "DAC1R", "DAC1R" },
1170 	{ "SPK2R Driver", "DAC2L", "DAC2L" },
1171 	{ "SPK2R Driver", "DAC2R", "DAC2R" },
1172 	{ "SPK2R Driver", NULL, "CLK_SYS" },
1173 
1174 	{ "SPK1L", NULL, "SPK1L Driver" },
1175 	{ "SPK1R", NULL, "SPK1R Driver" },
1176 	{ "SPK2L", NULL, "SPK2L Driver" },
1177 	{ "SPK2R", NULL, "SPK2R Driver" }
1178 };
1179 
wm8995_readable(struct device * dev,unsigned int reg)1180 static bool wm8995_readable(struct device *dev, unsigned int reg)
1181 {
1182 	switch (reg) {
1183 	case WM8995_SOFTWARE_RESET:
1184 	case WM8995_POWER_MANAGEMENT_1:
1185 	case WM8995_POWER_MANAGEMENT_2:
1186 	case WM8995_POWER_MANAGEMENT_3:
1187 	case WM8995_POWER_MANAGEMENT_4:
1188 	case WM8995_POWER_MANAGEMENT_5:
1189 	case WM8995_LEFT_LINE_INPUT_1_VOLUME:
1190 	case WM8995_RIGHT_LINE_INPUT_1_VOLUME:
1191 	case WM8995_LEFT_LINE_INPUT_CONTROL:
1192 	case WM8995_DAC1_LEFT_VOLUME:
1193 	case WM8995_DAC1_RIGHT_VOLUME:
1194 	case WM8995_DAC2_LEFT_VOLUME:
1195 	case WM8995_DAC2_RIGHT_VOLUME:
1196 	case WM8995_OUTPUT_VOLUME_ZC_1:
1197 	case WM8995_MICBIAS_1:
1198 	case WM8995_MICBIAS_2:
1199 	case WM8995_LDO_1:
1200 	case WM8995_LDO_2:
1201 	case WM8995_ACCESSORY_DETECT_MODE1:
1202 	case WM8995_ACCESSORY_DETECT_MODE2:
1203 	case WM8995_HEADPHONE_DETECT1:
1204 	case WM8995_HEADPHONE_DETECT2:
1205 	case WM8995_MIC_DETECT_1:
1206 	case WM8995_MIC_DETECT_2:
1207 	case WM8995_CHARGE_PUMP_1:
1208 	case WM8995_CLASS_W_1:
1209 	case WM8995_DC_SERVO_1:
1210 	case WM8995_DC_SERVO_2:
1211 	case WM8995_DC_SERVO_3:
1212 	case WM8995_DC_SERVO_5:
1213 	case WM8995_DC_SERVO_6:
1214 	case WM8995_DC_SERVO_7:
1215 	case WM8995_DC_SERVO_READBACK_0:
1216 	case WM8995_ANALOGUE_HP_1:
1217 	case WM8995_ANALOGUE_HP_2:
1218 	case WM8995_CHIP_REVISION:
1219 	case WM8995_CONTROL_INTERFACE_1:
1220 	case WM8995_CONTROL_INTERFACE_2:
1221 	case WM8995_WRITE_SEQUENCER_CTRL_1:
1222 	case WM8995_WRITE_SEQUENCER_CTRL_2:
1223 	case WM8995_AIF1_CLOCKING_1:
1224 	case WM8995_AIF1_CLOCKING_2:
1225 	case WM8995_AIF2_CLOCKING_1:
1226 	case WM8995_AIF2_CLOCKING_2:
1227 	case WM8995_CLOCKING_1:
1228 	case WM8995_CLOCKING_2:
1229 	case WM8995_AIF1_RATE:
1230 	case WM8995_AIF2_RATE:
1231 	case WM8995_RATE_STATUS:
1232 	case WM8995_FLL1_CONTROL_1:
1233 	case WM8995_FLL1_CONTROL_2:
1234 	case WM8995_FLL1_CONTROL_3:
1235 	case WM8995_FLL1_CONTROL_4:
1236 	case WM8995_FLL1_CONTROL_5:
1237 	case WM8995_FLL2_CONTROL_1:
1238 	case WM8995_FLL2_CONTROL_2:
1239 	case WM8995_FLL2_CONTROL_3:
1240 	case WM8995_FLL2_CONTROL_4:
1241 	case WM8995_FLL2_CONTROL_5:
1242 	case WM8995_AIF1_CONTROL_1:
1243 	case WM8995_AIF1_CONTROL_2:
1244 	case WM8995_AIF1_MASTER_SLAVE:
1245 	case WM8995_AIF1_BCLK:
1246 	case WM8995_AIF1ADC_LRCLK:
1247 	case WM8995_AIF1DAC_LRCLK:
1248 	case WM8995_AIF1DAC_DATA:
1249 	case WM8995_AIF1ADC_DATA:
1250 	case WM8995_AIF2_CONTROL_1:
1251 	case WM8995_AIF2_CONTROL_2:
1252 	case WM8995_AIF2_MASTER_SLAVE:
1253 	case WM8995_AIF2_BCLK:
1254 	case WM8995_AIF2ADC_LRCLK:
1255 	case WM8995_AIF2DAC_LRCLK:
1256 	case WM8995_AIF2DAC_DATA:
1257 	case WM8995_AIF2ADC_DATA:
1258 	case WM8995_AIF1_ADC1_LEFT_VOLUME:
1259 	case WM8995_AIF1_ADC1_RIGHT_VOLUME:
1260 	case WM8995_AIF1_DAC1_LEFT_VOLUME:
1261 	case WM8995_AIF1_DAC1_RIGHT_VOLUME:
1262 	case WM8995_AIF1_ADC2_LEFT_VOLUME:
1263 	case WM8995_AIF1_ADC2_RIGHT_VOLUME:
1264 	case WM8995_AIF1_DAC2_LEFT_VOLUME:
1265 	case WM8995_AIF1_DAC2_RIGHT_VOLUME:
1266 	case WM8995_AIF1_ADC1_FILTERS:
1267 	case WM8995_AIF1_ADC2_FILTERS:
1268 	case WM8995_AIF1_DAC1_FILTERS_1:
1269 	case WM8995_AIF1_DAC1_FILTERS_2:
1270 	case WM8995_AIF1_DAC2_FILTERS_1:
1271 	case WM8995_AIF1_DAC2_FILTERS_2:
1272 	case WM8995_AIF1_DRC1_1:
1273 	case WM8995_AIF1_DRC1_2:
1274 	case WM8995_AIF1_DRC1_3:
1275 	case WM8995_AIF1_DRC1_4:
1276 	case WM8995_AIF1_DRC1_5:
1277 	case WM8995_AIF1_DRC2_1:
1278 	case WM8995_AIF1_DRC2_2:
1279 	case WM8995_AIF1_DRC2_3:
1280 	case WM8995_AIF1_DRC2_4:
1281 	case WM8995_AIF1_DRC2_5:
1282 	case WM8995_AIF1_DAC1_EQ_GAINS_1:
1283 	case WM8995_AIF1_DAC1_EQ_GAINS_2:
1284 	case WM8995_AIF1_DAC1_EQ_BAND_1_A:
1285 	case WM8995_AIF1_DAC1_EQ_BAND_1_B:
1286 	case WM8995_AIF1_DAC1_EQ_BAND_1_PG:
1287 	case WM8995_AIF1_DAC1_EQ_BAND_2_A:
1288 	case WM8995_AIF1_DAC1_EQ_BAND_2_B:
1289 	case WM8995_AIF1_DAC1_EQ_BAND_2_C:
1290 	case WM8995_AIF1_DAC1_EQ_BAND_2_PG:
1291 	case WM8995_AIF1_DAC1_EQ_BAND_3_A:
1292 	case WM8995_AIF1_DAC1_EQ_BAND_3_B:
1293 	case WM8995_AIF1_DAC1_EQ_BAND_3_C:
1294 	case WM8995_AIF1_DAC1_EQ_BAND_3_PG:
1295 	case WM8995_AIF1_DAC1_EQ_BAND_4_A:
1296 	case WM8995_AIF1_DAC1_EQ_BAND_4_B:
1297 	case WM8995_AIF1_DAC1_EQ_BAND_4_C:
1298 	case WM8995_AIF1_DAC1_EQ_BAND_4_PG:
1299 	case WM8995_AIF1_DAC1_EQ_BAND_5_A:
1300 	case WM8995_AIF1_DAC1_EQ_BAND_5_B:
1301 	case WM8995_AIF1_DAC1_EQ_BAND_5_PG:
1302 	case WM8995_AIF1_DAC2_EQ_GAINS_1:
1303 	case WM8995_AIF1_DAC2_EQ_GAINS_2:
1304 	case WM8995_AIF1_DAC2_EQ_BAND_1_A:
1305 	case WM8995_AIF1_DAC2_EQ_BAND_1_B:
1306 	case WM8995_AIF1_DAC2_EQ_BAND_1_PG:
1307 	case WM8995_AIF1_DAC2_EQ_BAND_2_A:
1308 	case WM8995_AIF1_DAC2_EQ_BAND_2_B:
1309 	case WM8995_AIF1_DAC2_EQ_BAND_2_C:
1310 	case WM8995_AIF1_DAC2_EQ_BAND_2_PG:
1311 	case WM8995_AIF1_DAC2_EQ_BAND_3_A:
1312 	case WM8995_AIF1_DAC2_EQ_BAND_3_B:
1313 	case WM8995_AIF1_DAC2_EQ_BAND_3_C:
1314 	case WM8995_AIF1_DAC2_EQ_BAND_3_PG:
1315 	case WM8995_AIF1_DAC2_EQ_BAND_4_A:
1316 	case WM8995_AIF1_DAC2_EQ_BAND_4_B:
1317 	case WM8995_AIF1_DAC2_EQ_BAND_4_C:
1318 	case WM8995_AIF1_DAC2_EQ_BAND_4_PG:
1319 	case WM8995_AIF1_DAC2_EQ_BAND_5_A:
1320 	case WM8995_AIF1_DAC2_EQ_BAND_5_B:
1321 	case WM8995_AIF1_DAC2_EQ_BAND_5_PG:
1322 	case WM8995_AIF2_ADC_LEFT_VOLUME:
1323 	case WM8995_AIF2_ADC_RIGHT_VOLUME:
1324 	case WM8995_AIF2_DAC_LEFT_VOLUME:
1325 	case WM8995_AIF2_DAC_RIGHT_VOLUME:
1326 	case WM8995_AIF2_ADC_FILTERS:
1327 	case WM8995_AIF2_DAC_FILTERS_1:
1328 	case WM8995_AIF2_DAC_FILTERS_2:
1329 	case WM8995_AIF2_DRC_1:
1330 	case WM8995_AIF2_DRC_2:
1331 	case WM8995_AIF2_DRC_3:
1332 	case WM8995_AIF2_DRC_4:
1333 	case WM8995_AIF2_DRC_5:
1334 	case WM8995_AIF2_EQ_GAINS_1:
1335 	case WM8995_AIF2_EQ_GAINS_2:
1336 	case WM8995_AIF2_EQ_BAND_1_A:
1337 	case WM8995_AIF2_EQ_BAND_1_B:
1338 	case WM8995_AIF2_EQ_BAND_1_PG:
1339 	case WM8995_AIF2_EQ_BAND_2_A:
1340 	case WM8995_AIF2_EQ_BAND_2_B:
1341 	case WM8995_AIF2_EQ_BAND_2_C:
1342 	case WM8995_AIF2_EQ_BAND_2_PG:
1343 	case WM8995_AIF2_EQ_BAND_3_A:
1344 	case WM8995_AIF2_EQ_BAND_3_B:
1345 	case WM8995_AIF2_EQ_BAND_3_C:
1346 	case WM8995_AIF2_EQ_BAND_3_PG:
1347 	case WM8995_AIF2_EQ_BAND_4_A:
1348 	case WM8995_AIF2_EQ_BAND_4_B:
1349 	case WM8995_AIF2_EQ_BAND_4_C:
1350 	case WM8995_AIF2_EQ_BAND_4_PG:
1351 	case WM8995_AIF2_EQ_BAND_5_A:
1352 	case WM8995_AIF2_EQ_BAND_5_B:
1353 	case WM8995_AIF2_EQ_BAND_5_PG:
1354 	case WM8995_DAC1_MIXER_VOLUMES:
1355 	case WM8995_DAC1_LEFT_MIXER_ROUTING:
1356 	case WM8995_DAC1_RIGHT_MIXER_ROUTING:
1357 	case WM8995_DAC2_MIXER_VOLUMES:
1358 	case WM8995_DAC2_LEFT_MIXER_ROUTING:
1359 	case WM8995_DAC2_RIGHT_MIXER_ROUTING:
1360 	case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING:
1361 	case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING:
1362 	case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING:
1363 	case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING:
1364 	case WM8995_DAC_SOFTMUTE:
1365 	case WM8995_OVERSAMPLING:
1366 	case WM8995_SIDETONE:
1367 	case WM8995_GPIO_1:
1368 	case WM8995_GPIO_2:
1369 	case WM8995_GPIO_3:
1370 	case WM8995_GPIO_4:
1371 	case WM8995_GPIO_5:
1372 	case WM8995_GPIO_6:
1373 	case WM8995_GPIO_7:
1374 	case WM8995_GPIO_8:
1375 	case WM8995_GPIO_9:
1376 	case WM8995_GPIO_10:
1377 	case WM8995_GPIO_11:
1378 	case WM8995_GPIO_12:
1379 	case WM8995_GPIO_13:
1380 	case WM8995_GPIO_14:
1381 	case WM8995_PULL_CONTROL_1:
1382 	case WM8995_PULL_CONTROL_2:
1383 	case WM8995_INTERRUPT_STATUS_1:
1384 	case WM8995_INTERRUPT_STATUS_2:
1385 	case WM8995_INTERRUPT_RAW_STATUS_2:
1386 	case WM8995_INTERRUPT_STATUS_1_MASK:
1387 	case WM8995_INTERRUPT_STATUS_2_MASK:
1388 	case WM8995_INTERRUPT_CONTROL:
1389 	case WM8995_LEFT_PDM_SPEAKER_1:
1390 	case WM8995_RIGHT_PDM_SPEAKER_1:
1391 	case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE:
1392 	case WM8995_LEFT_PDM_SPEAKER_2:
1393 	case WM8995_RIGHT_PDM_SPEAKER_2:
1394 	case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE:
1395 		return true;
1396 	default:
1397 		return false;
1398 	}
1399 }
1400 
wm8995_volatile(struct device * dev,unsigned int reg)1401 static bool wm8995_volatile(struct device *dev, unsigned int reg)
1402 {
1403 	switch (reg) {
1404 	case WM8995_SOFTWARE_RESET:
1405 	case WM8995_DC_SERVO_READBACK_0:
1406 	case WM8995_INTERRUPT_STATUS_1:
1407 	case WM8995_INTERRUPT_STATUS_2:
1408 	case WM8995_INTERRUPT_CONTROL:
1409 	case WM8995_ACCESSORY_DETECT_MODE1:
1410 	case WM8995_ACCESSORY_DETECT_MODE2:
1411 	case WM8995_HEADPHONE_DETECT1:
1412 	case WM8995_HEADPHONE_DETECT2:
1413 	case WM8995_RATE_STATUS:
1414 		return true;
1415 	default:
1416 		return false;
1417 	}
1418 }
1419 
wm8995_aif_mute(struct snd_soc_dai * dai,int mute,int direction)1420 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute, int direction)
1421 {
1422 	struct snd_soc_component *component = dai->component;
1423 	int mute_reg;
1424 
1425 	switch (dai->id) {
1426 	case 0:
1427 		mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
1428 		break;
1429 	case 1:
1430 		mute_reg = WM8995_AIF2_DAC_FILTERS_1;
1431 		break;
1432 	default:
1433 		return -EINVAL;
1434 	}
1435 
1436 	snd_soc_component_update_bits(component, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
1437 			    !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
1438 	return 0;
1439 }
1440 
wm8995_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1441 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1442 {
1443 	struct snd_soc_component *component;
1444 	int master;
1445 	int aif;
1446 
1447 	component = dai->component;
1448 
1449 	master = 0;
1450 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1451 	case SND_SOC_DAIFMT_CBS_CFS:
1452 		break;
1453 	case SND_SOC_DAIFMT_CBM_CFM:
1454 		master = WM8995_AIF1_MSTR;
1455 		break;
1456 	default:
1457 		dev_err(dai->dev, "Unknown master/slave configuration\n");
1458 		return -EINVAL;
1459 	}
1460 
1461 	aif = 0;
1462 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1463 	case SND_SOC_DAIFMT_DSP_B:
1464 		aif |= WM8995_AIF1_LRCLK_INV;
1465 		fallthrough;
1466 	case SND_SOC_DAIFMT_DSP_A:
1467 		aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
1468 		break;
1469 	case SND_SOC_DAIFMT_I2S:
1470 		aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
1471 		break;
1472 	case SND_SOC_DAIFMT_RIGHT_J:
1473 		break;
1474 	case SND_SOC_DAIFMT_LEFT_J:
1475 		aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
1476 		break;
1477 	default:
1478 		dev_err(dai->dev, "Unknown dai format\n");
1479 		return -EINVAL;
1480 	}
1481 
1482 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1483 	case SND_SOC_DAIFMT_DSP_A:
1484 	case SND_SOC_DAIFMT_DSP_B:
1485 		/* frame inversion not valid for DSP modes */
1486 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1487 		case SND_SOC_DAIFMT_NB_NF:
1488 			break;
1489 		case SND_SOC_DAIFMT_IB_NF:
1490 			aif |= WM8995_AIF1_BCLK_INV;
1491 			break;
1492 		default:
1493 			return -EINVAL;
1494 		}
1495 		break;
1496 
1497 	case SND_SOC_DAIFMT_I2S:
1498 	case SND_SOC_DAIFMT_RIGHT_J:
1499 	case SND_SOC_DAIFMT_LEFT_J:
1500 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1501 		case SND_SOC_DAIFMT_NB_NF:
1502 			break;
1503 		case SND_SOC_DAIFMT_IB_IF:
1504 			aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1505 			break;
1506 		case SND_SOC_DAIFMT_IB_NF:
1507 			aif |= WM8995_AIF1_BCLK_INV;
1508 			break;
1509 		case SND_SOC_DAIFMT_NB_IF:
1510 			aif |= WM8995_AIF1_LRCLK_INV;
1511 			break;
1512 		default:
1513 			return -EINVAL;
1514 		}
1515 		break;
1516 	default:
1517 		return -EINVAL;
1518 	}
1519 
1520 	snd_soc_component_update_bits(component, WM8995_AIF1_CONTROL_1,
1521 			    WM8995_AIF1_BCLK_INV_MASK |
1522 			    WM8995_AIF1_LRCLK_INV_MASK |
1523 			    WM8995_AIF1_FMT_MASK, aif);
1524 	snd_soc_component_update_bits(component, WM8995_AIF1_MASTER_SLAVE,
1525 			    WM8995_AIF1_MSTR_MASK, master);
1526 	return 0;
1527 }
1528 
1529 static const int srs[] = {
1530 	8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1531 	48000, 88200, 96000
1532 };
1533 
1534 static const int fs_ratios[] = {
1535 	-1 /* reserved */,
1536 	128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1537 };
1538 
1539 static const int bclk_divs[] = {
1540 	10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1541 };
1542 
wm8995_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1543 static int wm8995_hw_params(struct snd_pcm_substream *substream,
1544 			    struct snd_pcm_hw_params *params,
1545 			    struct snd_soc_dai *dai)
1546 {
1547 	struct snd_soc_component *component;
1548 	struct wm8995_priv *wm8995;
1549 	int aif1_reg;
1550 	int bclk_reg;
1551 	int lrclk_reg;
1552 	int rate_reg;
1553 	int bclk_rate;
1554 	int aif1;
1555 	int lrclk, bclk;
1556 	int i, rate_val, best, best_val, cur_val;
1557 
1558 	component = dai->component;
1559 	wm8995 = snd_soc_component_get_drvdata(component);
1560 
1561 	switch (dai->id) {
1562 	case 0:
1563 		aif1_reg = WM8995_AIF1_CONTROL_1;
1564 		bclk_reg = WM8995_AIF1_BCLK;
1565 		rate_reg = WM8995_AIF1_RATE;
1566 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1567 			wm8995->lrclk_shared[0] */) {
1568 			lrclk_reg = WM8995_AIF1DAC_LRCLK;
1569 		} else {
1570 			lrclk_reg = WM8995_AIF1ADC_LRCLK;
1571 			dev_dbg(component->dev, "AIF1 using split LRCLK\n");
1572 		}
1573 		break;
1574 	case 1:
1575 		aif1_reg = WM8995_AIF2_CONTROL_1;
1576 		bclk_reg = WM8995_AIF2_BCLK;
1577 		rate_reg = WM8995_AIF2_RATE;
1578 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1579 		    wm8995->lrclk_shared[1] */) {
1580 			lrclk_reg = WM8995_AIF2DAC_LRCLK;
1581 		} else {
1582 			lrclk_reg = WM8995_AIF2ADC_LRCLK;
1583 			dev_dbg(component->dev, "AIF2 using split LRCLK\n");
1584 		}
1585 		break;
1586 	default:
1587 		return -EINVAL;
1588 	}
1589 
1590 	bclk_rate = snd_soc_params_to_bclk(params);
1591 	if (bclk_rate < 0)
1592 		return bclk_rate;
1593 
1594 	aif1 = 0;
1595 	switch (params_width(params)) {
1596 	case 16:
1597 		break;
1598 	case 20:
1599 		aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1600 		break;
1601 	case 24:
1602 		aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1603 		break;
1604 	case 32:
1605 		aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1606 		break;
1607 	default:
1608 		dev_err(dai->dev, "Unsupported word length %u\n",
1609 			params_width(params));
1610 		return -EINVAL;
1611 	}
1612 
1613 	/* try to find a suitable sample rate */
1614 	for (i = 0; i < ARRAY_SIZE(srs); ++i)
1615 		if (srs[i] == params_rate(params))
1616 			break;
1617 	if (i == ARRAY_SIZE(srs)) {
1618 		dev_err(dai->dev, "Sample rate %d is not supported\n",
1619 			params_rate(params));
1620 		return -EINVAL;
1621 	}
1622 	rate_val = i << WM8995_AIF1_SR_SHIFT;
1623 
1624 	dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1625 	dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1626 		dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1627 
1628 	/* AIFCLK/fs ratio; look for a close match in either direction */
1629 	best = 1;
1630 	best_val = abs((fs_ratios[1] * params_rate(params))
1631 		       - wm8995->aifclk[dai->id]);
1632 	for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1633 		cur_val = abs((fs_ratios[i] * params_rate(params))
1634 			      - wm8995->aifclk[dai->id]);
1635 		if (cur_val >= best_val)
1636 			continue;
1637 		best = i;
1638 		best_val = cur_val;
1639 	}
1640 	rate_val |= best;
1641 
1642 	dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1643 		dai->id + 1, fs_ratios[best]);
1644 
1645 	/*
1646 	 * We may not get quite the right frequency if using
1647 	 * approximate clocks so look for the closest match that is
1648 	 * higher than the target (we need to ensure that there enough
1649 	 * BCLKs to clock out the samples).
1650 	 */
1651 	best = 0;
1652 	bclk = 0;
1653 	for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1654 		cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1655 		if (cur_val < 0) /* BCLK table is sorted */
1656 			break;
1657 		best = i;
1658 	}
1659 	bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1660 
1661 	bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1662 	dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1663 		bclk_divs[best], bclk_rate);
1664 
1665 	lrclk = bclk_rate / params_rate(params);
1666 	dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1667 		lrclk, bclk_rate / lrclk);
1668 
1669 	snd_soc_component_update_bits(component, aif1_reg,
1670 			    WM8995_AIF1_WL_MASK, aif1);
1671 	snd_soc_component_update_bits(component, bclk_reg,
1672 			    WM8995_AIF1_BCLK_DIV_MASK, bclk);
1673 	snd_soc_component_update_bits(component, lrclk_reg,
1674 			    WM8995_AIF1DAC_RATE_MASK, lrclk);
1675 	snd_soc_component_update_bits(component, rate_reg,
1676 			    WM8995_AIF1_SR_MASK |
1677 			    WM8995_AIF1CLK_RATE_MASK, rate_val);
1678 	return 0;
1679 }
1680 
wm8995_set_tristate(struct snd_soc_dai * codec_dai,int tristate)1681 static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1682 {
1683 	struct snd_soc_component *component = codec_dai->component;
1684 	int reg, val, mask;
1685 
1686 	switch (codec_dai->id) {
1687 	case 0:
1688 		reg = WM8995_AIF1_MASTER_SLAVE;
1689 		mask = WM8995_AIF1_TRI;
1690 		break;
1691 	case 1:
1692 		reg = WM8995_AIF2_MASTER_SLAVE;
1693 		mask = WM8995_AIF2_TRI;
1694 		break;
1695 	case 2:
1696 		reg = WM8995_POWER_MANAGEMENT_5;
1697 		mask = WM8995_AIF3_TRI;
1698 		break;
1699 	default:
1700 		return -EINVAL;
1701 	}
1702 
1703 	if (tristate)
1704 		val = mask;
1705 	else
1706 		val = 0;
1707 
1708 	return snd_soc_component_update_bits(component, reg, mask, val);
1709 }
1710 
1711 /* The size in bits of the FLL divide multiplied by 10
1712  * to allow rounding later */
1713 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1714 
1715 struct fll_div {
1716 	u16 outdiv;
1717 	u16 n;
1718 	u16 k;
1719 	u16 clk_ref_div;
1720 	u16 fll_fratio;
1721 };
1722 
wm8995_get_fll_config(struct fll_div * fll,int freq_in,int freq_out)1723 static int wm8995_get_fll_config(struct fll_div *fll,
1724 				 int freq_in, int freq_out)
1725 {
1726 	u64 Kpart;
1727 	unsigned int K, Ndiv, Nmod;
1728 
1729 	pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1730 
1731 	/* Scale the input frequency down to <= 13.5MHz */
1732 	fll->clk_ref_div = 0;
1733 	while (freq_in > 13500000) {
1734 		fll->clk_ref_div++;
1735 		freq_in /= 2;
1736 
1737 		if (fll->clk_ref_div > 3)
1738 			return -EINVAL;
1739 	}
1740 	pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1741 
1742 	/* Scale the output to give 90MHz<=Fvco<=100MHz */
1743 	fll->outdiv = 3;
1744 	while (freq_out * (fll->outdiv + 1) < 90000000) {
1745 		fll->outdiv++;
1746 		if (fll->outdiv > 63)
1747 			return -EINVAL;
1748 	}
1749 	freq_out *= fll->outdiv + 1;
1750 	pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1751 
1752 	if (freq_in > 1000000) {
1753 		fll->fll_fratio = 0;
1754 	} else if (freq_in > 256000) {
1755 		fll->fll_fratio = 1;
1756 		freq_in *= 2;
1757 	} else if (freq_in > 128000) {
1758 		fll->fll_fratio = 2;
1759 		freq_in *= 4;
1760 	} else if (freq_in > 64000) {
1761 		fll->fll_fratio = 3;
1762 		freq_in *= 8;
1763 	} else {
1764 		fll->fll_fratio = 4;
1765 		freq_in *= 16;
1766 	}
1767 	pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1768 
1769 	/* Now, calculate N.K */
1770 	Ndiv = freq_out / freq_in;
1771 
1772 	fll->n = Ndiv;
1773 	Nmod = freq_out % freq_in;
1774 	pr_debug("Nmod=%d\n", Nmod);
1775 
1776 	/* Calculate fractional part - scale up so we can round. */
1777 	Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1778 
1779 	do_div(Kpart, freq_in);
1780 
1781 	K = Kpart & 0xFFFFFFFF;
1782 
1783 	if ((K % 10) >= 5)
1784 		K += 5;
1785 
1786 	/* Move down to proper range now rounding is done */
1787 	fll->k = K / 10;
1788 
1789 	pr_debug("N=%x K=%x\n", fll->n, fll->k);
1790 
1791 	return 0;
1792 }
1793 
wm8995_set_fll(struct snd_soc_dai * dai,int id,int src,unsigned int freq_in,unsigned int freq_out)1794 static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1795 			  int src, unsigned int freq_in,
1796 			  unsigned int freq_out)
1797 {
1798 	struct snd_soc_component *component;
1799 	struct wm8995_priv *wm8995;
1800 	int reg_offset, ret;
1801 	struct fll_div fll;
1802 	u16 reg, aif1, aif2;
1803 
1804 	component = dai->component;
1805 	wm8995 = snd_soc_component_get_drvdata(component);
1806 
1807 	aif1 = snd_soc_component_read(component, WM8995_AIF1_CLOCKING_1)
1808 	       & WM8995_AIF1CLK_ENA;
1809 
1810 	aif2 = snd_soc_component_read(component, WM8995_AIF2_CLOCKING_1)
1811 	       & WM8995_AIF2CLK_ENA;
1812 
1813 	switch (id) {
1814 	case WM8995_FLL1:
1815 		reg_offset = 0;
1816 		id = 0;
1817 		break;
1818 	case WM8995_FLL2:
1819 		reg_offset = 0x20;
1820 		id = 1;
1821 		break;
1822 	default:
1823 		return -EINVAL;
1824 	}
1825 
1826 	switch (src) {
1827 	case 0:
1828 		/* Allow no source specification when stopping */
1829 		if (freq_out)
1830 			return -EINVAL;
1831 		break;
1832 	case WM8995_FLL_SRC_MCLK1:
1833 	case WM8995_FLL_SRC_MCLK2:
1834 	case WM8995_FLL_SRC_LRCLK:
1835 	case WM8995_FLL_SRC_BCLK:
1836 		break;
1837 	default:
1838 		return -EINVAL;
1839 	}
1840 
1841 	/* Are we changing anything? */
1842 	if (wm8995->fll[id].src == src &&
1843 	    wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1844 		return 0;
1845 
1846 	/* If we're stopping the FLL redo the old config - no
1847 	 * registers will actually be written but we avoid GCC flow
1848 	 * analysis bugs spewing warnings.
1849 	 */
1850 	if (freq_out)
1851 		ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1852 	else
1853 		ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1854 					    wm8995->fll[id].out);
1855 	if (ret < 0)
1856 		return ret;
1857 
1858 	/* Gate the AIF clocks while we reclock */
1859 	snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
1860 			    WM8995_AIF1CLK_ENA_MASK, 0);
1861 	snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
1862 			    WM8995_AIF2CLK_ENA_MASK, 0);
1863 
1864 	/* We always need to disable the FLL while reconfiguring */
1865 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1866 			    WM8995_FLL1_ENA_MASK, 0);
1867 
1868 	reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1869 	      (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1870 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,
1871 			    WM8995_FLL1_OUTDIV_MASK |
1872 			    WM8995_FLL1_FRATIO_MASK, reg);
1873 
1874 	snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1875 
1876 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,
1877 			    WM8995_FLL1_N_MASK,
1878 			    fll.n << WM8995_FLL1_N_SHIFT);
1879 
1880 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,
1881 			    WM8995_FLL1_REFCLK_DIV_MASK |
1882 			    WM8995_FLL1_REFCLK_SRC_MASK,
1883 			    (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1884 			    (src - 1));
1885 
1886 	if (freq_out)
1887 		snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1888 				    WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1889 
1890 	wm8995->fll[id].in = freq_in;
1891 	wm8995->fll[id].out = freq_out;
1892 	wm8995->fll[id].src = src;
1893 
1894 	/* Enable any gated AIF clocks */
1895 	snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
1896 			    WM8995_AIF1CLK_ENA_MASK, aif1);
1897 	snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
1898 			    WM8995_AIF2CLK_ENA_MASK, aif2);
1899 
1900 	configure_clock(component);
1901 
1902 	return 0;
1903 }
1904 
wm8995_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1905 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1906 				 int clk_id, unsigned int freq, int dir)
1907 {
1908 	struct snd_soc_component *component;
1909 	struct wm8995_priv *wm8995;
1910 
1911 	component = dai->component;
1912 	wm8995 = snd_soc_component_get_drvdata(component);
1913 
1914 	switch (dai->id) {
1915 	case 0:
1916 	case 1:
1917 		break;
1918 	default:
1919 		/* AIF3 shares clocking with AIF1/2 */
1920 		return -EINVAL;
1921 	}
1922 
1923 	switch (clk_id) {
1924 	case WM8995_SYSCLK_MCLK1:
1925 		wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1926 		wm8995->mclk[0] = freq;
1927 		dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1928 			dai->id + 1, freq);
1929 		break;
1930 	case WM8995_SYSCLK_MCLK2:
1931 		wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2;
1932 		wm8995->mclk[1] = freq;
1933 		dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1934 			dai->id + 1, freq);
1935 		break;
1936 	case WM8995_SYSCLK_FLL1:
1937 		wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1938 		dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1939 		break;
1940 	case WM8995_SYSCLK_FLL2:
1941 		wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1942 		dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1943 		break;
1944 	case WM8995_SYSCLK_OPCLK:
1945 	default:
1946 		dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1947 		return -EINVAL;
1948 	}
1949 
1950 	configure_clock(component);
1951 
1952 	return 0;
1953 }
1954 
wm8995_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1955 static int wm8995_set_bias_level(struct snd_soc_component *component,
1956 				 enum snd_soc_bias_level level)
1957 {
1958 	struct wm8995_priv *wm8995;
1959 	int ret;
1960 
1961 	wm8995 = snd_soc_component_get_drvdata(component);
1962 	switch (level) {
1963 	case SND_SOC_BIAS_ON:
1964 	case SND_SOC_BIAS_PREPARE:
1965 		break;
1966 	case SND_SOC_BIAS_STANDBY:
1967 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1968 			ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
1969 						    wm8995->supplies);
1970 			if (ret)
1971 				return ret;
1972 
1973 			ret = regcache_sync(wm8995->regmap);
1974 			if (ret) {
1975 				dev_err(component->dev,
1976 					"Failed to sync cache: %d\n", ret);
1977 				return ret;
1978 			}
1979 
1980 			snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
1981 					    WM8995_BG_ENA_MASK, WM8995_BG_ENA);
1982 		}
1983 		break;
1984 	case SND_SOC_BIAS_OFF:
1985 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
1986 				    WM8995_BG_ENA_MASK, 0);
1987 		regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
1988 				       wm8995->supplies);
1989 		break;
1990 	}
1991 
1992 	return 0;
1993 }
1994 
wm8995_probe(struct snd_soc_component * component)1995 static int wm8995_probe(struct snd_soc_component *component)
1996 {
1997 	struct wm8995_priv *wm8995;
1998 	int i;
1999 	int ret;
2000 
2001 	wm8995 = snd_soc_component_get_drvdata(component);
2002 	wm8995->component = component;
2003 
2004 	for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
2005 		wm8995->supplies[i].supply = wm8995_supply_names[i];
2006 
2007 	ret = devm_regulator_bulk_get(component->dev,
2008 				      ARRAY_SIZE(wm8995->supplies),
2009 				      wm8995->supplies);
2010 	if (ret) {
2011 		dev_err(component->dev, "Failed to request supplies: %d\n", ret);
2012 		return ret;
2013 	}
2014 
2015 	wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
2016 	wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
2017 	wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
2018 	wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
2019 	wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
2020 	wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
2021 	wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
2022 	wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
2023 
2024 	/* This should really be moved into the regulator core */
2025 	for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
2026 		ret = devm_regulator_register_notifier(
2027 						wm8995->supplies[i].consumer,
2028 						&wm8995->disable_nb[i]);
2029 		if (ret) {
2030 			dev_err(component->dev,
2031 				"Failed to register regulator notifier: %d\n",
2032 				ret);
2033 		}
2034 	}
2035 
2036 	ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
2037 				    wm8995->supplies);
2038 	if (ret) {
2039 		dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
2040 		return ret;
2041 	}
2042 
2043 	ret = snd_soc_component_read(component, WM8995_SOFTWARE_RESET);
2044 	if (ret < 0) {
2045 		dev_err(component->dev, "Failed to read device ID: %d\n", ret);
2046 		goto err_reg_enable;
2047 	}
2048 
2049 	if (ret != 0x8995) {
2050 		dev_err(component->dev, "Invalid device ID: %#x\n", ret);
2051 		ret = -EINVAL;
2052 		goto err_reg_enable;
2053 	}
2054 
2055 	ret = snd_soc_component_write(component, WM8995_SOFTWARE_RESET, 0);
2056 	if (ret < 0) {
2057 		dev_err(component->dev, "Failed to issue reset: %d\n", ret);
2058 		goto err_reg_enable;
2059 	}
2060 
2061 	/* Latch volume updates (right only; we always do left then right). */
2062 	snd_soc_component_update_bits(component, WM8995_AIF1_DAC1_RIGHT_VOLUME,
2063 			    WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
2064 	snd_soc_component_update_bits(component, WM8995_AIF1_DAC2_RIGHT_VOLUME,
2065 			    WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
2066 	snd_soc_component_update_bits(component, WM8995_AIF2_DAC_RIGHT_VOLUME,
2067 			    WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
2068 	snd_soc_component_update_bits(component, WM8995_AIF1_ADC1_RIGHT_VOLUME,
2069 			    WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
2070 	snd_soc_component_update_bits(component, WM8995_AIF1_ADC2_RIGHT_VOLUME,
2071 			    WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
2072 	snd_soc_component_update_bits(component, WM8995_AIF2_ADC_RIGHT_VOLUME,
2073 			    WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
2074 	snd_soc_component_update_bits(component, WM8995_DAC1_RIGHT_VOLUME,
2075 			    WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
2076 	snd_soc_component_update_bits(component, WM8995_DAC2_RIGHT_VOLUME,
2077 			    WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
2078 	snd_soc_component_update_bits(component, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
2079 			    WM8995_IN1_VU_MASK, WM8995_IN1_VU);
2080 
2081 	wm8995_update_class_w(component);
2082 
2083 	return 0;
2084 
2085 err_reg_enable:
2086 	regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2087 	return ret;
2088 }
2089 
2090 #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2091 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2092 
2093 static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
2094 	.set_sysclk = wm8995_set_dai_sysclk,
2095 	.set_fmt = wm8995_set_dai_fmt,
2096 	.hw_params = wm8995_hw_params,
2097 	.mute_stream = wm8995_aif_mute,
2098 	.set_pll = wm8995_set_fll,
2099 	.set_tristate = wm8995_set_tristate,
2100 	.no_capture_mute = 1,
2101 };
2102 
2103 static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
2104 	.set_sysclk = wm8995_set_dai_sysclk,
2105 	.set_fmt = wm8995_set_dai_fmt,
2106 	.hw_params = wm8995_hw_params,
2107 	.mute_stream = wm8995_aif_mute,
2108 	.set_pll = wm8995_set_fll,
2109 	.set_tristate = wm8995_set_tristate,
2110 	.no_capture_mute = 1,
2111 };
2112 
2113 static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
2114 	.set_tristate = wm8995_set_tristate,
2115 };
2116 
2117 static struct snd_soc_dai_driver wm8995_dai[] = {
2118 	{
2119 		.name = "wm8995-aif1",
2120 		.playback = {
2121 			.stream_name = "AIF1 Playback",
2122 			.channels_min = 2,
2123 			.channels_max = 2,
2124 			.rates = SNDRV_PCM_RATE_8000_96000,
2125 			.formats = WM8995_FORMATS
2126 		},
2127 		.capture = {
2128 			.stream_name = "AIF1 Capture",
2129 			.channels_min = 2,
2130 			.channels_max = 2,
2131 			.rates = SNDRV_PCM_RATE_8000_48000,
2132 			.formats = WM8995_FORMATS
2133 		},
2134 		.ops = &wm8995_aif1_dai_ops
2135 	},
2136 	{
2137 		.name = "wm8995-aif2",
2138 		.playback = {
2139 			.stream_name = "AIF2 Playback",
2140 			.channels_min = 2,
2141 			.channels_max = 2,
2142 			.rates = SNDRV_PCM_RATE_8000_96000,
2143 			.formats = WM8995_FORMATS
2144 		},
2145 		.capture = {
2146 			.stream_name = "AIF2 Capture",
2147 			.channels_min = 2,
2148 			.channels_max = 2,
2149 			.rates = SNDRV_PCM_RATE_8000_48000,
2150 			.formats = WM8995_FORMATS
2151 		},
2152 		.ops = &wm8995_aif2_dai_ops
2153 	},
2154 	{
2155 		.name = "wm8995-aif3",
2156 		.playback = {
2157 			.stream_name = "AIF3 Playback",
2158 			.channels_min = 2,
2159 			.channels_max = 2,
2160 			.rates = SNDRV_PCM_RATE_8000_96000,
2161 			.formats = WM8995_FORMATS
2162 		},
2163 		.capture = {
2164 			.stream_name = "AIF3 Capture",
2165 			.channels_min = 2,
2166 			.channels_max = 2,
2167 			.rates = SNDRV_PCM_RATE_8000_48000,
2168 			.formats = WM8995_FORMATS
2169 		},
2170 		.ops = &wm8995_aif3_dai_ops
2171 	}
2172 };
2173 
2174 static const struct snd_soc_component_driver soc_component_dev_wm8995 = {
2175 	.probe			= wm8995_probe,
2176 	.set_bias_level		= wm8995_set_bias_level,
2177 	.controls		= wm8995_snd_controls,
2178 	.num_controls		= ARRAY_SIZE(wm8995_snd_controls),
2179 	.dapm_widgets		= wm8995_dapm_widgets,
2180 	.num_dapm_widgets	= ARRAY_SIZE(wm8995_dapm_widgets),
2181 	.dapm_routes		= wm8995_intercon,
2182 	.num_dapm_routes	= ARRAY_SIZE(wm8995_intercon),
2183 	.use_pmdown_time	= 1,
2184 	.endianness		= 1,
2185 };
2186 
2187 static const struct regmap_config wm8995_regmap = {
2188 	.reg_bits = 16,
2189 	.val_bits = 16,
2190 
2191 	.max_register = WM8995_MAX_REGISTER,
2192 	.reg_defaults = wm8995_reg_defaults,
2193 	.num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults),
2194 	.volatile_reg = wm8995_volatile,
2195 	.readable_reg = wm8995_readable,
2196 	.cache_type = REGCACHE_MAPLE,
2197 };
2198 
2199 #if defined(CONFIG_SPI_MASTER)
wm8995_spi_probe(struct spi_device * spi)2200 static int wm8995_spi_probe(struct spi_device *spi)
2201 {
2202 	struct wm8995_priv *wm8995;
2203 	int ret;
2204 
2205 	wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL);
2206 	if (!wm8995)
2207 		return -ENOMEM;
2208 
2209 	spi_set_drvdata(spi, wm8995);
2210 
2211 	wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap);
2212 	if (IS_ERR(wm8995->regmap)) {
2213 		ret = PTR_ERR(wm8995->regmap);
2214 		dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
2215 		return ret;
2216 	}
2217 
2218 	ret = devm_snd_soc_register_component(&spi->dev,
2219 				     &soc_component_dev_wm8995, wm8995_dai,
2220 				     ARRAY_SIZE(wm8995_dai));
2221 	return ret;
2222 }
2223 
2224 static struct spi_driver wm8995_spi_driver = {
2225 	.driver = {
2226 		.name = "wm8995",
2227 	},
2228 	.probe = wm8995_spi_probe,
2229 };
2230 #endif
2231 
2232 #if IS_ENABLED(CONFIG_I2C)
wm8995_i2c_probe(struct i2c_client * i2c)2233 static int wm8995_i2c_probe(struct i2c_client *i2c)
2234 {
2235 	struct wm8995_priv *wm8995;
2236 	int ret;
2237 
2238 	wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL);
2239 	if (!wm8995)
2240 		return -ENOMEM;
2241 
2242 	i2c_set_clientdata(i2c, wm8995);
2243 
2244 	wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap);
2245 	if (IS_ERR(wm8995->regmap)) {
2246 		ret = PTR_ERR(wm8995->regmap);
2247 		dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret);
2248 		return ret;
2249 	}
2250 
2251 	ret = devm_snd_soc_register_component(&i2c->dev,
2252 				     &soc_component_dev_wm8995, wm8995_dai,
2253 				     ARRAY_SIZE(wm8995_dai));
2254 	if (ret < 0)
2255 		dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
2256 
2257 	return ret;
2258 }
2259 
2260 static const struct i2c_device_id wm8995_i2c_id[] = {
2261 	{"wm8995"},
2262 	{}
2263 };
2264 
2265 MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
2266 
2267 static struct i2c_driver wm8995_i2c_driver = {
2268 	.driver = {
2269 		.name = "wm8995",
2270 	},
2271 	.probe = wm8995_i2c_probe,
2272 	.id_table = wm8995_i2c_id
2273 };
2274 #endif
2275 
wm8995_modinit(void)2276 static int __init wm8995_modinit(void)
2277 {
2278 	int ret = 0;
2279 
2280 #if IS_ENABLED(CONFIG_I2C)
2281 	ret = i2c_add_driver(&wm8995_i2c_driver);
2282 	if (ret) {
2283 		printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
2284 		       ret);
2285 	}
2286 #endif
2287 #if defined(CONFIG_SPI_MASTER)
2288 	ret = spi_register_driver(&wm8995_spi_driver);
2289 	if (ret) {
2290 		printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
2291 		       ret);
2292 	}
2293 #endif
2294 	return ret;
2295 }
2296 
2297 module_init(wm8995_modinit);
2298 
wm8995_exit(void)2299 static void __exit wm8995_exit(void)
2300 {
2301 #if IS_ENABLED(CONFIG_I2C)
2302 	i2c_del_driver(&wm8995_i2c_driver);
2303 #endif
2304 #if defined(CONFIG_SPI_MASTER)
2305 	spi_unregister_driver(&wm8995_spi_driver);
2306 #endif
2307 }
2308 
2309 module_exit(wm8995_exit);
2310 
2311 MODULE_DESCRIPTION("ASoC WM8995 driver");
2312 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
2313 MODULE_LICENSE("GPL");
2314