1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 /*******************************************************************************/ 24 /*! \file spcdefs.h 25 * \brief The file defines the MPI Application Programming Interface (API) 26 * 27 * The file defines the MPI Application Programming Interfacde (API) 28 * 29 */ 30 /*******************************************************************************/ 31 #ifndef __SPCDEFS_H__ 32 #define __SPCDEFS_H__ 33 34 /*******************************************************************************/ 35 /*******************************************************************************/ 36 /* CONSTANTS */ 37 /*******************************************************************************/ 38 /*******************************************************************************/ 39 /*******************************************************************************/ 40 /* MSGU CONFIGURATION TABLE */ 41 /*******************************************************************************/ 42 #define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */ 43 #define SPC_MSGU_CFG_TABLE_RESET 0x002 /* Inbound doorbell bit1 */ 44 #define SPC_MSGU_CFG_TABLE_FREEZE 0x004 /* Inbound doorbell bit2 */ 45 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x008 /* Inbound doorbell bit4 */ 46 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080 /* Inbound doorbell bit7 SPCV */ 47 #define SPCV_MSGU_HALT_CPUS 0x100 /* Inbound doorbell bit8 SPCV */ 48 49 /***** Notes *****/ 50 /* The firmware side is using Little Endian (MIPs). */ 51 /* So anything sending or receiving from FW must be in Little Endian */ 52 /*******************************************************************************/ 53 /** \struct mpiMsgHeader_s 54 * \brief MPI message header 55 * 56 * The mpiMsgHeader_s defines the fields in the header of every message 57 */ 58 /*******************************************************************************/ 59 /* This structire defines the fields in the header of every message */ 60 61 62 struct mpiMsgHeader_s 63 { 64 bit32 Header; /* Bits [11:0] - Message operation code */ 65 /* Bits [15:12] - Message Category */ 66 /* Bits [21:16] - Outboundqueue ID for the operation completion message */ 67 /* Bits [23:22] - Reserved */ 68 /* Bits [28:24] - Buffer Count, indicates how many buffer are allocated for the massage */ 69 /* Bits [30:29] - Reserved */ 70 /* Bits [31] - Message Valid bit */ 71 }; 72 73 typedef struct mpiMsgHeader_s mpiMsgHeader_t; 74 75 #define V_BIT 0x1 76 77 #define V_MASK 0x1 78 #define BC_MASK 0x1F 79 #define OBID_MASK 0x3F 80 #define CAT_MASK 0x0F 81 #define OPCODE_MASK 0xFFF 82 #define HEADER_V_MASK 0x80000000 83 #define HEADER_BC_MASK 0x1f000000 84 85 #ifndef SPC_CONFIG 86 /*******************************************************************************/ 87 /** \struct spc_ConfigMainDescriptor_s 88 * \brief This structure is used to configure main part of Configuration Table 89 * 90 * This structure specifies all required attributes to configuration table 91 */ 92 /*******************************************************************************/ 93 /* new MPI configuration main table */ 94 struct spc_configMainDescriptor_s 95 { 96 bit8 Signature[4]; /**< DW0 signature - Indicate coherent table */ 97 bit32 InterfaceRev; /**< DW1 Revsion of Interface */ 98 bit32 FWRevision; /**< DW2 Revsion of FW */ 99 bit32 MaxOutstandingIO; /**< DW3 Max outstanding IO */ 100 bit32 MDevMaxSGL; /**< DW4 Maximum SGL elements & Max Devices */ 101 /* bit0-15 Maximum SGL */ 102 /* bit16-31 Maximum Devices */ 103 bit32 ContrlCapFlag; /**< DW5 Controller Capability */ 104 /* bit0-7 Max number of inbound queue */ 105 /* bit8-15 Max number of outbound queue */ 106 /* bit16 high priority of inbound queue is supported */ 107 /* bit17 reserved */ 108 /* bit18 interrupt coalescing is supported, SPCV-reserved */ 109 /* bit19-24 Maximum number of valid phys */ 110 /* bit25-31 SAS Revision SPecification */ 111 bit32 GSTOffset; /**< DW6 General Status Table */ 112 bit32 inboundQueueOffset; /**< DW7 inbound configuration table offset */ 113 /* bit23-0 inbound queue table offset */ 114 /* bit31-24 entry size, new in SPCV */ 115 bit32 outboundQueueOffset; /**< DW8 outbound configuration table offset */ 116 /* bit23-0 outbound queue table offset */ 117 /* bit31-24 entry size, new in SPCV */ 118 bit32 iQNPPD_HPPD_GEvent; /**< DW9 inbound Queue Process depth and General Event */ 119 /* bit0-7 inbound normal priority process depth */ 120 /* bit8-15 inbound high priority process depth */ 121 /* bit16-23 OQ number to receive GENERAL_EVENT Notification */ 122 /* bit24-31 OQ number to receive DEVICE_HANDLE_REMOVAL Notification */ 123 bit32 outboundHWEventPID0_3; /**< DWA outbound HW event for PortId 0 to 3, SPCV-reserved */ 124 /* bit0-7 outbound queue number of SAS_HW event for PhyId 0 */ 125 /* bit8-15 outbound queue number of SAS_HW event for PhyId 1 */ 126 /* bit16-23 outbound queue number of SAS_HW event for PhyId 2 */ 127 /* bit24-31 outbound queue number of SAS_HW event for PhyId 3 */ 128 bit32 outboundHWEventPID4_7; /**< DWB outbound HW event for PortId 4 to 7, SPCV-reserved */ 129 /* bit0-7 outbound queue number of SAS_HW event for PhyId 4 */ 130 /* bit8-15 outbound queue number of SAS_HW event for PhyId 5 */ 131 /* bit16-23 outbound queue number of SAS_HW event for PhyId 6 */ 132 /* bit24-31 outbound queue number of SAS_HW event for PhyId 7 */ 133 bit32 outboundNCQEventPID0_3; /**< DWC outbound NCQ event for PortId 0 to 3, SPCV-reserved */ 134 /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 0 */ 135 /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 1 */ 136 /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 2 */ 137 /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */ 138 bit32 outboundNCQEventPID4_7; /**< DWD outbound NCQ event for PortId 4 to 7, SPCV-reserved*/ 139 /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 4 */ 140 /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 5 */ 141 /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 6 */ 142 /* bit24-31 outbound queue number of SATA_NCQ event for PhyId 7 */ 143 bit32 outboundTargetITNexusEventPID0_3; /**< DWE outbound target ITNexus Event for PortId 0 to 3, SPCV-reserved */ 144 /* bit0-7 outbound queue number of ITNexus event for PhyId 0 */ 145 /* bit8-15 outbound queue number of ITNexus event for PhyId 1 */ 146 /* bit16-23 outbound queue number of ITNexus event for PhyId 2 */ 147 /* bit24-31 outbound queue number of ITNexus event for PhyId 3 */ 148 bit32 outboundTargetITNexusEventPID4_7; /**< DWF outbound target ITNexus Event for PortId 4 to 7, SPCV-reserved */ 149 /* bit0-7 outbound queue number of ITNexus event for PhyId 4 */ 150 /* bit8-15 outbound queue number of ITNexus event for PhyId 5 */ 151 /* bit16-23 outbound queue number of ITNexus event for PhyId 6 */ 152 /* bit24-31 outbound queue number of ITNexus event for PhyId 7 */ 153 bit32 outboundTargetSSPEventPID0_3; /**< DW10 outbound target SSP event for PordId 0 to 3, SPCV-reserved */ 154 /* bit0-7 outbound queue number of SSP event for PhyId 0 */ 155 /* bit8-15 outbound queue number of SSP event for PhyId 1 */ 156 /* bit16-23 outbound queue number of SSP event for PhyId 2 */ 157 /* bit24-31 outbound queue number of SSP event for PhyId 3 */ 158 bit32 outboundTargetSSPEventPID4_7; /**< DW11 outbound target SSP event for PordId 4 to 7, SPCV-reserved */ 159 /* bit0-7 outbound queue number of SSP event for PhyId 4 */ 160 /* bit8-15 outbound queue number of SSP event for PhyId 5 */ 161 /* bit16-23 outbound queue number of SSP event for PhyId 6 */ 162 /* bit24-31 outbound queue number of SSP event for PhyId 7 */ 163 bit32 ioAbortDelay; /**< DW12 IO Abort Delay (bit15:0) MPI_TABLE_CHANGE*/ 164 bit32 custset; /**< DW13 custset */ 165 bit32 upperEventLogAddress; /**< DW14 Upper physical MSGU Event log address */ 166 bit32 lowerEventLogAddress; /**< DW15 Lower physical MSGU Event log address */ 167 bit32 eventLogSize; /**< DW16 Size of MSGU Event log, 0 means log disable */ 168 bit32 eventLogOption; /**< DW17 Option of MSGU Event log */ 169 /* bit3-0 log severity, 0x0 Disable Logging */ 170 /* 0x1 Critical Error */ 171 /* 0x2 Minor Error */ 172 /* 0x3 Warning */ 173 /* 0x4 Information */ 174 /* 0x5 Debugging */ 175 /* 0x6 - 0xF Reserved */ 176 bit32 upperIOPeventLogAddress; /**< DW18 Upper physical IOP Event log address */ 177 bit32 lowerIOPeventLogAddress; /**< DW19 Lower physical IOP Event log address */ 178 bit32 IOPeventLogSize; /**< DW1A Size of IOP Event log, 0 means log disable */ 179 bit32 IOPeventLogOption; /**< DW1B Option of IOP Event log */ 180 /* bit3-0 log severity, 0x0 Critical Error */ 181 /* 0x1 Minor Error */ 182 /* 0x2 Warning */ 183 /* 0x3 Information */ 184 /* 0x4 Unknown */ 185 /* 0x5 - 0xF Reserved */ 186 bit32 FatalErrorInterrupt; /**< DW1C Fatal Error Interrupt enable and vector */ 187 /* bit0 Fatal Error Interrupt Enable */ 188 /* bit1 PI/CI 64bit address */ 189 /* bit2 SGPIO IOMB support */ 190 /* bit6-2 Reserved */ 191 /* bit7 OQ NP/HPriority Path enable */ 192 /* bit15-8 Fatal Error Interrupt Vector */ 193 /* bit16 Enable IQ/OQ 64 */ 194 /* bit17 Interrupt Reassertion Enable */ 195 /* bit18 Interrupt Reassertion Delay in ms */ 196 /* bit31-19 Interrupt Reassertion delay, 0-default 1ms */ 197 bit32 FatalErrorDumpOffset0; /**< DW1D FERDOMS-GU Fatal Error Register Dump Offset for MSGU */ 198 bit32 FatalErrorDumpLength0; /**< DW1E FERDLMS-GU Fatal Error Register Dump Length for MSGU */ 199 bit32 FatalErrorDumpOffset1; /**< DW1F FERDO-SSTRUCPCS Fatal Error Register Dump Offset for IOP */ 200 bit32 FatalErrorDumpLength1; /**< DW20 FERDLSTRUCTTPCS Fatal Error Register Dump Length for IOP */ 201 bit32 HDAModeFlags; /**< DW21 HDA Mode Flags, SPCV-reserved */ 202 bit32 analogSetupTblOffset; /**< DW22 SPASTO Phy Calibration Table offset */ 203 /* bit23-0 phy calib table offset */ 204 /* bit31-24 entry size */ 205 bit32 InterruptVecTblOffset; /**< DW23 Interrupt Vector Table MPI_TABLE_CHANG */ 206 /* bit23-0 interrupt vector table offset */ 207 /* bit31-24 entry size */ 208 bit32 phyAttributeTblOffset; /**< DW24 SAS Phy Attribute Table Offset MPI_TABLE_CHANG*/ 209 /* bit23-0 phy attribute table offset */ 210 /* bit31-24 entry size */ 211 bit32 portRecoveryResetTimer; /* Offset 0x25 [31:16] Port recovery timer default that is 0 212 used for all SAS ports. Granularity of this timer is 100ms. The host can 213 change the individual port recovery timer by using the PORT_CONTROL 214 [15:0] Port reset timer default that is used 3 (i.e 300ms) for all 215 SAS ports. Granularity of this timer is 100ms. Host can change the 216 individual port recovery timer by using PORT_CONTROL Command */ 217 bit32 interruptReassertionDelay; /* Offset 0x26 [23:0] Remind host of outbound completion 0 disabled 100usec per increment */ 218 219 bit32 ilaRevision; /* Offset 0x27 */ 220 }; 221 222 /* main configuration offset - byte offset */ 223 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 (R) */ 224 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 (R) */ 225 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 (R) */ 226 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 (R) */ 227 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 (R) */ 228 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 (R) */ 229 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 (R) */ 230 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 (R) */ 231 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 (R) */ 232 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 (W) */ 233 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28 /* DWORD 0x0A (W) */ /* reserved for SPCV */ 234 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C /* DWORD 0x0B (W) */ /* reserved for SPCV */ 235 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30 /* DWORD 0x0C (W) */ /* reserved for SPCV */ 236 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34 /* DWORD 0x0D (W) */ /* reserved for SPCV */ 237 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38 /* DWORD 0x0E (W) */ /* reserved for SPCV */ 238 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C /* DWORD 0x0F (W) */ /* reserved for SPCV */ 239 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40 /* DWORD 0x10 (W) */ /* reserved for SPCV */ 240 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44 /* DWORD 0x11 (W) */ /* reserved for SPCV */ 241 #define MAIN_IO_ABORT_DELAY 0x48 /* DWORD 0x12 (W) */ /* reserved for SPCV */ 242 #define MAIN_CUSTOMER_SETTING 0x4C /* DWORD 0x13 (W) */ /* reserved for SPCV */ 243 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 (W) */ 244 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 (W) */ 245 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 (W) */ 246 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 (W) */ 247 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 (W) */ 248 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 (W) */ 249 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A (W) */ 250 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B (W) */ 251 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C (W) */ 252 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D (R) */ 253 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E (R) */ 254 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F (R) */ 255 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 (R) */ 256 #define MAIN_HDA_FLAGS_OFFSET 0x84 /* DWORD 0x21 (R) */ /* reserved for SPCV */ 257 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 (R) */ 258 #define MAIN_INT_VEC_TABLE_OFFSET 0x8C /* DWORD 0x23 (W) */ /* for SPCV */ 259 #define MAIN_PHY_ATTRIBUTE_OFFSET 0x90 /* DWORD 0x24 (W) */ /* for SPCV */ 260 #define MAIN_PRECTD_PRESETD 0x94 /* DWORD 0x25 (W) */ /* for SPCV */ 261 #define MAIN_IRAD_RESERVED 0x98 /* DWORD 0x26 (W) */ /* for SPCV */ 262 #define MAIN_MOQFOT_MOQFOES 0x9C /* DWORD 0x27 (W) */ /* for SPCV */ 263 #define MAIN_MERRDCTO_MERRDCES 0xA0 /* DWORD 0x28 (W) */ /* for SPCV */ 264 #define MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN 0xA4 /* DWORD 0x29 (W) */ /* for SPCV */ 265 #define MAIN_INACTIVE_ILA_REVSION 0xA8 /* DWORD 0x2A (W) */ /* for SPCV V 3.02 */ 266 #define MAIN_SEEPROM_REVSION 0xAC /* DWORD 0x2B (W) */ /* for SPCV V 3.02 */ 267 #define MAIN_UNKNOWN1 0xB0 /* DWORD 0x2C (W) */ /* for SPCV V 3.03 */ 268 #define MAIN_UNKNOWN2 0xB4 /* DWORD 0x2D (W) */ /* for SPCV V 3.03 */ 269 #define MAIN_UNKNOWN3 0xB8 /* DWORD 0x2E (W) */ /* for SPCV V 3.03 */ 270 #define MAIN_XCBI_REF_TAG_PAT 0xBC /* DWORD 0x2F (W) */ /* for SPCV V 3.03 */ 271 #define MAIN_AWT_MIDRANGE 0xC0 /* DWORD 0x30 (W) */ /* for SPCV V 3.03 */ 272 273 274 typedef struct spc_configMainDescriptor_s spc_configMainDescriptor_t; 275 #define SPC_CONFIG 276 #endif 277 278 /* bit to disable end to end crc checking ins SPCv */ 279 #define MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x00010000 280 281 /* bit mask for field Controller Capability in main part */ 282 #define MAIN_MAX_IB_MASK 0x000000ff /* bit7-0 */ 283 #define MAIN_MAX_OB_MASK 0x0000ff00 /* bit15-8 */ 284 #define MAIN_PHY_COUNT_MASK 0x01f80000 /* bit24-19 */ 285 #define MAIN_QSUPPORT_BITS 0x0007ffff 286 #define MAIN_SAS_SUPPORT_BITS 0xfe000000 287 288 /* bit mask for field max sgl in main part */ 289 #define MAIN_MAX_SGL_BITS 0xFFFF 290 #define MAIN_MAX_DEV_BITS 0xFFFF0000 291 292 /* bit mask for HDA flags field */ 293 #define MAIN_HDA_FLAG_BITS 0x000000FF 294 295 #define FATAL_ERROR_INT_BITS 0xFF 296 #define INT_REASRT_ENABLE 0x00020000 297 #define INT_REASRT_MS_ENABLE 0x00040000 298 #define INT_REASRT_DELAY_BITS 0xFFF80000 299 300 #define MAX_VALID_PHYS 8 301 #define IB_QUEUE_CFGSIZE 64 302 #define OB_QUEUE_CFGSIZE 64 303 304 /* inbound queue configuration offset - byte offset */ 305 #define IB_PROPERITY_OFFSET 0x00 306 #define IB_BASE_ADDR_HI_OFFSET 0x04 307 #define IB_BASE_ADDR_LO_OFFSET 0x08 308 #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C 309 #define IB_CI_BASE_ADDR_LO_OFFSET 0x10 310 #define IB_PIPCI_BAR 0x14 311 #define IB_PIPCI_BAR_OFFSET 0x18 312 #define IB_RESERVED_OFFSET 0x1C 313 314 /* outbound queue configuration offset - byte offset */ 315 #define OB_PROPERITY_OFFSET 0x00 316 #define OB_BASE_ADDR_HI_OFFSET 0x04 317 #define OB_BASE_ADDR_LO_OFFSET 0x08 318 #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C 319 #define OB_PI_BASE_ADDR_LO_OFFSET 0x10 320 #define OB_CIPCI_BAR 0x14 321 #define OB_CIPCI_BAR_OFFSET 0x18 322 #define OB_INTERRUPT_COALES_OFFSET 0x1C 323 #define OB_DYNAMIC_COALES_OFFSET 0x20 324 325 #define OB_PROPERTY_INT_ENABLE 0x40000000 326 327 /* General Status Table offset - byte offset */ 328 #define GST_GSTLEN_MPIS_OFFSET 0x00 329 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04 330 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08 331 #define GST_MSGUTCNT_OFFSET 0x0C 332 #define GST_IOPTCNT_OFFSET 0x10 333 #define GST_IOP1TCNT_OFFSET 0x14 334 #define GST_PHYSTATE_OFFSET 0x18 /* SPCV reserved */ 335 #define GST_PHYSTATE0_OFFSET 0x18 /* SPCV reserved */ 336 #define GST_PHYSTATE1_OFFSET 0x1C /* SPCV reserved */ 337 #define GST_PHYSTATE2_OFFSET 0x20 /* SPCV reserved */ 338 #define GST_PHYSTATE3_OFFSET 0x24 /* SPCV reserved */ 339 #define GST_PHYSTATE4_OFFSET 0x28 /* SPCV reserved */ 340 #define GST_PHYSTATE5_OFFSET 0x2C /* SPCV reserved */ 341 #define GST_PHYSTATE6_OFFSET 0x30 /* SPCV reserved */ 342 #define GST_PHYSTATE7_OFFSET 0x34 /* SPCV reserved */ 343 #define GST_GPIO_PINS_OFFSET 0x38 344 #define GST_RERRINFO_OFFSET 0x44 345 346 /* General Status Table - MPI state */ 347 #define GST_MPI_STATE_UNINIT 0x00 348 #define GST_MPI_STATE_INIT 0x01 349 #define GST_MPI_STATE_TERMINATION 0x02 350 #define GST_MPI_STATE_ERROR 0x03 351 #define GST_MPI_STATE_MASK 0x07 352 353 #define GST_INF_STATE_BITS 0xfffe0007 354 355 356 /* MPI fatal and non fatal offset mask */ 357 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF 358 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */ 359 360 /* MPI fatal and non fatal Error dump capture table offset - byte offset */ 361 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ 362 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ 363 #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ 364 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ 365 #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ 366 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ 367 /* */ 368 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 369 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 370 /* */ 371 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 372 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 373 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 374 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 375 376 #define IOCTL_ERROR_NO_FATAL_ERROR 0x77 377 378 /*******************************************************************************/ 379 /** \struct spc_GSTableDescriptor_s 380 * \brief This structure is used for SPC MPI General Status Table 381 * 382 * This structure specifies all required attributes to Gereral Status Table 383 */ 384 /*******************************************************************************/ 385 struct spc_GSTableDescriptor_s 386 { 387 bit32 GSTLenMPIS; /**< DW0 - GST Length, MPI State */ 388 /**< bit02-00 MPI state */ 389 /**< 000 - not initialized, 001 - initialized, 390 010 - Configuration termination in progress */ 391 /**< bit3 - IQ Frozen */ 392 /**< bit15-04 GST Length */ 393 /**< bit31-16 MPI-S Initialize Error */ 394 bit32 IQFreezeState0; /**< DW1 - Inbound Queue Freeze State0 */ 395 bit32 IQFreezeState1; /**< DW2 - Inbound Qeue Freeze State1 */ 396 bit32 MsguTcnt; /**< DW3 - MSGU Tick count */ 397 bit32 IopTcnt; /**< DW4 - IOP Tick count */ 398 bit32 Iop1Tcnt; /**< DW5 - IOP1 Tick count */ 399 bit32 PhyState[MAX_VALID_PHYS]; /* SPCV = reserved */ 400 /**< DW6 to DW 0D - Phy Link state 0 to 7, Phy Start State 0 to 7 */ 401 /**< bit00 Phy Start state n, 0 not started, 1 started */ 402 /**< bit01 Phy Link state n, 0 link down, 1 link up */ 403 /**< bit31-2 Reserved */ 404 bit32 GPIOpins; /**< DWE - GPIO pins */ 405 bit32 reserved1; /**< DWF - reserved */ 406 bit32 reserved2; /**< DW10 - reserved */ 407 bit32 recoverErrInfo[8]; /**< DW11 to DW18 - Recoverable Error Information */ 408 }; 409 410 typedef struct spc_GSTableDescriptor_s spc_GSTableDescriptor_t; 411 412 /*******************************************************************************/ 413 /** \struct spc_SPASTable_s 414 * \brief SAS Phy Analog Setup Table 415 * 416 * The spc_SPASTable_s structure is used to set Phy Calibration 417 * attributes 418 */ 419 /*******************************************************************************/ 420 struct spc_SPASTable_s 421 { 422 bit32 spaReg0; /* transmitter per port configuration 1 SAS_SATA G1 */ 423 bit32 spaReg1; /* transmitter per port configuration 2 SAS_SATA G1*/ 424 bit32 spaReg2; /* transmitter per port configuration 3 SAS_SATA G1*/ 425 bit32 spaReg3; /* transmitter configuration 1 */ 426 bit32 spaReg4; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 427 bit32 spaReg5; /* reveiver per port configuration 2 SAS_SATA G3 */ 428 bit32 spaReg6; /* reveiver per configuration 1 */ 429 bit32 spaReg7; /* reveiver per configuration 2 */ 430 bit32 reserved[2]; /* reserved */ 431 }; 432 433 typedef struct spc_SPASTable_s spc_SPASTable_t; 434 435 /*******************************************************************************/ 436 /** \struct spc_inboundQueueDescriptor_s 437 * \brief This structure is used to configure inbound queues 438 * 439 * This structure specifies all required attributes to configure inbound queues 440 */ 441 /*******************************************************************************/ 442 struct spc_inboundQueueDescriptor_s 443 { 444 bit32 elementPriSizeCount; /**< Priority, Size, Count in the queue */ 445 /**< bit00-15 Count */ 446 /**< When set to 0, this queue is disabled */ 447 /**< bit16-29 Size */ 448 /**< bit30-31 Priority 00:Normal, 01:High Priority */ 449 bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ 450 bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ 451 bit32 ciUpperBaseAddress; /**< Upper physical address for inbound queue CI */ 452 bit32 ciLowerBaseAddress; /**< Lower physical address for inbound queue CI */ 453 bit32 PIPCIBar; /**< PCI BAR for PI Offset */ 454 bit32 PIOffset; /**< Offset address for inbound queue PI */ 455 bit32 reserved; /**< reserved */ 456 }; 457 458 typedef struct spc_inboundQueueDescriptor_s spc_inboundQueueDescriptor_t; 459 460 /*******************************************************************************/ 461 /** \struct spc_outboundQueueDescriptor_s 462 * \brief This structure is used to configure outbound queues 463 * 464 * This structure specifies all required attributes to configure outbound queues 465 */ 466 /*******************************************************************************/ 467 struct spc_outboundQueueDescriptor_s 468 { 469 bit32 elementSizeCount; /**< Size & Count of each element (slot) in the queue) */ 470 /**< bit00-15 Count */ 471 /**< When set to 0, this queue is disabled */ 472 /**< bit16-29 Size */ 473 /**< bit30 Interrupt enable/disable */ 474 /**< bit31 reserved */ 475 bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ 476 bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ 477 bit32 piUpperBaseAddress; /**< PI Upper Base Address for outbound queue */ 478 bit32 piLowerBaseAddress; /**< PI Lower Base Address for outbound queue */ 479 bit32 CIPCIBar; /**< PCI BAR for CI Offset */ 480 bit32 CIOffset; /**< Offset address for outbound queue CI */ 481 bit32 interruptVecCntDelay; /**< Delay in microseconds before the interrupt is asserted */ 482 /**< if the interrupt threshold has not been reached */ 483 /**< Number of interrupt events before the interrupt is asserted */ 484 /**< If set to 0, interrupts for this queue are disable */ 485 /**< Interrupt vector number for this queue */ 486 /**< Note that the interrupt type can be MSI or MSI-X */ 487 /**< depending on the system configuration */ 488 /**< bit00-15 Delay */ 489 /**< bit16-23 Count */ 490 /**< bit24-31 Vector */ 491 bit32 DInterruptTOPCIOffset; /**< Dynamic Interrupt Coalescing Timeout PCI Bar Offset */ 492 }; 493 494 typedef struct spc_outboundQueueDescriptor_s spc_outboundQueueDescriptor_t; 495 496 typedef struct InterruptVT_s 497 { 498 bit32 iccict; /**< DW0 - Interrupt Colescing Control and Timer */ 499 bit32 iraeirad; /**< DW1 - Interrupt Reassertion Enable/Delay */ 500 } InterruptVT_t; 501 502 typedef struct mpiInterruptVT_s 503 { 504 InterruptVT_t IntVecTble[MAX_NUM_VECTOR << 1]; 505 } mpiInterruptVT_t; 506 507 #define INT_VT_Coal_CNT_TO 0 508 #define INT_VT_Coal_ReAssert_Enab 4 509 510 typedef struct phyAttrb_s 511 { 512 bit32 phyState; 513 bit32 phyEventOQ; 514 } phyAttrb_t; 515 516 typedef struct sasPhyAttribute_s 517 { 518 phyAttrb_t phyAttribute[MAX_VALID_PHYS]; 519 }sasPhyAttribute_t; 520 521 522 #define PHY_STATE 0 523 #define PHY_EVENT_OQ 4 524 525 /*******************************************************************************/ 526 /** \struct spcMSGUConfig_s 527 * \brief This structure is used to configure controller's message unit 528 * 529 */ 530 /*******************************************************************************/ 531 typedef struct fwMSGUConfig_s 532 { 533 spc_configMainDescriptor_t mainConfiguration; /**< main part of Configuration Table */ 534 spc_GSTableDescriptor_t GeneralStatusTable; /**< MPI general status table */ 535 spc_inboundQueueDescriptor_t inboundQueue[IB_QUEUE_CFGSIZE]; /**< Inbound queue configuration array */ 536 spc_outboundQueueDescriptor_t outboundQueue[OB_QUEUE_CFGSIZE]; /**< Outbound queue configuration array */ 537 agsaPhyAnalogSetupTable_t phyAnalogConfig; 538 mpiInterruptVT_t interruptVTable; 539 sasPhyAttribute_t phyAttributeTable; 540 }fwMSGUConfig_t; 541 542 543 typedef void (*EnadDisabHandler_t)( 544 agsaRoot_t *agRoot, 545 bit32 interruptVectorIndex 546 ); 547 548 typedef bit32 (*InterruptOurs_t)( 549 agsaRoot_t *agRoot, 550 bit32 interruptVectorIndex 551 ); 552 #endif /* __SPC_DEFS__ */ 553