1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7#include "imx8mm.dtsi" 8#include <dt-bindings/net/ti-dp83867.h> 9 10/ { 11 model = "PHYTEC phyCORE-i.MX8MM"; 12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 13 14 aliases { 15 rtc0 = &rv3028; 16 rtc1 = &snvs_rtc; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23 24 reg_vdd_3v3_s: regulator-vdd-3v3-s { 25 compatible = "regulator-fixed"; 26 regulator-always-on; 27 regulator-boot-on; 28 regulator-max-microvolt = <3300000>; 29 regulator-min-microvolt = <3300000>; 30 regulator-name = "VDD_3V3_S"; 31 }; 32}; 33 34&A53_0 { 35 cpu-supply = <®_vdd_arm>; 36}; 37 38&A53_1 { 39 cpu-supply = <®_vdd_arm>; 40}; 41 42&A53_2 { 43 cpu-supply = <®_vdd_arm>; 44}; 45 46&A53_3 { 47 cpu-supply = <®_vdd_arm>; 48}; 49 50&ddrc { 51 operating-points-v2 = <&ddrc_opp_table>; 52 53 ddrc_opp_table: opp-table { 54 compatible = "operating-points-v2"; 55 56 opp-25000000 { 57 opp-hz = /bits/ 64 <25000000>; 58 }; 59 60 opp-100000000 { 61 opp-hz = /bits/ 64 <100000000>; 62 }; 63 64 opp-750000000 { 65 opp-hz = /bits/ 64 <750000000>; 66 }; 67 }; 68}; 69 70/* Ethernet */ 71&fec1 { 72 phy-mode = "rgmii-id"; 73 phy-handle = <ðphy0>; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_fec1>; 76 status = "okay"; 77 78 mdio { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 ethphy0: ethernet-phy@0 { 83 compatible = "ethernet-phy-ieee802.3-c22"; 84 enet-phy-lane-no-swap; 85 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 86 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 87 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 88 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 89 reg = <0>; 90 reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 91 reset-assert-us = <1000>; 92 reset-deassert-us = <1000>; 93 }; 94 }; 95}; 96 97/* SPI Flash */ 98&flexspi { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_flexspi0>; 101 status = "okay"; 102 103 som_flash: flash@0 { 104 #address-cells = <1>; 105 #size-cells = <1>; 106 compatible = "jedec,spi-nor"; 107 reg = <0>; 108 spi-max-frequency = <80000000>; 109 spi-rx-bus-width = <4>; 110 spi-tx-bus-width = <1>; 111 }; 112}; 113 114&gpio1 { 115 gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT", 116 "", "", "", "RESET_ETHPHY", 117 "", "", "nENABLE_FLATLINK"; 118}; 119 120/* I2C1 */ 121&i2c1 { 122 clock-frequency = <400000>; 123 pinctrl-names = "default","gpio"; 124 pinctrl-0 = <&pinctrl_i2c1>; 125 pinctrl-1 = <&pinctrl_i2c1_gpio>; 126 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 127 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 128 status = "okay"; 129 130 pmic@8 { 131 compatible = "nxp,pf8121a"; 132 reg = <0x08>; 133 134 regulators { 135 reg_nvcc_sd1: ldo1 { 136 regulator-always-on; 137 regulator-boot-on; 138 regulator-max-microvolt = <3300000>; 139 regulator-min-microvolt = <3300000>; 140 regulator-name = "NVCC_SD1 (LDO1)"; 141 142 regulator-state-mem { 143 regulator-off-in-suspend; 144 }; 145 }; 146 147 reg_nvcc_sd2: ldo2 { 148 regulator-always-on; 149 regulator-boot-on; 150 regulator-max-microvolt = <3300000>; 151 regulator-min-microvolt = <1800000>; 152 regulator-name = "NVCC_SD2 (LDO2)"; 153 154 regulator-state-mem { 155 regulator-off-in-suspend; 156 }; 157 }; 158 159 reg_vcc_enet: ldo3 { 160 regulator-always-on; 161 regulator-boot-on; 162 regulator-max-microvolt = <2500000>; 163 regulator-min-microvolt = <2500000>; 164 regulator-name = "VCC_ENET_2V5 (LDO3)"; 165 166 regulator-state-mem { 167 regulator-on-in-suspend; 168 regulator-suspend-max-microvolt = <2500000>; 169 regulator-suspend-min-microvolt = <2500000>; 170 }; 171 }; 172 173 reg_vdda_1v8: ldo4 { 174 regulator-always-on; 175 regulator-boot-on; 176 regulator-max-microvolt = <1800000>; 177 regulator-min-microvolt = <1500000>; 178 regulator-name = "VDDA_1V8 (LDO4)"; 179 180 regulator-state-mem { 181 regulator-on-in-suspend; 182 regulator-suspend-min-microvolt = <1500000>; 183 regulator-suspend-max-microvolt = <1500000>; 184 }; 185 }; 186 187 reg_soc_vdda_phy: buck1 { 188 regulator-always-on; 189 regulator-boot-on; 190 regulator-max-microvolt = <900000>; 191 regulator-min-microvolt = <400000>; 192 regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; 193 194 regulator-state-mem { 195 regulator-on-in-suspend; 196 regulator-suspend-min-microvolt = <400000>; 197 regulator-suspend-max-microvolt = <400000>; 198 }; 199 }; 200 201 reg_vdd_gpu_dram: buck2 { 202 regulator-always-on; 203 regulator-boot-on; 204 regulator-max-microvolt = <1000000>; 205 regulator-min-microvolt = <1000000>; 206 regulator-name = "VDD_GPU_DRAM (BUCK2)"; 207 208 regulator-state-mem { 209 regulator-on-in-suspend; 210 regulator-suspend-max-microvolt = <1000000>; 211 regulator-suspend-min-microvolt = <1000000>; 212 }; 213 }; 214 215 reg_vdd_vpu: buck3 { 216 regulator-always-on; 217 regulator-boot-on; 218 regulator-max-microvolt = <1000000>; 219 regulator-min-microvolt = <400000>; 220 regulator-name = "VDD_VPU (BUCK3)"; 221 222 regulator-state-mem { 223 regulator-off-in-suspend; 224 }; 225 }; 226 227 reg_vdd_mipi: buck4 { 228 regulator-always-on; 229 regulator-boot-on; 230 regulator-max-microvolt = <1050000>; 231 regulator-min-microvolt = <900000>; 232 regulator-name = "VDD_MIPI_0P9 (BUCK4)"; 233 234 regulator-state-mem { 235 regulator-off-in-suspend; 236 }; 237 }; 238 239 reg_vdd_arm: buck5 { 240 regulator-always-on; 241 regulator-boot-on; 242 regulator-max-microvolt = <1050000>; 243 regulator-min-microvolt = <400000>; 244 regulator-name = "VDD_ARM (BUCK5)"; 245 246 regulator-state-mem { 247 regulator-off-in-suspend; 248 }; 249 }; 250 251 reg_vdd_1v8: buck6 { 252 regulator-always-on; 253 regulator-boot-on; 254 regulator-max-microvolt = <1800000>; 255 regulator-min-microvolt = <1800000>; 256 regulator-name = "VDD_1V8 (BUCK6)"; 257 258 regulator-state-mem { 259 regulator-on-in-suspend; 260 regulator-suspend-max-microvolt = <1800000>; 261 regulator-suspend-min-microvolt = <1800000>; 262 }; 263 }; 264 265 reg_nvcc_dram: buck7 { 266 regulator-always-on; 267 regulator-boot-on; 268 regulator-max-microvolt = <1100000>; 269 regulator-min-microvolt = <1100000>; 270 regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; 271 }; 272 273 reg_vsnvs: vsnvs { 274 regulator-always-on; 275 regulator-boot-on; 276 regulator-max-microvolt = <1800000>; 277 regulator-min-microvolt = <1800000>; 278 regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; 279 }; 280 }; 281 }; 282 283 sn65dsi83: bridge@2d { 284 compatible = "ti,sn65dsi83"; 285 enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_sn65dsi83>; 288 reg = <0x2d>; 289 vcc-supply = <®_vdd_1v8>; 290 status = "disabled"; 291 }; 292 293 /* EEPROM */ 294 eeprom@51 { 295 compatible = "atmel,24c32"; 296 pagesize = <32>; 297 reg = <0x51>; 298 vcc-supply = <®_vdd_3v3_s>; 299 }; 300 301 /* RTC */ 302 rv3028: rtc@52 { 303 compatible = "microcrystal,rv3028"; 304 reg = <0x52>; 305 }; 306}; 307 308/* eMMC */ 309&usdhc3 { 310 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 311 assigned-clock-rates = <400000000>; 312 bus-width = <8>; 313 keep-power-in-suspend; 314 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 315 pinctrl-0 = <&pinctrl_usdhc3>; 316 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 317 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 318 non-removable; 319 status = "okay"; 320}; 321 322/* Watchdog */ 323&wdog1 { 324 fsl,ext-reset-output; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_wdog>; 327 status = "okay"; 328}; 329 330&iomuxc { 331 pinctrl_fec1: fec1grp { 332 fsl,pins = < 333 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 334 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 335 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 336 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 337 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 338 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 339 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 340 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 341 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 342 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 343 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 344 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 345 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 346 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 347 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 348 >; 349 }; 350 351 pinctrl_flexspi0: flexspi0grp { 352 fsl,pins = < 353 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 354 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 355 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 356 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 357 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 358 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 359 >; 360 }; 361 362 pinctrl_i2c1: i2c1grp { 363 fsl,pins = < 364 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 365 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 366 >; 367 }; 368 369 pinctrl_i2c1_gpio: i2c1gpiogrp { 370 fsl,pins = < 371 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 372 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 373 >; 374 }; 375 376 pinctrl_sn65dsi83: sn65dsi83grp { 377 fsl,pins = < 378 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 379 >; 380 }; 381 382 pinctrl_usdhc3: usdhc3grp { 383 fsl,pins = < 384 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 385 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 386 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 387 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 388 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 389 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 390 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 391 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 392 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 393 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 394 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 395 >; 396 }; 397 398 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 399 fsl,pins = < 400 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 401 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 402 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 403 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 404 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 405 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 406 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 407 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 408 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 409 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 410 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 411 >; 412 }; 413 414 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 415 fsl,pins = < 416 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 417 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 418 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 419 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 420 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 421 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 422 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 423 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 424 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 425 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 426 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 427 >; 428 }; 429 430 pinctrl_wdog: wdoggrp { 431 fsl,pins = < 432 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 433 >; 434 }; 435}; 436