1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_0_ppt.h"
39 #include "smu_v13_0_0_pptable.h"
40 #include "smu_v13_0_0_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
72
73 #define mmMP1_SMN_C2PMSG_66 0x0282
74 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
75
76 #define mmMP1_SMN_C2PMSG_82 0x0292
77 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
78
79 #define mmMP1_SMN_C2PMSG_90 0x029a
80 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
81
82 #define mmMP1_SMN_C2PMSG_75 0x028b
83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
84
85 #define mmMP1_SMN_C2PMSG_53 0x0275
86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
87
88 #define mmMP1_SMN_C2PMSG_54 0x0276
89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
90
91 #define DEBUGSMC_MSG_Mode1Reset 2
92
93 /*
94 * SMU_v13_0_10 supports ECCTABLE since version 80.34.0,
95 * use this to check ECCTABLE feature whether support
96 */
97 #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200
98
99 #define PP_OD_FEATURE_GFXCLK_FMIN 0
100 #define PP_OD_FEATURE_GFXCLK_FMAX 1
101 #define PP_OD_FEATURE_UCLK_FMIN 2
102 #define PP_OD_FEATURE_UCLK_FMAX 3
103 #define PP_OD_FEATURE_GFX_VF_CURVE 4
104 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
105 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
106 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
107 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
108 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
109 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
110 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
111 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
112
113 #define LINK_SPEED_MAX 3
114
115 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
116 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
117 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
118 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
119 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
120 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
121 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
122 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
123 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
124 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
125 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
126 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
127 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
128 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
129 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
130 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
131 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
132 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
133 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
134 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
135 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
136 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
137 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
138 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
139 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
140 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
141 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
142 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
143 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
144 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
145 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
146 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
147 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
148 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
149 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
150 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
151 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
152 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
153 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
154 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
155 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
156 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
157 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
158 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
159 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
160 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
161 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
162 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
163 MSG_MAP(Mode2Reset, PPSMC_MSG_Mode2Reset, 0),
164 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
165 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
166 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
167 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
168 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
169 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
170 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
171 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
172 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
173 MSG_MAP(DALNotPresent, PPSMC_MSG_DALNotPresent, 0),
174 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
175 };
176
177 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
178 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
179 CLK_MAP(SCLK, PPCLK_GFXCLK),
180 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
181 CLK_MAP(FCLK, PPCLK_FCLK),
182 CLK_MAP(UCLK, PPCLK_UCLK),
183 CLK_MAP(MCLK, PPCLK_UCLK),
184 CLK_MAP(VCLK, PPCLK_VCLK_0),
185 CLK_MAP(VCLK1, PPCLK_VCLK_1),
186 CLK_MAP(DCLK, PPCLK_DCLK_0),
187 CLK_MAP(DCLK1, PPCLK_DCLK_1),
188 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
189 };
190
191 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
192 FEA_MAP(FW_DATA_READ),
193 FEA_MAP(DPM_GFXCLK),
194 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
195 FEA_MAP(DPM_UCLK),
196 FEA_MAP(DPM_FCLK),
197 FEA_MAP(DPM_SOCCLK),
198 FEA_MAP(DPM_MP0CLK),
199 FEA_MAP(DPM_LINK),
200 FEA_MAP(DPM_DCN),
201 FEA_MAP(VMEMP_SCALING),
202 FEA_MAP(VDDIO_MEM_SCALING),
203 FEA_MAP(DS_GFXCLK),
204 FEA_MAP(DS_SOCCLK),
205 FEA_MAP(DS_FCLK),
206 FEA_MAP(DS_LCLK),
207 FEA_MAP(DS_DCFCLK),
208 FEA_MAP(DS_UCLK),
209 FEA_MAP(GFX_ULV),
210 FEA_MAP(FW_DSTATE),
211 FEA_MAP(GFXOFF),
212 FEA_MAP(BACO),
213 FEA_MAP(MM_DPM),
214 FEA_MAP(SOC_MPCLK_DS),
215 FEA_MAP(BACO_MPCLK_DS),
216 FEA_MAP(THROTTLERS),
217 FEA_MAP(SMARTSHIFT),
218 FEA_MAP(GTHR),
219 FEA_MAP(ACDC),
220 FEA_MAP(VR0HOT),
221 FEA_MAP(FW_CTF),
222 FEA_MAP(FAN_CONTROL),
223 FEA_MAP(GFX_DCS),
224 FEA_MAP(GFX_READ_MARGIN),
225 FEA_MAP(LED_DISPLAY),
226 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
227 FEA_MAP(OUT_OF_BAND_MONITOR),
228 FEA_MAP(OPTIMIZED_VMIN),
229 FEA_MAP(GFX_IMU),
230 FEA_MAP(BOOT_TIME_CAL),
231 FEA_MAP(GFX_PCC_DFLL),
232 FEA_MAP(SOC_CG),
233 FEA_MAP(DF_CSTATE),
234 FEA_MAP(GFX_EDC),
235 FEA_MAP(BOOT_POWER_OPT),
236 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
237 FEA_MAP(DS_VCN),
238 FEA_MAP(BACO_CG),
239 FEA_MAP(MEM_TEMP_READ),
240 FEA_MAP(ATHUB_MMHUB_PG),
241 FEA_MAP(SOC_PCC),
242 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
243 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
244 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
245 };
246
247 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
248 TAB_MAP(PPTABLE),
249 TAB_MAP(WATERMARKS),
250 TAB_MAP(AVFS_PSM_DEBUG),
251 TAB_MAP(PMSTATUSLOG),
252 TAB_MAP(SMU_METRICS),
253 TAB_MAP(DRIVER_SMU_CONFIG),
254 TAB_MAP(ACTIVITY_MONITOR_COEFF),
255 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
256 TAB_MAP(I2C_COMMANDS),
257 TAB_MAP(ECCINFO),
258 TAB_MAP(OVERDRIVE),
259 TAB_MAP(WIFIBAND),
260 };
261
262 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
263 PWR_MAP(AC),
264 PWR_MAP(DC),
265 };
266
267 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
268 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
269 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
270 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
271 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
272 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
273 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
274 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
275 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
276 };
277
278 static const uint8_t smu_v13_0_0_throttler_map[] = {
279 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
280 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
281 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
282 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
283 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
284 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
285 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
286 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
287 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
288 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
289 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
290 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
291 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
292 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
293 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
294 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
295 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
296 };
297
298 static int
smu_v13_0_0_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)299 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
300 uint32_t *feature_mask, uint32_t num)
301 {
302 struct amdgpu_device *adev = smu->adev;
303
304 if (num > 2)
305 return -EINVAL;
306
307 memset(feature_mask, 0xff, sizeof(uint32_t) * num);
308
309 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
310 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
312 }
313
314 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
315 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
316 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
317
318 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
320
321 /* PMFW 78.58 contains a critical fix for gfxoff feature */
322 if ((smu->smc_fw_version < 0x004e3a00) ||
323 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
324 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
325
326 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
327 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
328 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
329 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
330 }
331
332 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
333 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
334
335 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
336 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
337 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
338 }
339
340 if (!(adev->pm.pp_feature & PP_ULV_MASK))
341 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
342
343 return 0;
344 }
345
smu_v13_0_0_check_powerplay_table(struct smu_context * smu)346 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
347 {
348 struct smu_table_context *table_context = &smu->smu_table;
349 struct smu_13_0_0_powerplay_table *powerplay_table =
350 table_context->power_play_table;
351 struct smu_baco_context *smu_baco = &smu->smu_baco;
352 PPTable_t *pptable = smu->smu_table.driver_pptable;
353 const OverDriveLimits_t * const overdrive_upperlimits =
354 &pptable->SkuTable.OverDriveLimitsBasicMax;
355 const OverDriveLimits_t * const overdrive_lowerlimits =
356 &pptable->SkuTable.OverDriveLimitsMin;
357
358 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
359 smu->dc_controlled_by_gpio = true;
360
361 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) {
362 smu_baco->platform_support = true;
363
364 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
365 smu_baco->maco_support = true;
366 }
367
368 if (!overdrive_lowerlimits->FeatureCtrlMask ||
369 !overdrive_upperlimits->FeatureCtrlMask)
370 smu->od_enabled = false;
371
372 table_context->thermal_controller_type =
373 powerplay_table->thermal_controller_type;
374
375 /*
376 * Instead of having its own buffer space and get overdrive_table copied,
377 * smu->od_settings just points to the actual overdrive_table
378 */
379 smu->od_settings = &powerplay_table->overdrive_table;
380
381 smu->adev->pm.no_fan =
382 !(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
383
384 return 0;
385 }
386
smu_v13_0_0_store_powerplay_table(struct smu_context * smu)387 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
388 {
389 struct smu_table_context *table_context = &smu->smu_table;
390 struct smu_13_0_0_powerplay_table *powerplay_table =
391 table_context->power_play_table;
392
393 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
394 sizeof(PPTable_t));
395
396 return 0;
397 }
398
399 #ifndef atom_smc_dpm_info_table_13_0_0
400 struct atom_smc_dpm_info_table_13_0_0 {
401 struct atom_common_table_header table_header;
402 BoardTable_t BoardTable;
403 };
404 #endif
405
smu_v13_0_0_append_powerplay_table(struct smu_context * smu)406 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
407 {
408 struct smu_table_context *table_context = &smu->smu_table;
409 PPTable_t *smc_pptable = table_context->driver_pptable;
410 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
411 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
412 int index, ret;
413
414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
415 smc_dpm_info);
416
417 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
418 (uint8_t **)&smc_dpm_table);
419 if (ret)
420 return ret;
421
422 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
423
424 return 0;
425 }
426
smu_v13_0_0_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)427 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
428 void **table,
429 uint32_t *size)
430 {
431 struct smu_table_context *smu_table = &smu->smu_table;
432 void *combo_pptable = smu_table->combo_pptable;
433 int ret = 0;
434
435 ret = smu_cmn_get_combo_pptable(smu);
436 if (ret)
437 return ret;
438
439 *table = combo_pptable;
440 *size = sizeof(struct smu_13_0_0_powerplay_table);
441
442 return 0;
443 }
444
smu_v13_0_0_setup_pptable(struct smu_context * smu)445 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
446 {
447 struct smu_table_context *smu_table = &smu->smu_table;
448 struct amdgpu_device *adev = smu->adev;
449 int ret = 0;
450
451 if (amdgpu_sriov_vf(smu->adev))
452 return 0;
453
454 ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
455 &smu_table->power_play_table,
456 &smu_table->power_play_table_size);
457 if (ret)
458 return ret;
459
460 ret = smu_v13_0_0_store_powerplay_table(smu);
461 if (ret)
462 return ret;
463
464 /*
465 * With SCPM enabled, the operation below will be handled
466 * by PSP. Driver involvment is unnecessary and useless.
467 */
468 if (!adev->scpm_enabled) {
469 ret = smu_v13_0_0_append_powerplay_table(smu);
470 if (ret)
471 return ret;
472 }
473
474 ret = smu_v13_0_0_check_powerplay_table(smu);
475 if (ret)
476 return ret;
477
478 return ret;
479 }
480
smu_v13_0_0_tables_init(struct smu_context * smu)481 static int smu_v13_0_0_tables_init(struct smu_context *smu)
482 {
483 struct smu_table_context *smu_table = &smu->smu_table;
484 struct smu_table *tables = smu_table->tables;
485
486 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
487 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
488 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
489 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
490 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
491 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
492 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
493 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
494 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
496 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
497 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
498 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
499 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
500 AMDGPU_GEM_DOMAIN_VRAM);
501 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
506 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
507 AMDGPU_GEM_DOMAIN_VRAM);
508
509 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
510 if (!smu_table->metrics_table)
511 goto err0_out;
512 smu_table->metrics_time = 0;
513
514 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
515 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
516 if (!smu_table->gpu_metrics_table)
517 goto err1_out;
518
519 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
520 if (!smu_table->watermarks_table)
521 goto err2_out;
522
523 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
524 if (!smu_table->ecc_table)
525 goto err3_out;
526
527 return 0;
528
529 err3_out:
530 kfree(smu_table->watermarks_table);
531 err2_out:
532 kfree(smu_table->gpu_metrics_table);
533 err1_out:
534 kfree(smu_table->metrics_table);
535 err0_out:
536 return -ENOMEM;
537 }
538
smu_v13_0_0_allocate_dpm_context(struct smu_context * smu)539 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
540 {
541 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
542
543 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
544 GFP_KERNEL);
545 if (!smu_dpm->dpm_context)
546 return -ENOMEM;
547
548 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
549
550 return 0;
551 }
552
smu_v13_0_0_init_smc_tables(struct smu_context * smu)553 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
554 {
555 int ret = 0;
556
557 ret = smu_v13_0_0_tables_init(smu);
558 if (ret)
559 return ret;
560
561 ret = smu_v13_0_0_allocate_dpm_context(smu);
562 if (ret)
563 return ret;
564
565 return smu_v13_0_init_smc_tables(smu);
566 }
567
smu_v13_0_0_set_default_dpm_table(struct smu_context * smu)568 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
569 {
570 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
571 struct smu_table_context *table_context = &smu->smu_table;
572 PPTable_t *pptable = table_context->driver_pptable;
573 SkuTable_t *skutable = &pptable->SkuTable;
574 struct smu_13_0_dpm_table *dpm_table;
575 struct smu_13_0_pcie_table *pcie_table;
576 uint32_t link_level;
577 int ret = 0;
578
579 /* socclk dpm table setup */
580 dpm_table = &dpm_context->dpm_tables.soc_table;
581 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
582 ret = smu_v13_0_set_single_dpm_table(smu,
583 SMU_SOCCLK,
584 dpm_table);
585 if (ret)
586 return ret;
587 } else {
588 dpm_table->count = 1;
589 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
590 dpm_table->dpm_levels[0].enabled = true;
591 dpm_table->min = dpm_table->dpm_levels[0].value;
592 dpm_table->max = dpm_table->dpm_levels[0].value;
593 }
594
595 /* gfxclk dpm table setup */
596 dpm_table = &dpm_context->dpm_tables.gfx_table;
597 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
598 ret = smu_v13_0_set_single_dpm_table(smu,
599 SMU_GFXCLK,
600 dpm_table);
601 if (ret)
602 return ret;
603
604 /*
605 * Update the reported maximum shader clock to the value
606 * which can be guarded to be achieved on all cards. This
607 * is aligned with Window setting. And considering that value
608 * might be not the peak frequency the card can achieve, it
609 * is normal some real-time clock frequency can overtake this
610 * labelled maximum clock frequency(for example in pp_dpm_sclk
611 * sysfs output).
612 */
613 if (skutable->DriverReportedClocks.GameClockAc &&
614 (dpm_table->dpm_levels[dpm_table->count - 1].value >
615 skutable->DriverReportedClocks.GameClockAc)) {
616 dpm_table->dpm_levels[dpm_table->count - 1].value =
617 skutable->DriverReportedClocks.GameClockAc;
618 dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
619 }
620 } else {
621 dpm_table->count = 1;
622 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
623 dpm_table->dpm_levels[0].enabled = true;
624 dpm_table->min = dpm_table->dpm_levels[0].value;
625 dpm_table->max = dpm_table->dpm_levels[0].value;
626 }
627
628 /* uclk dpm table setup */
629 dpm_table = &dpm_context->dpm_tables.uclk_table;
630 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
631 ret = smu_v13_0_set_single_dpm_table(smu,
632 SMU_UCLK,
633 dpm_table);
634 if (ret)
635 return ret;
636 } else {
637 dpm_table->count = 1;
638 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
639 dpm_table->dpm_levels[0].enabled = true;
640 dpm_table->min = dpm_table->dpm_levels[0].value;
641 dpm_table->max = dpm_table->dpm_levels[0].value;
642 }
643
644 /* fclk dpm table setup */
645 dpm_table = &dpm_context->dpm_tables.fclk_table;
646 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
647 ret = smu_v13_0_set_single_dpm_table(smu,
648 SMU_FCLK,
649 dpm_table);
650 if (ret)
651 return ret;
652 } else {
653 dpm_table->count = 1;
654 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
655 dpm_table->dpm_levels[0].enabled = true;
656 dpm_table->min = dpm_table->dpm_levels[0].value;
657 dpm_table->max = dpm_table->dpm_levels[0].value;
658 }
659
660 /* vclk dpm table setup */
661 dpm_table = &dpm_context->dpm_tables.vclk_table;
662 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
663 ret = smu_v13_0_set_single_dpm_table(smu,
664 SMU_VCLK,
665 dpm_table);
666 if (ret)
667 return ret;
668 } else {
669 dpm_table->count = 1;
670 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
671 dpm_table->dpm_levels[0].enabled = true;
672 dpm_table->min = dpm_table->dpm_levels[0].value;
673 dpm_table->max = dpm_table->dpm_levels[0].value;
674 }
675
676 /* dclk dpm table setup */
677 dpm_table = &dpm_context->dpm_tables.dclk_table;
678 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
679 ret = smu_v13_0_set_single_dpm_table(smu,
680 SMU_DCLK,
681 dpm_table);
682 if (ret)
683 return ret;
684 } else {
685 dpm_table->count = 1;
686 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
687 dpm_table->dpm_levels[0].enabled = true;
688 dpm_table->min = dpm_table->dpm_levels[0].value;
689 dpm_table->max = dpm_table->dpm_levels[0].value;
690 }
691
692 /* lclk dpm table setup */
693 pcie_table = &dpm_context->dpm_tables.pcie_table;
694 pcie_table->num_of_link_levels = 0;
695 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
696 if (!skutable->PcieGenSpeed[link_level] &&
697 !skutable->PcieLaneCount[link_level] &&
698 !skutable->LclkFreq[link_level])
699 continue;
700
701 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
702 skutable->PcieGenSpeed[link_level];
703 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
704 skutable->PcieLaneCount[link_level];
705 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
706 skutable->LclkFreq[link_level];
707 pcie_table->num_of_link_levels++;
708 }
709
710 /* dcefclk dpm table setup */
711 dpm_table = &dpm_context->dpm_tables.dcef_table;
712 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
713 ret = smu_v13_0_set_single_dpm_table(smu,
714 SMU_DCEFCLK,
715 dpm_table);
716 if (ret)
717 return ret;
718 } else {
719 dpm_table->count = 1;
720 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
721 dpm_table->dpm_levels[0].enabled = true;
722 dpm_table->min = dpm_table->dpm_levels[0].value;
723 dpm_table->max = dpm_table->dpm_levels[0].value;
724 }
725
726 return 0;
727 }
728
smu_v13_0_0_is_dpm_running(struct smu_context * smu)729 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
730 {
731 int ret = 0;
732 uint64_t feature_enabled;
733
734 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
735 if (ret)
736 return false;
737
738 return !!(feature_enabled & SMC_DPM_FEATURE);
739 }
740
smu_v13_0_0_system_features_control(struct smu_context * smu,bool en)741 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
742 bool en)
743 {
744 return smu_v13_0_system_features_control(smu, en);
745 }
746
smu_v13_0_get_throttler_status(SmuMetrics_t * metrics)747 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
748 {
749 uint32_t throttler_status = 0;
750 int i;
751
752 for (i = 0; i < THROTTLER_COUNT; i++)
753 throttler_status |=
754 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
755
756 return throttler_status;
757 }
758
759 #define SMU_13_0_0_BUSY_THRESHOLD 15
smu_v13_0_0_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)760 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
761 MetricsMember_t member,
762 uint32_t *value)
763 {
764 struct smu_table_context *smu_table = &smu->smu_table;
765 SmuMetrics_t *metrics =
766 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
767 int ret = 0;
768
769 ret = smu_cmn_get_metrics_table(smu,
770 NULL,
771 false);
772 if (ret)
773 return ret;
774
775 switch (member) {
776 case METRICS_CURR_GFXCLK:
777 *value = metrics->CurrClock[PPCLK_GFXCLK];
778 break;
779 case METRICS_CURR_SOCCLK:
780 *value = metrics->CurrClock[PPCLK_SOCCLK];
781 break;
782 case METRICS_CURR_UCLK:
783 *value = metrics->CurrClock[PPCLK_UCLK];
784 break;
785 case METRICS_CURR_VCLK:
786 *value = metrics->CurrClock[PPCLK_VCLK_0];
787 break;
788 case METRICS_CURR_VCLK1:
789 *value = metrics->CurrClock[PPCLK_VCLK_1];
790 break;
791 case METRICS_CURR_DCLK:
792 *value = metrics->CurrClock[PPCLK_DCLK_0];
793 break;
794 case METRICS_CURR_DCLK1:
795 *value = metrics->CurrClock[PPCLK_DCLK_1];
796 break;
797 case METRICS_CURR_FCLK:
798 *value = metrics->CurrClock[PPCLK_FCLK];
799 break;
800 case METRICS_CURR_DCEFCLK:
801 *value = metrics->CurrClock[PPCLK_DCFCLK];
802 break;
803 case METRICS_AVERAGE_GFXCLK:
804 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
805 *value = metrics->AverageGfxclkFrequencyPostDs;
806 else
807 *value = metrics->AverageGfxclkFrequencyPreDs;
808 break;
809 case METRICS_AVERAGE_FCLK:
810 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
811 *value = metrics->AverageFclkFrequencyPostDs;
812 else
813 *value = metrics->AverageFclkFrequencyPreDs;
814 break;
815 case METRICS_AVERAGE_UCLK:
816 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
817 *value = metrics->AverageMemclkFrequencyPostDs;
818 else
819 *value = metrics->AverageMemclkFrequencyPreDs;
820 break;
821 case METRICS_AVERAGE_VCLK:
822 *value = metrics->AverageVclk0Frequency;
823 break;
824 case METRICS_AVERAGE_DCLK:
825 *value = metrics->AverageDclk0Frequency;
826 break;
827 case METRICS_AVERAGE_VCLK1:
828 *value = metrics->AverageVclk1Frequency;
829 break;
830 case METRICS_AVERAGE_DCLK1:
831 *value = metrics->AverageDclk1Frequency;
832 break;
833 case METRICS_AVERAGE_GFXACTIVITY:
834 *value = metrics->AverageGfxActivity;
835 break;
836 case METRICS_AVERAGE_MEMACTIVITY:
837 *value = metrics->AverageUclkActivity;
838 break;
839 case METRICS_AVERAGE_SOCKETPOWER:
840 *value = metrics->AverageSocketPower << 8;
841 break;
842 case METRICS_TEMPERATURE_EDGE:
843 *value = metrics->AvgTemperature[TEMP_EDGE] *
844 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
845 break;
846 case METRICS_TEMPERATURE_HOTSPOT:
847 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
848 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
849 break;
850 case METRICS_TEMPERATURE_MEM:
851 *value = metrics->AvgTemperature[TEMP_MEM] *
852 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
853 break;
854 case METRICS_TEMPERATURE_VRGFX:
855 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
856 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
857 break;
858 case METRICS_TEMPERATURE_VRSOC:
859 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
860 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
861 break;
862 case METRICS_THROTTLER_STATUS:
863 *value = smu_v13_0_get_throttler_status(metrics);
864 break;
865 case METRICS_CURR_FANSPEED:
866 *value = metrics->AvgFanRpm;
867 break;
868 case METRICS_CURR_FANPWM:
869 *value = metrics->AvgFanPwm;
870 break;
871 case METRICS_VOLTAGE_VDDGFX:
872 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
873 break;
874 case METRICS_PCIE_RATE:
875 *value = metrics->PcieRate;
876 break;
877 case METRICS_PCIE_WIDTH:
878 *value = metrics->PcieWidth;
879 break;
880 default:
881 *value = UINT_MAX;
882 break;
883 }
884
885 return ret;
886 }
887
smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)888 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
889 enum smu_clk_type clk_type,
890 uint32_t *min,
891 uint32_t *max)
892 {
893 struct smu_13_0_dpm_context *dpm_context =
894 smu->smu_dpm.dpm_context;
895 struct smu_13_0_dpm_table *dpm_table;
896
897 switch (clk_type) {
898 case SMU_MCLK:
899 case SMU_UCLK:
900 /* uclk dpm table */
901 dpm_table = &dpm_context->dpm_tables.uclk_table;
902 break;
903 case SMU_GFXCLK:
904 case SMU_SCLK:
905 /* gfxclk dpm table */
906 dpm_table = &dpm_context->dpm_tables.gfx_table;
907 break;
908 case SMU_SOCCLK:
909 /* socclk dpm table */
910 dpm_table = &dpm_context->dpm_tables.soc_table;
911 break;
912 case SMU_FCLK:
913 /* fclk dpm table */
914 dpm_table = &dpm_context->dpm_tables.fclk_table;
915 break;
916 case SMU_VCLK:
917 case SMU_VCLK1:
918 /* vclk dpm table */
919 dpm_table = &dpm_context->dpm_tables.vclk_table;
920 break;
921 case SMU_DCLK:
922 case SMU_DCLK1:
923 /* dclk dpm table */
924 dpm_table = &dpm_context->dpm_tables.dclk_table;
925 break;
926 default:
927 dev_err(smu->adev->dev, "Unsupported clock type!\n");
928 return -EINVAL;
929 }
930
931 if (min)
932 *min = dpm_table->min;
933 if (max)
934 *max = dpm_table->max;
935
936 return 0;
937 }
938
smu_v13_0_0_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)939 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
940 enum amd_pp_sensors sensor,
941 void *data,
942 uint32_t *size)
943 {
944 struct smu_table_context *table_context = &smu->smu_table;
945 PPTable_t *smc_pptable = table_context->driver_pptable;
946 int ret = 0;
947
948 switch (sensor) {
949 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
950 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
951 *size = 4;
952 break;
953 case AMDGPU_PP_SENSOR_MEM_LOAD:
954 ret = smu_v13_0_0_get_smu_metrics_data(smu,
955 METRICS_AVERAGE_MEMACTIVITY,
956 (uint32_t *)data);
957 *size = 4;
958 break;
959 case AMDGPU_PP_SENSOR_GPU_LOAD:
960 ret = smu_v13_0_0_get_smu_metrics_data(smu,
961 METRICS_AVERAGE_GFXACTIVITY,
962 (uint32_t *)data);
963 *size = 4;
964 break;
965 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
966 ret = smu_v13_0_0_get_smu_metrics_data(smu,
967 METRICS_AVERAGE_SOCKETPOWER,
968 (uint32_t *)data);
969 *size = 4;
970 break;
971 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
972 ret = smu_v13_0_0_get_smu_metrics_data(smu,
973 METRICS_TEMPERATURE_HOTSPOT,
974 (uint32_t *)data);
975 *size = 4;
976 break;
977 case AMDGPU_PP_SENSOR_EDGE_TEMP:
978 ret = smu_v13_0_0_get_smu_metrics_data(smu,
979 METRICS_TEMPERATURE_EDGE,
980 (uint32_t *)data);
981 *size = 4;
982 break;
983 case AMDGPU_PP_SENSOR_MEM_TEMP:
984 ret = smu_v13_0_0_get_smu_metrics_data(smu,
985 METRICS_TEMPERATURE_MEM,
986 (uint32_t *)data);
987 *size = 4;
988 break;
989 case AMDGPU_PP_SENSOR_GFX_MCLK:
990 ret = smu_v13_0_0_get_smu_metrics_data(smu,
991 METRICS_CURR_UCLK,
992 (uint32_t *)data);
993 *(uint32_t *)data *= 100;
994 *size = 4;
995 break;
996 case AMDGPU_PP_SENSOR_GFX_SCLK:
997 ret = smu_v13_0_0_get_smu_metrics_data(smu,
998 METRICS_AVERAGE_GFXCLK,
999 (uint32_t *)data);
1000 *(uint32_t *)data *= 100;
1001 *size = 4;
1002 break;
1003 case AMDGPU_PP_SENSOR_VDDGFX:
1004 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1005 METRICS_VOLTAGE_VDDGFX,
1006 (uint32_t *)data);
1007 *size = 4;
1008 break;
1009 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1010 default:
1011 ret = -EOPNOTSUPP;
1012 break;
1013 }
1014
1015 return ret;
1016 }
1017
smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1018 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
1019 enum smu_clk_type clk_type,
1020 uint32_t *value)
1021 {
1022 MetricsMember_t member_type;
1023 int clk_id = 0;
1024
1025 clk_id = smu_cmn_to_asic_specific_index(smu,
1026 CMN2ASIC_MAPPING_CLK,
1027 clk_type);
1028 if (clk_id < 0)
1029 return -EINVAL;
1030
1031 switch (clk_id) {
1032 case PPCLK_GFXCLK:
1033 member_type = METRICS_AVERAGE_GFXCLK;
1034 break;
1035 case PPCLK_UCLK:
1036 member_type = METRICS_CURR_UCLK;
1037 break;
1038 case PPCLK_FCLK:
1039 member_type = METRICS_CURR_FCLK;
1040 break;
1041 case PPCLK_SOCCLK:
1042 member_type = METRICS_CURR_SOCCLK;
1043 break;
1044 case PPCLK_VCLK_0:
1045 member_type = METRICS_AVERAGE_VCLK;
1046 break;
1047 case PPCLK_DCLK_0:
1048 member_type = METRICS_AVERAGE_DCLK;
1049 break;
1050 case PPCLK_VCLK_1:
1051 member_type = METRICS_AVERAGE_VCLK1;
1052 break;
1053 case PPCLK_DCLK_1:
1054 member_type = METRICS_AVERAGE_DCLK1;
1055 break;
1056 case PPCLK_DCFCLK:
1057 member_type = METRICS_CURR_DCEFCLK;
1058 break;
1059 default:
1060 return -EINVAL;
1061 }
1062
1063 return smu_v13_0_0_get_smu_metrics_data(smu,
1064 member_type,
1065 value);
1066 }
1067
smu_v13_0_0_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1068 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
1069 int od_feature_bit)
1070 {
1071 PPTable_t *pptable = smu->smu_table.driver_pptable;
1072 const OverDriveLimits_t * const overdrive_upperlimits =
1073 &pptable->SkuTable.OverDriveLimitsBasicMax;
1074
1075 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1076 }
1077
smu_v13_0_0_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1078 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
1079 int od_feature_bit,
1080 int32_t *min,
1081 int32_t *max)
1082 {
1083 PPTable_t *pptable = smu->smu_table.driver_pptable;
1084 const OverDriveLimits_t * const overdrive_upperlimits =
1085 &pptable->SkuTable.OverDriveLimitsBasicMax;
1086 const OverDriveLimits_t * const overdrive_lowerlimits =
1087 &pptable->SkuTable.OverDriveLimitsMin;
1088 int32_t od_min_setting, od_max_setting;
1089
1090 switch (od_feature_bit) {
1091 case PP_OD_FEATURE_GFXCLK_FMIN:
1092 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1093 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1094 break;
1095 case PP_OD_FEATURE_GFXCLK_FMAX:
1096 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1097 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1098 break;
1099 case PP_OD_FEATURE_UCLK_FMIN:
1100 od_min_setting = overdrive_lowerlimits->UclkFmin;
1101 od_max_setting = overdrive_upperlimits->UclkFmin;
1102 break;
1103 case PP_OD_FEATURE_UCLK_FMAX:
1104 od_min_setting = overdrive_lowerlimits->UclkFmax;
1105 od_max_setting = overdrive_upperlimits->UclkFmax;
1106 break;
1107 case PP_OD_FEATURE_GFX_VF_CURVE:
1108 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1109 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1110 break;
1111 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1112 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1113 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1114 break;
1115 case PP_OD_FEATURE_FAN_CURVE_PWM:
1116 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1117 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1118 break;
1119 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1120 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1121 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1122 break;
1123 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1124 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1125 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1126 break;
1127 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1128 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1129 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1130 break;
1131 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1132 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1133 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1134 break;
1135 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1136 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1137 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1138 break;
1139 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1140 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1141 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1142 break;
1143 default:
1144 od_min_setting = od_max_setting = INT_MAX;
1145 break;
1146 }
1147
1148 if (min)
1149 *min = od_min_setting;
1150 if (max)
1151 *max = od_max_setting;
1152 }
1153
smu_v13_0_0_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1154 static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
1155 OverDriveTableExternal_t *od_table)
1156 {
1157 struct amdgpu_device *adev = smu->adev;
1158
1159 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1160 od_table->OverDriveTable.GfxclkFmax);
1161 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1162 od_table->OverDriveTable.UclkFmax);
1163 }
1164
smu_v13_0_0_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1165 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
1166 OverDriveTableExternal_t *od_table)
1167 {
1168 int ret = 0;
1169
1170 ret = smu_cmn_update_table(smu,
1171 SMU_TABLE_OVERDRIVE,
1172 0,
1173 (void *)od_table,
1174 false);
1175 if (ret)
1176 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1177
1178 return ret;
1179 }
1180
smu_v13_0_0_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1181 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
1182 OverDriveTableExternal_t *od_table)
1183 {
1184 int ret = 0;
1185
1186 ret = smu_cmn_update_table(smu,
1187 SMU_TABLE_OVERDRIVE,
1188 0,
1189 (void *)od_table,
1190 true);
1191 if (ret)
1192 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1193
1194 return ret;
1195 }
1196
smu_v13_0_0_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1197 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
1198 enum smu_clk_type clk_type,
1199 char *buf)
1200 {
1201 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1202 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1203 OverDriveTableExternal_t *od_table =
1204 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1205 struct smu_13_0_dpm_table *single_dpm_table;
1206 struct smu_13_0_pcie_table *pcie_table;
1207 uint32_t gen_speed, lane_width;
1208 int i, curr_freq, size = 0;
1209 int32_t min_value, max_value;
1210 int ret = 0;
1211
1212 smu_cmn_get_sysfs_buf(&buf, &size);
1213
1214 if (amdgpu_ras_intr_triggered()) {
1215 size += sysfs_emit_at(buf, size, "unavailable\n");
1216 return size;
1217 }
1218
1219 switch (clk_type) {
1220 case SMU_SCLK:
1221 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1222 break;
1223 case SMU_MCLK:
1224 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1225 break;
1226 case SMU_SOCCLK:
1227 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1228 break;
1229 case SMU_FCLK:
1230 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1231 break;
1232 case SMU_VCLK:
1233 case SMU_VCLK1:
1234 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1235 break;
1236 case SMU_DCLK:
1237 case SMU_DCLK1:
1238 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1239 break;
1240 case SMU_DCEFCLK:
1241 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1242 break;
1243 default:
1244 break;
1245 }
1246
1247 switch (clk_type) {
1248 case SMU_SCLK:
1249 case SMU_MCLK:
1250 case SMU_SOCCLK:
1251 case SMU_FCLK:
1252 case SMU_VCLK:
1253 case SMU_VCLK1:
1254 case SMU_DCLK:
1255 case SMU_DCLK1:
1256 case SMU_DCEFCLK:
1257 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1258 if (ret) {
1259 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1260 return ret;
1261 }
1262
1263 if (single_dpm_table->is_fine_grained) {
1264 /*
1265 * For fine grained dpms, there are only two dpm levels:
1266 * - level 0 -> min clock freq
1267 * - level 1 -> max clock freq
1268 * And the current clock frequency can be any value between them.
1269 * So, if the current clock frequency is not at level 0 or level 1,
1270 * we will fake it as three dpm levels:
1271 * - level 0 -> min clock freq
1272 * - level 1 -> current actual clock freq
1273 * - level 2 -> max clock freq
1274 */
1275 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1276 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1277 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1278 single_dpm_table->dpm_levels[0].value);
1279 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1280 curr_freq);
1281 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1282 single_dpm_table->dpm_levels[1].value);
1283 } else {
1284 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1285 single_dpm_table->dpm_levels[0].value,
1286 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1287 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1288 single_dpm_table->dpm_levels[1].value,
1289 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1290 }
1291 } else {
1292 for (i = 0; i < single_dpm_table->count; i++)
1293 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1294 i, single_dpm_table->dpm_levels[i].value,
1295 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1296 }
1297 break;
1298 case SMU_PCIE:
1299 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1300 METRICS_PCIE_RATE,
1301 &gen_speed);
1302 if (ret)
1303 return ret;
1304
1305 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1306 METRICS_PCIE_WIDTH,
1307 &lane_width);
1308 if (ret)
1309 return ret;
1310
1311 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1312 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1313 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1314 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1315 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1316 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1317 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1318 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1319 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1320 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1321 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1322 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1323 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1324 pcie_table->clk_freq[i],
1325 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1326 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1327 "*" : "");
1328 break;
1329
1330 case SMU_OD_SCLK:
1331 if (!smu_v13_0_0_is_od_feature_supported(smu,
1332 PP_OD_FEATURE_GFXCLK_BIT))
1333 break;
1334
1335 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1336 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1337 od_table->OverDriveTable.GfxclkFmin,
1338 od_table->OverDriveTable.GfxclkFmax);
1339 break;
1340
1341 case SMU_OD_MCLK:
1342 if (!smu_v13_0_0_is_od_feature_supported(smu,
1343 PP_OD_FEATURE_UCLK_BIT))
1344 break;
1345
1346 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1347 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1348 od_table->OverDriveTable.UclkFmin,
1349 od_table->OverDriveTable.UclkFmax);
1350 break;
1351
1352 case SMU_OD_VDDGFX_OFFSET:
1353 if (!smu_v13_0_0_is_od_feature_supported(smu,
1354 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1355 break;
1356
1357 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1358 size += sysfs_emit_at(buf, size, "%dmV\n",
1359 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1360 break;
1361
1362 case SMU_OD_FAN_CURVE:
1363 if (!smu_v13_0_0_is_od_feature_supported(smu,
1364 PP_OD_FEATURE_FAN_CURVE_BIT))
1365 break;
1366
1367 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1368 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1369 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1370 i,
1371 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1372 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1373
1374 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1375 smu_v13_0_0_get_od_setting_limits(smu,
1376 PP_OD_FEATURE_FAN_CURVE_TEMP,
1377 &min_value,
1378 &max_value);
1379 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1380 min_value, max_value);
1381
1382 smu_v13_0_0_get_od_setting_limits(smu,
1383 PP_OD_FEATURE_FAN_CURVE_PWM,
1384 &min_value,
1385 &max_value);
1386 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1387 min_value, max_value);
1388
1389 break;
1390
1391 case SMU_OD_ACOUSTIC_LIMIT:
1392 if (!smu_v13_0_0_is_od_feature_supported(smu,
1393 PP_OD_FEATURE_FAN_CURVE_BIT))
1394 break;
1395
1396 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1397 size += sysfs_emit_at(buf, size, "%d\n",
1398 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1399
1400 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1401 smu_v13_0_0_get_od_setting_limits(smu,
1402 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1403 &min_value,
1404 &max_value);
1405 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1406 min_value, max_value);
1407 break;
1408
1409 case SMU_OD_ACOUSTIC_TARGET:
1410 if (!smu_v13_0_0_is_od_feature_supported(smu,
1411 PP_OD_FEATURE_FAN_CURVE_BIT))
1412 break;
1413
1414 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1415 size += sysfs_emit_at(buf, size, "%d\n",
1416 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1417
1418 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1419 smu_v13_0_0_get_od_setting_limits(smu,
1420 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1421 &min_value,
1422 &max_value);
1423 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1424 min_value, max_value);
1425 break;
1426
1427 case SMU_OD_FAN_TARGET_TEMPERATURE:
1428 if (!smu_v13_0_0_is_od_feature_supported(smu,
1429 PP_OD_FEATURE_FAN_CURVE_BIT))
1430 break;
1431
1432 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1433 size += sysfs_emit_at(buf, size, "%d\n",
1434 (int)od_table->OverDriveTable.FanTargetTemperature);
1435
1436 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1437 smu_v13_0_0_get_od_setting_limits(smu,
1438 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1439 &min_value,
1440 &max_value);
1441 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1442 min_value, max_value);
1443 break;
1444
1445 case SMU_OD_FAN_MINIMUM_PWM:
1446 if (!smu_v13_0_0_is_od_feature_supported(smu,
1447 PP_OD_FEATURE_FAN_CURVE_BIT))
1448 break;
1449
1450 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1451 size += sysfs_emit_at(buf, size, "%d\n",
1452 (int)od_table->OverDriveTable.FanMinimumPwm);
1453
1454 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1455 smu_v13_0_0_get_od_setting_limits(smu,
1456 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1457 &min_value,
1458 &max_value);
1459 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1460 min_value, max_value);
1461 break;
1462
1463 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1464 if (!smu_v13_0_0_is_od_feature_supported(smu,
1465 PP_OD_FEATURE_ZERO_FAN_BIT))
1466 break;
1467
1468 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1469 size += sysfs_emit_at(buf, size, "%d\n",
1470 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1471
1472 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1473 smu_v13_0_0_get_od_setting_limits(smu,
1474 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1475 &min_value,
1476 &max_value);
1477 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1478 min_value, max_value);
1479 break;
1480
1481 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1482 if (!smu_v13_0_0_is_od_feature_supported(smu,
1483 PP_OD_FEATURE_ZERO_FAN_BIT))
1484 break;
1485
1486 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1487 size += sysfs_emit_at(buf, size, "%d\n",
1488 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1489
1490 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1491 smu_v13_0_0_get_od_setting_limits(smu,
1492 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1493 &min_value,
1494 &max_value);
1495 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1496 min_value, max_value);
1497 break;
1498
1499 case SMU_OD_RANGE:
1500 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1501 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1502 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1503 break;
1504
1505 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1506
1507 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1508 smu_v13_0_0_get_od_setting_limits(smu,
1509 PP_OD_FEATURE_GFXCLK_FMIN,
1510 &min_value,
1511 NULL);
1512 smu_v13_0_0_get_od_setting_limits(smu,
1513 PP_OD_FEATURE_GFXCLK_FMAX,
1514 NULL,
1515 &max_value);
1516 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1517 min_value, max_value);
1518 }
1519
1520 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1521 smu_v13_0_0_get_od_setting_limits(smu,
1522 PP_OD_FEATURE_UCLK_FMIN,
1523 &min_value,
1524 NULL);
1525 smu_v13_0_0_get_od_setting_limits(smu,
1526 PP_OD_FEATURE_UCLK_FMAX,
1527 NULL,
1528 &max_value);
1529 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1530 min_value, max_value);
1531 }
1532
1533 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1534 smu_v13_0_0_get_od_setting_limits(smu,
1535 PP_OD_FEATURE_GFX_VF_CURVE,
1536 &min_value,
1537 &max_value);
1538 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1539 min_value, max_value);
1540 }
1541 break;
1542
1543 default:
1544 break;
1545 }
1546
1547 return size;
1548 }
1549
1550
smu_v13_0_0_od_restore_table_single(struct smu_context * smu,long input)1551 static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input)
1552 {
1553 struct smu_table_context *table_context = &smu->smu_table;
1554 OverDriveTableExternal_t *boot_overdrive_table =
1555 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1556 OverDriveTableExternal_t *od_table =
1557 (OverDriveTableExternal_t *)table_context->overdrive_table;
1558 struct amdgpu_device *adev = smu->adev;
1559 int i;
1560
1561 switch (input) {
1562 case PP_OD_EDIT_FAN_CURVE:
1563 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1564 od_table->OverDriveTable.FanLinearTempPoints[i] =
1565 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1566 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1567 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1568 }
1569 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1570 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1571 break;
1572 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1573 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1574 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1575 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1576 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1577 break;
1578 case PP_OD_EDIT_ACOUSTIC_TARGET:
1579 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1580 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1581 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1582 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1583 break;
1584 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1585 od_table->OverDriveTable.FanTargetTemperature =
1586 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1587 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1588 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1589 break;
1590 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1591 od_table->OverDriveTable.FanMinimumPwm =
1592 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1593 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1594 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1595 break;
1596 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1597 od_table->OverDriveTable.FanZeroRpmEnable =
1598 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1599 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1600 break;
1601 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1602 od_table->OverDriveTable.FanZeroRpmStopTemp =
1603 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1604 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1605 break;
1606 default:
1607 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1608 return -EINVAL;
1609 }
1610
1611 return 0;
1612 }
1613
smu_v13_0_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1614 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
1615 enum PP_OD_DPM_TABLE_COMMAND type,
1616 long input[],
1617 uint32_t size)
1618 {
1619 struct smu_table_context *table_context = &smu->smu_table;
1620 OverDriveTableExternal_t *od_table =
1621 (OverDriveTableExternal_t *)table_context->overdrive_table;
1622 struct amdgpu_device *adev = smu->adev;
1623 uint32_t offset_of_voltageoffset;
1624 int32_t minimum, maximum;
1625 uint32_t feature_ctrlmask;
1626 int i, ret = 0;
1627
1628 switch (type) {
1629 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1630 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1631 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1632 return -ENOTSUPP;
1633 }
1634
1635 for (i = 0; i < size; i += 2) {
1636 if (i + 2 > size) {
1637 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1638 return -EINVAL;
1639 }
1640
1641 switch (input[i]) {
1642 case 0:
1643 smu_v13_0_0_get_od_setting_limits(smu,
1644 PP_OD_FEATURE_GFXCLK_FMIN,
1645 &minimum,
1646 &maximum);
1647 if (input[i + 1] < minimum ||
1648 input[i + 1] > maximum) {
1649 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1650 input[i + 1], minimum, maximum);
1651 return -EINVAL;
1652 }
1653
1654 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1655 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1656 break;
1657
1658 case 1:
1659 smu_v13_0_0_get_od_setting_limits(smu,
1660 PP_OD_FEATURE_GFXCLK_FMAX,
1661 &minimum,
1662 &maximum);
1663 if (input[i + 1] < minimum ||
1664 input[i + 1] > maximum) {
1665 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1666 input[i + 1], minimum, maximum);
1667 return -EINVAL;
1668 }
1669
1670 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1671 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1672 break;
1673
1674 default:
1675 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1676 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1677 return -EINVAL;
1678 }
1679 }
1680
1681 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1682 dev_err(adev->dev,
1683 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1684 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1685 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1686 return -EINVAL;
1687 }
1688 break;
1689
1690 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1691 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1692 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1693 return -ENOTSUPP;
1694 }
1695
1696 for (i = 0; i < size; i += 2) {
1697 if (i + 2 > size) {
1698 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1699 return -EINVAL;
1700 }
1701
1702 switch (input[i]) {
1703 case 0:
1704 smu_v13_0_0_get_od_setting_limits(smu,
1705 PP_OD_FEATURE_UCLK_FMIN,
1706 &minimum,
1707 &maximum);
1708 if (input[i + 1] < minimum ||
1709 input[i + 1] > maximum) {
1710 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1711 input[i + 1], minimum, maximum);
1712 return -EINVAL;
1713 }
1714
1715 od_table->OverDriveTable.UclkFmin = input[i + 1];
1716 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1717 break;
1718
1719 case 1:
1720 smu_v13_0_0_get_od_setting_limits(smu,
1721 PP_OD_FEATURE_UCLK_FMAX,
1722 &minimum,
1723 &maximum);
1724 if (input[i + 1] < minimum ||
1725 input[i + 1] > maximum) {
1726 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1727 input[i + 1], minimum, maximum);
1728 return -EINVAL;
1729 }
1730
1731 od_table->OverDriveTable.UclkFmax = input[i + 1];
1732 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1733 break;
1734
1735 default:
1736 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1737 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1738 return -EINVAL;
1739 }
1740 }
1741
1742 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1743 dev_err(adev->dev,
1744 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1745 (uint32_t)od_table->OverDriveTable.UclkFmin,
1746 (uint32_t)od_table->OverDriveTable.UclkFmax);
1747 return -EINVAL;
1748 }
1749 break;
1750
1751 case PP_OD_EDIT_VDDGFX_OFFSET:
1752 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1753 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1754 return -ENOTSUPP;
1755 }
1756
1757 smu_v13_0_0_get_od_setting_limits(smu,
1758 PP_OD_FEATURE_GFX_VF_CURVE,
1759 &minimum,
1760 &maximum);
1761 if (input[0] < minimum ||
1762 input[0] > maximum) {
1763 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1764 input[0], minimum, maximum);
1765 return -EINVAL;
1766 }
1767
1768 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1769 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1770 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1771 break;
1772
1773 case PP_OD_EDIT_FAN_CURVE:
1774 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1775 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1776 return -ENOTSUPP;
1777 }
1778
1779 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1780 input[0] < 0)
1781 return -EINVAL;
1782
1783 smu_v13_0_0_get_od_setting_limits(smu,
1784 PP_OD_FEATURE_FAN_CURVE_TEMP,
1785 &minimum,
1786 &maximum);
1787 if (input[1] < minimum ||
1788 input[1] > maximum) {
1789 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1790 input[1], minimum, maximum);
1791 return -EINVAL;
1792 }
1793
1794 smu_v13_0_0_get_od_setting_limits(smu,
1795 PP_OD_FEATURE_FAN_CURVE_PWM,
1796 &minimum,
1797 &maximum);
1798 if (input[2] < minimum ||
1799 input[2] > maximum) {
1800 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1801 input[2], minimum, maximum);
1802 return -EINVAL;
1803 }
1804
1805 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1806 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1807 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1808 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1809 break;
1810
1811 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1812 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1813 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1814 return -ENOTSUPP;
1815 }
1816
1817 smu_v13_0_0_get_od_setting_limits(smu,
1818 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1819 &minimum,
1820 &maximum);
1821 if (input[0] < minimum ||
1822 input[0] > maximum) {
1823 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1824 input[0], minimum, maximum);
1825 return -EINVAL;
1826 }
1827
1828 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1829 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1830 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1831 break;
1832
1833 case PP_OD_EDIT_ACOUSTIC_TARGET:
1834 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1835 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1836 return -ENOTSUPP;
1837 }
1838
1839 smu_v13_0_0_get_od_setting_limits(smu,
1840 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1841 &minimum,
1842 &maximum);
1843 if (input[0] < minimum ||
1844 input[0] > maximum) {
1845 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1846 input[0], minimum, maximum);
1847 return -EINVAL;
1848 }
1849
1850 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1851 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1852 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1853 break;
1854
1855 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1856 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1857 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1858 return -ENOTSUPP;
1859 }
1860
1861 smu_v13_0_0_get_od_setting_limits(smu,
1862 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1863 &minimum,
1864 &maximum);
1865 if (input[0] < minimum ||
1866 input[0] > maximum) {
1867 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1868 input[0], minimum, maximum);
1869 return -EINVAL;
1870 }
1871
1872 od_table->OverDriveTable.FanTargetTemperature = input[0];
1873 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1874 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1875 break;
1876
1877 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1878 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1879 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1880 return -ENOTSUPP;
1881 }
1882
1883 smu_v13_0_0_get_od_setting_limits(smu,
1884 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1885 &minimum,
1886 &maximum);
1887 if (input[0] < minimum ||
1888 input[0] > maximum) {
1889 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1890 input[0], minimum, maximum);
1891 return -EINVAL;
1892 }
1893
1894 od_table->OverDriveTable.FanMinimumPwm = input[0];
1895 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1896 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1897 break;
1898
1899 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1900 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1901 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1902 return -ENOTSUPP;
1903 }
1904
1905 smu_v13_0_0_get_od_setting_limits(smu,
1906 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1907 &minimum,
1908 &maximum);
1909 if (input[0] < minimum ||
1910 input[0] > maximum) {
1911 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1912 input[0], minimum, maximum);
1913 return -EINVAL;
1914 }
1915
1916 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1917 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1918 break;
1919
1920 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1921 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1922 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1923 return -ENOTSUPP;
1924 }
1925
1926 smu_v13_0_0_get_od_setting_limits(smu,
1927 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1928 &minimum,
1929 &maximum);
1930 if (input[0] < minimum ||
1931 input[0] > maximum) {
1932 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1933 input[0], minimum, maximum);
1934 return -EINVAL;
1935 }
1936
1937 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1938 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1939 break;
1940
1941 case PP_OD_RESTORE_DEFAULT_TABLE:
1942 if (size == 1) {
1943 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]);
1944 if (ret)
1945 return ret;
1946 } else {
1947 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1948 memcpy(od_table,
1949 table_context->boot_overdrive_table,
1950 sizeof(OverDriveTableExternal_t));
1951 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1952 }
1953 fallthrough;
1954 case PP_OD_COMMIT_DPM_TABLE:
1955 /*
1956 * The member below instructs PMFW the settings focused in
1957 * this single operation.
1958 * `uint32_t FeatureCtrlMask;`
1959 * It does not contain actual informations about user's custom
1960 * settings. Thus we do not cache it.
1961 */
1962 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1963 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1964 table_context->user_overdrive_table + offset_of_voltageoffset,
1965 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1966 smu_v13_0_0_dump_od_table(smu, od_table);
1967
1968 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
1969 if (ret) {
1970 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1971 return ret;
1972 }
1973
1974 od_table->OverDriveTable.FeatureCtrlMask = 0;
1975 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1976 (u8 *)od_table + offset_of_voltageoffset,
1977 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1978
1979 if (!memcmp(table_context->user_overdrive_table,
1980 table_context->boot_overdrive_table,
1981 sizeof(OverDriveTableExternal_t)))
1982 smu->user_dpm_profile.user_od = false;
1983 else
1984 smu->user_dpm_profile.user_od = true;
1985 }
1986 break;
1987
1988 default:
1989 return -ENOSYS;
1990 }
1991
1992 return ret;
1993 }
1994
smu_v13_0_0_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1995 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1996 enum smu_clk_type clk_type,
1997 uint32_t mask)
1998 {
1999 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2000 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2001 struct smu_13_0_dpm_table *single_dpm_table;
2002 uint32_t soft_min_level, soft_max_level;
2003 uint32_t min_freq, max_freq;
2004 int ret = 0;
2005
2006 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2007 soft_max_level = mask ? (fls(mask) - 1) : 0;
2008
2009 switch (clk_type) {
2010 case SMU_GFXCLK:
2011 case SMU_SCLK:
2012 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
2013 break;
2014 case SMU_MCLK:
2015 case SMU_UCLK:
2016 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
2017 break;
2018 case SMU_SOCCLK:
2019 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
2020 break;
2021 case SMU_FCLK:
2022 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
2023 break;
2024 case SMU_VCLK:
2025 case SMU_VCLK1:
2026 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
2027 break;
2028 case SMU_DCLK:
2029 case SMU_DCLK1:
2030 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
2031 break;
2032 default:
2033 break;
2034 }
2035
2036 switch (clk_type) {
2037 case SMU_GFXCLK:
2038 case SMU_SCLK:
2039 case SMU_MCLK:
2040 case SMU_UCLK:
2041 case SMU_SOCCLK:
2042 case SMU_FCLK:
2043 case SMU_VCLK:
2044 case SMU_VCLK1:
2045 case SMU_DCLK:
2046 case SMU_DCLK1:
2047 if (single_dpm_table->is_fine_grained) {
2048 /* There is only 2 levels for fine grained DPM */
2049 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2050 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2051 } else {
2052 if ((soft_max_level >= single_dpm_table->count) ||
2053 (soft_min_level >= single_dpm_table->count))
2054 return -EINVAL;
2055 }
2056
2057 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2058 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2059
2060 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2061 clk_type,
2062 min_freq,
2063 max_freq,
2064 false);
2065 break;
2066 case SMU_DCEFCLK:
2067 case SMU_PCIE:
2068 default:
2069 break;
2070 }
2071
2072 return ret;
2073 }
2074
2075 static const struct smu_temperature_range smu13_thermal_policy[] = {
2076 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2077 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2078 };
2079
smu_v13_0_0_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2080 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
2081 struct smu_temperature_range *range)
2082 {
2083 struct smu_table_context *table_context = &smu->smu_table;
2084 struct smu_13_0_0_powerplay_table *powerplay_table =
2085 table_context->power_play_table;
2086 PPTable_t *pptable = smu->smu_table.driver_pptable;
2087
2088 if (amdgpu_sriov_vf(smu->adev))
2089 return 0;
2090
2091 if (!range)
2092 return -EINVAL;
2093
2094 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2095
2096 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2097 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2098 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2099 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2100 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2101 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2102 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2103 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2104 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2105 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2106 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2107 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2108 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2109 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2110
2111 return 0;
2112 }
2113
smu_v13_0_0_get_gpu_metrics(struct smu_context * smu,void ** table)2114 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
2115 void **table)
2116 {
2117 struct smu_table_context *smu_table = &smu->smu_table;
2118 struct gpu_metrics_v1_3 *gpu_metrics =
2119 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2120 SmuMetricsExternal_t metrics_ext;
2121 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2122 int ret = 0;
2123
2124 ret = smu_cmn_get_metrics_table(smu,
2125 &metrics_ext,
2126 true);
2127 if (ret)
2128 return ret;
2129
2130 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2131
2132 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2133 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2134 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2135 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2136 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2137 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2138 metrics->AvgTemperature[TEMP_VR_MEM1]);
2139
2140 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2141 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2142 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2143 metrics->Vcn1ActivityPercentage);
2144
2145 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2146 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2147
2148 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2149 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2150 else
2151 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2152
2153 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2154 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2155 else
2156 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2157
2158 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2159 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2160 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2161 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2162
2163 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2164 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2165 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2166 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2167 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2168 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2169 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2170
2171 gpu_metrics->throttle_status =
2172 smu_v13_0_get_throttler_status(metrics);
2173 gpu_metrics->indep_throttle_status =
2174 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2175 smu_v13_0_0_throttler_map);
2176
2177 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2178
2179 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2180 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2181 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2182 else
2183 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2184
2185 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2186
2187 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2188 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2189 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2190
2191 *table = (void *)gpu_metrics;
2192
2193 return sizeof(struct gpu_metrics_v1_3);
2194 }
2195
smu_v13_0_0_set_supported_od_feature_mask(struct smu_context * smu)2196 static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu)
2197 {
2198 struct amdgpu_device *adev = smu->adev;
2199
2200 if (smu_v13_0_0_is_od_feature_supported(smu,
2201 PP_OD_FEATURE_FAN_CURVE_BIT))
2202 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2203 OD_OPS_SUPPORT_FAN_CURVE_SET |
2204 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2205 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2206 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2207 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2208 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2209 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2210 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2211 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2212 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2213 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2214 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2215 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2216 }
2217
smu_v13_0_0_set_default_od_settings(struct smu_context * smu)2218 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu)
2219 {
2220 OverDriveTableExternal_t *od_table =
2221 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2222 OverDriveTableExternal_t *boot_od_table =
2223 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2224 OverDriveTableExternal_t *user_od_table =
2225 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2226 OverDriveTableExternal_t user_od_table_bak;
2227 int ret = 0;
2228 int i;
2229
2230 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table);
2231 if (ret)
2232 return ret;
2233
2234 smu_v13_0_0_dump_od_table(smu, boot_od_table);
2235
2236 memcpy(od_table,
2237 boot_od_table,
2238 sizeof(OverDriveTableExternal_t));
2239
2240 /*
2241 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2242 * but we have to preserve user defined values in "user_od_table".
2243 */
2244 if (!smu->adev->in_suspend) {
2245 memcpy(user_od_table,
2246 boot_od_table,
2247 sizeof(OverDriveTableExternal_t));
2248 smu->user_dpm_profile.user_od = false;
2249 } else if (smu->user_dpm_profile.user_od) {
2250 memcpy(&user_od_table_bak,
2251 user_od_table,
2252 sizeof(OverDriveTableExternal_t));
2253 memcpy(user_od_table,
2254 boot_od_table,
2255 sizeof(OverDriveTableExternal_t));
2256 user_od_table->OverDriveTable.GfxclkFmin =
2257 user_od_table_bak.OverDriveTable.GfxclkFmin;
2258 user_od_table->OverDriveTable.GfxclkFmax =
2259 user_od_table_bak.OverDriveTable.GfxclkFmax;
2260 user_od_table->OverDriveTable.UclkFmin =
2261 user_od_table_bak.OverDriveTable.UclkFmin;
2262 user_od_table->OverDriveTable.UclkFmax =
2263 user_od_table_bak.OverDriveTable.UclkFmax;
2264 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2265 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2266 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2267 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2268 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2269 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2270 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2271 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2272 }
2273 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2274 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2275 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2276 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2277 user_od_table->OverDriveTable.FanTargetTemperature =
2278 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2279 user_od_table->OverDriveTable.FanMinimumPwm =
2280 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2281 user_od_table->OverDriveTable.FanZeroRpmEnable =
2282 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2283 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2284 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2285 }
2286
2287 smu_v13_0_0_set_supported_od_feature_mask(smu);
2288
2289 return 0;
2290 }
2291
smu_v13_0_0_restore_user_od_settings(struct smu_context * smu)2292 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu)
2293 {
2294 struct smu_table_context *table_context = &smu->smu_table;
2295 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2296 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2297 int res;
2298
2299 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2300 BIT(PP_OD_FEATURE_UCLK_BIT) |
2301 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2302 BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2303 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table);
2304 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2305 if (res == 0)
2306 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2307
2308 return res;
2309 }
2310
smu_v13_0_0_populate_umd_state_clk(struct smu_context * smu)2311 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
2312 {
2313 struct smu_13_0_dpm_context *dpm_context =
2314 smu->smu_dpm.dpm_context;
2315 struct smu_13_0_dpm_table *gfx_table =
2316 &dpm_context->dpm_tables.gfx_table;
2317 struct smu_13_0_dpm_table *mem_table =
2318 &dpm_context->dpm_tables.uclk_table;
2319 struct smu_13_0_dpm_table *soc_table =
2320 &dpm_context->dpm_tables.soc_table;
2321 struct smu_13_0_dpm_table *vclk_table =
2322 &dpm_context->dpm_tables.vclk_table;
2323 struct smu_13_0_dpm_table *dclk_table =
2324 &dpm_context->dpm_tables.dclk_table;
2325 struct smu_13_0_dpm_table *fclk_table =
2326 &dpm_context->dpm_tables.fclk_table;
2327 struct smu_umd_pstate_table *pstate_table =
2328 &smu->pstate_table;
2329 struct smu_table_context *table_context = &smu->smu_table;
2330 PPTable_t *pptable = table_context->driver_pptable;
2331 DriverReportedClocks_t driver_clocks =
2332 pptable->SkuTable.DriverReportedClocks;
2333
2334 pstate_table->gfxclk_pstate.min = gfx_table->min;
2335 if (driver_clocks.GameClockAc &&
2336 (driver_clocks.GameClockAc < gfx_table->max))
2337 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2338 else
2339 pstate_table->gfxclk_pstate.peak = gfx_table->max;
2340
2341 pstate_table->uclk_pstate.min = mem_table->min;
2342 pstate_table->uclk_pstate.peak = mem_table->max;
2343
2344 pstate_table->socclk_pstate.min = soc_table->min;
2345 pstate_table->socclk_pstate.peak = soc_table->max;
2346
2347 pstate_table->vclk_pstate.min = vclk_table->min;
2348 pstate_table->vclk_pstate.peak = vclk_table->max;
2349
2350 pstate_table->dclk_pstate.min = dclk_table->min;
2351 pstate_table->dclk_pstate.peak = dclk_table->max;
2352
2353 pstate_table->fclk_pstate.min = fclk_table->min;
2354 pstate_table->fclk_pstate.peak = fclk_table->max;
2355
2356 if (driver_clocks.BaseClockAc &&
2357 driver_clocks.BaseClockAc < gfx_table->max)
2358 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2359 else
2360 pstate_table->gfxclk_pstate.standard = gfx_table->max;
2361 pstate_table->uclk_pstate.standard = mem_table->max;
2362 pstate_table->socclk_pstate.standard = soc_table->min;
2363 pstate_table->vclk_pstate.standard = vclk_table->min;
2364 pstate_table->dclk_pstate.standard = dclk_table->min;
2365 pstate_table->fclk_pstate.standard = fclk_table->min;
2366
2367 return 0;
2368 }
2369
smu_v13_0_0_get_unique_id(struct smu_context * smu)2370 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
2371 {
2372 struct smu_table_context *smu_table = &smu->smu_table;
2373 SmuMetrics_t *metrics =
2374 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
2375 struct amdgpu_device *adev = smu->adev;
2376 uint32_t upper32 = 0, lower32 = 0;
2377 int ret;
2378
2379 ret = smu_cmn_get_metrics_table(smu, NULL, false);
2380 if (ret)
2381 goto out;
2382
2383 upper32 = metrics->PublicSerialNumberUpper;
2384 lower32 = metrics->PublicSerialNumberLower;
2385
2386 out:
2387 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2388 }
2389
smu_v13_0_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2390 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
2391 uint32_t *speed)
2392 {
2393 int ret;
2394
2395 if (!speed)
2396 return -EINVAL;
2397
2398 ret = smu_v13_0_0_get_smu_metrics_data(smu,
2399 METRICS_CURR_FANPWM,
2400 speed);
2401 if (ret) {
2402 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2403 return ret;
2404 }
2405
2406 /* Convert the PMFW output which is in percent to pwm(255) based */
2407 *speed = min(*speed * 255 / 100, (uint32_t)255);
2408
2409 return 0;
2410 }
2411
smu_v13_0_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2412 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
2413 uint32_t *speed)
2414 {
2415 if (!speed)
2416 return -EINVAL;
2417
2418 return smu_v13_0_0_get_smu_metrics_data(smu,
2419 METRICS_CURR_FANSPEED,
2420 speed);
2421 }
2422
smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context * smu)2423 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
2424 {
2425 struct smu_table_context *table_context = &smu->smu_table;
2426 PPTable_t *pptable = table_context->driver_pptable;
2427 SkuTable_t *skutable = &pptable->SkuTable;
2428
2429 /*
2430 * Skip the MGpuFanBoost setting for those ASICs
2431 * which do not support it
2432 */
2433 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2434 return 0;
2435
2436 return smu_cmn_send_smc_msg_with_param(smu,
2437 SMU_MSG_SetMGpuFanBoostLimitRpm,
2438 0,
2439 NULL);
2440 }
2441
smu_v13_0_0_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2442 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
2443 uint32_t *current_power_limit,
2444 uint32_t *default_power_limit,
2445 uint32_t *max_power_limit,
2446 uint32_t *min_power_limit)
2447 {
2448 struct smu_table_context *table_context = &smu->smu_table;
2449 struct smu_13_0_0_powerplay_table *powerplay_table =
2450 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
2451 PPTable_t *pptable = table_context->driver_pptable;
2452 SkuTable_t *skutable = &pptable->SkuTable;
2453 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2454 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2455
2456 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2457 power_limit = smu->adev->pm.ac_power ?
2458 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2459 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2460
2461 if (current_power_limit)
2462 *current_power_limit = power_limit;
2463 if (default_power_limit)
2464 *default_power_limit = power_limit;
2465
2466 if (powerplay_table) {
2467 if (smu->od_enabled &&
2468 smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2469 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2470 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2471 } else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2472 od_percent_upper = 0;
2473 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2474 }
2475 }
2476
2477 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2478 od_percent_upper, od_percent_lower, power_limit);
2479
2480 if (max_power_limit) {
2481 *max_power_limit = msg_limit * (100 + od_percent_upper);
2482 *max_power_limit /= 100;
2483 }
2484
2485 if (min_power_limit) {
2486 *min_power_limit = power_limit * (100 - od_percent_lower);
2487 *min_power_limit /= 100;
2488 }
2489
2490 return 0;
2491 }
2492
smu_v13_0_0_get_power_profile_mode(struct smu_context * smu,char * buf)2493 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
2494 char *buf)
2495 {
2496 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2497 DpmActivityMonitorCoeffInt_t *activity_monitor =
2498 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2499 static const char *title[] = {
2500 "PROFILE_INDEX(NAME)",
2501 "CLOCK_TYPE(NAME)",
2502 "FPS",
2503 "MinActiveFreqType",
2504 "MinActiveFreq",
2505 "BoosterFreqType",
2506 "BoosterFreq",
2507 "PD_Data_limit_c",
2508 "PD_Data_error_coeff",
2509 "PD_Data_error_rate_coeff"};
2510 int16_t workload_type = 0;
2511 uint32_t i, size = 0;
2512 int result = 0;
2513
2514 if (!buf)
2515 return -EINVAL;
2516
2517 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
2518 title[0], title[1], title[2], title[3], title[4], title[5],
2519 title[6], title[7], title[8], title[9]);
2520
2521 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2522 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2523 workload_type = smu_cmn_to_asic_specific_index(smu,
2524 CMN2ASIC_MAPPING_WORKLOAD,
2525 i);
2526 if (workload_type == -ENOTSUPP)
2527 continue;
2528 else if (workload_type < 0)
2529 return -EINVAL;
2530
2531 result = smu_cmn_update_table(smu,
2532 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2533 workload_type,
2534 (void *)(&activity_monitor_external),
2535 false);
2536 if (result) {
2537 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2538 return result;
2539 }
2540
2541 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
2542 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
2543
2544 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2545 " ",
2546 0,
2547 "GFXCLK",
2548 activity_monitor->Gfx_FPS,
2549 activity_monitor->Gfx_MinActiveFreqType,
2550 activity_monitor->Gfx_MinActiveFreq,
2551 activity_monitor->Gfx_BoosterFreqType,
2552 activity_monitor->Gfx_BoosterFreq,
2553 activity_monitor->Gfx_PD_Data_limit_c,
2554 activity_monitor->Gfx_PD_Data_error_coeff,
2555 activity_monitor->Gfx_PD_Data_error_rate_coeff);
2556
2557 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2558 " ",
2559 1,
2560 "FCLK",
2561 activity_monitor->Fclk_FPS,
2562 activity_monitor->Fclk_MinActiveFreqType,
2563 activity_monitor->Fclk_MinActiveFreq,
2564 activity_monitor->Fclk_BoosterFreqType,
2565 activity_monitor->Fclk_BoosterFreq,
2566 activity_monitor->Fclk_PD_Data_limit_c,
2567 activity_monitor->Fclk_PD_Data_error_coeff,
2568 activity_monitor->Fclk_PD_Data_error_rate_coeff);
2569 }
2570
2571 return size;
2572 }
2573
2574 #define SMU_13_0_0_CUSTOM_PARAMS_COUNT 9
2575 #define SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT 2
2576 #define SMU_13_0_0_CUSTOM_PARAMS_SIZE (SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_0_CUSTOM_PARAMS_COUNT * sizeof(long))
2577
smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2578 static int smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context *smu,
2579 long *input)
2580 {
2581 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2582 DpmActivityMonitorCoeffInt_t *activity_monitor =
2583 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2584 int ret, idx;
2585
2586 ret = smu_cmn_update_table(smu,
2587 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2588 WORKLOAD_PPLIB_CUSTOM_BIT,
2589 (void *)(&activity_monitor_external),
2590 false);
2591 if (ret) {
2592 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2593 return ret;
2594 }
2595
2596 idx = 0 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2597 if (input[idx]) {
2598 /* Gfxclk */
2599 activity_monitor->Gfx_FPS = input[idx + 1];
2600 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2];
2601 activity_monitor->Gfx_MinActiveFreq = input[idx + 3];
2602 activity_monitor->Gfx_BoosterFreqType = input[idx + 4];
2603 activity_monitor->Gfx_BoosterFreq = input[idx + 5];
2604 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6];
2605 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7];
2606 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8];
2607 }
2608 idx = 1 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2609 if (input[idx]) {
2610 /* Fclk */
2611 activity_monitor->Fclk_FPS = input[idx + 1];
2612 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2];
2613 activity_monitor->Fclk_MinActiveFreq = input[idx + 3];
2614 activity_monitor->Fclk_BoosterFreqType = input[idx + 4];
2615 activity_monitor->Fclk_BoosterFreq = input[idx + 5];
2616 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6];
2617 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7];
2618 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8];
2619 }
2620
2621 ret = smu_cmn_update_table(smu,
2622 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2623 WORKLOAD_PPLIB_CUSTOM_BIT,
2624 (void *)(&activity_monitor_external),
2625 true);
2626 if (ret) {
2627 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2628 return ret;
2629 }
2630
2631 return ret;
2632 }
2633
smu_v13_0_0_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2634 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
2635 u32 workload_mask,
2636 long *custom_params,
2637 u32 custom_params_max_idx)
2638 {
2639 u32 backend_workload_mask = 0;
2640 int workload_type, ret, idx = -1, i;
2641
2642 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2643 &backend_workload_mask);
2644
2645 /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
2646 if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) &&
2647 ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2648 ((smu->adev->pm.fw_version == 0x004e6601) ||
2649 (smu->adev->pm.fw_version >= 0x004e7300))) ||
2650 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2651 smu->adev->pm.fw_version >= 0x00504500))) {
2652 workload_type = smu_cmn_to_asic_specific_index(smu,
2653 CMN2ASIC_MAPPING_WORKLOAD,
2654 PP_SMC_POWER_PROFILE_POWERSAVING);
2655 if (workload_type >= 0)
2656 backend_workload_mask |= 1 << workload_type;
2657 }
2658
2659 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2660 if (!smu->custom_profile_params) {
2661 smu->custom_profile_params =
2662 kzalloc(SMU_13_0_0_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2663 if (!smu->custom_profile_params)
2664 return -ENOMEM;
2665 }
2666 if (custom_params && custom_params_max_idx) {
2667 if (custom_params_max_idx != SMU_13_0_0_CUSTOM_PARAMS_COUNT)
2668 return -EINVAL;
2669 if (custom_params[0] >= SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT)
2670 return -EINVAL;
2671 idx = custom_params[0] * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2672 smu->custom_profile_params[idx] = 1;
2673 for (i = 1; i < custom_params_max_idx; i++)
2674 smu->custom_profile_params[idx + i] = custom_params[i];
2675 }
2676 ret = smu_v13_0_0_set_power_profile_mode_coeff(smu,
2677 smu->custom_profile_params);
2678 if (ret) {
2679 if (idx != -1)
2680 smu->custom_profile_params[idx] = 0;
2681 return ret;
2682 }
2683 } else if (smu->custom_profile_params) {
2684 memset(smu->custom_profile_params, 0, SMU_13_0_0_CUSTOM_PARAMS_SIZE);
2685 }
2686
2687 ret = smu_cmn_send_smc_msg_with_param(smu,
2688 SMU_MSG_SetWorkloadMask,
2689 backend_workload_mask,
2690 NULL);
2691 if (ret) {
2692 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2693 workload_mask);
2694 if (idx != -1)
2695 smu->custom_profile_params[idx] = 0;
2696 return ret;
2697 }
2698
2699 return ret;
2700 }
2701
smu_v13_0_0_is_mode1_reset_supported(struct smu_context * smu)2702 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
2703 {
2704 struct amdgpu_device *adev = smu->adev;
2705 u32 smu_version;
2706 int ret;
2707
2708 /* SRIOV does not support SMU mode1 reset */
2709 if (amdgpu_sriov_vf(adev))
2710 return false;
2711
2712 /* PMFW support is available since 78.41 */
2713 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2714 if (ret)
2715 return false;
2716
2717 if (smu_version < 0x004e2900)
2718 return false;
2719
2720 return true;
2721 }
2722
smu_v13_0_0_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2723 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
2724 struct i2c_msg *msg, int num_msgs)
2725 {
2726 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2727 struct amdgpu_device *adev = smu_i2c->adev;
2728 struct smu_context *smu = adev->powerplay.pp_handle;
2729 struct smu_table_context *smu_table = &smu->smu_table;
2730 struct smu_table *table = &smu_table->driver_table;
2731 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2732 int i, j, r, c;
2733 u16 dir;
2734
2735 if (!adev->pm.dpm_enabled)
2736 return -EBUSY;
2737
2738 req = kzalloc(sizeof(*req), GFP_KERNEL);
2739 if (!req)
2740 return -ENOMEM;
2741
2742 req->I2CcontrollerPort = smu_i2c->port;
2743 req->I2CSpeed = I2C_SPEED_FAST_400K;
2744 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2745 dir = msg[0].flags & I2C_M_RD;
2746
2747 for (c = i = 0; i < num_msgs; i++) {
2748 for (j = 0; j < msg[i].len; j++, c++) {
2749 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2750
2751 if (!(msg[i].flags & I2C_M_RD)) {
2752 /* write */
2753 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2754 cmd->ReadWriteData = msg[i].buf[j];
2755 }
2756
2757 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2758 /* The direction changes.
2759 */
2760 dir = msg[i].flags & I2C_M_RD;
2761 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2762 }
2763
2764 req->NumCmds++;
2765
2766 /*
2767 * Insert STOP if we are at the last byte of either last
2768 * message for the transaction or the client explicitly
2769 * requires a STOP at this particular message.
2770 */
2771 if ((j == msg[i].len - 1) &&
2772 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2773 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2774 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2775 }
2776 }
2777 }
2778 mutex_lock(&adev->pm.mutex);
2779 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2780 if (r)
2781 goto fail;
2782
2783 for (c = i = 0; i < num_msgs; i++) {
2784 if (!(msg[i].flags & I2C_M_RD)) {
2785 c += msg[i].len;
2786 continue;
2787 }
2788 for (j = 0; j < msg[i].len; j++, c++) {
2789 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2790
2791 msg[i].buf[j] = cmd->ReadWriteData;
2792 }
2793 }
2794 r = num_msgs;
2795 fail:
2796 mutex_unlock(&adev->pm.mutex);
2797 kfree(req);
2798 return r;
2799 }
2800
smu_v13_0_0_i2c_func(struct i2c_adapter * adap)2801 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
2802 {
2803 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2804 }
2805
2806 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
2807 .master_xfer = smu_v13_0_0_i2c_xfer,
2808 .functionality = smu_v13_0_0_i2c_func,
2809 };
2810
2811 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
2812 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2813 .max_read_len = MAX_SW_I2C_COMMANDS,
2814 .max_write_len = MAX_SW_I2C_COMMANDS,
2815 .max_comb_1st_msg_len = 2,
2816 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2817 };
2818
smu_v13_0_0_i2c_control_init(struct smu_context * smu)2819 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
2820 {
2821 struct amdgpu_device *adev = smu->adev;
2822 int res, i;
2823
2824 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2825 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2826 struct i2c_adapter *control = &smu_i2c->adapter;
2827
2828 smu_i2c->adev = adev;
2829 smu_i2c->port = i;
2830 mutex_init(&smu_i2c->mutex);
2831 control->owner = THIS_MODULE;
2832 control->dev.parent = &adev->pdev->dev;
2833 control->algo = &smu_v13_0_0_i2c_algo;
2834 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2835 control->quirks = &smu_v13_0_0_i2c_control_quirks;
2836 i2c_set_adapdata(control, smu_i2c);
2837
2838 res = i2c_add_adapter(control);
2839 if (res) {
2840 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2841 goto Out_err;
2842 }
2843 }
2844
2845 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2846 /* XXX ideally this would be something in a vbios data table */
2847 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2848 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2849
2850 return 0;
2851 Out_err:
2852 for ( ; i >= 0; i--) {
2853 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2854 struct i2c_adapter *control = &smu_i2c->adapter;
2855
2856 i2c_del_adapter(control);
2857 }
2858 return res;
2859 }
2860
smu_v13_0_0_i2c_control_fini(struct smu_context * smu)2861 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
2862 {
2863 struct amdgpu_device *adev = smu->adev;
2864 int i;
2865
2866 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2867 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2868 struct i2c_adapter *control = &smu_i2c->adapter;
2869
2870 i2c_del_adapter(control);
2871 }
2872 adev->pm.ras_eeprom_i2c_bus = NULL;
2873 adev->pm.fru_eeprom_i2c_bus = NULL;
2874 }
2875
smu_v13_0_0_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2876 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
2877 enum pp_mp1_state mp1_state)
2878 {
2879 int ret;
2880
2881 switch (mp1_state) {
2882 case PP_MP1_STATE_UNLOAD:
2883 ret = smu_cmn_send_smc_msg_with_param(smu,
2884 SMU_MSG_PrepareMp1ForUnload,
2885 0x55, NULL);
2886
2887 if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT)
2888 ret = smu_v13_0_disable_pmfw_state(smu);
2889
2890 break;
2891 default:
2892 /* Ignore others */
2893 ret = 0;
2894 }
2895
2896 return ret;
2897 }
2898
smu_v13_0_0_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2899 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
2900 enum pp_df_cstate state)
2901 {
2902 return smu_cmn_send_smc_msg_with_param(smu,
2903 SMU_MSG_DFCstateControl,
2904 state,
2905 NULL);
2906 }
2907
smu_v13_0_0_set_mode1_reset_param(struct smu_context * smu,uint32_t supported_version,uint32_t * param)2908 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu,
2909 uint32_t supported_version,
2910 uint32_t *param)
2911 {
2912 struct amdgpu_device *adev = smu->adev;
2913
2914 if ((smu->smc_fw_version >= supported_version) &&
2915 amdgpu_ras_get_fed_status(adev))
2916 /* Set RAS fatal error reset flag */
2917 *param = 1 << 16;
2918 else
2919 *param = 0;
2920 }
2921
smu_v13_0_0_mode1_reset(struct smu_context * smu)2922 static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
2923 {
2924 int ret;
2925 uint32_t param;
2926 struct amdgpu_device *adev = smu->adev;
2927
2928 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2929 case IP_VERSION(13, 0, 0):
2930 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */
2931 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m);
2932
2933 ret = smu_cmn_send_smc_msg_with_param(smu,
2934 SMU_MSG_Mode1Reset, param, NULL);
2935 break;
2936
2937 case IP_VERSION(13, 0, 10):
2938 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */
2939 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m);
2940
2941 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2942 DEBUGSMC_MSG_Mode1Reset, param);
2943 break;
2944
2945 default:
2946 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2947 break;
2948 }
2949
2950 if (!ret)
2951 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2952
2953 return ret;
2954 }
2955
smu_v13_0_0_mode2_reset(struct smu_context * smu)2956 static int smu_v13_0_0_mode2_reset(struct smu_context *smu)
2957 {
2958 int ret;
2959 struct amdgpu_device *adev = smu->adev;
2960
2961 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2962 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL);
2963 else
2964 return -EOPNOTSUPP;
2965
2966 return ret;
2967 }
2968
smu_v13_0_0_enable_gfx_features(struct smu_context * smu)2969 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu)
2970 {
2971 struct amdgpu_device *adev = smu->adev;
2972
2973 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2974 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2975 FEATURE_PWR_GFX, NULL);
2976 else
2977 return -EOPNOTSUPP;
2978 }
2979
smu_v13_0_0_set_smu_mailbox_registers(struct smu_context * smu)2980 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
2981 {
2982 struct amdgpu_device *adev = smu->adev;
2983
2984 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2985 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2986 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2987
2988 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2989 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2990 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2991 }
2992
smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context * smu,uint32_t size)2993 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
2994 uint32_t size)
2995 {
2996 int ret = 0;
2997
2998 /* message SMU to update the bad page number on SMUBUS */
2999 ret = smu_cmn_send_smc_msg_with_param(smu,
3000 SMU_MSG_SetNumBadMemoryPagesRetired,
3001 size, NULL);
3002 if (ret)
3003 dev_err(smu->adev->dev,
3004 "[%s] failed to message SMU to update bad memory pages number\n",
3005 __func__);
3006
3007 return ret;
3008 }
3009
smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context * smu,uint32_t size)3010 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
3011 uint32_t size)
3012 {
3013 int ret = 0;
3014
3015 /* message SMU to update the bad channel info on SMUBUS */
3016 ret = smu_cmn_send_smc_msg_with_param(smu,
3017 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
3018 size, NULL);
3019 if (ret)
3020 dev_err(smu->adev->dev,
3021 "[%s] failed to message SMU to update bad memory pages channel info\n",
3022 __func__);
3023
3024 return ret;
3025 }
3026
smu_v13_0_0_check_ecc_table_support(struct smu_context * smu)3027 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu)
3028 {
3029 struct amdgpu_device *adev = smu->adev;
3030 int ret = 0;
3031
3032 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) &&
3033 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION))
3034 return ret;
3035 else
3036 return -EOPNOTSUPP;
3037 }
3038
smu_v13_0_0_get_ecc_info(struct smu_context * smu,void * table)3039 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,
3040 void *table)
3041 {
3042 struct smu_table_context *smu_table = &smu->smu_table;
3043 struct amdgpu_device *adev = smu->adev;
3044 EccInfoTable_t *ecc_table = NULL;
3045 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
3046 int i, ret = 0;
3047 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
3048
3049 ret = smu_v13_0_0_check_ecc_table_support(smu);
3050 if (ret)
3051 return ret;
3052
3053 ret = smu_cmn_update_table(smu,
3054 SMU_TABLE_ECCINFO,
3055 0,
3056 smu_table->ecc_table,
3057 false);
3058 if (ret) {
3059 dev_info(adev->dev, "Failed to export SMU ecc table!\n");
3060 return ret;
3061 }
3062
3063 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
3064
3065 for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
3066 ecc_info_per_channel = &(eccinfo->ecc[i]);
3067 ecc_info_per_channel->ce_count_lo_chip =
3068 ecc_table->EccInfo[i].ce_count_lo_chip;
3069 ecc_info_per_channel->ce_count_hi_chip =
3070 ecc_table->EccInfo[i].ce_count_hi_chip;
3071 ecc_info_per_channel->mca_umc_status =
3072 ecc_table->EccInfo[i].mca_umc_status;
3073 ecc_info_per_channel->mca_umc_addr =
3074 ecc_table->EccInfo[i].mca_umc_addr;
3075 }
3076
3077 return ret;
3078 }
3079
smu_v13_0_0_wbrf_support_check(struct smu_context * smu)3080 static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)
3081 {
3082 struct amdgpu_device *adev = smu->adev;
3083
3084 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3085 case IP_VERSION(13, 0, 0):
3086 return smu->smc_fw_version >= 0x004e6300;
3087 case IP_VERSION(13, 0, 10):
3088 return smu->smc_fw_version >= 0x00503300;
3089 default:
3090 return false;
3091 }
3092 }
3093
smu_v13_0_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)3094 static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
3095 enum smu_ppt_limit_type limit_type,
3096 uint32_t limit)
3097 {
3098 PPTable_t *pptable = smu->smu_table.driver_pptable;
3099 SkuTable_t *skutable = &pptable->SkuTable;
3100 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
3101 struct smu_table_context *table_context = &smu->smu_table;
3102 OverDriveTableExternal_t *od_table =
3103 (OverDriveTableExternal_t *)table_context->overdrive_table;
3104 int ret = 0;
3105
3106 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
3107 return -EINVAL;
3108
3109 if (limit <= msg_limit) {
3110 if (smu->current_power_limit > msg_limit) {
3111 od_table->OverDriveTable.Ppt = 0;
3112 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3113
3114 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3115 if (ret) {
3116 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3117 return ret;
3118 }
3119 }
3120 return smu_v13_0_set_power_limit(smu, limit_type, limit);
3121 } else if (smu->od_enabled) {
3122 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
3123 if (ret)
3124 return ret;
3125
3126 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
3127 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3128
3129 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3130 if (ret) {
3131 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3132 return ret;
3133 }
3134
3135 smu->current_power_limit = limit;
3136 } else {
3137 return -EINVAL;
3138 }
3139
3140 return 0;
3141 }
3142
3143 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
3144 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
3145 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
3146 .i2c_init = smu_v13_0_0_i2c_control_init,
3147 .i2c_fini = smu_v13_0_0_i2c_control_fini,
3148 .is_dpm_running = smu_v13_0_0_is_dpm_running,
3149 .init_microcode = smu_v13_0_init_microcode,
3150 .load_microcode = smu_v13_0_load_microcode,
3151 .fini_microcode = smu_v13_0_fini_microcode,
3152 .init_smc_tables = smu_v13_0_0_init_smc_tables,
3153 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3154 .init_power = smu_v13_0_init_power,
3155 .fini_power = smu_v13_0_fini_power,
3156 .check_fw_status = smu_v13_0_check_fw_status,
3157 .setup_pptable = smu_v13_0_0_setup_pptable,
3158 .check_fw_version = smu_v13_0_check_fw_version,
3159 .write_pptable = smu_cmn_write_pptable,
3160 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3161 .system_features_control = smu_v13_0_0_system_features_control,
3162 .set_allowed_mask = smu_v13_0_set_allowed_mask,
3163 .get_enabled_mask = smu_cmn_get_enabled_mask,
3164 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
3165 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
3166 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
3167 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
3168 .read_sensor = smu_v13_0_0_read_sensor,
3169 .feature_is_enabled = smu_cmn_feature_is_enabled,
3170 .print_clk_levels = smu_v13_0_0_print_clk_levels,
3171 .force_clk_levels = smu_v13_0_0_force_clk_levels,
3172 .update_pcie_parameters = smu_v13_0_update_pcie_parameters,
3173 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
3174 .register_irq_handler = smu_v13_0_register_irq_handler,
3175 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3176 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3177 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3178 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
3179 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
3180 .set_default_od_settings = smu_v13_0_0_set_default_od_settings,
3181 .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings,
3182 .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table,
3183 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
3184 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
3185 .set_performance_level = smu_v13_0_set_performance_level,
3186 .gfx_off_control = smu_v13_0_gfx_off_control,
3187 .get_unique_id = smu_v13_0_0_get_unique_id,
3188 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
3189 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
3190 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
3191 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
3192 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
3193 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
3194 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
3195 .get_power_limit = smu_v13_0_0_get_power_limit,
3196 .set_power_limit = smu_v13_0_0_set_power_limit,
3197 .set_power_source = smu_v13_0_set_power_source,
3198 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
3199 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
3200 .run_btc = smu_v13_0_run_btc,
3201 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3202 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3203 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3204 .deep_sleep_control = smu_v13_0_deep_sleep_control,
3205 .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
3206 .get_bamaco_support = smu_v13_0_get_bamaco_support,
3207 .baco_enter = smu_v13_0_baco_enter,
3208 .baco_exit = smu_v13_0_baco_exit,
3209 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
3210 .mode1_reset = smu_v13_0_0_mode1_reset,
3211 .mode2_reset = smu_v13_0_0_mode2_reset,
3212 .enable_gfx_features = smu_v13_0_0_enable_gfx_features,
3213 .set_mp1_state = smu_v13_0_0_set_mp1_state,
3214 .set_df_cstate = smu_v13_0_0_set_df_cstate,
3215 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num,
3216 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag,
3217 .gpo_control = smu_v13_0_gpo_control,
3218 .get_ecc_info = smu_v13_0_0_get_ecc_info,
3219 .notify_display_change = smu_v13_0_notify_display_change,
3220 .is_asic_wbrf_supported = smu_v13_0_0_wbrf_support_check,
3221 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
3222 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
3223 .interrupt_work = smu_v13_0_interrupt_work,
3224 };
3225
smu_v13_0_0_set_ppt_funcs(struct smu_context * smu)3226 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
3227 {
3228 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
3229 smu->message_map = smu_v13_0_0_message_map;
3230 smu->clock_map = smu_v13_0_0_clk_map;
3231 smu->feature_map = smu_v13_0_0_feature_mask_map;
3232 smu->table_map = smu_v13_0_0_table_map;
3233 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
3234 smu->workload_map = smu_v13_0_0_workload_map;
3235 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;
3236 smu_v13_0_0_set_smu_mailbox_registers(smu);
3237 }
3238