1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26
27 /*
28 * This is the nexus driver for SMBUS devices. It mostly does not use
29 * the SMBUS protocol so that it fits better into the solaris i2c
30 * framework.
31 */
32
33 #include <sys/types.h>
34 #include <sys/conf.h>
35 #include <sys/file.h>
36 #include <sys/open.h>
37 #include <sys/ddi.h>
38 #include <sys/sunddi.h>
39 #include <sys/modctl.h>
40 #include <sys/stat.h>
41 #include <sys/kmem.h>
42 #include <sys/archsystm.h>
43 #include <sys/platform_module.h>
44
45 #include <sys/i2c/clients/i2c_client.h>
46 #include <sys/i2c/misc/i2c_svc.h>
47 #include <sys/i2c/misc/i2c_svc_impl.h>
48 #include <sys/i2c/nexus/smbus.h>
49
50 /*
51 * static function declarations
52 */
53 static uint_t smbus_intr_cmn(smbus_t *smbus, char *src);
54 static void smbus_intr_timeout(void *arg);
55 static void smbus_resume(dev_info_t *dip);
56 static void smbus_suspend(dev_info_t *dip);
57 static int smbus_bus_ctl(dev_info_t *dip, dev_info_t *rdip,
58 ddi_ctl_enum_t op, void *arg, void *result);
59 static int smbus_acquire(smbus_t *, dev_info_t *dip,
60 i2c_transfer_t *tp);
61 static void smbus_release(smbus_t *);
62 static int smbus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
63 static int smbus_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
64 static void smbus_free_regs(smbus_t *smbus);
65 static int smbus_setup_regs(dev_info_t *dip, smbus_t *smbus);
66 static void smbus_reportdev(dev_info_t *dip, dev_info_t *rdip);
67 static void smbus_uninitchild(dev_info_t *cdip);
68 static int smbus_initchild(dev_info_t *cdip);
69 static int smbus_rd(smbus_t *smbus);
70 static int smbus_wr(smbus_t *smbus);
71 static void smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags);
72 static uint8_t smbus_get(smbus_t *smbus, uint8_t reg);
73 static int smbus_dip_to_addr(dev_info_t *dip);
74 static uint_t smbus_intr(caddr_t arg);
75 static int smbus_switch(smbus_t *smbus);
76
77 static struct bus_ops smbus_busops = {
78 BUSO_REV,
79 nullbusmap, /* bus_map */
80 NULL, /* bus_get_intrspec */
81 NULL, /* bus_add_intrspec */
82 NULL, /* bus_remove_intrspec */
83 NULL, /* bus_map_fault */
84 ddi_no_dma_map, /* bus_dma_map */
85 ddi_no_dma_allochdl, /* bus_dma_allochdl */
86 ddi_no_dma_freehdl, /* bus_dma_freehdl */
87 ddi_no_dma_bindhdl, /* bus_dma_bindhdl */
88 ddi_no_dma_unbindhdl, /* bus_unbindhdl */
89 ddi_no_dma_flush, /* bus_dma_flush */
90 ddi_no_dma_win, /* bus_dma_win */
91 ddi_no_dma_mctl, /* bus_dma_ctl */
92 smbus_bus_ctl, /* bus_ctl */
93 ddi_bus_prop_op, /* bus_prop_op */
94 NULL, /* bus_get_eventcookie */
95 NULL, /* bus_add_eventcall */
96 NULL, /* bus_remove_eventcall */
97 NULL, /* bus_post_event */
98 0, /* bus_intr_ctl */
99 0, /* bus_config */
100 0, /* bus_unconfig */
101 0, /* bus_fm_init */
102 0, /* bus_fm_fini */
103 0, /* bus_fm_access_enter */
104 0, /* bus_fm_access_exit */
105 0, /* bus_power */
106 i_ddi_intr_ops /* bus_intr_op */
107 };
108
109 struct cb_ops smbus_cb_ops = {
110 nodev, /* open */
111 nodev, /* close */
112 nodev, /* strategy */
113 nodev, /* print */
114 nodev, /* dump */
115 nodev, /* read */
116 nodev, /* write */
117 nodev, /* ioctl */
118 nodev, /* devmap */
119 nodev, /* mmap */
120 nodev, /* segmap */
121 nochpoll, /* poll */
122 ddi_prop_op, /* cb_prop_op */
123 0, /* streamtab */
124 D_MP | D_NEW /* Driver compatibility flag */
125 };
126
127 static struct dev_ops smbus_ops = {
128 DEVO_REV,
129 0,
130 ddi_no_info,
131 nulldev,
132 nulldev,
133 smbus_attach,
134 smbus_detach,
135 nodev,
136 &smbus_cb_ops,
137 &smbus_busops,
138 NULL,
139 ddi_quiesce_not_supported, /* devo_quiesce */
140 };
141
142 static struct modldrv modldrv = {
143 &mod_driverops, /* Type of module. This one is a driver */
144 "SMBUS nexus Driver", /* Name of the module. */
145 &smbus_ops, /* driver ops */
146 };
147
148 static struct modlinkage modlinkage = {
149 MODREV_1,
150 &modldrv,
151 NULL
152 };
153
154 /*
155 * Globals
156 */
157 static void *smbus_state;
158
159 static int intr_timeout = INTR_TIMEOUT;
160
161 /*
162 * The "interrupt-priorities" property is how a driver can specify a SPARC
163 * PIL level to associate with each of its interrupt properties. Most
164 * self-identifying busses have a better mechanism for managing this, but I2C
165 * doesn't.
166 */
167 int smbus_pil = SMBUS_PIL;
168
169 i2c_nexus_reg_t smbus_regvec = {
170 I2C_NEXUS_REV,
171 smbus_transfer,
172 };
173
174 #ifdef DEBUG
175
176 static int smbus_print_lvl = 0;
177 static char msg_buff[1024];
178 static kmutex_t msg_buf_lock;
179
180 void
smbus_print(int flags,const char * fmt,...)181 smbus_print(int flags, const char *fmt, ...)
182 {
183 if (flags & smbus_print_lvl) {
184 va_list ap;
185
186 va_start(ap, fmt);
187
188 if (smbus_print_lvl & PRT_PROM) {
189 prom_vprintf(fmt, ap);
190 } else {
191
192 mutex_enter(&msg_buf_lock);
193 (void) vsprintf(msg_buff, fmt, ap);
194 if (smbus_print_lvl & PRT_BUFFONLY) {
195 cmn_err(CE_CONT, "?%s", msg_buff);
196 } else {
197 cmn_err(CE_CONT, "%s", msg_buff);
198 }
199 mutex_exit(&msg_buf_lock);
200 }
201 va_end(ap);
202 }
203 }
204 #endif /* DEBUG */
205
206 int
_init(void)207 _init(void)
208 {
209 int status;
210
211 status = ddi_soft_state_init(&smbus_state, sizeof (smbus_t),
212 1);
213 if (status != 0) {
214
215 return (status);
216 }
217
218 if ((status = mod_install(&modlinkage)) != 0) {
219 ddi_soft_state_fini(&smbus_state);
220 } else {
221 #ifdef DEBUG
222 mutex_init(&msg_buf_lock, NULL, MUTEX_DRIVER, NULL);
223 #endif
224 }
225 return (status);
226 }
227
228 int
_fini(void)229 _fini(void)
230 {
231 int status;
232
233 if ((status = mod_remove(&modlinkage)) == 0) {
234 ddi_soft_state_fini(&smbus_state);
235 #ifdef DEBUG
236 mutex_destroy(&msg_buf_lock);
237 #endif
238 }
239
240 return (status);
241 }
242
243 /*
244 * The loadable-module _info(9E) entry point
245 */
246 int
_info(struct modinfo * modinfop)247 _info(struct modinfo *modinfop)
248 {
249 return (mod_info(&modlinkage, modinfop));
250 }
251
252 static void
smbus_interrupts_on(smbus_t * smbus)253 smbus_interrupts_on(smbus_t *smbus)
254 {
255 int src_enable;
256
257 src_enable = ddi_get32(smbus->smbus_confighandle,
258 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]);
259 src_enable |= SMBUS_SMI;
260 ddi_put32(smbus->smbus_confighandle,
261 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA],
262 src_enable);
263 (void) ddi_get32(smbus->smbus_confighandle,
264 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]);
265 }
266
267 static void
smbus_interrupts_off(smbus_t * smbus)268 smbus_interrupts_off(smbus_t *smbus)
269 {
270 int src_enable;
271
272 src_enable = ddi_get32(smbus->smbus_confighandle,
273 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]);
274 src_enable &= ~SMBUS_SMI;
275 ddi_put32(smbus->smbus_confighandle,
276 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA],
277 src_enable);
278 (void) ddi_get32(smbus->smbus_confighandle,
279 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]);
280 }
281
282 static void
smbus_dodetach(dev_info_t * dip)283 smbus_dodetach(dev_info_t *dip)
284 {
285 smbus_t *smbus;
286 int instance = ddi_get_instance(dip);
287
288 smbus = ddi_get_soft_state(smbus_state, instance);
289
290 if (smbus == NULL) {
291
292 return;
293 }
294
295 cv_destroy(&smbus->smbus_cv);
296 mutex_destroy(&smbus->smbus_mutex);
297
298 if ((smbus->smbus_attachflags & INTERRUPT_PRI) != 0) {
299 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
300 "interrupt-priorities");
301 }
302
303 smbus_free_regs(smbus);
304
305 if ((smbus->smbus_attachflags & NEXUS_REGISTER) != 0) {
306 i2c_nexus_unregister(dip);
307 }
308 if ((smbus->smbus_attachflags & IMUTEX) != 0) {
309 mutex_destroy(&smbus->smbus_imutex);
310 cv_destroy(&smbus->smbus_icv);
311 }
312
313 if (smbus->smbus_timeout != 0) {
314 (void) untimeout(smbus->smbus_timeout);
315 }
316
317 if ((smbus->smbus_attachflags & ADD_INTR) != 0) {
318 ddi_remove_intr(dip, 0, smbus->smbus_icookie);
319 }
320
321 ddi_soft_state_free(smbus_state, instance);
322 }
323
324 static int
smbus_doattach(dev_info_t * dip)325 smbus_doattach(dev_info_t *dip)
326 {
327 smbus_t *smbus;
328 int instance = ddi_get_instance(dip);
329
330 /*
331 * Allocate soft state structure.
332 */
333 if (ddi_soft_state_zalloc(smbus_state, instance) != DDI_SUCCESS) {
334
335 goto bad;
336 }
337
338 smbus = ddi_get_soft_state(smbus_state, instance);
339
340 (void) snprintf(smbus->smbus_name, sizeof (smbus->smbus_name),
341 "%s%d", ddi_node_name(dip), instance);
342
343 smbus->smbus_dip = dip;
344
345 mutex_init(&smbus->smbus_mutex, NULL, MUTEX_DRIVER, NULL);
346 mutex_init(&smbus->smbus_imutex, NULL, MUTEX_DRIVER, NULL);
347 cv_init(&smbus->smbus_cv, NULL, CV_DRIVER, NULL);
348 cv_init(&smbus->smbus_intr_cv, NULL, CV_DRIVER, NULL);
349
350 if (smbus_setup_regs(dip, smbus) != DDI_SUCCESS) {
351 goto bad;
352 }
353
354 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
355 "interrupts") == 1) {
356 smbus->smbus_polling = 0;
357 /*
358 * The "interrupt-priorities" property is how a driver can
359 * specify a SPARC PIL level to associate with each of its
360 * interrupt properties. Most self-identifying busses have
361 * a better mechanism for managing this, but I2C doesn't.
362 */
363 if (ddi_prop_exists(DDI_DEV_T_ANY, dip,
364 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS,
365 "interrupt-priorities") != 1) {
366 (void) ddi_prop_create(DDI_DEV_T_NONE, dip,
367 DDI_PROP_CANSLEEP, "interrupt-priorities",
368 (caddr_t)&smbus_pil,
369 sizeof (smbus_pil));
370 smbus->smbus_attachflags |= INTERRUPT_PRI;
371 }
372
373 /*
374 * Clear status to clear any possible interrupt
375 */
376 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH);
377
378 if (ddi_get_iblock_cookie(dip, 0, &smbus->smbus_icookie) !=
379 DDI_SUCCESS) {
380 goto bad;
381 }
382
383 if (ddi_add_intr(dip, 0, NULL, NULL, smbus_intr,
384 (caddr_t)smbus) != DDI_SUCCESS) {
385 cmn_err(CE_WARN, "%s failed to add interrupt",
386 smbus->smbus_name);
387 goto bad;
388 }
389 smbus->smbus_attachflags |= ADD_INTR;
390 } else {
391 smbus->smbus_polling = 1;
392 /* Clear status */
393 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH);
394 }
395
396 /*
397 * initialize a cv and mutex
398 */
399 cv_init(&smbus->smbus_icv, NULL, CV_DRIVER, NULL);
400 mutex_init(&smbus->smbus_imutex, NULL, MUTEX_DRIVER,
401 (void *)smbus->smbus_icookie);
402 smbus->smbus_attachflags |= IMUTEX;
403
404 /*
405 * Register with the i2c framework
406 */
407 i2c_nexus_register(dip, &smbus_regvec);
408 smbus->smbus_attachflags |= NEXUS_REGISTER;
409
410 return (DDI_SUCCESS);
411
412 bad:
413 smbus_dodetach(dip);
414
415 return (DDI_FAILURE);
416 }
417
418 static int
smbus_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)419 smbus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
420 {
421 switch (cmd) {
422 case DDI_ATTACH:
423
424 return (smbus_doattach(dip));
425 case DDI_RESUME:
426 smbus_resume(dip);
427
428 return (DDI_SUCCESS);
429 default:
430
431 return (DDI_FAILURE);
432 }
433 }
434
435 static int
smbus_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)436 smbus_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
437 {
438 switch (cmd) {
439 case DDI_DETACH:
440 smbus_dodetach(dip);
441
442 return (DDI_SUCCESS);
443 case DDI_SUSPEND:
444 smbus_suspend(dip);
445
446 return (DDI_SUCCESS);
447 default:
448
449 return (DDI_FAILURE);
450 }
451 }
452
453 static int
smbus_bus_ctl(dev_info_t * dip,dev_info_t * rdip,ddi_ctl_enum_t op,void * arg,void * result)454 smbus_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op,
455 void *arg, void *result)
456 {
457 switch (op) {
458 case DDI_CTLOPS_INITCHILD:
459
460 return (smbus_initchild((dev_info_t *)arg));
461 case DDI_CTLOPS_UNINITCHILD:
462 smbus_uninitchild((dev_info_t *)arg);
463
464 return (DDI_SUCCESS);
465 case DDI_CTLOPS_REPORTDEV:
466 smbus_reportdev(dip, rdip);
467
468 return (DDI_SUCCESS);
469 case DDI_CTLOPS_DMAPMAPC:
470 case DDI_CTLOPS_POKE:
471 case DDI_CTLOPS_PEEK:
472 case DDI_CTLOPS_IOMIN:
473 case DDI_CTLOPS_REPORTINT:
474 case DDI_CTLOPS_SIDDEV:
475 case DDI_CTLOPS_SLAVEONLY:
476 case DDI_CTLOPS_AFFINITY:
477 case DDI_CTLOPS_PTOB:
478 case DDI_CTLOPS_BTOP:
479 case DDI_CTLOPS_BTOPR:
480 case DDI_CTLOPS_DVMAPAGESIZE:
481
482 return (DDI_FAILURE);
483 default:
484
485 return (ddi_ctlops(dip, rdip, op, arg, result));
486 }
487 }
488
489 static int
smbus_initchild(dev_info_t * cdip)490 smbus_initchild(dev_info_t *cdip)
491 {
492 int32_t cell_size;
493 int len;
494 int32_t regs[2];
495 int err;
496 smbus_ppvt_t *ppvt;
497 char name[30];
498
499 SMBUS_PRINT((PRT_INIT, "smbus_initchild ENTER: %s\n",
500 ddi_node_name(cdip)));
501
502 len = sizeof (cell_size);
503 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip,
504 DDI_PROP_CANSLEEP, "#address-cells",
505 (caddr_t)&cell_size, &len);
506 if (err != DDI_PROP_SUCCESS || len != sizeof (cell_size)) {
507 cmn_err(CE_WARN, "cannot find address-cells");
508
509 return (DDI_FAILURE);
510 }
511
512 len = sizeof (regs);
513 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip,
514 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP,
515 "reg", (caddr_t)regs, &len);
516
517 if (err != DDI_PROP_SUCCESS) {
518 cmn_err(CE_WARN, "cannot get reg property");
519
520 return (DDI_FAILURE);
521 }
522
523 ppvt = kmem_zalloc(sizeof (smbus_ppvt_t), KM_SLEEP);
524 ddi_set_parent_data(cdip, ppvt);
525
526 /*
527 * The reg property contains an unused first element (which is
528 * the mux addr on xcal), and the second element is the i2c bus
529 * address of the device.
530 */
531 ppvt->smbus_ppvt_addr = regs[1];
532 (void) sprintf(name, "%x", regs[1]);
533
534 ddi_set_name_addr(cdip, name);
535
536 SMBUS_PRINT((PRT_INIT, "smbus_initchild SUCCESS: %s\n",
537 ddi_node_name(cdip)));
538
539 return (DDI_SUCCESS);
540 }
541
542 static void
smbus_uninitchild(dev_info_t * cdip)543 smbus_uninitchild(dev_info_t *cdip)
544 {
545 smbus_ppvt_t *ppvt;
546
547 ppvt = ddi_get_parent_data(cdip);
548 ddi_set_parent_data(cdip, NULL);
549
550 ddi_set_name_addr(cdip, NULL);
551
552 kmem_free(ppvt, sizeof (smbus_ppvt_t));
553
554 SMBUS_PRINT((PRT_INIT, "smbus_uninitchild: %s\n", ddi_node_name(cdip)));
555 }
556
557 static void
smbus_reportdev(dev_info_t * dip,dev_info_t * rdip)558 smbus_reportdev(dev_info_t *dip, dev_info_t *rdip)
559 {
560 smbus_ppvt_t *ppvt;
561
562 ppvt = ddi_get_parent_data(rdip);
563
564 cmn_err(CE_CONT, "?%s%d at %s%d: addr 0x%x",
565 ddi_driver_name(rdip), ddi_get_instance(rdip),
566 ddi_driver_name(dip), ddi_get_instance(dip),
567 ppvt->smbus_ppvt_addr);
568 }
569
570 /*
571 * smbus_setup_regs() is called to map in the registers
572 * specific to the smbus.
573 */
574 static int
smbus_setup_regs(dev_info_t * dip,smbus_t * smbus)575 smbus_setup_regs(dev_info_t *dip, smbus_t *smbus)
576 {
577 ddi_device_acc_attr_t attr;
578 int ret;
579
580 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
581 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
582 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
583
584 ret = ddi_regs_map_setup(dip, 1, (caddr_t *)&smbus->smbus_regaddr,
585 0, 0, &attr, &smbus->smbus_rhandle);
586
587 if (ret == DDI_FAILURE) {
588 cmn_err(CE_WARN, "%s unable to map regs", smbus->smbus_name);
589
590 } else if (ret == DDI_REGS_ACC_CONFLICT) {
591 cmn_err(CE_WARN,
592 "%s unable to map regs because of conflict",
593 smbus->smbus_name);
594 ret = DDI_FAILURE;
595 }
596
597 if (ret == DDI_FAILURE) {
598
599 return (ret);
600 }
601
602 ret = ddi_regs_map_setup(dip, 0, (caddr_t *)&smbus->smbus_configregaddr,
603 0, 0, &attr, &smbus->smbus_confighandle);
604
605 if (ret == DDI_FAILURE) {
606 cmn_err(CE_WARN, "%s unable to map config regs",
607 smbus->smbus_name);
608
609 } else if (ret == DDI_REGS_ACC_CONFLICT) {
610 cmn_err(CE_WARN,
611 "%s unable to map config regs because of conflict",
612 smbus->smbus_name);
613 ret = DDI_FAILURE;
614 }
615
616 return (ret);
617 }
618
619 /*
620 * smbus_free_regs() frees any registers previously allocated.
621 */
622 static void
smbus_free_regs(smbus_t * smbus)623 smbus_free_regs(smbus_t *smbus)
624 {
625 if (smbus->smbus_regaddr != NULL) {
626 ddi_regs_map_free(&smbus->smbus_rhandle);
627 }
628
629 if (smbus->smbus_configregaddr != NULL) {
630 ddi_regs_map_free(&smbus->smbus_confighandle);
631 }
632 }
633
634 /*
635 * smbus_dip_to_addr() takes a dip and returns an I2C address.
636 */
637 static int
smbus_dip_to_addr(dev_info_t * cdip)638 smbus_dip_to_addr(dev_info_t *cdip)
639 {
640 smbus_ppvt_t *ppvt;
641
642 ppvt = ddi_get_parent_data(cdip);
643
644 return (ppvt->smbus_ppvt_addr);
645 }
646
647 /*
648 * smbus_suspend() is called before the system suspends. Existing
649 * transfer in progress or waiting will complete, but new transfers are
650 * effectively blocked by "acquiring" the bus.
651 */
652 static void
smbus_suspend(dev_info_t * dip)653 smbus_suspend(dev_info_t *dip)
654 {
655 smbus_t *smbus;
656 int instance;
657
658 instance = ddi_get_instance(dip);
659 smbus = ddi_get_soft_state(smbus_state, instance);
660
661 (void) smbus_acquire(smbus, NULL, NULL);
662 }
663
664 /*
665 * smbus_resume() is called when the system resumes from CPR. It releases
666 * the hold that was placed on the i2c bus, which allows any real
667 * transfers to continue.
668 */
669 static void
smbus_resume(dev_info_t * dip)670 smbus_resume(dev_info_t *dip)
671 {
672 smbus_t *smbus;
673 int instance;
674
675 instance = ddi_get_instance(dip);
676 smbus = ddi_get_soft_state(smbus_state, instance);
677
678 smbus_release(smbus);
679 }
680
681 /*
682 * smbus_acquire() is called by a thread wishing to "own" the SMbus.
683 * It should not be held across multiple transfers.
684 */
685 static int
smbus_acquire(smbus_t * smbus,dev_info_t * dip,i2c_transfer_t * tp)686 smbus_acquire(smbus_t *smbus, dev_info_t *dip, i2c_transfer_t *tp)
687 {
688 mutex_enter(&smbus->smbus_mutex);
689 while (smbus->smbus_busy) {
690 cv_wait(&smbus->smbus_cv, &smbus->smbus_mutex);
691 }
692 smbus->smbus_busy = 1;
693 mutex_exit(&smbus->smbus_mutex);
694
695 /*
696 * On systems where OBP shares a smbus controller with the
697 * OS, plat_shared_i2c_enter will serialize access to the
698 * smbus controller. Do not grab this lock during CPR
699 * suspend as the CPR thread also acquires this muxex
700 * through through prom_setprop which causes recursive
701 * mutex enter.
702 *
703 * dip == NULL during CPR.
704 */
705 if ((&plat_shared_i2c_enter != NULL) && (dip != NULL)) {
706 plat_shared_i2c_enter(smbus->smbus_dip);
707 }
708
709 smbus->smbus_cur_tran = tp;
710 smbus->smbus_cur_dip = dip;
711
712 return (SMBUS_SUCCESS);
713 }
714
715 /*
716 * smbus_release() is called to release a hold made by smbus_acquire().
717 */
718 static void
smbus_release(smbus_t * smbus)719 smbus_release(smbus_t *smbus)
720 {
721 mutex_enter(&smbus->smbus_mutex);
722 smbus->smbus_busy = 0;
723 cv_signal(&smbus->smbus_cv);
724 smbus->smbus_cur_tran = NULL;
725 smbus->smbus_cur_dip = NULL;
726 mutex_exit(&smbus->smbus_mutex);
727
728 if ((&plat_shared_i2c_exit != NULL) && (smbus->smbus_cur_dip != NULL)) {
729 plat_shared_i2c_exit(smbus->smbus_dip);
730 }
731 }
732
733 static void
smbus_put(smbus_t * smbus,uint8_t reg,uint8_t data,uint8_t flags)734 smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags)
735 {
736 ddi_acc_handle_t hp = smbus->smbus_rhandle;
737 uint8_t *reg_addr = smbus->smbus_regaddr;
738 uint8_t *config_addr = smbus->smbus_configregaddr;
739 ddi_acc_handle_t config_handle = smbus->smbus_confighandle;
740
741 ddi_put8(hp, ®_addr[reg], data);
742
743 SMBUS_PRINT((PRT_PUT, "smbus_put: addr = %p data = %x\n",
744 ®_addr[reg], data));
745
746 /*
747 * if FLUSH flag is passed, read a config regs to make sure
748 * data written is flushed.
749 */
750 if (flags & SMBUS_FLUSH) {
751 (void) ddi_get8(config_handle, &config_addr[0]);
752 }
753 }
754
755 static uint8_t
smbus_get(smbus_t * smbus,uint8_t reg)756 smbus_get(smbus_t *smbus, uint8_t reg)
757 {
758
759 ddi_acc_handle_t hp = smbus->smbus_rhandle;
760 uint8_t *regaddr = smbus->smbus_regaddr;
761 uint8_t data;
762
763 data = ddi_get8(hp, ®addr[reg]);
764
765 SMBUS_PRINT((PRT_GET, "smbus_get: data = %x\n", data));
766
767 return (data);
768 }
769
770
771 /*
772 * The southbridge smbus device appears to have a feature where
773 * reads from the status register return 0 for a few microseconds
774 * after clearing the status.
775 *
776 * "status_wait_idle" allows for this by retrying until
777 * it gets the right answer or times out. The loop count
778 * and the delay are empirical. The routine uses up
779 * 400 us if it fails.
780 *
781 * The fact that this routine waits for 10 us before the
782 * first check is deliberate.
783 */
784 static int
smbus_wait_idle(smbus_t * smbus)785 smbus_wait_idle(smbus_t *smbus)
786 {
787 int retries = 40;
788 int status;
789
790 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH);
791 do {
792 drv_usecwait(10);
793 status = smbus_get(smbus, SMB_STS);
794 } while (status != IDLE && --retries > 0);
795 return (status);
796 }
797 /*
798 * smbus_transfer is the function that is registered with
799 * I2C services to be called for each i2c transaction.
800 */
801 int
smbus_transfer(dev_info_t * dip,i2c_transfer_t * tp)802 smbus_transfer(dev_info_t *dip, i2c_transfer_t *tp)
803 {
804 smbus_t *smbus;
805 uint8_t status;
806 clock_t ctime;
807
808 smbus = ddi_get_soft_state(smbus_state,
809 ddi_get_instance(ddi_get_parent(dip)));
810
811 if (smbus_acquire(smbus, dip, tp) == SMBUS_FAILURE) {
812 tp->i2c_result = I2C_FAILURE;
813
814 return (I2C_FAILURE);
815 }
816
817 tp->i2c_r_resid = tp->i2c_rlen;
818 tp->i2c_w_resid = tp->i2c_wlen;
819 tp->i2c_result = I2C_SUCCESS;
820 smbus->smbus_retries = 0;
821 smbus->smbus_bytes_to_read = 0;
822
823 mutex_enter(&smbus->smbus_imutex);
824
825 SMBUS_PRINT((PRT_TRANS, "smbus_transfer: rlen=%d wlen=%d flags=%d",
826 tp->i2c_r_resid, tp->i2c_w_resid, tp->i2c_flags));
827
828 /*
829 * First clear the status bits, then read them back to determine
830 * the current state.
831 */
832 status = smbus_wait_idle(smbus);
833
834 if (status != IDLE) {
835 /*
836 * Try to issue bus reset
837 * First reset the state machine.
838 */
839 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH);
840 status = smbus_wait_idle(smbus);
841
842 if (status != IDLE) {
843
844 smbus_put(smbus, SMB_TYP, T_OUT, SMBUS_FLUSH);
845 status = smbus_wait_idle(smbus);
846 if (status != IDLE) {
847 cmn_err(CE_WARN,
848 "%s smbus not idle. Unable to reset %x",
849 smbus->smbus_name, status);
850 smbus->smbus_cur_tran->i2c_result = I2C_FAILURE;
851 mutex_exit(&smbus->smbus_imutex);
852 smbus_release(smbus);
853
854 return (I2C_FAILURE);
855 } else {
856 cmn_err(CE_WARN, "%s T_OUT reset required",
857 smbus->smbus_name);
858 }
859 }
860 }
861
862 if (smbus_switch(smbus) != SMBUS_COMPLETE) {
863 if (smbus->smbus_polling) {
864 smbus->smbus_poll_complete = 0;
865 smbus->smbus_poll_retries = 0;
866 do {
867 drv_usecwait(SMBUS_POLL_INTERVAL);
868 (void) smbus_intr_cmn(smbus, SMBUS_POLL);
869 } while (!smbus->smbus_poll_complete);
870 } else {
871 /*
872 * Start a timeout as there is a bug in southbridge
873 * smbus where sometimes a transaction never starts,
874 * and needs to be reinitiated.
875 */
876
877 smbus->smbus_timeout = timeout(smbus_intr_timeout,
878 smbus, drv_usectohz(intr_timeout));
879 SMBUS_PRINT((PRT_TRANS,
880 "starting timeout in smbus_transfer %p",
881 smbus->smbus_timeout));
882
883 ctime = ddi_get_lbolt();
884 ctime += drv_usectohz(SMBUS_TRANS_TIMEOUT);
885
886 smbus_interrupts_on(smbus);
887
888
889 cv_wait(&smbus->smbus_icv, &smbus->smbus_imutex);
890 }
891 }
892
893
894 mutex_exit(&smbus->smbus_imutex);
895 smbus_release(smbus);
896
897 return (tp->i2c_result);
898 }
899
900 /*
901 * This is called by smbus_intr_cmn() to figure out whether to call
902 * smbus_wr or smbus_rd depending on the command and current state.
903 */
904 static int
smbus_switch(smbus_t * smbus)905 smbus_switch(smbus_t *smbus)
906 {
907 int ret;
908 i2c_transfer_t *tp = smbus->smbus_cur_tran;
909
910 if (tp == NULL) {
911 cmn_err(CE_WARN,
912 "%s smbus_cur_tran is NULL. Transaction failed",
913 smbus->smbus_name);
914
915 return (SMBUS_FAILURE);
916 }
917
918 smbus->smbus_saved_w_resid = tp->i2c_w_resid;
919
920 switch (tp->i2c_flags) {
921 case I2C_WR:
922 ret = smbus_wr(smbus);
923 break;
924 case I2C_RD:
925 ret = smbus_rd(smbus);
926 break;
927 case I2C_WR_RD:
928 /*
929 * We could do a bit more decoding here,
930 * to allow the transactions that would
931 * work as a single smbus command to
932 * be done as such. It's not really
933 * worth the trouble.
934 */
935 if (tp->i2c_w_resid > 0) {
936 ret = smbus_wr(smbus);
937 } else {
938 ret = smbus_rd(smbus);
939 }
940 break;
941 default:
942 tp->i2c_result = I2C_FAILURE;
943 ret = SMBUS_COMPLETE;
944 break;
945 }
946
947 return (ret);
948 }
949
950 /*
951 *
952 */
953 static void
smbus_intr_timeout(void * arg)954 smbus_intr_timeout(void *arg)
955 {
956 smbus_t *smbus = (smbus_t *)arg;
957
958 mutex_enter(&smbus->smbus_imutex);
959 /*
960 * If timeout is already cleared, it means interrupt arrived
961 * while timeout fired. In this case, just return from here.
962 */
963 if (smbus->smbus_timeout == 0) {
964
965 mutex_exit(&smbus->smbus_imutex);
966
967 return;
968 }
969
970 (void) smbus_intr_cmn(smbus, SMBUS_TIMEOUT);
971 mutex_exit(&smbus->smbus_imutex);
972 }
973
974 /*
975 * smbus_intr() is the interrupt handler for smbus.
976 */
977 static uint_t
smbus_intr(caddr_t arg)978 smbus_intr(caddr_t arg)
979 {
980 smbus_t *smbus = (smbus_t *)arg;
981 uint32_t intr_status;
982 uint_t result;
983
984 /*
985 * Check to see if intr is really from smbus
986 */
987 intr_status = ddi_get32(smbus->smbus_confighandle,
988 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_STATUS]);
989
990
991 if ((intr_status & SMBUS_SMB_INTR_STATUS) == 0) {
992 SMBUS_PRINT((PRT_INTR, "smbus_intr: intr not from smbus\n"));
993
994 return (DDI_INTR_UNCLAIMED);
995 }
996
997 mutex_enter(&smbus->smbus_imutex);
998
999 /*
1000 * If timeout is already cleared, it means it arrived before the intr.
1001 * In that case, just return from here.
1002 */
1003 if (smbus->smbus_timeout == 0) {
1004
1005 mutex_exit(&smbus->smbus_imutex);
1006
1007 return (DDI_INTR_CLAIMED);
1008 }
1009
1010 result = smbus_intr_cmn(smbus, SMBUS_INTR);
1011 mutex_exit(&smbus->smbus_imutex);
1012 return (result);
1013 }
1014
1015 /*
1016 * smbus_intr() is the interrupt handler for smbus.
1017 */
1018 static uint_t
smbus_intr_cmn(smbus_t * smbus,char * src)1019 smbus_intr_cmn(smbus_t *smbus, char *src)
1020 {
1021 i2c_transfer_t *tp;
1022 char error_str[128];
1023 uint8_t status;
1024 int ret = SMBUS_SUCCESS;
1025 timeout_id_t timer_id;
1026
1027 ASSERT(mutex_owned(&smbus->smbus_imutex));
1028 error_str[0] = '\0';
1029
1030 smbus_interrupts_off(smbus);
1031
1032 tp = smbus->smbus_cur_tran;
1033 /*
1034 * This only happens when top half is interrupted or
1035 * times out, then the interrupt arrives. Interrupt
1036 * was already disabled by top half, so just exit.
1037 */
1038 if (tp == NULL) {
1039 return (DDI_INTR_CLAIMED);
1040 }
1041
1042 /*
1043 * This wait is required before reading the status, otherwise
1044 * a parity error can occur which causes a panic. A bug with
1045 * southbridge SMBUS.
1046 */
1047 drv_usecwait(15);
1048 status = smbus_get(smbus, SMB_STS);
1049 if (smbus->smbus_polling) {
1050 /*
1051 * If we are polling, then we expect not to
1052 * get the right answer for a while,
1053 * so we don't go on to that error stuff
1054 * until we've polled the status for a
1055 * few times. We check for errors here to save time,
1056 * otherwise we would have to wait for the full
1057 * poll timeout before dealing with them.
1058 */
1059 if (status != (CMD_CMPL|IDLE) &&
1060 (status & (FAILED|BUS_ERR|DRV_ERR)) == 0 &&
1061 smbus->smbus_poll_retries++ < SMBUS_POLL_MAX_RETRIES) {
1062 return (DDI_INTR_CLAIMED);
1063 }
1064 /*
1065 * else either ...
1066 * [] the command has completed, or;
1067 * [] There has been an error, or;
1068 * [] we timed out waiting for something useful
1069 * to happen, so we go on to to the error handling bit that
1070 * follows, * which will reset the controller then restart the
1071 * whole transaction.
1072 *
1073 * In all cases, clear "poll_retries" for the next command or
1074 * retry
1075 */
1076 smbus->smbus_poll_retries = 0;
1077 }
1078
1079 /*
1080 * A bug in southbridge SMBUS sometimes requires a reset. Status
1081 * should NOT be IDLE without any other bit set. If it is, the
1082 * transaction should be restarted.
1083 */
1084
1085 if (status == IDLE) {
1086 (void) sprintf(error_str, "%s bus is idle, ", error_str);
1087 }
1088
1089 if ((status & CMD_CMPL) == 0) {
1090 (void) sprintf(error_str, "%s command failed to complete, ",
1091 error_str);
1092 }
1093 if (status & BUS_ERR) {
1094 (void) sprintf(error_str, "%s bus error, ", error_str);
1095 }
1096 if (status & FAILED) {
1097 (void) sprintf(error_str, "%s failed transaction, ", error_str);
1098 }
1099 if (status & DRV_ERR) {
1100 (void) sprintf(error_str, "%s timeout or bus reset", error_str);
1101 }
1102
1103 if (error_str[0] != '\0') {
1104 (void) sprintf(error_str, "%s %s ", error_str, src);
1105 }
1106
1107 /*
1108 * Clear status to clear the interrupt.
1109 */
1110 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH);
1111 if (error_str[0] != '\0') {
1112 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH);
1113 if (smbus->smbus_retries++ < SMBUS_MAX_RETRIES) {
1114 /*
1115 * XXXX There was a panic here when the
1116 * intr timeout was greater than the timeout
1117 * for the entire transfer.
1118 *
1119 * Restore the value of w_resid before the
1120 * last transaction. r_resid doesn't need to
1121 * be restored because it is only decremented
1122 * after a successful read. Need to do this
1123 * here since smbus_switch() keys off of a
1124 * resid to know whether to call smbus_rd() or
1125 * smbus_wr().
1126 */
1127 tp->i2c_w_resid = smbus->smbus_saved_w_resid;
1128 smbus->smbus_bytes_to_read = 0;
1129
1130 SMBUS_PRINT((PRT_INTR_ERR,
1131 "retrying: %s %s w_resid=%d\n", error_str,
1132 src, tp->i2c_w_resid));
1133 } else {
1134 cmn_err(CE_WARN, "%s max retries exceeded: %s",
1135 smbus->smbus_name, error_str);
1136 /*
1137 * bailing, but first will reset the bus.
1138 */
1139 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH);
1140 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH);
1141 smbus->smbus_cur_tran->i2c_result = I2C_FAILURE;
1142
1143 ret = SMBUS_FAILURE;
1144 }
1145 } else {
1146 smbus->smbus_retries = 0;
1147 }
1148
1149 if (tp != NULL) {
1150 SMBUS_PRINT((PRT_INTR, "flags=%d wresid=%d r_resid=%d %s\n",
1151 tp->i2c_flags, tp->i2c_w_resid, tp->i2c_r_resid, src));
1152 }
1153
1154 if (ret != SMBUS_FAILURE) {
1155 ret = smbus_switch(smbus);
1156 }
1157
1158 if (smbus->smbus_polling) {
1159 if (ret == SMBUS_COMPLETE || ret == SMBUS_FAILURE) {
1160 smbus->smbus_poll_complete = 1;
1161 }
1162 } else {
1163 /*
1164 * Disable previous timeout. In case it was about to fire this
1165 * will let it exit without doing anything.
1166 */
1167 timer_id = smbus->smbus_timeout;
1168 smbus->smbus_timeout = 0;
1169 mutex_exit(&smbus->smbus_imutex);
1170 (void) untimeout(timer_id);
1171 mutex_enter(&smbus->smbus_imutex);
1172 if (ret == SMBUS_COMPLETE || ret == SMBUS_FAILURE) {
1173 cv_signal(&smbus->smbus_icv);
1174 } else {
1175 smbus_interrupts_on(smbus);
1176 smbus->smbus_timeout = timeout(smbus_intr_timeout,
1177 smbus, drv_usectohz(intr_timeout));
1178 SMBUS_PRINT((PRT_INTR, "smbus_intr starting timeout %p "
1179 "%s", smbus->smbus_timeout, src));
1180 }
1181 }
1182
1183 return (DDI_INTR_CLAIMED);
1184 }
1185
1186 /*
1187 * smbus_wr handles writes to the smbus. Unlike true I2C busses
1188 * such as provided by pcf8584, smbus attaches a start and stop bit for each
1189 * transaction, so this limits writes to the maximum number of bytes
1190 * in a single transaction, which is 33.
1191 *
1192 * If more than 33 bytes are contained in the transfer, a non-zero
1193 * residual has to be returned, and the calling driver has to restart
1194 * another transaction to complete writing out any remaining data. The
1195 * reason for this is that most devices require a register/offset as the
1196 * first byte to be written for each SMBUS transaction.
1197 */
1198 static int
smbus_wr(smbus_t * smbus)1199 smbus_wr(smbus_t *smbus)
1200 {
1201 i2c_transfer_t *tp = smbus->smbus_cur_tran;
1202 uint8_t addr = smbus_dip_to_addr(smbus->smbus_cur_dip);
1203 int bytes_written = 0;
1204 uint8_t a;
1205 uint8_t b;
1206
1207 if (tp->i2c_w_resid != tp->i2c_wlen) {
1208 return (SMBUS_COMPLETE);
1209 }
1210
1211 SMBUS_PRINT((PRT_WR, "smbus_wr: addr = %x resid = %d\n",
1212 addr, tp->i2c_w_resid));
1213
1214 smbus_put(smbus, SMB_STS, 0xff, 0);
1215
1216 /*
1217 * Address must be re-written for each command and it has to
1218 * be written before SMB_TYP.
1219 */
1220 smbus_put(smbus, DEV_ADDR, addr, 0);
1221
1222 switch (tp->i2c_w_resid) {
1223
1224 case 1:
1225 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--];
1226 smbus_put(smbus, SMB_CMD, a, 0);
1227 smbus_put(smbus, SMB_TYP, SEND_BYTE, 0);
1228 SMBUS_PRINT((PRT_WR, "smbus_wr: send one byte:"
1229 " %d\n", a));
1230 break;
1231 case 2:
1232 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--];
1233 smbus_put(smbus, SMB_CMD, a, 0);
1234
1235 b = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--];
1236 smbus_put(smbus, DEV_DATA0, b, 0);
1237 smbus_put(smbus, SMB_TYP, WR_BYTE, 0);
1238 SMBUS_PRINT((PRT_WR, "smbus_wr: send two bytes:"
1239 " %d %d\n", a, b));
1240 break;
1241
1242 default:
1243 /*
1244 * Write out as many bytes as possible in a single command.
1245 * Note that BLK_DATA just creats a byte stream. ie, the
1246 * smbus protocol is not used or interpreted by this driver.
1247 */
1248 smbus_put(smbus, SMB_TYP, WR_BLK, 0);
1249 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--];
1250
1251 smbus_put(smbus, SMB_CMD, a, 0);
1252
1253 SMBUS_PRINT((PRT_WR, "smbus_wr: send multiple bytes: "));
1254 SMBUS_PRINT((PRT_WR, "%x ", a));
1255
1256 while (tp->i2c_w_resid != 0) {
1257 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--];
1258 smbus_put(smbus, BLK_DATA, a, 0);
1259 SMBUS_PRINT((PRT_WR, "%x ", a));
1260 /*
1261 * Note that MAX_BLK_SEND defines how many bytes may
1262 * be sent to the BLK_DATA register. The leading byte
1263 * already sent to the SMB_CMD register doesn't count
1264 * But ALL the BLK_DATA bytes count so pre-increment
1265 * bytes_written before testing.
1266 */
1267 if (++bytes_written == MAX_BLK_SEND) {
1268 break;
1269 }
1270 }
1271 SMBUS_PRINT((PRT_WR, "\n"));
1272 smbus_put(smbus, DEV_DATA0, bytes_written, 0);
1273 break;
1274 }
1275
1276 /*
1277 * writing anything to port reg starts transfer
1278 */
1279 smbus_put(smbus, STR_PORT, 0, SMBUS_FLUSH);
1280
1281 return (SMBUS_PENDING);
1282 }
1283
1284 /*
1285 * smbus_rd handles reads to the smbus. Unlike a true I2C bus
1286 * such as provided by pcf8584, smbus attaches a start and stop bit
1287 * for each transaction, which limits reads to the maximum number of
1288 * bytes in a single SMBUS transaction. (Block reads don't
1289 * seem to work on smbus, and the southbridge documentation is poor).
1290 *
1291 * It doesn't appear that reads spanning multiple I2C transactions
1292 * (ie each with a start-stop) affects the transfer when reading
1293 * multiple bytes from devices with internal counters. The counter
1294 * is correctly maintained.
1295 *
1296 * RD_WORD and RD_BYTE write out the byte in the SMB_CMD register
1297 * before reading, so RCV_BYTE is used instead.
1298 *
1299 * Multi-byte reads iniatiate a SMBUS transaction for each byte to be
1300 * received. Because register/offset information doesn't need to
1301 * be resent for each I2C transaction (as opposed to when writing data),
1302 * the driver can continue reading data in separate SMBUS transactions
1303 * until the requested buffer is filled.
1304 */
1305 static int
smbus_rd(smbus_t * smbus)1306 smbus_rd(smbus_t *smbus)
1307 {
1308 i2c_transfer_t *tp = smbus->smbus_cur_tran;
1309 uint8_t addr = smbus_dip_to_addr(smbus->smbus_cur_dip);
1310
1311 if (smbus->smbus_bytes_to_read == 1) {
1312 tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid] =
1313 smbus_get(smbus, DEV_DATA0);
1314 SMBUS_PRINT((PRT_RD, "smbus_rd: data in = %d\n",
1315 tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid]));
1316 tp->i2c_r_resid--;
1317 smbus->smbus_bytes_to_read = 0;
1318
1319 if (tp->i2c_r_resid == 0) {
1320 return (SMBUS_COMPLETE);
1321 }
1322 }
1323
1324 /*
1325 * Address must be re-written for each command. It must
1326 * be written before SMB_TYP.
1327 */
1328 smbus_put(smbus, DEV_ADDR, addr | I2C_READ, 0);
1329
1330 if (tp->i2c_r_resid == 0) {
1331 smbus->smbus_bytes_to_read = 0;
1332
1333 return (SMBUS_COMPLETE);
1334 }
1335
1336 smbus->smbus_bytes_to_read = 1;
1337 smbus_put(smbus, SMB_TYP, RCV_BYTE, 0);
1338
1339 smbus_put(smbus, SMB_STS, 0xff, 0);
1340
1341 SMBUS_PRINT((PRT_RD, "smbus_rd: starting a read addr = %x resid = %d "
1342 "bytes_to_read=%d\n", addr, tp->i2c_r_resid,
1343 smbus->smbus_bytes_to_read));
1344
1345 smbus_put(smbus, STR_PORT, 0, SMBUS_FLUSH);
1346
1347 return (SMBUS_PENDING);
1348 }
1349