1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 *
4 * Shared code by both skx_edac and i10nm_edac. Originally split out
5 * from the skx_edac driver.
6 *
7 * This file is linked into both skx_edac and i10nm_edac drivers. In
8 * order to avoid link errors, this file must be like a pure library
9 * without including symbols and defines which would otherwise conflict,
10 * when linked once into a module and into a built-in object, at the
11 * same time. For example, __this_module symbol references when that
12 * file is being linked into a built-in object.
13 *
14 * Copyright (c) 2018, Intel Corporation.
15 */
16
17 #include <linux/acpi.h>
18 #include <linux/dmi.h>
19 #include <linux/adxl.h>
20 #include <acpi/nfit.h>
21 #include <asm/mce.h>
22 #include <asm/uv/uv.h>
23 #include "edac_module.h"
24 #include "skx_common.h"
25
26 static const char * const component_names[] = {
27 [INDEX_SOCKET] = "ProcessorSocketId",
28 [INDEX_MEMCTRL] = "MemoryControllerId",
29 [INDEX_CHANNEL] = "ChannelId",
30 [INDEX_DIMM] = "DimmSlotId",
31 [INDEX_CS] = "ChipSelect",
32 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId",
33 [INDEX_NM_CHANNEL] = "NmChannelId",
34 [INDEX_NM_DIMM] = "NmDimmSlotId",
35 [INDEX_NM_CS] = "NmChipSelect",
36 };
37
38 static int component_indices[ARRAY_SIZE(component_names)];
39 static int adxl_component_count;
40 static const char * const *adxl_component_names;
41 static u64 *adxl_values;
42 static char *adxl_msg;
43 static unsigned long adxl_nm_bitmap;
44
45 static char skx_msg[MSG_SIZE];
46 static skx_decode_f driver_decode;
47 static skx_show_retry_log_f skx_show_retry_rd_err_log;
48 static u64 skx_tolm, skx_tohm;
49 static LIST_HEAD(dev_edac_list);
50 static bool skx_mem_cfg_2lm;
51 static struct res_config *skx_res_cfg;
52
skx_adxl_get(void)53 int skx_adxl_get(void)
54 {
55 const char * const *names;
56 int i, j;
57
58 names = adxl_get_component_names();
59 if (!names) {
60 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
61 return -ENODEV;
62 }
63
64 for (i = 0; i < INDEX_MAX; i++) {
65 for (j = 0; names[j]; j++) {
66 if (!strcmp(component_names[i], names[j])) {
67 component_indices[i] = j;
68
69 if (i >= INDEX_NM_FIRST)
70 adxl_nm_bitmap |= 1 << i;
71
72 break;
73 }
74 }
75
76 if (!names[j] && i < INDEX_NM_FIRST)
77 goto err;
78 }
79
80 if (skx_mem_cfg_2lm) {
81 if (!adxl_nm_bitmap)
82 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n");
83 else
84 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap);
85 }
86
87 adxl_component_names = names;
88 while (*names++)
89 adxl_component_count++;
90
91 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
92 GFP_KERNEL);
93 if (!adxl_values) {
94 adxl_component_count = 0;
95 return -ENOMEM;
96 }
97
98 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
99 if (!adxl_msg) {
100 adxl_component_count = 0;
101 kfree(adxl_values);
102 return -ENOMEM;
103 }
104
105 return 0;
106 err:
107 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
108 component_names[i]);
109 for (j = 0; names[j]; j++)
110 skx_printk(KERN_CONT, "%s ", names[j]);
111 skx_printk(KERN_CONT, "\n");
112
113 return -ENODEV;
114 }
115 EXPORT_SYMBOL_GPL(skx_adxl_get);
116
skx_adxl_put(void)117 void skx_adxl_put(void)
118 {
119 adxl_component_count = 0;
120 kfree(adxl_values);
121 kfree(adxl_msg);
122 }
123 EXPORT_SYMBOL_GPL(skx_adxl_put);
124
skx_init_mc_mapping(struct skx_dev * d)125 static void skx_init_mc_mapping(struct skx_dev *d)
126 {
127 /*
128 * By default, the BIOS presents all memory controllers within each
129 * socket to the EDAC driver. The physical indices are the same as
130 * the logical indices of the memory controllers enumerated by the
131 * EDAC driver.
132 */
133 for (int i = 0; i < NUM_IMC; i++)
134 d->mc_mapping[i] = i;
135 }
136
skx_set_mc_mapping(struct skx_dev * d,u8 pmc,u8 lmc)137 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc)
138 {
139 edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n",
140 pmc, lmc);
141
142 d->mc_mapping[pmc] = lmc;
143 }
144 EXPORT_SYMBOL_GPL(skx_set_mc_mapping);
145
skx_get_mc_mapping(struct skx_dev * d,u8 pmc)146 static u8 skx_get_mc_mapping(struct skx_dev *d, u8 pmc)
147 {
148 edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n",
149 pmc, d->mc_mapping[pmc]);
150
151 return d->mc_mapping[pmc];
152 }
153
skx_adxl_decode(struct decoded_addr * res,enum error_source err_src)154 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src)
155 {
156 struct skx_dev *d;
157 int i, len = 0;
158
159 if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
160 res->addr < BIT_ULL(32))) {
161 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
162 return false;
163 }
164
165 if (adxl_decode(res->addr, adxl_values)) {
166 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
167 return false;
168 }
169
170 /*
171 * GNR with a Flat2LM memory configuration may mistakenly classify
172 * a near-memory error(DDR5) as a far-memory error(CXL), resulting
173 * in the incorrect selection of decoded ADXL components.
174 * To address this, prefetch the decoded far-memory controller ID
175 * and adjust the error source to near-memory if the far-memory
176 * controller ID is invalid.
177 */
178 if (skx_res_cfg && skx_res_cfg->type == GNR && err_src == ERR_SRC_2LM_FM) {
179 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
180 if (res->imc == -1) {
181 err_src = ERR_SRC_2LM_NM;
182 edac_dbg(0, "Adjust the error source to near-memory.\n");
183 }
184 }
185
186 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
187 if (err_src == ERR_SRC_2LM_NM) {
188 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ?
189 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1;
190 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ?
191 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1;
192 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ?
193 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
194 res->cs = (adxl_nm_bitmap & BIT_NM_CS) ?
195 (int)adxl_values[component_indices[INDEX_NM_CS]] : -1;
196 } else {
197 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
198 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
199 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
200 res->cs = (int)adxl_values[component_indices[INDEX_CS]];
201 }
202
203 if (res->imc > NUM_IMC - 1 || res->imc < 0) {
204 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
205 return false;
206 }
207
208 list_for_each_entry(d, &dev_edac_list, list) {
209 if (d->imc[0].src_id == res->socket) {
210 res->dev = d;
211 break;
212 }
213 }
214
215 if (!res->dev) {
216 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
217 res->socket, res->imc);
218 return false;
219 }
220
221 res->imc = skx_get_mc_mapping(d, res->imc);
222
223 for (i = 0; i < adxl_component_count; i++) {
224 if (adxl_values[i] == ~0x0ull)
225 continue;
226
227 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
228 adxl_component_names[i], adxl_values[i]);
229 if (MSG_SIZE - len <= 0)
230 break;
231 }
232
233 res->decoded_by_adxl = true;
234
235 return true;
236 }
237
skx_set_mem_cfg(bool mem_cfg_2lm)238 void skx_set_mem_cfg(bool mem_cfg_2lm)
239 {
240 skx_mem_cfg_2lm = mem_cfg_2lm;
241 }
242 EXPORT_SYMBOL_GPL(skx_set_mem_cfg);
243
skx_set_res_cfg(struct res_config * cfg)244 void skx_set_res_cfg(struct res_config *cfg)
245 {
246 skx_res_cfg = cfg;
247 }
248 EXPORT_SYMBOL_GPL(skx_set_res_cfg);
249
skx_set_decode(skx_decode_f decode,skx_show_retry_log_f show_retry_log)250 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
251 {
252 driver_decode = decode;
253 skx_show_retry_rd_err_log = show_retry_log;
254 }
255 EXPORT_SYMBOL_GPL(skx_set_decode);
256
skx_get_pkg_id(struct skx_dev * d,u8 * id)257 static int skx_get_pkg_id(struct skx_dev *d, u8 *id)
258 {
259 int node;
260 int cpu;
261
262 node = pcibus_to_node(d->util_all->bus);
263 if (numa_valid_node(node)) {
264 for_each_cpu(cpu, cpumask_of_pcibus(d->util_all->bus)) {
265 struct cpuinfo_x86 *c = &cpu_data(cpu);
266
267 if (c->initialized && cpu_to_node(cpu) == node) {
268 *id = c->topo.pkg_id;
269 return 0;
270 }
271 }
272 }
273
274 skx_printk(KERN_ERR, "Failed to get package ID from NUMA information\n");
275 return -ENODEV;
276 }
277
skx_get_src_id(struct skx_dev * d,int off,u8 * id)278 int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
279 {
280 u32 reg;
281
282 /*
283 * The 3-bit source IDs in PCI configuration space registers are limited
284 * to 8 unique IDs, and each ID is local to a UPI/QPI domain.
285 *
286 * Source IDs cannot be used to map devices to sockets on UV systems
287 * because they can exceed 8 sockets and have multiple UPI/QPI domains
288 * with identical, repeating source IDs.
289 */
290 if (is_uv_system())
291 return skx_get_pkg_id(d, id);
292
293 if (pci_read_config_dword(d->util_all, off, ®)) {
294 skx_printk(KERN_ERR, "Failed to read src id\n");
295 return -ENODEV;
296 }
297
298 *id = GET_BITFIELD(reg, 12, 14);
299 return 0;
300 }
301 EXPORT_SYMBOL_GPL(skx_get_src_id);
302
get_width(u32 mtr)303 static int get_width(u32 mtr)
304 {
305 switch (GET_BITFIELD(mtr, 8, 9)) {
306 case 0:
307 return DEV_X4;
308 case 1:
309 return DEV_X8;
310 case 2:
311 return DEV_X16;
312 }
313 return DEV_UNKNOWN;
314 }
315
316 /*
317 * We use the per-socket device @cfg->did to count how many sockets are present,
318 * and to detemine which PCI buses are associated with each socket. Allocate
319 * and build the full list of all the skx_dev structures that we need here.
320 */
skx_get_all_bus_mappings(struct res_config * cfg,struct list_head ** list)321 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
322 {
323 struct pci_dev *pdev, *prev;
324 struct skx_dev *d;
325 u32 reg;
326 int ndev = 0;
327
328 prev = NULL;
329 for (;;) {
330 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
331 if (!pdev)
332 break;
333 ndev++;
334 d = kzalloc(sizeof(*d), GFP_KERNEL);
335 if (!d) {
336 pci_dev_put(pdev);
337 return -ENOMEM;
338 }
339
340 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) {
341 kfree(d);
342 pci_dev_put(pdev);
343 skx_printk(KERN_ERR, "Failed to read bus idx\n");
344 return -ENODEV;
345 }
346
347 d->bus[0] = GET_BITFIELD(reg, 0, 7);
348 d->bus[1] = GET_BITFIELD(reg, 8, 15);
349 if (cfg->type == SKX) {
350 d->seg = pci_domain_nr(pdev->bus);
351 d->bus[2] = GET_BITFIELD(reg, 16, 23);
352 d->bus[3] = GET_BITFIELD(reg, 24, 31);
353 } else {
354 d->seg = GET_BITFIELD(reg, 16, 23);
355 }
356
357 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
358 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
359 list_add_tail(&d->list, &dev_edac_list);
360 prev = pdev;
361
362 skx_init_mc_mapping(d);
363 }
364
365 if (list)
366 *list = &dev_edac_list;
367 return ndev;
368 }
369 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings);
370
skx_get_hi_lo(unsigned int did,int off[],u64 * tolm,u64 * tohm)371 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
372 {
373 struct pci_dev *pdev;
374 u32 reg;
375
376 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
377 if (!pdev) {
378 edac_dbg(2, "Can't get tolm/tohm\n");
379 return -ENODEV;
380 }
381
382 if (pci_read_config_dword(pdev, off[0], ®)) {
383 skx_printk(KERN_ERR, "Failed to read tolm\n");
384 goto fail;
385 }
386 skx_tolm = reg;
387
388 if (pci_read_config_dword(pdev, off[1], ®)) {
389 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
390 goto fail;
391 }
392 skx_tohm = reg;
393
394 if (pci_read_config_dword(pdev, off[2], ®)) {
395 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
396 goto fail;
397 }
398 skx_tohm |= (u64)reg << 32;
399
400 pci_dev_put(pdev);
401 *tolm = skx_tolm;
402 *tohm = skx_tohm;
403 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
404 return 0;
405 fail:
406 pci_dev_put(pdev);
407 return -ENODEV;
408 }
409 EXPORT_SYMBOL_GPL(skx_get_hi_lo);
410
skx_get_dimm_attr(u32 reg,int lobit,int hibit,int add,int minval,int maxval,const char * name)411 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
412 int minval, int maxval, const char *name)
413 {
414 u32 val = GET_BITFIELD(reg, lobit, hibit);
415
416 if (val < minval || val > maxval) {
417 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
418 return -EINVAL;
419 }
420 return val + add;
421 }
422
423 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
424 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
425 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
426
skx_get_dimm_info(u32 mtr,u32 mcmtr,u32 amap,struct dimm_info * dimm,struct skx_imc * imc,int chan,int dimmno,struct res_config * cfg)427 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
428 struct skx_imc *imc, int chan, int dimmno,
429 struct res_config *cfg)
430 {
431 int banks, ranks, rows, cols, npages;
432 enum mem_type mtype;
433 u64 size;
434
435 ranks = numrank(mtr);
436 rows = numrow(mtr);
437 cols = imc->hbm_mc ? 6 : numcol(mtr);
438
439 if (imc->hbm_mc) {
440 banks = 32;
441 mtype = MEM_HBM2;
442 } else if (cfg->support_ddr5) {
443 banks = 32;
444 mtype = MEM_DDR5;
445 } else {
446 banks = 16;
447 mtype = MEM_DDR4;
448 }
449
450 /*
451 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
452 */
453 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
454 npages = MiB_TO_PAGES(size);
455
456 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
457 imc->mc, chan, dimmno, size, npages,
458 banks, 1 << ranks, rows, cols);
459
460 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
461 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
462 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
463 imc->chan[chan].dimms[dimmno].rowbits = rows;
464 imc->chan[chan].dimms[dimmno].colbits = cols;
465
466 dimm->nr_pages = npages;
467 dimm->grain = 32;
468 dimm->dtype = get_width(mtr);
469 dimm->mtype = mtype;
470 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
471
472 if (imc->hbm_mc)
473 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
474 imc->src_id, imc->lmc, chan);
475 else
476 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
477 imc->src_id, imc->lmc, chan, dimmno);
478
479 return 1;
480 }
481 EXPORT_SYMBOL_GPL(skx_get_dimm_info);
482
skx_get_nvdimm_info(struct dimm_info * dimm,struct skx_imc * imc,int chan,int dimmno,const char * mod_str)483 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
484 int chan, int dimmno, const char *mod_str)
485 {
486 int smbios_handle;
487 u32 dev_handle;
488 u16 flags;
489 u64 size = 0;
490
491 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
492 imc->src_id, 0);
493
494 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
495 if (smbios_handle == -EOPNOTSUPP) {
496 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
497 goto unknown_size;
498 }
499
500 if (smbios_handle < 0) {
501 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
502 goto unknown_size;
503 }
504
505 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
506 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
507 goto unknown_size;
508 }
509
510 size = dmi_memdev_size(smbios_handle);
511 if (size == ~0ull)
512 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
513 dev_handle, smbios_handle);
514
515 unknown_size:
516 dimm->nr_pages = size >> PAGE_SHIFT;
517 dimm->grain = 32;
518 dimm->dtype = DEV_UNKNOWN;
519 dimm->mtype = MEM_NVDIMM;
520 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
521
522 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
523 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
524
525 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
526 imc->src_id, imc->lmc, chan, dimmno);
527
528 return (size == 0 || size == ~0ull) ? 0 : 1;
529 }
530 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info);
531
skx_register_mci(struct skx_imc * imc,struct pci_dev * pdev,const char * ctl_name,const char * mod_str,get_dimm_config_f get_dimm_config,struct res_config * cfg)532 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
533 const char *ctl_name, const char *mod_str,
534 get_dimm_config_f get_dimm_config,
535 struct res_config *cfg)
536 {
537 struct mem_ctl_info *mci;
538 struct edac_mc_layer layers[2];
539 struct skx_pvt *pvt;
540 int rc;
541
542 /* Allocate a new MC control structure */
543 layers[0].type = EDAC_MC_LAYER_CHANNEL;
544 layers[0].size = NUM_CHANNELS;
545 layers[0].is_virt_csrow = false;
546 layers[1].type = EDAC_MC_LAYER_SLOT;
547 layers[1].size = NUM_DIMMS;
548 layers[1].is_virt_csrow = true;
549 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
550 sizeof(struct skx_pvt));
551
552 if (unlikely(!mci))
553 return -ENOMEM;
554
555 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
556
557 /* Associate skx_dev and mci for future usage */
558 imc->mci = mci;
559 pvt = mci->pvt_info;
560 pvt->imc = imc;
561
562 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
563 imc->src_id, imc->lmc);
564 if (!mci->ctl_name) {
565 rc = -ENOMEM;
566 goto fail0;
567 }
568
569 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
570 if (cfg->support_ddr5)
571 mci->mtype_cap |= MEM_FLAG_DDR5;
572 mci->edac_ctl_cap = EDAC_FLAG_NONE;
573 mci->edac_cap = EDAC_FLAG_NONE;
574 mci->mod_name = mod_str;
575 mci->dev_name = pci_name(pdev);
576 mci->ctl_page_to_phys = NULL;
577
578 rc = get_dimm_config(mci, cfg);
579 if (rc < 0)
580 goto fail;
581
582 /* Record ptr to the generic device */
583 mci->pdev = &pdev->dev;
584
585 /* Add this new MC control structure to EDAC's list of MCs */
586 if (unlikely(edac_mc_add_mc(mci))) {
587 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
588 rc = -EINVAL;
589 goto fail;
590 }
591
592 return 0;
593
594 fail:
595 kfree(mci->ctl_name);
596 fail0:
597 edac_mc_free(mci);
598 imc->mci = NULL;
599 return rc;
600 }
601 EXPORT_SYMBOL_GPL(skx_register_mci);
602
skx_unregister_mci(struct skx_imc * imc)603 static void skx_unregister_mci(struct skx_imc *imc)
604 {
605 struct mem_ctl_info *mci = imc->mci;
606
607 if (!mci)
608 return;
609
610 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
611
612 /* Remove MC sysfs nodes */
613 edac_mc_del_mc(mci->pdev);
614
615 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
616 kfree(mci->ctl_name);
617 edac_mc_free(mci);
618 }
619
skx_mce_output_error(struct mem_ctl_info * mci,const struct mce * m,struct decoded_addr * res)620 static void skx_mce_output_error(struct mem_ctl_info *mci,
621 const struct mce *m,
622 struct decoded_addr *res)
623 {
624 enum hw_event_mc_err_type tp_event;
625 char *optype;
626 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
627 bool overflow = GET_BITFIELD(m->status, 62, 62);
628 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
629 bool scrub_err = false;
630 bool recoverable;
631 int len;
632 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
633 u32 mscod = GET_BITFIELD(m->status, 16, 31);
634 u32 errcode = GET_BITFIELD(m->status, 0, 15);
635 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
636
637 recoverable = GET_BITFIELD(m->status, 56, 56);
638
639 if (uncorrected_error) {
640 core_err_cnt = 1;
641 if (ripv) {
642 tp_event = HW_EVENT_ERR_UNCORRECTED;
643 } else {
644 tp_event = HW_EVENT_ERR_FATAL;
645 }
646 } else {
647 tp_event = HW_EVENT_ERR_CORRECTED;
648 }
649
650 switch (optypenum) {
651 case 0:
652 optype = "generic undef request error";
653 break;
654 case 1:
655 optype = "memory read error";
656 break;
657 case 2:
658 optype = "memory write error";
659 break;
660 case 3:
661 optype = "addr/cmd error";
662 break;
663 case 4:
664 optype = "memory scrubbing error";
665 scrub_err = true;
666 break;
667 default:
668 optype = "reserved";
669 break;
670 }
671
672 if (res->decoded_by_adxl) {
673 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
674 overflow ? " OVERFLOW" : "",
675 (uncorrected_error && recoverable) ? " recoverable" : "",
676 mscod, errcode, adxl_msg);
677 } else {
678 len = snprintf(skx_msg, MSG_SIZE,
679 "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x",
680 overflow ? " OVERFLOW" : "",
681 (uncorrected_error && recoverable) ? " recoverable" : "",
682 mscod, errcode,
683 res->socket, res->imc, res->rank,
684 res->row, res->column, res->bank_address, res->bank_group);
685 }
686
687 if (skx_show_retry_rd_err_log)
688 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err);
689
690 edac_dbg(0, "%s\n", skx_msg);
691
692 /* Call the helper to output message */
693 edac_mc_handle_error(tp_event, mci, core_err_cnt,
694 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
695 res->channel, res->dimm, -1,
696 optype, skx_msg);
697 }
698
skx_error_source(const struct mce * m)699 static enum error_source skx_error_source(const struct mce *m)
700 {
701 u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK;
702
703 if (errcode != MCACOD_MEM_CTL_ERR && errcode != MCACOD_EXT_MEM_ERR)
704 return ERR_SRC_NOT_MEMORY;
705
706 if (!skx_mem_cfg_2lm)
707 return ERR_SRC_1LM;
708
709 if (errcode == MCACOD_EXT_MEM_ERR)
710 return ERR_SRC_2LM_NM;
711
712 return ERR_SRC_2LM_FM;
713 }
714
skx_mce_check_error(struct notifier_block * nb,unsigned long val,void * data)715 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
716 void *data)
717 {
718 struct mce *mce = (struct mce *)data;
719 enum error_source err_src;
720 struct decoded_addr res;
721 struct mem_ctl_info *mci;
722 char *type;
723
724 if (mce->kflags & MCE_HANDLED_CEC)
725 return NOTIFY_DONE;
726
727 err_src = skx_error_source(mce);
728
729 /* Ignore unless this is memory related with an address */
730 if (err_src == ERR_SRC_NOT_MEMORY || !(mce->status & MCI_STATUS_ADDRV))
731 return NOTIFY_DONE;
732
733 memset(&res, 0, sizeof(res));
734 res.mce = mce;
735 res.addr = mce->addr & MCI_ADDR_PHYSADDR;
736 if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) {
737 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank);
738 return NOTIFY_DONE;
739 }
740
741 /* Try driver decoder first */
742 if (!(driver_decode && driver_decode(&res))) {
743 /* Then try firmware decoder (ACPI DSM methods) */
744 if (!(adxl_component_count && skx_adxl_decode(&res, err_src)))
745 return NOTIFY_DONE;
746 }
747
748 mci = res.dev->imc[res.imc].mci;
749
750 if (!mci)
751 return NOTIFY_DONE;
752
753 if (mce->mcgstatus & MCG_STATUS_MCIP)
754 type = "Exception";
755 else
756 type = "Event";
757
758 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
759
760 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
761 "Bank %d: 0x%llx\n", mce->extcpu, type,
762 mce->mcgstatus, mce->bank, mce->status);
763 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
764 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
765 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
766
767 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
768 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
769 mce->time, mce->socketid, mce->apicid);
770
771 skx_mce_output_error(mci, mce, &res);
772
773 mce->kflags |= MCE_HANDLED_EDAC;
774 return NOTIFY_DONE;
775 }
776 EXPORT_SYMBOL_GPL(skx_mce_check_error);
777
skx_remove(void)778 void skx_remove(void)
779 {
780 int i, j;
781 struct skx_dev *d, *tmp;
782
783 edac_dbg(0, "\n");
784
785 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
786 list_del(&d->list);
787 for (i = 0; i < NUM_IMC; i++) {
788 if (d->imc[i].mci)
789 skx_unregister_mci(&d->imc[i]);
790
791 if (d->imc[i].mdev)
792 pci_dev_put(d->imc[i].mdev);
793
794 if (d->imc[i].mbase)
795 iounmap(d->imc[i].mbase);
796
797 for (j = 0; j < NUM_CHANNELS; j++) {
798 if (d->imc[i].chan[j].cdev)
799 pci_dev_put(d->imc[i].chan[j].cdev);
800 }
801 }
802 if (d->util_all)
803 pci_dev_put(d->util_all);
804 if (d->pcu_cr3)
805 pci_dev_put(d->pcu_cr3);
806 if (d->sad_all)
807 pci_dev_put(d->sad_all);
808 if (d->uracu)
809 pci_dev_put(d->uracu);
810
811 kfree(d);
812 }
813 }
814 EXPORT_SYMBOL_GPL(skx_remove);
815
816 #ifdef CONFIG_EDAC_DEBUG
817 /*
818 * Debug feature.
819 * Exercise the address decode logic by writing an address to
820 * /sys/kernel/debug/edac/{skx,i10nm}_test/addr.
821 */
822 static struct dentry *skx_test;
823
debugfs_u64_set(void * data,u64 val)824 static int debugfs_u64_set(void *data, u64 val)
825 {
826 struct mce m;
827
828 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
829
830 memset(&m, 0, sizeof(m));
831 /* ADDRV + MemRd + Unknown channel */
832 m.status = MCI_STATUS_ADDRV + 0x90;
833 /* One corrected error */
834 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
835 m.addr = val;
836 skx_mce_check_error(NULL, 0, &m);
837
838 return 0;
839 }
840 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
841
skx_setup_debug(const char * name)842 void skx_setup_debug(const char *name)
843 {
844 skx_test = edac_debugfs_create_dir(name);
845 if (!skx_test)
846 return;
847
848 if (!edac_debugfs_create_file("addr", 0200, skx_test,
849 NULL, &fops_u64_wo)) {
850 debugfs_remove(skx_test);
851 skx_test = NULL;
852 }
853 }
854 EXPORT_SYMBOL_GPL(skx_setup_debug);
855
skx_teardown_debug(void)856 void skx_teardown_debug(void)
857 {
858 debugfs_remove_recursive(skx_test);
859 }
860 EXPORT_SYMBOL_GPL(skx_teardown_debug);
861 #endif /*CONFIG_EDAC_DEBUG*/
862
863 MODULE_LICENSE("GPL v2");
864 MODULE_AUTHOR("Tony Luck");
865 MODULE_DESCRIPTION("MC Driver for Intel server processors");
866