1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
3 /**
4 *****************************************************************************
5 * @file icp_qat_hw_2x_comp.h
6 * @defgroup ICP QAT HW accessors for using the for 2.x Compression Slice
7 * definitions
8 * @ingroup icp_qat_hw_2x_comp
9 * @description
10 * This file documents definitions for the QAT HW COMP SLICE
11 *
12 *****************************************************************************/
13
14 #ifndef _ICP_QAT_HW_20_COMP_H_
15 #define _ICP_QAT_HW_20_COMP_H_
16
17 #include "icp_qat_hw_20_comp_defs.h" /* For HW definitions */
18 #include "icp_qat_fw.h" /* For Set Field Macros. */
19
20
21 #define BYTE_SWAP_32 __builtin_bswap32
22
23 /**
24 *****************************************************************************
25 * @ingroup icp_qat_fw_comn
26 *
27 * @description
28 * Definition of the hw config csr. This representation has to be further
29 * processed by the corresponding config build function.
30 *
31 *****************************************************************************/
32 typedef struct icp_qat_hw_comp_20_config_csr_lower_s {
33 /* Fields programmable directly by the SW. */
34 icp_qat_hw_comp_20_extended_delay_match_mode_t edmm;
35 icp_qat_hw_comp_20_hw_comp_format_t algo;
36 icp_qat_hw_comp_20_search_depth_t sd;
37 icp_qat_hw_comp_20_hbs_control_t hbs;
38 /* Fields programmable directly by the FW. */
39 /* Block Drop enable. (Set by FW) */
40 icp_qat_hw_comp_20_abd_t abd;
41 icp_qat_hw_comp_20_lllbd_ctrl_t lllbd;
42 /* Advanced HW control (Set to default vals) */
43 icp_qat_hw_comp_20_min_match_control_t mmctrl;
44 icp_qat_hw_comp_20_skip_hash_collision_t hash_col;
45 icp_qat_hw_comp_20_skip_hash_update_t hash_update;
46 icp_qat_hw_comp_20_byte_skip_t skip_ctrl;
47
48 } icp_qat_hw_comp_20_config_csr_lower_t;
49
50 /**
51 *****************************************************************************
52 * @ingroup icp_qat_fw_comn
53 *
54 * @description
55 * Build the longword as expected by the HW
56 *
57 *****************************************************************************/
58 static inline uint32_t
ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr)59 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr)
60 {
61 uint32_t val32 = 0;
62 /* Programmable values */
63 QAT_FIELD_SET(val32,
64 csr.algo,
65 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
66 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
67
68 QAT_FIELD_SET(val32,
69 csr.sd,
70 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
71 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
72
73 QAT_FIELD_SET(
74 val32,
75 csr.edmm,
76 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
77 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
78
79 QAT_FIELD_SET(val32,
80 csr.hbs,
81 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
82 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
83
84 QAT_FIELD_SET(val32,
85 csr.mmctrl,
86 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
87 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
88
89 QAT_FIELD_SET(val32,
90 csr.hash_col,
91 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
92 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
93
94 QAT_FIELD_SET(val32,
95 csr.hash_update,
96 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
97 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
98
99 QAT_FIELD_SET(val32,
100 csr.skip_ctrl,
101 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
102 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
103 /* Default values. */
104
105 QAT_FIELD_SET(val32,
106 csr.abd,
107 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
108 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
109
110 QAT_FIELD_SET(val32,
111 csr.lllbd,
112 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
113 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
114
115 return BYTE_SWAP_32(val32);
116 }
117
118 /**
119 *****************************************************************************
120 * @ingroup icp_qat_fw_comn
121 *
122 * @description
123 * Definition of the hw config csr. This representation has to be further
124 * processed by the corresponding config build function.
125 *
126 *****************************************************************************/
127 typedef struct icp_qat_hw_comp_20_config_csr_upper_s {
128 icp_qat_hw_comp_20_scb_control_t scb_ctrl;
129 icp_qat_hw_comp_20_rmb_control_t rmb_ctrl;
130 icp_qat_hw_comp_20_som_control_t som_ctrl;
131 icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl;
132 icp_qat_hw_comp_20_scb_unload_control_t scb_unload_ctrl;
133 icp_qat_hw_comp_20_disable_token_fusion_control_t
134 disable_token_fusion_ctrl;
135 icp_qat_hw_comp_20_lbms_t lbms;
136 icp_qat_hw_comp_20_scb_mode_reset_mask_t scb_mode_reset;
137 uint16_t lazy;
138 uint16_t nice;
139 } icp_qat_hw_comp_20_config_csr_upper_t;
140
141 /**
142 *****************************************************************************
143 * @ingroup icp_qat_fw_comn
144 *
145 * @description
146 * Build the longword as expected by the HW
147 *
148 *****************************************************************************/
149 static inline uint32_t
ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr)150 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr)
151 {
152 uint32_t val32 = 0;
153
154 QAT_FIELD_SET(val32,
155 csr.scb_ctrl,
156 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,
157 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);
158
159 QAT_FIELD_SET(val32,
160 csr.rmb_ctrl,
161 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,
162 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);
163
164 QAT_FIELD_SET(val32,
165 csr.som_ctrl,
166 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,
167 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);
168
169 QAT_FIELD_SET(val32,
170 csr.skip_hash_ctrl,
171 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,
172 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);
173
174 QAT_FIELD_SET(val32,
175 csr.scb_unload_ctrl,
176 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,
177 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);
178
179 QAT_FIELD_SET(
180 val32,
181 csr.disable_token_fusion_ctrl,
182 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,
183 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);
184
185 QAT_FIELD_SET(val32,
186 csr.lbms,
187 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,
188 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);
189
190 QAT_FIELD_SET(val32,
191 csr.scb_mode_reset,
192 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,
193 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);
194
195 QAT_FIELD_SET(val32,
196 csr.lazy,
197 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS,
198 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK);
199
200 QAT_FIELD_SET(val32,
201 csr.nice,
202 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS,
203 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK);
204
205 return BYTE_SWAP_32(val32);
206 }
207
208 /**
209 *****************************************************************************
210 * @ingroup icp_qat_fw_comn
211 *
212 * @description
213 * Definition of the hw config csr. This representation has to be further
214 * processed by the corresponding config build function.
215 *
216 *****************************************************************************/
217 typedef struct icp_qat_hw_decomp_20_config_csr_lower_s {
218 /* Fields programmable directly by the SW. */
219 icp_qat_hw_decomp_20_hbs_control_t hbs;
220 icp_qat_hw_decomp_20_lbms_t lbms;
221 /* Advanced HW control (Set to default vals) */
222 icp_qat_hw_decomp_20_hw_comp_format_t algo;
223 icp_qat_hw_decomp_20_min_match_control_t mmctrl;
224 icp_qat_hw_decomp_20_lz4_block_checksum_present_t lbc;
225 } icp_qat_hw_decomp_20_config_csr_lower_t;
226
227 /**
228 *****************************************************************************
229 * @ingroup icp_qat_fw_comn
230 *
231 * @description
232 * Build the longword as expected by the HW
233 *
234 *****************************************************************************/
235 static inline uint32_t
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_decomp_20_config_csr_lower_t csr)236 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(
237 icp_qat_hw_decomp_20_config_csr_lower_t csr)
238 {
239 uint32_t val32 = 0;
240
241 QAT_FIELD_SET(val32,
242 csr.hbs,
243 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
244 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
245
246 QAT_FIELD_SET(val32,
247 csr.lbms,
248 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS,
249 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK);
250
251 QAT_FIELD_SET(val32,
252 csr.algo,
253 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS,
254 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK);
255
256 QAT_FIELD_SET(val32,
257 csr.mmctrl,
258 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
259 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
260
261 QAT_FIELD_SET(
262 val32,
263 csr.lbc,
264 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS,
265 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK);
266
267 return BYTE_SWAP_32(val32);
268 }
269
270 /**
271 *****************************************************************************
272 * @ingroup icp_qat_fw_comn
273 *
274 * @description
275 * Definition of the hw config csr. This representation has to be further
276 * processed by the corresponding config build function.
277 *
278 *****************************************************************************/
279 typedef struct icp_qat_hw_decomp_20_config_csr_upper_s {
280 /* Advanced HW control (Set to default vals) */
281 icp_qat_hw_decomp_20_speculative_decoder_control_t sdc;
282 icp_qat_hw_decomp_20_reserved4_control_t res4;
283 } icp_qat_hw_decomp_20_config_csr_upper_t;
284
285 /**
286 *****************************************************************************
287 * @ingroup icp_qat_fw_comn
288 *
289 * @description
290 * Build the longword as expected by the HW
291 *
292 *****************************************************************************/
293 static inline uint32_t
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_decomp_20_config_csr_upper_t csr)294 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(
295 icp_qat_hw_decomp_20_config_csr_upper_t csr)
296 {
297 uint32_t val32 = 0;
298
299 QAT_FIELD_SET(
300 val32,
301 csr.sdc,
302 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS,
303 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK);
304
305 QAT_FIELD_SET(val32,
306 csr.res4,
307 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_BITPOS,
308 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_MASK);
309
310 return BYTE_SWAP_32(val32);
311 }
312 #endif /* ICP_QAT_HW__2X_COMP_H_ */
313