1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
5 *
6 * Copyright (c) 1997, 1998, 1999, 2000
7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Bill Paul.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
35 */
36 /*-
37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
38 *
39 * Permission to use, copy, modify, and distribute this software for any
40 * purpose with or without fee is hereby granted, provided that the above
41 * copyright notice and this permission notice appear in all copies.
42 *
43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50 */
51
52 #include <sys/cdefs.h>
53 /*
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
56 * References:
57 * The XaQti XMAC II datasheet,
58 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 *
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
64 *
65 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 *
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
70 */
71 /*
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
78 *
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
86 */
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/bus.h>
91 #include <sys/endian.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
100
101 #include <net/bpf.h>
102 #include <net/ethernet.h>
103 #include <net/if.h>
104 #include <net/if_var.h>
105 #include <net/if_arp.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/if_types.h>
109 #include <net/if_vlan_var.h>
110
111 #include <netinet/in.h>
112 #include <netinet/in_systm.h>
113 #include <netinet/ip.h>
114
115 #include <machine/bus.h>
116 #include <machine/in_cksum.h>
117 #include <machine/resource.h>
118 #include <sys/rman.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122 #include <dev/mii/brgphyreg.h>
123
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
126
127 #if 0
128 #define SK_USEIOSPACE
129 #endif
130
131 #include <dev/sk/if_skreg.h>
132 #include <dev/sk/xmaciireg.h>
133 #include <dev/sk/yukonreg.h>
134
135 MODULE_DEPEND(sk, pci, 1, 1, 1);
136 MODULE_DEPEND(sk, ether, 1, 1, 1);
137 MODULE_DEPEND(sk, miibus, 1, 1, 1);
138
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
141
142 static const struct sk_type sk_devs[] = {
143 {
144 VENDORID_SK,
145 DEVICEID_SK_V1,
146 "SysKonnect Gigabit Ethernet (V1.0)"
147 },
148 {
149 VENDORID_SK,
150 DEVICEID_SK_V2,
151 "SysKonnect Gigabit Ethernet (V2.0)"
152 },
153 {
154 VENDORID_MARVELL,
155 DEVICEID_SK_V2,
156 "Marvell Gigabit Ethernet"
157 },
158 {
159 VENDORID_MARVELL,
160 DEVICEID_BELKIN_5005,
161 "Belkin F5D5005 Gigabit Ethernet"
162 },
163 {
164 VENDORID_3COM,
165 DEVICEID_3COM_3C940,
166 "3Com 3C940 Gigabit Ethernet"
167 },
168 {
169 VENDORID_LINKSYS,
170 DEVICEID_LINKSYS_EG1032,
171 "Linksys EG1032 Gigabit Ethernet"
172 },
173 {
174 VENDORID_DLINK,
175 DEVICEID_DLINK_DGE530T_A1,
176 "D-Link DGE-530T Gigabit Ethernet"
177 },
178 {
179 VENDORID_DLINK,
180 DEVICEID_DLINK_DGE530T_B1,
181 "D-Link DGE-530T Gigabit Ethernet"
182 },
183 { 0, 0, NULL }
184 };
185
186 static int skc_probe(device_t);
187 static int skc_attach(device_t);
188 static void skc_child_deleted(device_t, device_t);
189 static int skc_detach(device_t);
190 static int skc_shutdown(device_t);
191 static int skc_suspend(device_t);
192 static int skc_resume(device_t);
193 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
194 static int sk_detach(device_t);
195 static int sk_probe(device_t);
196 static int sk_attach(device_t);
197 static void sk_tick(void *);
198 static void sk_yukon_tick(void *);
199 static void sk_intr(void *);
200 static void sk_intr_xmac(struct sk_if_softc *);
201 static void sk_intr_bcom(struct sk_if_softc *);
202 static void sk_intr_yukon(struct sk_if_softc *);
203 static __inline void sk_rxcksum(if_t, struct mbuf *, u_int32_t);
204 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
205 static void sk_rxeof(struct sk_if_softc *);
206 static void sk_jumbo_rxeof(struct sk_if_softc *);
207 static void sk_txeof(struct sk_if_softc *);
208 static void sk_txcksum(if_t, struct mbuf *, struct sk_tx_desc *);
209 static int sk_encap(struct sk_if_softc *, struct mbuf **);
210 static void sk_start(if_t);
211 static void sk_start_locked(if_t);
212 static int sk_ioctl(if_t, u_long, caddr_t);
213 static void sk_init(void *);
214 static void sk_init_locked(struct sk_if_softc *);
215 static void sk_init_xmac(struct sk_if_softc *);
216 static void sk_init_yukon(struct sk_if_softc *);
217 static void sk_stop(struct sk_if_softc *);
218 static void sk_watchdog(void *);
219 static int sk_ifmedia_upd(if_t);
220 static void sk_ifmedia_sts(if_t, struct ifmediareq *);
221 static void sk_reset(struct sk_softc *);
222 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
223 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
224 static int sk_newbuf(struct sk_if_softc *, int);
225 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
226 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
227 static int sk_dma_alloc(struct sk_if_softc *);
228 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
229 static void sk_dma_free(struct sk_if_softc *);
230 static void sk_dma_jumbo_free(struct sk_if_softc *);
231 static int sk_init_rx_ring(struct sk_if_softc *);
232 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
233 static void sk_init_tx_ring(struct sk_if_softc *);
234 static u_int32_t sk_win_read_4(struct sk_softc *, int);
235 static u_int16_t sk_win_read_2(struct sk_softc *, int);
236 static u_int8_t sk_win_read_1(struct sk_softc *, int);
237 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
238 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
239 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
240
241 static int sk_miibus_readreg(device_t, int, int);
242 static int sk_miibus_writereg(device_t, int, int, int);
243 static void sk_miibus_statchg(device_t);
244
245 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
246 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
247 int);
248 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
249
250 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
251 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
252 int);
253 static void sk_marv_miibus_statchg(struct sk_if_softc *);
254
255 static uint32_t sk_xmchash(const uint8_t *);
256 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
257 static void sk_rxfilter(struct sk_if_softc *);
258 static void sk_rxfilter_genesis(struct sk_if_softc *);
259 static void sk_rxfilter_yukon(struct sk_if_softc *);
260
261 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
262 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
263
264 /* Tunables. */
265 static int jumbo_disable = 0;
266 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
267
268 /*
269 * It seems that SK-NET GENESIS supports very simple checksum offload
270 * capability for Tx and I believe it can generate 0 checksum value for
271 * UDP packets in Tx as the hardware can't differenciate UDP packets from
272 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
273 * means sender didn't perforam checksum computation. For the safety I
274 * disabled UDP checksum offload capability at the moment.
275 */
276 #define SK_CSUM_FEATURES (CSUM_TCP)
277
278 /*
279 * Note that we have newbus methods for both the GEnesis controller
280 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
281 * the miibus code is a child of the XMACs. We need to do it this way
282 * so that the miibus drivers can access the PHY registers on the
283 * right PHY. It's not quite what I had in mind, but it's the only
284 * design that achieves the desired effect.
285 */
286 static device_method_t skc_methods[] = {
287 /* Device interface */
288 DEVMETHOD(device_probe, skc_probe),
289 DEVMETHOD(device_attach, skc_attach),
290 DEVMETHOD(device_detach, skc_detach),
291 DEVMETHOD(device_suspend, skc_suspend),
292 DEVMETHOD(device_resume, skc_resume),
293 DEVMETHOD(device_shutdown, skc_shutdown),
294
295 DEVMETHOD(bus_child_deleted, skc_child_deleted),
296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag),
297
298 DEVMETHOD_END
299 };
300
301 static driver_t skc_driver = {
302 "skc",
303 skc_methods,
304 sizeof(struct sk_softc)
305 };
306
307 static device_method_t sk_methods[] = {
308 /* Device interface */
309 DEVMETHOD(device_probe, sk_probe),
310 DEVMETHOD(device_attach, sk_attach),
311 DEVMETHOD(device_detach, sk_detach),
312 DEVMETHOD(device_shutdown, bus_generic_shutdown),
313
314 /* MII interface */
315 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
316 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
317 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
318
319 DEVMETHOD_END
320 };
321
322 static driver_t sk_driver = {
323 "sk",
324 sk_methods,
325 sizeof(struct sk_if_softc)
326 };
327
328 DRIVER_MODULE(skc, pci, skc_driver, NULL, NULL);
329 DRIVER_MODULE(sk, skc, sk_driver, NULL, NULL);
330 DRIVER_MODULE(miibus, sk, miibus_driver, NULL, NULL);
331
332 static struct resource_spec sk_res_spec_io[] = {
333 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
334 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
335 { -1, 0, 0 }
336 };
337
338 static struct resource_spec sk_res_spec_mem[] = {
339 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
340 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
341 { -1, 0, 0 }
342 };
343
344 #define SK_SETBIT(sc, reg, x) \
345 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
346
347 #define SK_CLRBIT(sc, reg, x) \
348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
349
350 #define SK_WIN_SETBIT_4(sc, reg, x) \
351 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
352
353 #define SK_WIN_CLRBIT_4(sc, reg, x) \
354 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
355
356 #define SK_WIN_SETBIT_2(sc, reg, x) \
357 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
358
359 #define SK_WIN_CLRBIT_2(sc, reg, x) \
360 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
361
362 static u_int32_t
sk_win_read_4(struct sk_softc * sc,int reg)363 sk_win_read_4(struct sk_softc *sc, int reg)
364 {
365 #ifdef SK_USEIOSPACE
366 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
367 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
368 #else
369 return(CSR_READ_4(sc, reg));
370 #endif
371 }
372
373 static u_int16_t
sk_win_read_2(struct sk_softc * sc,int reg)374 sk_win_read_2(struct sk_softc *sc, int reg)
375 {
376 #ifdef SK_USEIOSPACE
377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
378 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
379 #else
380 return(CSR_READ_2(sc, reg));
381 #endif
382 }
383
384 static u_int8_t
sk_win_read_1(struct sk_softc * sc,int reg)385 sk_win_read_1(struct sk_softc *sc, int reg)
386 {
387 #ifdef SK_USEIOSPACE
388 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
389 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
390 #else
391 return(CSR_READ_1(sc, reg));
392 #endif
393 }
394
395 static void
sk_win_write_4(struct sk_softc * sc,int reg,u_int32_t val)396 sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val)
397 {
398 #ifdef SK_USEIOSPACE
399 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
400 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
401 #else
402 CSR_WRITE_4(sc, reg, val);
403 #endif
404 return;
405 }
406
407 static void
sk_win_write_2(struct sk_softc * sc,int reg,u_int32_t val)408 sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val)
409 {
410 #ifdef SK_USEIOSPACE
411 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
412 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
413 #else
414 CSR_WRITE_2(sc, reg, val);
415 #endif
416 return;
417 }
418
419 static void
sk_win_write_1(struct sk_softc * sc,int reg,u_int32_t val)420 sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val)
421 {
422 #ifdef SK_USEIOSPACE
423 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
424 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
425 #else
426 CSR_WRITE_1(sc, reg, val);
427 #endif
428 return;
429 }
430
431 static int
sk_miibus_readreg(device_t dev,int phy,int reg)432 sk_miibus_readreg(device_t dev, int phy, int reg)
433 {
434 struct sk_if_softc *sc_if;
435 int v;
436
437 sc_if = device_get_softc(dev);
438
439 SK_IF_MII_LOCK(sc_if);
440 switch(sc_if->sk_softc->sk_type) {
441 case SK_GENESIS:
442 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
443 break;
444 case SK_YUKON:
445 case SK_YUKON_LITE:
446 case SK_YUKON_LP:
447 v = sk_marv_miibus_readreg(sc_if, phy, reg);
448 break;
449 default:
450 v = 0;
451 break;
452 }
453 SK_IF_MII_UNLOCK(sc_if);
454
455 return (v);
456 }
457
458 static int
sk_miibus_writereg(device_t dev,int phy,int reg,int val)459 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
460 {
461 struct sk_if_softc *sc_if;
462 int v;
463
464 sc_if = device_get_softc(dev);
465
466 SK_IF_MII_LOCK(sc_if);
467 switch(sc_if->sk_softc->sk_type) {
468 case SK_GENESIS:
469 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
470 break;
471 case SK_YUKON:
472 case SK_YUKON_LITE:
473 case SK_YUKON_LP:
474 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
475 break;
476 default:
477 v = 0;
478 break;
479 }
480 SK_IF_MII_UNLOCK(sc_if);
481
482 return (v);
483 }
484
485 static void
sk_miibus_statchg(device_t dev)486 sk_miibus_statchg(device_t dev)
487 {
488 struct sk_if_softc *sc_if;
489
490 sc_if = device_get_softc(dev);
491
492 SK_IF_MII_LOCK(sc_if);
493 switch(sc_if->sk_softc->sk_type) {
494 case SK_GENESIS:
495 sk_xmac_miibus_statchg(sc_if);
496 break;
497 case SK_YUKON:
498 case SK_YUKON_LITE:
499 case SK_YUKON_LP:
500 sk_marv_miibus_statchg(sc_if);
501 break;
502 }
503 SK_IF_MII_UNLOCK(sc_if);
504
505 return;
506 }
507
508 static int
sk_xmac_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)509 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
510 {
511 int i;
512
513 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
514 SK_XM_READ_2(sc_if, XM_PHY_DATA);
515 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
516 for (i = 0; i < SK_TIMEOUT; i++) {
517 DELAY(1);
518 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
519 XM_MMUCMD_PHYDATARDY)
520 break;
521 }
522
523 if (i == SK_TIMEOUT) {
524 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
525 return(0);
526 }
527 }
528 DELAY(1);
529 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
530
531 return(i);
532 }
533
534 static int
sk_xmac_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)535 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
536 {
537 int i;
538
539 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
540 for (i = 0; i < SK_TIMEOUT; i++) {
541 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
542 break;
543 }
544
545 if (i == SK_TIMEOUT) {
546 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
547 return (ETIMEDOUT);
548 }
549
550 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
551 for (i = 0; i < SK_TIMEOUT; i++) {
552 DELAY(1);
553 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
554 break;
555 }
556 if (i == SK_TIMEOUT)
557 if_printf(sc_if->sk_ifp, "phy write timed out\n");
558
559 return(0);
560 }
561
562 static void
sk_xmac_miibus_statchg(struct sk_if_softc * sc_if)563 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
564 {
565 struct mii_data *mii;
566
567 mii = device_get_softc(sc_if->sk_miibus);
568
569 /*
570 * If this is a GMII PHY, manually set the XMAC's
571 * duplex mode accordingly.
572 */
573 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
574 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
575 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
576 } else {
577 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
578 }
579 }
580 }
581
582 static int
sk_marv_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)583 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
584 {
585 u_int16_t val;
586 int i;
587
588 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
589 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
590 return(0);
591 }
592
593 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
594 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
595
596 for (i = 0; i < SK_TIMEOUT; i++) {
597 DELAY(1);
598 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
599 if (val & YU_SMICR_READ_VALID)
600 break;
601 }
602
603 if (i == SK_TIMEOUT) {
604 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
605 return(0);
606 }
607
608 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
609
610 return(val);
611 }
612
613 static int
sk_marv_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)614 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
615 {
616 int i;
617
618 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
619 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
620 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
621
622 for (i = 0; i < SK_TIMEOUT; i++) {
623 DELAY(1);
624 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
625 break;
626 }
627 if (i == SK_TIMEOUT)
628 if_printf(sc_if->sk_ifp, "phy write timeout\n");
629
630 return(0);
631 }
632
633 static void
sk_marv_miibus_statchg(struct sk_if_softc * sc_if)634 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
635 {
636 return;
637 }
638
639 #define HASH_BITS 6
640
641 static u_int32_t
sk_xmchash(const uint8_t * addr)642 sk_xmchash(const uint8_t *addr)
643 {
644 uint32_t crc;
645
646 /* Compute CRC for the address value. */
647 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
648
649 return (~crc & ((1 << HASH_BITS) - 1));
650 }
651
652 static void
sk_setfilt(struct sk_if_softc * sc_if,u_int16_t * addr,int slot)653 sk_setfilt(struct sk_if_softc *sc_if, u_int16_t *addr, int slot)
654 {
655 int base;
656
657 base = XM_RXFILT_ENTRY(slot);
658
659 SK_XM_WRITE_2(sc_if, base, addr[0]);
660 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
661 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
662
663 return;
664 }
665
666 static void
sk_rxfilter(struct sk_if_softc * sc_if)667 sk_rxfilter(struct sk_if_softc *sc_if)
668 {
669 struct sk_softc *sc;
670
671 SK_IF_LOCK_ASSERT(sc_if);
672
673 sc = sc_if->sk_softc;
674 if (sc->sk_type == SK_GENESIS)
675 sk_rxfilter_genesis(sc_if);
676 else
677 sk_rxfilter_yukon(sc_if);
678 }
679
680 struct sk_add_maddr_genesis_ctx {
681 struct sk_if_softc *sc_if;
682 uint32_t hashes[2];
683 uint32_t mode;
684 };
685
686 static u_int
sk_add_maddr_genesis(void * arg,struct sockaddr_dl * sdl,u_int cnt)687 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt)
688 {
689 struct sk_add_maddr_genesis_ctx *ctx = arg;
690 int h;
691
692 /*
693 * Program the first XM_RXFILT_MAX multicast groups
694 * into the perfect filter.
695 */
696 if (cnt + 1 < XM_RXFILT_MAX) {
697 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1);
698 ctx->mode |= XM_MODE_RX_USE_PERFECT;
699 return (1);
700 }
701 h = sk_xmchash((const uint8_t *)LLADDR(sdl));
702 if (h < 32)
703 ctx->hashes[0] |= (1 << h);
704 else
705 ctx->hashes[1] |= (1 << (h - 32));
706 ctx->mode |= XM_MODE_RX_USE_HASH;
707
708 return (1);
709 }
710
711 static void
sk_rxfilter_genesis(struct sk_if_softc * sc_if)712 sk_rxfilter_genesis(struct sk_if_softc *sc_if)
713 {
714 if_t ifp = sc_if->sk_ifp;
715 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } };
716 int i;
717 u_int16_t dummy[] = { 0, 0, 0 };
718
719 SK_IF_LOCK_ASSERT(sc_if);
720
721 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE);
722 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
723 XM_MODE_RX_USE_PERFECT);
724 /* First, zot all the existing perfect filters. */
725 for (i = 1; i < XM_RXFILT_MAX; i++)
726 sk_setfilt(sc_if, dummy, i);
727
728 /* Now program new ones. */
729 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
730 if (if_getflags(ifp) & IFF_ALLMULTI)
731 ctx.mode |= XM_MODE_RX_USE_HASH;
732 if (if_getflags(ifp) & IFF_PROMISC)
733 ctx.mode |= XM_MODE_RX_PROMISC;
734 ctx.hashes[0] = 0xFFFFFFFF;
735 ctx.hashes[1] = 0xFFFFFFFF;
736 } else
737 /* XXX want to maintain reverse semantics */
738 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx);
739
740 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode);
741 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]);
742 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]);
743 }
744
745 static u_int
sk_hash_maddr_yukon(void * arg,struct sockaddr_dl * sdl,u_int cnt)746 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt)
747 {
748 uint32_t crc, *hashes = arg;
749
750 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
751 /* Just want the 6 least significant bits. */
752 crc &= 0x3f;
753 /* Set the corresponding bit in the hash table. */
754 hashes[crc >> 5] |= 1 << (crc & 0x1f);
755
756 return (1);
757 }
758
759 static void
sk_rxfilter_yukon(struct sk_if_softc * sc_if)760 sk_rxfilter_yukon(struct sk_if_softc *sc_if)
761 {
762 if_t ifp;
763 uint32_t hashes[2] = { 0, 0 }, mode;
764
765 SK_IF_LOCK_ASSERT(sc_if);
766
767 ifp = sc_if->sk_ifp;
768 mode = SK_YU_READ_2(sc_if, YUKON_RCR);
769 if (if_getflags(ifp) & IFF_PROMISC)
770 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
771 else if (if_getflags(ifp) & IFF_ALLMULTI) {
772 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
773 hashes[0] = 0xFFFFFFFF;
774 hashes[1] = 0xFFFFFFFF;
775 } else {
776 mode |= YU_RCR_UFLEN;
777 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes);
778 if (hashes[0] != 0 || hashes[1] != 0)
779 mode |= YU_RCR_MUFLEN;
780 }
781
782 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
783 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
784 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
785 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
786 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
787 }
788
789 static int
sk_init_rx_ring(struct sk_if_softc * sc_if)790 sk_init_rx_ring(struct sk_if_softc *sc_if)
791 {
792 struct sk_ring_data *rd;
793 bus_addr_t addr;
794 u_int32_t csum_start;
795 int i;
796
797 sc_if->sk_cdata.sk_rx_cons = 0;
798
799 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
800 ETHER_HDR_LEN;
801 rd = &sc_if->sk_rdata;
802 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
803 for (i = 0; i < SK_RX_RING_CNT; i++) {
804 if (sk_newbuf(sc_if, i) != 0)
805 return (ENOBUFS);
806 if (i == (SK_RX_RING_CNT - 1))
807 addr = SK_RX_RING_ADDR(sc_if, 0);
808 else
809 addr = SK_RX_RING_ADDR(sc_if, i + 1);
810 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
811 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
812 }
813
814 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
815 sc_if->sk_cdata.sk_rx_ring_map,
816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
817
818 return(0);
819 }
820
821 static int
sk_init_jumbo_rx_ring(struct sk_if_softc * sc_if)822 sk_init_jumbo_rx_ring(struct sk_if_softc *sc_if)
823 {
824 struct sk_ring_data *rd;
825 bus_addr_t addr;
826 u_int32_t csum_start;
827 int i;
828
829 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
830
831 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
832 ETHER_HDR_LEN;
833 rd = &sc_if->sk_rdata;
834 bzero(rd->sk_jumbo_rx_ring,
835 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
836 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
837 if (sk_jumbo_newbuf(sc_if, i) != 0)
838 return (ENOBUFS);
839 if (i == (SK_JUMBO_RX_RING_CNT - 1))
840 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
841 else
842 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
843 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
844 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
845 }
846
847 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
848 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
849 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
850
851 return (0);
852 }
853
854 static void
sk_init_tx_ring(struct sk_if_softc * sc_if)855 sk_init_tx_ring(struct sk_if_softc *sc_if)
856 {
857 struct sk_ring_data *rd;
858 struct sk_txdesc *txd;
859 bus_addr_t addr;
860 int i;
861
862 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
863 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
864
865 sc_if->sk_cdata.sk_tx_prod = 0;
866 sc_if->sk_cdata.sk_tx_cons = 0;
867 sc_if->sk_cdata.sk_tx_cnt = 0;
868
869 rd = &sc_if->sk_rdata;
870 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
871 for (i = 0; i < SK_TX_RING_CNT; i++) {
872 if (i == (SK_TX_RING_CNT - 1))
873 addr = SK_TX_RING_ADDR(sc_if, 0);
874 else
875 addr = SK_TX_RING_ADDR(sc_if, i + 1);
876 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
877 txd = &sc_if->sk_cdata.sk_txdesc[i];
878 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
879 }
880
881 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
882 sc_if->sk_cdata.sk_tx_ring_map,
883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
884 }
885
886 static __inline void
sk_discard_rxbuf(struct sk_if_softc * sc_if,int idx)887 sk_discard_rxbuf(struct sk_if_softc *sc_if, int idx)
888 {
889 struct sk_rx_desc *r;
890 struct sk_rxdesc *rxd;
891 struct mbuf *m;
892
893 r = &sc_if->sk_rdata.sk_rx_ring[idx];
894 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
895 m = rxd->rx_m;
896 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
897 }
898
899 static __inline void
sk_discard_jumbo_rxbuf(struct sk_if_softc * sc_if,int idx)900 sk_discard_jumbo_rxbuf(struct sk_if_softc *sc_if, int idx)
901 {
902 struct sk_rx_desc *r;
903 struct sk_rxdesc *rxd;
904 struct mbuf *m;
905
906 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
907 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
908 m = rxd->rx_m;
909 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
910 }
911
912 static int
sk_newbuf(struct sk_if_softc * sc_if,int idx)913 sk_newbuf(struct sk_if_softc *sc_if, int idx)
914 {
915 struct sk_rx_desc *r;
916 struct sk_rxdesc *rxd;
917 struct mbuf *m;
918 bus_dma_segment_t segs[1];
919 bus_dmamap_t map;
920 int nsegs;
921
922 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
923 if (m == NULL)
924 return (ENOBUFS);
925 m->m_len = m->m_pkthdr.len = MCLBYTES;
926 m_adj(m, ETHER_ALIGN);
927
928 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
929 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
930 m_freem(m);
931 return (ENOBUFS);
932 }
933 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
934
935 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
936 if (rxd->rx_m != NULL) {
937 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
938 BUS_DMASYNC_POSTREAD);
939 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
940 }
941 map = rxd->rx_dmamap;
942 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
943 sc_if->sk_cdata.sk_rx_sparemap = map;
944 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
945 BUS_DMASYNC_PREREAD);
946 rxd->rx_m = m;
947 r = &sc_if->sk_rdata.sk_rx_ring[idx];
948 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
949 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
950 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
951
952 return (0);
953 }
954
955 static int
sk_jumbo_newbuf(struct sk_if_softc * sc_if,int idx)956 sk_jumbo_newbuf(struct sk_if_softc *sc_if, int idx)
957 {
958 struct sk_rx_desc *r;
959 struct sk_rxdesc *rxd;
960 struct mbuf *m;
961 bus_dma_segment_t segs[1];
962 bus_dmamap_t map;
963 int nsegs;
964
965 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
966 if (m == NULL)
967 return (ENOBUFS);
968 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
969 /*
970 * Adjust alignment so packet payload begins on a
971 * longword boundary. Mandatory for Alpha, useful on
972 * x86 too.
973 */
974 m_adj(m, ETHER_ALIGN);
975
976 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
977 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
978 m_freem(m);
979 return (ENOBUFS);
980 }
981 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
982
983 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
984 if (rxd->rx_m != NULL) {
985 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
986 BUS_DMASYNC_POSTREAD);
987 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
988 rxd->rx_dmamap);
989 }
990 map = rxd->rx_dmamap;
991 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
992 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
993 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
994 BUS_DMASYNC_PREREAD);
995 rxd->rx_m = m;
996 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
997 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
998 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
999 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1000
1001 return (0);
1002 }
1003
1004 /*
1005 * Set media options.
1006 */
1007 static int
sk_ifmedia_upd(if_t ifp)1008 sk_ifmedia_upd(if_t ifp)
1009 {
1010 struct sk_if_softc *sc_if = if_getsoftc(ifp);
1011 struct mii_data *mii;
1012
1013 mii = device_get_softc(sc_if->sk_miibus);
1014 sk_init(sc_if);
1015 mii_mediachg(mii);
1016
1017 return(0);
1018 }
1019
1020 /*
1021 * Report current media status.
1022 */
1023 static void
sk_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1024 sk_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1025 {
1026 struct sk_if_softc *sc_if;
1027 struct mii_data *mii;
1028
1029 sc_if = if_getsoftc(ifp);
1030 mii = device_get_softc(sc_if->sk_miibus);
1031
1032 mii_pollstat(mii);
1033 ifmr->ifm_active = mii->mii_media_active;
1034 ifmr->ifm_status = mii->mii_media_status;
1035
1036 return;
1037 }
1038
1039 static int
sk_ioctl(if_t ifp,u_long command,caddr_t data)1040 sk_ioctl(if_t ifp, u_long command, caddr_t data)
1041 {
1042 struct sk_if_softc *sc_if = if_getsoftc(ifp);
1043 struct ifreq *ifr = (struct ifreq *) data;
1044 int error, mask;
1045 struct mii_data *mii;
1046
1047 error = 0;
1048 switch(command) {
1049 case SIOCSIFMTU:
1050 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1051 error = EINVAL;
1052 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1053 if (sc_if->sk_jumbo_disable != 0 &&
1054 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1055 error = EINVAL;
1056 else {
1057 SK_IF_LOCK(sc_if);
1058 if_setmtu(ifp, ifr->ifr_mtu);
1059 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1060 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1061 sk_init_locked(sc_if);
1062 }
1063 SK_IF_UNLOCK(sc_if);
1064 }
1065 }
1066 break;
1067 case SIOCSIFFLAGS:
1068 SK_IF_LOCK(sc_if);
1069 if (if_getflags(ifp) & IFF_UP) {
1070 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1071 if ((if_getflags(ifp) ^ sc_if->sk_if_flags)
1072 & (IFF_PROMISC | IFF_ALLMULTI))
1073 sk_rxfilter(sc_if);
1074 } else
1075 sk_init_locked(sc_if);
1076 } else {
1077 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1078 sk_stop(sc_if);
1079 }
1080 sc_if->sk_if_flags = if_getflags(ifp);
1081 SK_IF_UNLOCK(sc_if);
1082 break;
1083 case SIOCADDMULTI:
1084 case SIOCDELMULTI:
1085 SK_IF_LOCK(sc_if);
1086 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1087 sk_rxfilter(sc_if);
1088 SK_IF_UNLOCK(sc_if);
1089 break;
1090 case SIOCGIFMEDIA:
1091 case SIOCSIFMEDIA:
1092 mii = device_get_softc(sc_if->sk_miibus);
1093 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1094 break;
1095 case SIOCSIFCAP:
1096 SK_IF_LOCK(sc_if);
1097 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1098 SK_IF_UNLOCK(sc_if);
1099 break;
1100 }
1101 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1102 if ((mask & IFCAP_TXCSUM) != 0 &&
1103 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
1104 if_togglecapenable(ifp, IFCAP_TXCSUM);
1105 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1106 if_sethwassistbits(ifp, SK_CSUM_FEATURES, 0);
1107 else
1108 if_sethwassistbits(ifp, 0, SK_CSUM_FEATURES);
1109 }
1110 if ((mask & IFCAP_RXCSUM) != 0 &&
1111 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0)
1112 if_togglecapenable(ifp, IFCAP_RXCSUM);
1113 SK_IF_UNLOCK(sc_if);
1114 break;
1115 default:
1116 error = ether_ioctl(ifp, command, data);
1117 break;
1118 }
1119
1120 return (error);
1121 }
1122
1123 /*
1124 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1125 * IDs against our list and return a device name if we find a match.
1126 */
1127 static int
skc_probe(device_t dev)1128 skc_probe(device_t dev)
1129 {
1130 const struct sk_type *t = sk_devs;
1131
1132 while(t->sk_name != NULL) {
1133 if ((pci_get_vendor(dev) == t->sk_vid) &&
1134 (pci_get_device(dev) == t->sk_did)) {
1135 /*
1136 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1137 * Rev. 3 is supported by re(4).
1138 */
1139 if ((t->sk_vid == VENDORID_LINKSYS) &&
1140 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1141 (pci_get_subdevice(dev) !=
1142 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1143 t++;
1144 continue;
1145 }
1146 device_set_desc(dev, t->sk_name);
1147 return (BUS_PROBE_DEFAULT);
1148 }
1149 t++;
1150 }
1151
1152 return(ENXIO);
1153 }
1154
1155 /*
1156 * Force the GEnesis into reset, then bring it out of reset.
1157 */
1158 static void
sk_reset(struct sk_softc * sc)1159 sk_reset(struct sk_softc *sc)
1160 {
1161
1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1164 if (SK_YUKON_FAMILY(sc->sk_type))
1165 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1166
1167 DELAY(1000);
1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1169 DELAY(2);
1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1171 if (SK_YUKON_FAMILY(sc->sk_type))
1172 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1173
1174 if (sc->sk_type == SK_GENESIS) {
1175 /* Configure packet arbiter */
1176 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1177 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1178 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1179 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1180 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1181 }
1182
1183 /* Enable RAM interface */
1184 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1185
1186 /*
1187 * Configure interrupt moderation. The moderation timer
1188 * defers interrupts specified in the interrupt moderation
1189 * timer mask based on the timeout specified in the interrupt
1190 * moderation timer init register. Each bit in the timer
1191 * register represents one tick, so to specify a timeout in
1192 * microseconds, we have to multiply by the correct number of
1193 * ticks-per-microsecond.
1194 */
1195 switch (sc->sk_type) {
1196 case SK_GENESIS:
1197 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1198 break;
1199 default:
1200 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1201 break;
1202 }
1203 if (bootverbose)
1204 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1205 sc->sk_int_mod);
1206 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1207 sc->sk_int_ticks));
1208 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1209 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1210 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1211
1212 return;
1213 }
1214
1215 static int
sk_probe(device_t dev)1216 sk_probe(device_t dev)
1217 {
1218 struct sk_softc *sc;
1219
1220 sc = device_get_softc(device_get_parent(dev));
1221
1222 /*
1223 * Not much to do here. We always know there will be
1224 * at least one XMAC present, and if there are two,
1225 * skc_attach() will create a second device instance
1226 * for us.
1227 */
1228 switch (sc->sk_type) {
1229 case SK_GENESIS:
1230 device_set_desc(dev, "XaQti Corp. XMAC II");
1231 break;
1232 case SK_YUKON:
1233 case SK_YUKON_LITE:
1234 case SK_YUKON_LP:
1235 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1236 break;
1237 }
1238
1239 return (BUS_PROBE_DEFAULT);
1240 }
1241
1242 /*
1243 * Each XMAC chip is attached as a separate logical IP interface.
1244 * Single port cards will have only one logical interface of course.
1245 */
1246 static int
sk_attach(device_t dev)1247 sk_attach(device_t dev)
1248 {
1249 struct sk_softc *sc;
1250 struct sk_if_softc *sc_if;
1251 if_t ifp;
1252 u_int32_t r;
1253 int error, i, phy, port;
1254 u_char eaddr[6];
1255 u_char inv_mac[] = {0, 0, 0, 0, 0, 0};
1256
1257 if (dev == NULL)
1258 return(EINVAL);
1259
1260 error = 0;
1261 sc_if = device_get_softc(dev);
1262 sc = device_get_softc(device_get_parent(dev));
1263 port = *(int *)device_get_ivars(dev);
1264
1265 sc_if->sk_if_dev = dev;
1266 sc_if->sk_port = port;
1267 sc_if->sk_softc = sc;
1268 sc->sk_if[port] = sc_if;
1269 if (port == SK_PORT_A)
1270 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1271 if (port == SK_PORT_B)
1272 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1273
1274 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1275 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1276
1277 if (sk_dma_alloc(sc_if) != 0) {
1278 error = ENOMEM;
1279 goto fail;
1280 }
1281 sk_dma_jumbo_alloc(sc_if);
1282
1283 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1284 if_setsoftc(ifp, sc_if);
1285 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1286 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1287 /*
1288 * SK_GENESIS has a bug in checksum offload - From linux.
1289 */
1290 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1291 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM);
1292 if_sethwassist(ifp, 0);
1293 } else {
1294 if_setcapabilities(ifp, 0);
1295 if_sethwassist(ifp, 0);
1296 }
1297 if_setcapenable(ifp, if_getcapabilities(ifp));
1298 /*
1299 * Some revision of Yukon controller generates corrupted
1300 * frame when TX checksum offloading is enabled. The
1301 * frame has a valid checksum value so payload might be
1302 * modified during TX checksum calculation. Disable TX
1303 * checksum offloading but give users chance to enable it
1304 * when they know their controller works without problems
1305 * with TX checksum offloading.
1306 */
1307 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
1308 if_setioctlfn(ifp, sk_ioctl);
1309 if_setstartfn(ifp, sk_start);
1310 if_setinitfn(ifp, sk_init);
1311 if_setsendqlen(ifp, SK_TX_RING_CNT - 1);
1312 if_setsendqready(ifp);
1313
1314 /*
1315 * Get station address for this interface. Note that
1316 * dual port cards actually come with three station
1317 * addresses: one for each port, plus an extra. The
1318 * extra one is used by the SysKonnect driver software
1319 * as a 'virtual' station address for when both ports
1320 * are operating in failover mode. Currently we don't
1321 * use this extra address.
1322 */
1323 SK_IF_LOCK(sc_if);
1324 for (i = 0; i < ETHER_ADDR_LEN; i++)
1325 eaddr[i] =
1326 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1327
1328 /* Verify whether the station address is invalid or not. */
1329 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1330 device_printf(sc_if->sk_if_dev,
1331 "Generating random ethernet address\n");
1332 r = arc4random();
1333 /*
1334 * Set OUI to convenient locally assigned address. 'b'
1335 * is 0x62, which has the locally assigned bit set, and
1336 * the broadcast/multicast bit clear.
1337 */
1338 eaddr[0] = 'b';
1339 eaddr[1] = 's';
1340 eaddr[2] = 'd';
1341 eaddr[3] = (r >> 16) & 0xff;
1342 eaddr[4] = (r >> 8) & 0xff;
1343 eaddr[5] = (r >> 0) & 0xff;
1344 }
1345 /*
1346 * Set up RAM buffer addresses. The NIC will have a certain
1347 * amount of SRAM on it, somewhere between 512K and 2MB. We
1348 * need to divide this up a) between the transmitter and
1349 * receiver and b) between the two XMACs, if this is a
1350 * dual port NIC. Our algotithm is to divide up the memory
1351 * evenly so that everyone gets a fair share.
1352 *
1353 * Just to be contrary, Yukon2 appears to have separate memory
1354 * for each MAC.
1355 */
1356 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1357 u_int32_t chunk, val;
1358
1359 chunk = sc->sk_ramsize / 2;
1360 val = sc->sk_rboff / sizeof(u_int64_t);
1361 sc_if->sk_rx_ramstart = val;
1362 val += (chunk / sizeof(u_int64_t));
1363 sc_if->sk_rx_ramend = val - 1;
1364 sc_if->sk_tx_ramstart = val;
1365 val += (chunk / sizeof(u_int64_t));
1366 sc_if->sk_tx_ramend = val - 1;
1367 } else {
1368 u_int32_t chunk, val;
1369
1370 chunk = sc->sk_ramsize / 4;
1371 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1372 sizeof(u_int64_t);
1373 sc_if->sk_rx_ramstart = val;
1374 val += (chunk / sizeof(u_int64_t));
1375 sc_if->sk_rx_ramend = val - 1;
1376 sc_if->sk_tx_ramstart = val;
1377 val += (chunk / sizeof(u_int64_t));
1378 sc_if->sk_tx_ramend = val - 1;
1379 }
1380
1381 /* Read and save PHY type and set PHY address */
1382 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1383 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1384 switch(sc_if->sk_phytype) {
1385 case SK_PHYTYPE_XMAC:
1386 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1387 break;
1388 case SK_PHYTYPE_BCOM:
1389 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1390 break;
1391 default:
1392 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1393 sc_if->sk_phytype);
1394 error = ENODEV;
1395 SK_IF_UNLOCK(sc_if);
1396 goto fail;
1397 }
1398 } else {
1399 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1400 sc->sk_pmd != 'S') {
1401 /* not initialized, punt */
1402 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1403 sc->sk_coppertype = 1;
1404 }
1405
1406 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1407
1408 if (!(sc->sk_coppertype))
1409 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1410 }
1411
1412 /*
1413 * Call MI attach routine. Can't hold locks when calling into ether_*.
1414 */
1415 SK_IF_UNLOCK(sc_if);
1416 ether_ifattach(ifp, eaddr);
1417 SK_IF_LOCK(sc_if);
1418
1419 /*
1420 * The hardware should be ready for VLAN_MTU by default:
1421 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1422 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1423 *
1424 */
1425 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1426 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
1427 /*
1428 * Tell the upper layer(s) we support long frames.
1429 * Must appear after the call to ether_ifattach() because
1430 * ether_ifattach() sets ifi_hdrlen to the default value.
1431 */
1432 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1433
1434 /*
1435 * Do miibus setup.
1436 */
1437 phy = MII_PHY_ANY;
1438 switch (sc->sk_type) {
1439 case SK_GENESIS:
1440 sk_init_xmac(sc_if);
1441 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1442 phy = 0;
1443 break;
1444 case SK_YUKON:
1445 case SK_YUKON_LITE:
1446 case SK_YUKON_LP:
1447 sk_init_yukon(sc_if);
1448 phy = 0;
1449 break;
1450 }
1451
1452 SK_IF_UNLOCK(sc_if);
1453 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1454 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1455 if (error != 0) {
1456 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1457 ether_ifdetach(ifp);
1458 goto fail;
1459 }
1460
1461 fail:
1462 if (error) {
1463 /* Access should be ok even though lock has been dropped */
1464 sc->sk_if[port] = NULL;
1465 sk_detach(dev);
1466 }
1467
1468 return(error);
1469 }
1470
1471 /*
1472 * Attach the interface. Allocate softc structures, do ifmedia
1473 * setup and ethernet/BPF attach.
1474 */
1475 static int
skc_attach(device_t dev)1476 skc_attach(device_t dev)
1477 {
1478 struct sk_softc *sc;
1479 int error = 0, *port;
1480 uint8_t skrs;
1481 const char *pname = NULL;
1482 char *revstr;
1483
1484 sc = device_get_softc(dev);
1485 sc->sk_dev = dev;
1486
1487 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1488 MTX_DEF);
1489 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1490 /*
1491 * Map control/status registers.
1492 */
1493 pci_enable_busmaster(dev);
1494
1495 /* Allocate resources */
1496 #ifdef SK_USEIOSPACE
1497 sc->sk_res_spec = sk_res_spec_io;
1498 #else
1499 sc->sk_res_spec = sk_res_spec_mem;
1500 #endif
1501 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1502 if (error) {
1503 if (sc->sk_res_spec == sk_res_spec_mem)
1504 sc->sk_res_spec = sk_res_spec_io;
1505 else
1506 sc->sk_res_spec = sk_res_spec_mem;
1507 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1508 if (error) {
1509 device_printf(dev, "couldn't allocate %s resources\n",
1510 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1511 "I/O");
1512 goto fail;
1513 }
1514 }
1515
1516 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1517 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1518
1519 /* Bail out if chip is not recognized. */
1520 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1521 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1522 sc->sk_type, sc->sk_rev);
1523 error = ENXIO;
1524 goto fail;
1525 }
1526
1527 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1528 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1529 OID_AUTO, "int_mod",
1530 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1531 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1532 "SK interrupt moderation");
1533
1534 /* Pull in device tunables. */
1535 sc->sk_int_mod = SK_IM_DEFAULT;
1536 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1537 "int_mod", &sc->sk_int_mod);
1538 if (error == 0) {
1539 if (sc->sk_int_mod < SK_IM_MIN ||
1540 sc->sk_int_mod > SK_IM_MAX) {
1541 device_printf(dev, "int_mod value out of range; "
1542 "using default: %d\n", SK_IM_DEFAULT);
1543 sc->sk_int_mod = SK_IM_DEFAULT;
1544 }
1545 }
1546
1547 /* Reset the adapter. */
1548 sk_reset(sc);
1549
1550 skrs = sk_win_read_1(sc, SK_EPROM0);
1551 if (sc->sk_type == SK_GENESIS) {
1552 /* Read and save RAM size and RAMbuffer offset */
1553 switch(skrs) {
1554 case SK_RAMSIZE_512K_64:
1555 sc->sk_ramsize = 0x80000;
1556 sc->sk_rboff = SK_RBOFF_0;
1557 break;
1558 case SK_RAMSIZE_1024K_64:
1559 sc->sk_ramsize = 0x100000;
1560 sc->sk_rboff = SK_RBOFF_80000;
1561 break;
1562 case SK_RAMSIZE_1024K_128:
1563 sc->sk_ramsize = 0x100000;
1564 sc->sk_rboff = SK_RBOFF_0;
1565 break;
1566 case SK_RAMSIZE_2048K_128:
1567 sc->sk_ramsize = 0x200000;
1568 sc->sk_rboff = SK_RBOFF_0;
1569 break;
1570 default:
1571 device_printf(dev, "unknown ram size: %d\n", skrs);
1572 error = ENXIO;
1573 goto fail;
1574 }
1575 } else { /* SK_YUKON_FAMILY */
1576 if (skrs == 0x00)
1577 sc->sk_ramsize = 0x20000;
1578 else
1579 sc->sk_ramsize = skrs * (1<<12);
1580 sc->sk_rboff = SK_RBOFF_0;
1581 }
1582
1583 /* Read and save physical media type */
1584 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1585
1586 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1587 sc->sk_coppertype = 1;
1588 else
1589 sc->sk_coppertype = 0;
1590
1591 /* Determine whether to name it with VPD PN or just make it up.
1592 * Marvell Yukon VPD PN seems to freqently be bogus. */
1593 switch (pci_get_device(dev)) {
1594 case DEVICEID_SK_V1:
1595 case DEVICEID_BELKIN_5005:
1596 case DEVICEID_3COM_3C940:
1597 case DEVICEID_LINKSYS_EG1032:
1598 case DEVICEID_DLINK_DGE530T_A1:
1599 case DEVICEID_DLINK_DGE530T_B1:
1600 /* Stay with VPD PN. */
1601 (void) pci_get_vpd_ident(dev, &pname);
1602 break;
1603 case DEVICEID_SK_V2:
1604 /* YUKON VPD PN might bear no resemblance to reality. */
1605 switch (sc->sk_type) {
1606 case SK_GENESIS:
1607 /* Stay with VPD PN. */
1608 (void) pci_get_vpd_ident(dev, &pname);
1609 break;
1610 case SK_YUKON:
1611 pname = "Marvell Yukon Gigabit Ethernet";
1612 break;
1613 case SK_YUKON_LITE:
1614 pname = "Marvell Yukon Lite Gigabit Ethernet";
1615 break;
1616 case SK_YUKON_LP:
1617 pname = "Marvell Yukon LP Gigabit Ethernet";
1618 break;
1619 default:
1620 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1621 break;
1622 }
1623
1624 /* Yukon Lite Rev. A0 needs special test. */
1625 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1626 u_int32_t far;
1627 u_int8_t testbyte;
1628
1629 /* Save flash address register before testing. */
1630 far = sk_win_read_4(sc, SK_EP_ADDR);
1631
1632 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1633 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1634
1635 if (testbyte != 0x00) {
1636 /* Yukon Lite Rev. A0 detected. */
1637 sc->sk_type = SK_YUKON_LITE;
1638 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1639 /* Restore flash address register. */
1640 sk_win_write_4(sc, SK_EP_ADDR, far);
1641 }
1642 }
1643 break;
1644 default:
1645 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1646 "chipver=%02x, rev=%x\n",
1647 pci_get_vendor(dev), pci_get_device(dev),
1648 sc->sk_type, sc->sk_rev);
1649 error = ENXIO;
1650 goto fail;
1651 }
1652
1653 if (sc->sk_type == SK_YUKON_LITE) {
1654 switch (sc->sk_rev) {
1655 case SK_YUKON_LITE_REV_A0:
1656 revstr = "A0";
1657 break;
1658 case SK_YUKON_LITE_REV_A1:
1659 revstr = "A1";
1660 break;
1661 case SK_YUKON_LITE_REV_A3:
1662 revstr = "A3";
1663 break;
1664 default:
1665 revstr = "";
1666 break;
1667 }
1668 } else {
1669 revstr = "";
1670 }
1671
1672 /* Announce the product name and more VPD data if there. */
1673 if (pname != NULL)
1674 device_printf(dev, "%s rev. %s(0x%x)\n",
1675 pname, revstr, sc->sk_rev);
1676
1677 if (bootverbose) {
1678 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1679 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1680 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1681 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1682 }
1683
1684 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", DEVICE_UNIT_ANY);
1685 if (sc->sk_devs[SK_PORT_A] == NULL) {
1686 device_printf(dev, "failed to add child for PORT_A\n");
1687 error = ENXIO;
1688 goto fail;
1689 }
1690 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1691 if (port == NULL) {
1692 device_printf(dev, "failed to allocate memory for "
1693 "ivars of PORT_A\n");
1694 error = ENXIO;
1695 goto fail;
1696 }
1697 *port = SK_PORT_A;
1698 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1699
1700 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1701 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", DEVICE_UNIT_ANY);
1702 if (sc->sk_devs[SK_PORT_B] == NULL) {
1703 device_printf(dev, "failed to add child for PORT_B\n");
1704 error = ENXIO;
1705 goto fail;
1706 }
1707 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1708 if (port == NULL) {
1709 device_printf(dev, "failed to allocate memory for "
1710 "ivars of PORT_B\n");
1711 error = ENXIO;
1712 goto fail;
1713 }
1714 *port = SK_PORT_B;
1715 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1716 }
1717
1718 /* Turn on the 'driver is loaded' LED. */
1719 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1720
1721 bus_attach_children(dev);
1722
1723 /* Hook interrupt last to avoid having to lock softc */
1724 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1725 NULL, sk_intr, sc, &sc->sk_intrhand);
1726
1727 if (error) {
1728 device_printf(dev, "couldn't set up irq\n");
1729 goto fail;
1730 }
1731
1732 fail:
1733 if (error)
1734 skc_detach(dev);
1735
1736 return(error);
1737 }
1738
1739 static void
skc_child_deleted(device_t dev,device_t child)1740 skc_child_deleted(device_t dev, device_t child)
1741 {
1742 free(device_get_ivars(child), M_DEVBUF);
1743 }
1744
1745 /*
1746 * Shutdown hardware and free up resources. This can be called any
1747 * time after the mutex has been initialized. It is called in both
1748 * the error case in attach and the normal detach case so it needs
1749 * to be careful about only freeing resources that have actually been
1750 * allocated.
1751 */
1752 static int
sk_detach(device_t dev)1753 sk_detach(device_t dev)
1754 {
1755 struct sk_if_softc *sc_if;
1756 if_t ifp;
1757
1758 sc_if = device_get_softc(dev);
1759 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1760 ("sk mutex not initialized in sk_detach"));
1761 SK_IF_LOCK(sc_if);
1762
1763 ifp = sc_if->sk_ifp;
1764 /* These should only be active if attach_xmac succeeded */
1765 if (device_is_attached(dev)) {
1766 sk_stop(sc_if);
1767 /* Can't hold locks while calling detach */
1768 SK_IF_UNLOCK(sc_if);
1769 callout_drain(&sc_if->sk_tick_ch);
1770 callout_drain(&sc_if->sk_watchdog_ch);
1771 ether_ifdetach(ifp);
1772 SK_IF_LOCK(sc_if);
1773 }
1774 /*
1775 * We're generally called from skc_detach() which is using
1776 * device_delete_child() to get to here. It's already trashed
1777 * miibus for us, so don't do it here or we'll panic.
1778 */
1779 /*
1780 if (sc_if->sk_miibus != NULL)
1781 device_delete_child(dev, sc_if->sk_miibus);
1782 */
1783 bus_generic_detach(dev);
1784 sk_dma_jumbo_free(sc_if);
1785 sk_dma_free(sc_if);
1786 SK_IF_UNLOCK(sc_if);
1787 if (ifp)
1788 if_free(ifp);
1789
1790 return(0);
1791 }
1792
1793 static int
skc_detach(device_t dev)1794 skc_detach(device_t dev)
1795 {
1796 struct sk_softc *sc;
1797
1798 sc = device_get_softc(dev);
1799 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1800
1801 if (device_is_alive(dev)) {
1802 if (sc->sk_devs[SK_PORT_A] != NULL) {
1803 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1804 }
1805 if (sc->sk_devs[SK_PORT_B] != NULL) {
1806 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1807 }
1808 bus_generic_detach(dev);
1809 }
1810
1811 if (sc->sk_intrhand)
1812 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1813 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1814
1815 mtx_destroy(&sc->sk_mii_mtx);
1816 mtx_destroy(&sc->sk_mtx);
1817
1818 return(0);
1819 }
1820
1821 static bus_dma_tag_t
skc_get_dma_tag(device_t bus,device_t child __unused)1822 skc_get_dma_tag(device_t bus, device_t child __unused)
1823 {
1824
1825 return (bus_get_dma_tag(bus));
1826 }
1827
1828 struct sk_dmamap_arg {
1829 bus_addr_t sk_busaddr;
1830 };
1831
1832 static void
sk_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)1833 sk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1834 {
1835 struct sk_dmamap_arg *ctx;
1836
1837 if (error != 0)
1838 return;
1839
1840 ctx = arg;
1841 ctx->sk_busaddr = segs[0].ds_addr;
1842 }
1843
1844 /*
1845 * Allocate jumbo buffer storage. The SysKonnect adapters support
1846 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1847 * use them in their drivers. In order for us to use them, we need
1848 * large 9K receive buffers, however standard mbuf clusters are only
1849 * 2048 bytes in size. Consequently, we need to allocate and manage
1850 * our own jumbo buffer pool. Fortunately, this does not require an
1851 * excessive amount of additional code.
1852 */
1853 static int
sk_dma_alloc(struct sk_if_softc * sc_if)1854 sk_dma_alloc(struct sk_if_softc *sc_if)
1855 {
1856 struct sk_dmamap_arg ctx;
1857 struct sk_txdesc *txd;
1858 struct sk_rxdesc *rxd;
1859 int error, i;
1860
1861 /* create parent tag */
1862 /*
1863 * XXX
1864 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1865 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1866 * However bz@ reported that it does not work on amd64 with > 4GB
1867 * RAM. Until we have more clues of the breakage, disable DAC mode
1868 * by limiting DMA address to be in 32bit address space.
1869 */
1870 error = bus_dma_tag_create(
1871 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1872 1, 0, /* algnmnt, boundary */
1873 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1874 BUS_SPACE_MAXADDR, /* highaddr */
1875 NULL, NULL, /* filter, filterarg */
1876 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1877 0, /* nsegments */
1878 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1879 0, /* flags */
1880 NULL, NULL, /* lockfunc, lockarg */
1881 &sc_if->sk_cdata.sk_parent_tag);
1882 if (error != 0) {
1883 device_printf(sc_if->sk_if_dev,
1884 "failed to create parent DMA tag\n");
1885 goto fail;
1886 }
1887
1888 /* create tag for Tx ring */
1889 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1890 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1891 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1892 BUS_SPACE_MAXADDR, /* highaddr */
1893 NULL, NULL, /* filter, filterarg */
1894 SK_TX_RING_SZ, /* maxsize */
1895 1, /* nsegments */
1896 SK_TX_RING_SZ, /* maxsegsize */
1897 0, /* flags */
1898 NULL, NULL, /* lockfunc, lockarg */
1899 &sc_if->sk_cdata.sk_tx_ring_tag);
1900 if (error != 0) {
1901 device_printf(sc_if->sk_if_dev,
1902 "failed to allocate Tx ring DMA tag\n");
1903 goto fail;
1904 }
1905
1906 /* create tag for Rx ring */
1907 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1908 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1909 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1910 BUS_SPACE_MAXADDR, /* highaddr */
1911 NULL, NULL, /* filter, filterarg */
1912 SK_RX_RING_SZ, /* maxsize */
1913 1, /* nsegments */
1914 SK_RX_RING_SZ, /* maxsegsize */
1915 0, /* flags */
1916 NULL, NULL, /* lockfunc, lockarg */
1917 &sc_if->sk_cdata.sk_rx_ring_tag);
1918 if (error != 0) {
1919 device_printf(sc_if->sk_if_dev,
1920 "failed to allocate Rx ring DMA tag\n");
1921 goto fail;
1922 }
1923
1924 /* create tag for Tx buffers */
1925 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1926 1, 0, /* algnmnt, boundary */
1927 BUS_SPACE_MAXADDR, /* lowaddr */
1928 BUS_SPACE_MAXADDR, /* highaddr */
1929 NULL, NULL, /* filter, filterarg */
1930 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
1931 SK_MAXTXSEGS, /* nsegments */
1932 MCLBYTES, /* maxsegsize */
1933 0, /* flags */
1934 NULL, NULL, /* lockfunc, lockarg */
1935 &sc_if->sk_cdata.sk_tx_tag);
1936 if (error != 0) {
1937 device_printf(sc_if->sk_if_dev,
1938 "failed to allocate Tx DMA tag\n");
1939 goto fail;
1940 }
1941
1942 /* create tag for Rx buffers */
1943 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1944 1, 0, /* algnmnt, boundary */
1945 BUS_SPACE_MAXADDR, /* lowaddr */
1946 BUS_SPACE_MAXADDR, /* highaddr */
1947 NULL, NULL, /* filter, filterarg */
1948 MCLBYTES, /* maxsize */
1949 1, /* nsegments */
1950 MCLBYTES, /* maxsegsize */
1951 0, /* flags */
1952 NULL, NULL, /* lockfunc, lockarg */
1953 &sc_if->sk_cdata.sk_rx_tag);
1954 if (error != 0) {
1955 device_printf(sc_if->sk_if_dev,
1956 "failed to allocate Rx DMA tag\n");
1957 goto fail;
1958 }
1959
1960 /* allocate DMA'able memory and load the DMA map for Tx ring */
1961 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
1962 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
1963 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
1964 if (error != 0) {
1965 device_printf(sc_if->sk_if_dev,
1966 "failed to allocate DMA'able memory for Tx ring\n");
1967 goto fail;
1968 }
1969
1970 ctx.sk_busaddr = 0;
1971 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
1972 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
1973 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1974 if (error != 0) {
1975 device_printf(sc_if->sk_if_dev,
1976 "failed to load DMA'able memory for Tx ring\n");
1977 goto fail;
1978 }
1979 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
1980
1981 /* allocate DMA'able memory and load the DMA map for Rx ring */
1982 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
1983 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
1984 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
1985 if (error != 0) {
1986 device_printf(sc_if->sk_if_dev,
1987 "failed to allocate DMA'able memory for Rx ring\n");
1988 goto fail;
1989 }
1990
1991 ctx.sk_busaddr = 0;
1992 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
1993 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
1994 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1995 if (error != 0) {
1996 device_printf(sc_if->sk_if_dev,
1997 "failed to load DMA'able memory for Rx ring\n");
1998 goto fail;
1999 }
2000 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2001
2002 /* create DMA maps for Tx buffers */
2003 for (i = 0; i < SK_TX_RING_CNT; i++) {
2004 txd = &sc_if->sk_cdata.sk_txdesc[i];
2005 txd->tx_m = NULL;
2006 txd->tx_dmamap = NULL;
2007 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2008 &txd->tx_dmamap);
2009 if (error != 0) {
2010 device_printf(sc_if->sk_if_dev,
2011 "failed to create Tx dmamap\n");
2012 goto fail;
2013 }
2014 }
2015
2016 /* create DMA maps for Rx buffers */
2017 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2018 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2019 device_printf(sc_if->sk_if_dev,
2020 "failed to create spare Rx dmamap\n");
2021 goto fail;
2022 }
2023 for (i = 0; i < SK_RX_RING_CNT; i++) {
2024 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2025 rxd->rx_m = NULL;
2026 rxd->rx_dmamap = NULL;
2027 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2028 &rxd->rx_dmamap);
2029 if (error != 0) {
2030 device_printf(sc_if->sk_if_dev,
2031 "failed to create Rx dmamap\n");
2032 goto fail;
2033 }
2034 }
2035
2036 fail:
2037 return (error);
2038 }
2039
2040 static int
sk_dma_jumbo_alloc(struct sk_if_softc * sc_if)2041 sk_dma_jumbo_alloc(struct sk_if_softc *sc_if)
2042 {
2043 struct sk_dmamap_arg ctx;
2044 struct sk_rxdesc *jrxd;
2045 int error, i;
2046
2047 if (jumbo_disable != 0) {
2048 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2049 sc_if->sk_jumbo_disable = 1;
2050 return (0);
2051 }
2052 /* create tag for jumbo Rx ring */
2053 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2054 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2055 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2056 BUS_SPACE_MAXADDR, /* highaddr */
2057 NULL, NULL, /* filter, filterarg */
2058 SK_JUMBO_RX_RING_SZ, /* maxsize */
2059 1, /* nsegments */
2060 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2061 0, /* flags */
2062 NULL, NULL, /* lockfunc, lockarg */
2063 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2064 if (error != 0) {
2065 device_printf(sc_if->sk_if_dev,
2066 "failed to allocate jumbo Rx ring DMA tag\n");
2067 goto jumbo_fail;
2068 }
2069
2070 /* create tag for jumbo Rx buffers */
2071 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2072 1, 0, /* algnmnt, boundary */
2073 BUS_SPACE_MAXADDR, /* lowaddr */
2074 BUS_SPACE_MAXADDR, /* highaddr */
2075 NULL, NULL, /* filter, filterarg */
2076 MJUM9BYTES, /* maxsize */
2077 1, /* nsegments */
2078 MJUM9BYTES, /* maxsegsize */
2079 0, /* flags */
2080 NULL, NULL, /* lockfunc, lockarg */
2081 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2082 if (error != 0) {
2083 device_printf(sc_if->sk_if_dev,
2084 "failed to allocate jumbo Rx DMA tag\n");
2085 goto jumbo_fail;
2086 }
2087
2088 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2089 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2090 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2091 BUS_DMA_COHERENT | BUS_DMA_ZERO,
2092 &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2093 if (error != 0) {
2094 device_printf(sc_if->sk_if_dev,
2095 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2096 goto jumbo_fail;
2097 }
2098
2099 ctx.sk_busaddr = 0;
2100 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2101 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2102 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2103 &ctx, BUS_DMA_NOWAIT);
2104 if (error != 0) {
2105 device_printf(sc_if->sk_if_dev,
2106 "failed to load DMA'able memory for jumbo Rx ring\n");
2107 goto jumbo_fail;
2108 }
2109 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2110
2111 /* create DMA maps for jumbo Rx buffers */
2112 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2113 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2114 device_printf(sc_if->sk_if_dev,
2115 "failed to create spare jumbo Rx dmamap\n");
2116 goto jumbo_fail;
2117 }
2118 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2119 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2120 jrxd->rx_m = NULL;
2121 jrxd->rx_dmamap = NULL;
2122 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2123 &jrxd->rx_dmamap);
2124 if (error != 0) {
2125 device_printf(sc_if->sk_if_dev,
2126 "failed to create jumbo Rx dmamap\n");
2127 goto jumbo_fail;
2128 }
2129 }
2130
2131 return (0);
2132
2133 jumbo_fail:
2134 sk_dma_jumbo_free(sc_if);
2135 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2136 "resource shortage\n");
2137 sc_if->sk_jumbo_disable = 1;
2138 return (0);
2139 }
2140
2141 static void
sk_dma_free(struct sk_if_softc * sc_if)2142 sk_dma_free(struct sk_if_softc *sc_if)
2143 {
2144 struct sk_txdesc *txd;
2145 struct sk_rxdesc *rxd;
2146 int i;
2147
2148 /* Tx ring */
2149 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2150 if (sc_if->sk_rdata.sk_tx_ring_paddr)
2151 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2152 sc_if->sk_cdata.sk_tx_ring_map);
2153 if (sc_if->sk_rdata.sk_tx_ring)
2154 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2155 sc_if->sk_rdata.sk_tx_ring,
2156 sc_if->sk_cdata.sk_tx_ring_map);
2157 sc_if->sk_rdata.sk_tx_ring = NULL;
2158 sc_if->sk_rdata.sk_tx_ring_paddr = 0;
2159 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2160 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2161 }
2162 /* Rx ring */
2163 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2164 if (sc_if->sk_rdata.sk_rx_ring_paddr)
2165 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2166 sc_if->sk_cdata.sk_rx_ring_map);
2167 if (sc_if->sk_rdata.sk_rx_ring)
2168 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2169 sc_if->sk_rdata.sk_rx_ring,
2170 sc_if->sk_cdata.sk_rx_ring_map);
2171 sc_if->sk_rdata.sk_rx_ring = NULL;
2172 sc_if->sk_rdata.sk_rx_ring_paddr = 0;
2173 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2174 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2175 }
2176 /* Tx buffers */
2177 if (sc_if->sk_cdata.sk_tx_tag) {
2178 for (i = 0; i < SK_TX_RING_CNT; i++) {
2179 txd = &sc_if->sk_cdata.sk_txdesc[i];
2180 if (txd->tx_dmamap) {
2181 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2182 txd->tx_dmamap);
2183 txd->tx_dmamap = NULL;
2184 }
2185 }
2186 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2187 sc_if->sk_cdata.sk_tx_tag = NULL;
2188 }
2189 /* Rx buffers */
2190 if (sc_if->sk_cdata.sk_rx_tag) {
2191 for (i = 0; i < SK_RX_RING_CNT; i++) {
2192 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2193 if (rxd->rx_dmamap) {
2194 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2195 rxd->rx_dmamap);
2196 rxd->rx_dmamap = NULL;
2197 }
2198 }
2199 if (sc_if->sk_cdata.sk_rx_sparemap) {
2200 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2201 sc_if->sk_cdata.sk_rx_sparemap);
2202 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2203 }
2204 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2205 sc_if->sk_cdata.sk_rx_tag = NULL;
2206 }
2207
2208 if (sc_if->sk_cdata.sk_parent_tag) {
2209 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2210 sc_if->sk_cdata.sk_parent_tag = NULL;
2211 }
2212 }
2213
2214 static void
sk_dma_jumbo_free(struct sk_if_softc * sc_if)2215 sk_dma_jumbo_free(struct sk_if_softc *sc_if)
2216 {
2217 struct sk_rxdesc *jrxd;
2218 int i;
2219
2220 /* jumbo Rx ring */
2221 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2222 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr)
2223 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2224 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2225 if (sc_if->sk_rdata.sk_jumbo_rx_ring)
2226 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2227 sc_if->sk_rdata.sk_jumbo_rx_ring,
2228 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2229 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2230 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0;
2231 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2232 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2233 }
2234
2235 /* jumbo Rx buffers */
2236 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2237 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2238 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2239 if (jrxd->rx_dmamap) {
2240 bus_dmamap_destroy(
2241 sc_if->sk_cdata.sk_jumbo_rx_tag,
2242 jrxd->rx_dmamap);
2243 jrxd->rx_dmamap = NULL;
2244 }
2245 }
2246 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2247 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2248 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2249 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2250 }
2251 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2252 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2253 }
2254 }
2255
2256 static void
sk_txcksum(if_t ifp,struct mbuf * m,struct sk_tx_desc * f)2257 sk_txcksum(if_t ifp, struct mbuf *m, struct sk_tx_desc *f)
2258 {
2259 struct ip *ip;
2260 u_int16_t offset;
2261 u_int8_t *p;
2262
2263 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2264 for(; m && m->m_len == 0; m = m->m_next)
2265 ;
2266 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2267 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2268 /* checksum may be corrupted */
2269 goto sendit;
2270 }
2271 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2272 if (m->m_len != ETHER_HDR_LEN) {
2273 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2274 __func__);
2275 /* checksum may be corrupted */
2276 goto sendit;
2277 }
2278 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2279 ;
2280 if (m == NULL) {
2281 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2282 /* checksum may be corrupted */
2283 goto sendit;
2284 }
2285 ip = mtod(m, struct ip *);
2286 } else {
2287 p = mtod(m, u_int8_t *);
2288 p += ETHER_HDR_LEN;
2289 ip = (struct ip *)p;
2290 }
2291 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2292
2293 sendit:
2294 f->sk_csum_startval = 0;
2295 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2296 (offset << 16));
2297 }
2298
2299 static int
sk_encap(struct sk_if_softc * sc_if,struct mbuf ** m_head)2300 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head)
2301 {
2302 struct sk_txdesc *txd;
2303 struct sk_tx_desc *f = NULL;
2304 struct mbuf *m;
2305 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2306 u_int32_t cflags, frag, si, sk_ctl;
2307 int error, i, nseg;
2308
2309 SK_IF_LOCK_ASSERT(sc_if);
2310
2311 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2312 return (ENOBUFS);
2313
2314 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2315 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2316 if (error == EFBIG) {
2317 m = m_defrag(*m_head, M_NOWAIT);
2318 if (m == NULL) {
2319 m_freem(*m_head);
2320 *m_head = NULL;
2321 return (ENOMEM);
2322 }
2323 *m_head = m;
2324 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2325 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2326 if (error != 0) {
2327 m_freem(*m_head);
2328 *m_head = NULL;
2329 return (error);
2330 }
2331 } else if (error != 0)
2332 return (error);
2333 if (nseg == 0) {
2334 m_freem(*m_head);
2335 *m_head = NULL;
2336 return (EIO);
2337 }
2338 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2339 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2340 return (ENOBUFS);
2341 }
2342
2343 m = *m_head;
2344 if ((m->m_pkthdr.csum_flags & if_gethwassist(sc_if->sk_ifp)) != 0)
2345 cflags = SK_OPCODE_CSUM;
2346 else
2347 cflags = SK_OPCODE_DEFAULT;
2348 si = frag = sc_if->sk_cdata.sk_tx_prod;
2349 for (i = 0; i < nseg; i++) {
2350 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2351 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2352 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2353 sk_ctl = txsegs[i].ds_len | cflags;
2354 if (i == 0) {
2355 if (cflags == SK_OPCODE_CSUM)
2356 sk_txcksum(sc_if->sk_ifp, m, f);
2357 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2358 } else
2359 sk_ctl |= SK_TXCTL_OWN;
2360 f->sk_ctl = htole32(sk_ctl);
2361 sc_if->sk_cdata.sk_tx_cnt++;
2362 SK_INC(frag, SK_TX_RING_CNT);
2363 }
2364 sc_if->sk_cdata.sk_tx_prod = frag;
2365
2366 /* set EOF on the last descriptor */
2367 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2368 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2369 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2370
2371 /* turn the first descriptor ownership to NIC */
2372 f = &sc_if->sk_rdata.sk_tx_ring[si];
2373 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2374
2375 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2376 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2377 txd->tx_m = m;
2378
2379 /* sync descriptors */
2380 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2381 BUS_DMASYNC_PREWRITE);
2382 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2383 sc_if->sk_cdata.sk_tx_ring_map,
2384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2385
2386 return (0);
2387 }
2388
2389 static void
sk_start(if_t ifp)2390 sk_start(if_t ifp)
2391 {
2392 struct sk_if_softc *sc_if;
2393
2394 sc_if = if_getsoftc(ifp);
2395
2396 SK_IF_LOCK(sc_if);
2397 sk_start_locked(ifp);
2398 SK_IF_UNLOCK(sc_if);
2399
2400 return;
2401 }
2402
2403 static void
sk_start_locked(if_t ifp)2404 sk_start_locked(if_t ifp)
2405 {
2406 struct sk_softc *sc;
2407 struct sk_if_softc *sc_if;
2408 struct mbuf *m_head;
2409 int enq;
2410
2411 sc_if = if_getsoftc(ifp);
2412 sc = sc_if->sk_softc;
2413
2414 SK_IF_LOCK_ASSERT(sc_if);
2415
2416 for (enq = 0; !if_sendq_empty(ifp) &&
2417 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2418 m_head = if_dequeue(ifp);
2419 if (m_head == NULL)
2420 break;
2421
2422 /*
2423 * Pack the data into the transmit ring. If we
2424 * don't have room, set the OACTIVE flag and wait
2425 * for the NIC to drain the ring.
2426 */
2427 if (sk_encap(sc_if, &m_head)) {
2428 if (m_head == NULL)
2429 break;
2430 if_sendq_prepend(ifp, m_head);
2431 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2432 break;
2433 }
2434
2435 enq++;
2436 /*
2437 * If there's a BPF listener, bounce a copy of this frame
2438 * to him.
2439 */
2440 BPF_MTAP(ifp, m_head);
2441 }
2442
2443 if (enq > 0) {
2444 /* Transmit */
2445 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2446
2447 /* Set a timeout in case the chip goes out to lunch. */
2448 sc_if->sk_watchdog_timer = 5;
2449 }
2450 }
2451
2452 static void
sk_watchdog(void * arg)2453 sk_watchdog(void *arg)
2454 {
2455 struct sk_if_softc *sc_if;
2456 if_t ifp;
2457
2458 ifp = arg;
2459 sc_if = if_getsoftc(ifp);
2460
2461 SK_IF_LOCK_ASSERT(sc_if);
2462
2463 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2464 goto done;
2465
2466 /*
2467 * Reclaim first as there is a possibility of losing Tx completion
2468 * interrupts.
2469 */
2470 sk_txeof(sc_if);
2471 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2472 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2473 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2474 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2475 sk_init_locked(sc_if);
2476 }
2477
2478 done:
2479 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2480
2481 return;
2482 }
2483
2484 static int
skc_shutdown(device_t dev)2485 skc_shutdown(device_t dev)
2486 {
2487 struct sk_softc *sc;
2488
2489 sc = device_get_softc(dev);
2490 SK_LOCK(sc);
2491
2492 /* Turn off the 'driver is loaded' LED. */
2493 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2494
2495 /*
2496 * Reset the GEnesis controller. Doing this should also
2497 * assert the resets on the attached XMAC(s).
2498 */
2499 sk_reset(sc);
2500 SK_UNLOCK(sc);
2501
2502 return (0);
2503 }
2504
2505 static int
skc_suspend(device_t dev)2506 skc_suspend(device_t dev)
2507 {
2508 struct sk_softc *sc;
2509 struct sk_if_softc *sc_if0, *sc_if1;
2510 if_t ifp0 = NULL, ifp1 = NULL;
2511
2512 sc = device_get_softc(dev);
2513
2514 SK_LOCK(sc);
2515
2516 sc_if0 = sc->sk_if[SK_PORT_A];
2517 sc_if1 = sc->sk_if[SK_PORT_B];
2518 if (sc_if0 != NULL)
2519 ifp0 = sc_if0->sk_ifp;
2520 if (sc_if1 != NULL)
2521 ifp1 = sc_if1->sk_ifp;
2522 if (ifp0 != NULL)
2523 sk_stop(sc_if0);
2524 if (ifp1 != NULL)
2525 sk_stop(sc_if1);
2526 sc->sk_suspended = 1;
2527
2528 SK_UNLOCK(sc);
2529
2530 return (0);
2531 }
2532
2533 static int
skc_resume(device_t dev)2534 skc_resume(device_t dev)
2535 {
2536 struct sk_softc *sc;
2537 struct sk_if_softc *sc_if0, *sc_if1;
2538 if_t ifp0 = NULL, ifp1 = NULL;
2539
2540 sc = device_get_softc(dev);
2541
2542 SK_LOCK(sc);
2543
2544 sc_if0 = sc->sk_if[SK_PORT_A];
2545 sc_if1 = sc->sk_if[SK_PORT_B];
2546 if (sc_if0 != NULL)
2547 ifp0 = sc_if0->sk_ifp;
2548 if (sc_if1 != NULL)
2549 ifp1 = sc_if1->sk_ifp;
2550 if (ifp0 != NULL && if_getflags(ifp0) & IFF_UP)
2551 sk_init_locked(sc_if0);
2552 if (ifp1 != NULL && if_getflags(ifp1) & IFF_UP)
2553 sk_init_locked(sc_if1);
2554 sc->sk_suspended = 0;
2555
2556 SK_UNLOCK(sc);
2557
2558 return (0);
2559 }
2560
2561 /*
2562 * According to the data sheet from SK-NET GENESIS the hardware can compute
2563 * two Rx checksums at the same time(Each checksum start position is
2564 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2565 * does not work at least on my Yukon hardware. I tried every possible ways
2566 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2567 * checksum offload was disabled at the moment and only IP checksum offload
2568 * was enabled.
2569 * As normal IP header size is 20 bytes I can't expect it would give an
2570 * increase in throughput. However it seems it doesn't hurt performance in
2571 * my testing. If there is a more detailed information for checksum secret
2572 * of the hardware in question please contact yongari@FreeBSD.org to add
2573 * TCP/UDP checksum offload support.
2574 */
2575 static __inline void
sk_rxcksum(if_t ifp,struct mbuf * m,u_int32_t csum)2576 sk_rxcksum(if_t ifp, struct mbuf *m, u_int32_t csum)
2577 {
2578 struct ether_header *eh;
2579 struct ip *ip;
2580 int32_t hlen, len, pktlen;
2581 u_int16_t csum1, csum2, ipcsum;
2582
2583 pktlen = m->m_pkthdr.len;
2584 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2585 return;
2586 eh = mtod(m, struct ether_header *);
2587 if (eh->ether_type != htons(ETHERTYPE_IP))
2588 return;
2589 ip = (struct ip *)(eh + 1);
2590 if (ip->ip_v != IPVERSION)
2591 return;
2592 hlen = ip->ip_hl << 2;
2593 pktlen -= sizeof(struct ether_header);
2594 if (hlen < sizeof(struct ip))
2595 return;
2596 if (ntohs(ip->ip_len) < hlen)
2597 return;
2598 if (ntohs(ip->ip_len) != pktlen)
2599 return;
2600
2601 csum1 = htons(csum & 0xffff);
2602 csum2 = htons((csum >> 16) & 0xffff);
2603 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2604 /* checksum fixup for IP options */
2605 len = hlen - sizeof(struct ip);
2606 if (len > 0) {
2607 /*
2608 * If the second checksum value is correct we can compute IP
2609 * checksum with simple math. Unfortunately the second checksum
2610 * value is wrong so we can't verify the checksum from the
2611 * value(It seems there is some magic here to get correct
2612 * value). If the second checksum value is correct it also
2613 * means we can get TCP/UDP checksum) here. However, it still
2614 * needs pseudo header checksum calculation due to hardware
2615 * limitations.
2616 */
2617 return;
2618 }
2619 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2620 if (ipcsum == 0xffff)
2621 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2622 }
2623
2624 static __inline int
sk_rxvalid(struct sk_softc * sc,u_int32_t stat,u_int32_t len)2625 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
2626 {
2627
2628 if (sc->sk_type == SK_GENESIS) {
2629 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2630 XM_RXSTAT_BYTES(stat) != len)
2631 return (0);
2632 } else {
2633 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2634 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2635 YU_RXSTAT_JABBER)) != 0 ||
2636 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2637 YU_RXSTAT_BYTES(stat) != len)
2638 return (0);
2639 }
2640
2641 return (1);
2642 }
2643
2644 static void
sk_rxeof(struct sk_if_softc * sc_if)2645 sk_rxeof(struct sk_if_softc *sc_if)
2646 {
2647 struct sk_softc *sc;
2648 struct mbuf *m;
2649 if_t ifp;
2650 struct sk_rx_desc *cur_rx;
2651 struct sk_rxdesc *rxd;
2652 int cons, prog;
2653 u_int32_t csum, rxstat, sk_ctl;
2654
2655 sc = sc_if->sk_softc;
2656 ifp = sc_if->sk_ifp;
2657
2658 SK_IF_LOCK_ASSERT(sc_if);
2659
2660 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2661 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2662
2663 prog = 0;
2664 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2665 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2666 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2667 sk_ctl = le32toh(cur_rx->sk_ctl);
2668 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2669 break;
2670 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2671 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2672
2673 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2674 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2675 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2676 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2677 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2678 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2679 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2680 sk_discard_rxbuf(sc_if, cons);
2681 continue;
2682 }
2683
2684 m = rxd->rx_m;
2685 csum = le32toh(cur_rx->sk_csum);
2686 if (sk_newbuf(sc_if, cons) != 0) {
2687 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2688 /* reuse old buffer */
2689 sk_discard_rxbuf(sc_if, cons);
2690 continue;
2691 }
2692 m->m_pkthdr.rcvif = ifp;
2693 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2694 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2695 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2696 sk_rxcksum(ifp, m, csum);
2697 SK_IF_UNLOCK(sc_if);
2698 if_input(ifp, m);
2699 SK_IF_LOCK(sc_if);
2700 }
2701
2702 if (prog > 0) {
2703 sc_if->sk_cdata.sk_rx_cons = cons;
2704 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2705 sc_if->sk_cdata.sk_rx_ring_map,
2706 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2707 }
2708 }
2709
2710 static void
sk_jumbo_rxeof(struct sk_if_softc * sc_if)2711 sk_jumbo_rxeof(struct sk_if_softc *sc_if)
2712 {
2713 struct sk_softc *sc;
2714 struct mbuf *m;
2715 if_t ifp;
2716 struct sk_rx_desc *cur_rx;
2717 struct sk_rxdesc *jrxd;
2718 int cons, prog;
2719 u_int32_t csum, rxstat, sk_ctl;
2720
2721 sc = sc_if->sk_softc;
2722 ifp = sc_if->sk_ifp;
2723
2724 SK_IF_LOCK_ASSERT(sc_if);
2725
2726 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2727 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2728
2729 prog = 0;
2730 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2731 prog < SK_JUMBO_RX_RING_CNT;
2732 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2733 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2734 sk_ctl = le32toh(cur_rx->sk_ctl);
2735 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2736 break;
2737 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2738 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2739
2740 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2741 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2742 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2743 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2744 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2745 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2746 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2747 sk_discard_jumbo_rxbuf(sc_if, cons);
2748 continue;
2749 }
2750
2751 m = jrxd->rx_m;
2752 csum = le32toh(cur_rx->sk_csum);
2753 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2754 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2755 /* reuse old buffer */
2756 sk_discard_jumbo_rxbuf(sc_if, cons);
2757 continue;
2758 }
2759 m->m_pkthdr.rcvif = ifp;
2760 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2761 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2762 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2763 sk_rxcksum(ifp, m, csum);
2764 SK_IF_UNLOCK(sc_if);
2765 if_input(ifp, m);
2766 SK_IF_LOCK(sc_if);
2767 }
2768
2769 if (prog > 0) {
2770 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2771 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2772 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2773 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2774 }
2775 }
2776
2777 static void
sk_txeof(struct sk_if_softc * sc_if)2778 sk_txeof(struct sk_if_softc *sc_if)
2779 {
2780 struct sk_txdesc *txd;
2781 struct sk_tx_desc *cur_tx;
2782 if_t ifp;
2783 u_int32_t idx, sk_ctl;
2784
2785 ifp = sc_if->sk_ifp;
2786
2787 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2788 if (txd == NULL)
2789 return;
2790 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2791 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2792 /*
2793 * Go through our tx ring and free mbufs for those
2794 * frames that have been sent.
2795 */
2796 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2797 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2798 break;
2799 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2800 sk_ctl = le32toh(cur_tx->sk_ctl);
2801 if (sk_ctl & SK_TXCTL_OWN)
2802 break;
2803 sc_if->sk_cdata.sk_tx_cnt--;
2804 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2805 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2806 continue;
2807 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2808 BUS_DMASYNC_POSTWRITE);
2809 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2810
2811 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2812 m_freem(txd->tx_m);
2813 txd->tx_m = NULL;
2814 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2815 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2816 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2817 }
2818 sc_if->sk_cdata.sk_tx_cons = idx;
2819 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2820
2821 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2822 sc_if->sk_cdata.sk_tx_ring_map,
2823 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2824 }
2825
2826 static void
sk_tick(void * xsc_if)2827 sk_tick(void *xsc_if)
2828 {
2829 struct sk_if_softc *sc_if;
2830 struct mii_data *mii;
2831 if_t ifp;
2832 int i;
2833
2834 sc_if = xsc_if;
2835 ifp = sc_if->sk_ifp;
2836 mii = device_get_softc(sc_if->sk_miibus);
2837
2838 if (!(if_getflags(ifp) & IFF_UP))
2839 return;
2840
2841 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2842 sk_intr_bcom(sc_if);
2843 return;
2844 }
2845
2846 /*
2847 * According to SysKonnect, the correct way to verify that
2848 * the link has come back up is to poll bit 0 of the GPIO
2849 * register three times. This pin has the signal from the
2850 * link_sync pin connected to it; if we read the same link
2851 * state 3 times in a row, we know the link is up.
2852 */
2853 for (i = 0; i < 3; i++) {
2854 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2855 break;
2856 }
2857
2858 if (i != 3) {
2859 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2860 return;
2861 }
2862
2863 /* Turn the GP0 interrupt back on. */
2864 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2865 SK_XM_READ_2(sc_if, XM_ISR);
2866 mii_tick(mii);
2867 callout_stop(&sc_if->sk_tick_ch);
2868 }
2869
2870 static void
sk_yukon_tick(void * xsc_if)2871 sk_yukon_tick(void *xsc_if)
2872 {
2873 struct sk_if_softc *sc_if;
2874 struct mii_data *mii;
2875
2876 sc_if = xsc_if;
2877 mii = device_get_softc(sc_if->sk_miibus);
2878
2879 mii_tick(mii);
2880 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2881 }
2882
2883 static void
sk_intr_bcom(struct sk_if_softc * sc_if)2884 sk_intr_bcom(struct sk_if_softc *sc_if)
2885 {
2886 struct mii_data *mii;
2887 if_t ifp;
2888 int status;
2889 mii = device_get_softc(sc_if->sk_miibus);
2890 ifp = sc_if->sk_ifp;
2891
2892 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2893
2894 /*
2895 * Read the PHY interrupt register to make sure
2896 * we clear any pending interrupts.
2897 */
2898 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2899
2900 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
2901 sk_init_xmac(sc_if);
2902 return;
2903 }
2904
2905 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2906 int lstat;
2907 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2908 BRGPHY_MII_AUXSTS);
2909
2910 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2911 mii_mediachg(mii);
2912 /* Turn off the link LED. */
2913 SK_IF_WRITE_1(sc_if, 0,
2914 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2915 sc_if->sk_link = 0;
2916 } else if (status & BRGPHY_ISR_LNK_CHG) {
2917 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2918 BRGPHY_MII_IMR, 0xFF00);
2919 mii_tick(mii);
2920 sc_if->sk_link = 1;
2921 /* Turn on the link LED. */
2922 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2923 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2924 SK_LINKLED_BLINK_OFF);
2925 } else {
2926 mii_tick(mii);
2927 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2928 }
2929 }
2930
2931 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2932
2933 return;
2934 }
2935
2936 static void
sk_intr_xmac(struct sk_if_softc * sc_if)2937 sk_intr_xmac(struct sk_if_softc *sc_if)
2938 {
2939 u_int16_t status;
2940
2941 status = SK_XM_READ_2(sc_if, XM_ISR);
2942
2943 /*
2944 * Link has gone down. Start MII tick timeout to
2945 * watch for link resync.
2946 */
2947 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2948 if (status & XM_ISR_GP0_SET) {
2949 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2950 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2951 }
2952
2953 if (status & XM_ISR_AUTONEG_DONE) {
2954 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2955 }
2956 }
2957
2958 if (status & XM_IMR_TX_UNDERRUN)
2959 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2960
2961 if (status & XM_IMR_RX_OVERRUN)
2962 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2963
2964 status = SK_XM_READ_2(sc_if, XM_ISR);
2965
2966 return;
2967 }
2968
2969 static void
sk_intr_yukon(struct sk_if_softc * sc_if)2970 sk_intr_yukon(struct sk_if_softc *sc_if)
2971 {
2972 u_int8_t status;
2973
2974 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2975 /* RX overrun */
2976 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2977 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2978 SK_RFCTL_RX_FIFO_OVER);
2979 }
2980 /* TX underrun */
2981 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2982 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2983 SK_TFCTL_TX_FIFO_UNDER);
2984 }
2985 }
2986
2987 static void
sk_intr(void * xsc)2988 sk_intr(void *xsc)
2989 {
2990 struct sk_softc *sc = xsc;
2991 struct sk_if_softc *sc_if0, *sc_if1;
2992 if_t ifp0 = NULL, ifp1 = NULL;
2993 u_int32_t status;
2994
2995 SK_LOCK(sc);
2996
2997 status = CSR_READ_4(sc, SK_ISSR);
2998 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
2999 goto done_locked;
3000
3001 sc_if0 = sc->sk_if[SK_PORT_A];
3002 sc_if1 = sc->sk_if[SK_PORT_B];
3003
3004 if (sc_if0 != NULL)
3005 ifp0 = sc_if0->sk_ifp;
3006 if (sc_if1 != NULL)
3007 ifp1 = sc_if1->sk_ifp;
3008
3009 for (; (status &= sc->sk_intrmask) != 0;) {
3010 /* Handle receive interrupts first. */
3011 if (status & SK_ISR_RX1_EOF) {
3012 if (if_getmtu(ifp0) > SK_MAX_FRAMELEN)
3013 sk_jumbo_rxeof(sc_if0);
3014 else
3015 sk_rxeof(sc_if0);
3016 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3017 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3018 }
3019 if (status & SK_ISR_RX2_EOF) {
3020 if (if_getflags(ifp1) > SK_MAX_FRAMELEN)
3021 sk_jumbo_rxeof(sc_if1);
3022 else
3023 sk_rxeof(sc_if1);
3024 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3025 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3026 }
3027
3028 /* Then transmit interrupts. */
3029 if (status & SK_ISR_TX1_S_EOF) {
3030 sk_txeof(sc_if0);
3031 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3032 }
3033 if (status & SK_ISR_TX2_S_EOF) {
3034 sk_txeof(sc_if1);
3035 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3036 }
3037
3038 /* Then MAC interrupts. */
3039 if (status & SK_ISR_MAC1 &&
3040 if_getdrvflags(ifp0) & IFF_DRV_RUNNING) {
3041 if (sc->sk_type == SK_GENESIS)
3042 sk_intr_xmac(sc_if0);
3043 else
3044 sk_intr_yukon(sc_if0);
3045 }
3046
3047 if (status & SK_ISR_MAC2 &&
3048 if_getdrvflags(ifp1) & IFF_DRV_RUNNING) {
3049 if (sc->sk_type == SK_GENESIS)
3050 sk_intr_xmac(sc_if1);
3051 else
3052 sk_intr_yukon(sc_if1);
3053 }
3054
3055 if (status & SK_ISR_EXTERNAL_REG) {
3056 if (ifp0 != NULL &&
3057 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3058 sk_intr_bcom(sc_if0);
3059 if (ifp1 != NULL &&
3060 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3061 sk_intr_bcom(sc_if1);
3062 }
3063 status = CSR_READ_4(sc, SK_ISSR);
3064 }
3065
3066 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3067
3068 if (ifp0 != NULL && !if_sendq_empty(ifp0))
3069 sk_start_locked(ifp0);
3070 if (ifp1 != NULL && !if_sendq_empty(ifp1))
3071 sk_start_locked(ifp1);
3072
3073 done_locked:
3074 SK_UNLOCK(sc);
3075 }
3076
3077 static void
sk_init_xmac(struct sk_if_softc * sc_if)3078 sk_init_xmac(struct sk_if_softc *sc_if)
3079 {
3080 struct sk_softc *sc;
3081 if_t ifp;
3082 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3083 static const struct sk_bcom_hack bhack[] = {
3084 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3085 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3086 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3087 { 0, 0 } };
3088
3089 SK_IF_LOCK_ASSERT(sc_if);
3090
3091 sc = sc_if->sk_softc;
3092 ifp = sc_if->sk_ifp;
3093
3094 /* Unreset the XMAC. */
3095 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3096 DELAY(1000);
3097
3098 /* Reset the XMAC's internal state. */
3099 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3100
3101 /* Save the XMAC II revision */
3102 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3103
3104 /*
3105 * Perform additional initialization for external PHYs,
3106 * namely for the 1000baseTX cards that use the XMAC's
3107 * GMII mode.
3108 */
3109 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3110 int i = 0;
3111 u_int32_t val;
3112
3113 /* Take PHY out of reset. */
3114 val = sk_win_read_4(sc, SK_GPIO);
3115 if (sc_if->sk_port == SK_PORT_A)
3116 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3117 else
3118 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3119 sk_win_write_4(sc, SK_GPIO, val);
3120
3121 /* Enable GMII mode on the XMAC. */
3122 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3123
3124 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3125 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3126 DELAY(10000);
3127 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3128 BRGPHY_MII_IMR, 0xFFF0);
3129
3130 /*
3131 * Early versions of the BCM5400 apparently have
3132 * a bug that requires them to have their reserved
3133 * registers initialized to some magic values. I don't
3134 * know what the numbers do, I'm just the messenger.
3135 */
3136 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3137 == 0x6041) {
3138 while(bhack[i].reg) {
3139 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3140 bhack[i].reg, bhack[i].val);
3141 i++;
3142 }
3143 }
3144 }
3145
3146 /* Set station address */
3147 bcopy(if_getlladdr(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3148 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3149 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3150 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3151 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3152
3153 if (if_getflags(ifp) & IFF_BROADCAST) {
3154 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3155 } else {
3156 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3157 }
3158
3159 /* We don't need the FCS appended to the packet. */
3160 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3161
3162 /* We want short frames padded to 60 bytes. */
3163 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3164
3165 /*
3166 * Enable the reception of all error frames. This is is
3167 * a necessary evil due to the design of the XMAC. The
3168 * XMAC's receive FIFO is only 8K in size, however jumbo
3169 * frames can be up to 9000 bytes in length. When bad
3170 * frame filtering is enabled, the XMAC's RX FIFO operates
3171 * in 'store and forward' mode. For this to work, the
3172 * entire frame has to fit into the FIFO, but that means
3173 * that jumbo frames larger than 8192 bytes will be
3174 * truncated. Disabling all bad frame filtering causes
3175 * the RX FIFO to operate in streaming mode, in which
3176 * case the XMAC will start transferring frames out of the
3177 * RX FIFO as soon as the FIFO threshold is reached.
3178 */
3179 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) {
3180 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3181 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3182 XM_MODE_RX_INRANGELEN);
3183 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3184 } else
3185 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3186
3187 /*
3188 * Bump up the transmit threshold. This helps hold off transmit
3189 * underruns when we're blasting traffic from both ports at once.
3190 */
3191 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3192
3193 /* Set Rx filter */
3194 sk_rxfilter_genesis(sc_if);
3195
3196 /* Clear and enable interrupts */
3197 SK_XM_READ_2(sc_if, XM_ISR);
3198 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3199 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3200 else
3201 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3202
3203 /* Configure MAC arbiter */
3204 switch(sc_if->sk_xmac_rev) {
3205 case XM_XMAC_REV_B2:
3206 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3207 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3208 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3209 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3210 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3211 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3212 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3213 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3214 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3215 break;
3216 case XM_XMAC_REV_C1:
3217 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3218 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3219 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3220 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3221 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3222 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3223 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3224 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3225 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3226 break;
3227 default:
3228 break;
3229 }
3230 sk_win_write_2(sc, SK_MACARB_CTL,
3231 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3232
3233 sc_if->sk_link = 1;
3234
3235 return;
3236 }
3237
3238 static void
sk_init_yukon(struct sk_if_softc * sc_if)3239 sk_init_yukon(struct sk_if_softc *sc_if)
3240 {
3241 u_int32_t phy, v;
3242 u_int16_t reg;
3243 struct sk_softc *sc;
3244 if_t ifp;
3245 u_int8_t *eaddr;
3246 int i;
3247
3248 SK_IF_LOCK_ASSERT(sc_if);
3249
3250 sc = sc_if->sk_softc;
3251 ifp = sc_if->sk_ifp;
3252
3253 if (sc->sk_type == SK_YUKON_LITE &&
3254 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3255 /*
3256 * Workaround code for COMA mode, set PHY reset.
3257 * Otherwise it will not correctly take chip out of
3258 * powerdown (coma)
3259 */
3260 v = sk_win_read_4(sc, SK_GPIO);
3261 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3262 sk_win_write_4(sc, SK_GPIO, v);
3263 }
3264
3265 /* GMAC and GPHY Reset */
3266 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3267 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3268 DELAY(1000);
3269
3270 if (sc->sk_type == SK_YUKON_LITE &&
3271 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3272 /*
3273 * Workaround code for COMA mode, clear PHY reset
3274 */
3275 v = sk_win_read_4(sc, SK_GPIO);
3276 v |= SK_GPIO_DIR9;
3277 v &= ~SK_GPIO_DAT9;
3278 sk_win_write_4(sc, SK_GPIO, v);
3279 }
3280
3281 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3282 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3283
3284 if (sc->sk_coppertype)
3285 phy |= SK_GPHY_COPPER;
3286 else
3287 phy |= SK_GPHY_FIBER;
3288
3289 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3290 DELAY(1000);
3291 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3292 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3293 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3294
3295 /* unused read of the interrupt source register */
3296 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3297
3298 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3299
3300 /* MIB Counter Clear Mode set */
3301 reg |= YU_PAR_MIB_CLR;
3302 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3303
3304 /* MIB Counter Clear Mode clear */
3305 reg &= ~YU_PAR_MIB_CLR;
3306 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3307
3308 /* receive control reg */
3309 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3310
3311 /* transmit parameter register */
3312 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3313 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3314
3315 /* serial mode register */
3316 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3317 if (if_getmtu(ifp) > SK_MAX_FRAMELEN)
3318 reg |= YU_SMR_MFL_JUMBO;
3319 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3320
3321 /* Setup Yukon's station address */
3322 eaddr = if_getlladdr(sc_if->sk_ifp);
3323 for (i = 0; i < 3; i++)
3324 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3325 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3326 /* Set GMAC source address of flow control. */
3327 for (i = 0; i < 3; i++)
3328 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3329 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3330 /* Set GMAC virtual address. */
3331 for (i = 0; i < 3; i++)
3332 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3333 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3334
3335 /* Set Rx filter */
3336 sk_rxfilter_yukon(sc_if);
3337
3338 /* enable interrupt mask for counter overflows */
3339 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3340 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3341 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3342
3343 /* Configure RX MAC FIFO Flush Mask */
3344 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3345 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3346 YU_RXSTAT_JABBER;
3347 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3348
3349 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3350 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3351 v = SK_TFCTL_OPERATION_ON;
3352 else
3353 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3354 /* Configure RX MAC FIFO */
3355 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3356 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3357
3358 /* Increase flush threshould to 64 bytes */
3359 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3360 SK_RFCTL_FIFO_THRESHOLD + 1);
3361
3362 /* Configure TX MAC FIFO */
3363 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3364 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3365 }
3366
3367 /*
3368 * Note that to properly initialize any part of the GEnesis chip,
3369 * you first have to take it out of reset mode.
3370 */
3371 static void
sk_init(void * xsc)3372 sk_init(void *xsc)
3373 {
3374 struct sk_if_softc *sc_if = xsc;
3375
3376 SK_IF_LOCK(sc_if);
3377 sk_init_locked(sc_if);
3378 SK_IF_UNLOCK(sc_if);
3379
3380 return;
3381 }
3382
3383 static void
sk_init_locked(struct sk_if_softc * sc_if)3384 sk_init_locked(struct sk_if_softc *sc_if)
3385 {
3386 struct sk_softc *sc;
3387 if_t ifp;
3388 struct mii_data *mii;
3389 u_int16_t reg;
3390 u_int32_t imr;
3391 int error;
3392
3393 SK_IF_LOCK_ASSERT(sc_if);
3394
3395 ifp = sc_if->sk_ifp;
3396 sc = sc_if->sk_softc;
3397 mii = device_get_softc(sc_if->sk_miibus);
3398
3399 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3400 return;
3401
3402 /* Cancel pending I/O and free all RX/TX buffers. */
3403 sk_stop(sc_if);
3404
3405 if (sc->sk_type == SK_GENESIS) {
3406 /* Configure LINK_SYNC LED */
3407 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3408 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3409 SK_LINKLED_LINKSYNC_ON);
3410
3411 /* Configure RX LED */
3412 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3413 SK_RXLEDCTL_COUNTER_START);
3414
3415 /* Configure TX LED */
3416 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3417 SK_TXLEDCTL_COUNTER_START);
3418 }
3419
3420 /*
3421 * Configure descriptor poll timer
3422 *
3423 * SK-NET GENESIS data sheet says that possibility of losing Start
3424 * transmit command due to CPU/cache related interim storage problems
3425 * under certain conditions. The document recommends a polling
3426 * mechanism to send a Start transmit command to initiate transfer
3427 * of ready descriptors regulary. To cope with this issue sk(4) now
3428 * enables descriptor poll timer to initiate descriptor processing
3429 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3430 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3431 * command instead of waiting for next descriptor polling time.
3432 * The same rule may apply to Rx side too but it seems that is not
3433 * needed at the moment.
3434 * Since sk(4) uses descriptor polling as a last resort there is no
3435 * need to set smaller polling time than maximum allowable one.
3436 */
3437 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3438
3439 /* Configure I2C registers */
3440
3441 /* Configure XMAC(s) */
3442 switch (sc->sk_type) {
3443 case SK_GENESIS:
3444 sk_init_xmac(sc_if);
3445 break;
3446 case SK_YUKON:
3447 case SK_YUKON_LITE:
3448 case SK_YUKON_LP:
3449 sk_init_yukon(sc_if);
3450 break;
3451 }
3452 mii_mediachg(mii);
3453
3454 if (sc->sk_type == SK_GENESIS) {
3455 /* Configure MAC FIFOs */
3456 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3457 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3458 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3459
3460 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3461 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3462 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3463 }
3464
3465 /* Configure transmit arbiter(s) */
3466 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3467 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3468
3469 /* Configure RAMbuffers */
3470 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3471 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3472 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3473 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3474 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3475 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3476
3477 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3478 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3479 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3480 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3481 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3482 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3483 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3484
3485 /* Configure BMUs */
3486 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3487 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) {
3488 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3489 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3490 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3491 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3492 } else {
3493 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3494 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3495 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3496 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3497 }
3498
3499 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3500 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3501 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3502 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3503 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3504
3505 /* Init descriptors */
3506 if (if_getmtu(ifp) > SK_MAX_FRAMELEN)
3507 error = sk_init_jumbo_rx_ring(sc_if);
3508 else
3509 error = sk_init_rx_ring(sc_if);
3510 if (error != 0) {
3511 device_printf(sc_if->sk_if_dev,
3512 "initialization failed: no memory for rx buffers\n");
3513 sk_stop(sc_if);
3514 return;
3515 }
3516 sk_init_tx_ring(sc_if);
3517
3518 /* Set interrupt moderation if changed via sysctl. */
3519 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3520 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3521 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3522 sc->sk_int_ticks));
3523 if (bootverbose)
3524 device_printf(sc_if->sk_if_dev,
3525 "interrupt moderation is %d us.\n",
3526 sc->sk_int_mod);
3527 }
3528
3529 /* Configure interrupt handling */
3530 CSR_READ_4(sc, SK_ISSR);
3531 if (sc_if->sk_port == SK_PORT_A)
3532 sc->sk_intrmask |= SK_INTRS1;
3533 else
3534 sc->sk_intrmask |= SK_INTRS2;
3535
3536 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3537
3538 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3539
3540 /* Start BMUs. */
3541 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3542
3543 switch(sc->sk_type) {
3544 case SK_GENESIS:
3545 /* Enable XMACs TX and RX state machines */
3546 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3547 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3548 break;
3549 case SK_YUKON:
3550 case SK_YUKON_LITE:
3551 case SK_YUKON_LP:
3552 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3553 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3554 #if 0
3555 /* XXX disable 100Mbps and full duplex mode? */
3556 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3557 #endif
3558 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3559 }
3560
3561 /* Activate descriptor polling timer */
3562 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3563 /* start transfer of Tx descriptors */
3564 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3565
3566 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3567 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3568
3569 switch (sc->sk_type) {
3570 case SK_YUKON:
3571 case SK_YUKON_LITE:
3572 case SK_YUKON_LP:
3573 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3574 break;
3575 }
3576
3577 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3578
3579 return;
3580 }
3581
3582 static void
sk_stop(struct sk_if_softc * sc_if)3583 sk_stop(struct sk_if_softc *sc_if)
3584 {
3585 int i;
3586 struct sk_softc *sc;
3587 struct sk_txdesc *txd;
3588 struct sk_rxdesc *rxd;
3589 struct sk_rxdesc *jrxd;
3590 if_t ifp;
3591 u_int32_t val;
3592
3593 SK_IF_LOCK_ASSERT(sc_if);
3594 sc = sc_if->sk_softc;
3595 ifp = sc_if->sk_ifp;
3596
3597 callout_stop(&sc_if->sk_tick_ch);
3598 callout_stop(&sc_if->sk_watchdog_ch);
3599
3600 /* stop Tx descriptor polling timer */
3601 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3602 /* stop transfer of Tx descriptors */
3603 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3604 for (i = 0; i < SK_TIMEOUT; i++) {
3605 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3606 if ((val & SK_TXBMU_TX_STOP) == 0)
3607 break;
3608 DELAY(1);
3609 }
3610 if (i == SK_TIMEOUT)
3611 device_printf(sc_if->sk_if_dev,
3612 "can not stop transfer of Tx descriptor\n");
3613 /* stop transfer of Rx descriptors */
3614 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3615 for (i = 0; i < SK_TIMEOUT; i++) {
3616 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3617 if ((val & SK_RXBMU_RX_STOP) == 0)
3618 break;
3619 DELAY(1);
3620 }
3621 if (i == SK_TIMEOUT)
3622 device_printf(sc_if->sk_if_dev,
3623 "can not stop transfer of Rx descriptor\n");
3624
3625 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3626 /* Put PHY back into reset. */
3627 val = sk_win_read_4(sc, SK_GPIO);
3628 if (sc_if->sk_port == SK_PORT_A) {
3629 val |= SK_GPIO_DIR0;
3630 val &= ~SK_GPIO_DAT0;
3631 } else {
3632 val |= SK_GPIO_DIR2;
3633 val &= ~SK_GPIO_DAT2;
3634 }
3635 sk_win_write_4(sc, SK_GPIO, val);
3636 }
3637
3638 /* Turn off various components of this interface. */
3639 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3640 switch (sc->sk_type) {
3641 case SK_GENESIS:
3642 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3643 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3644 break;
3645 case SK_YUKON:
3646 case SK_YUKON_LITE:
3647 case SK_YUKON_LP:
3648 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3649 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3650 break;
3651 }
3652 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3653 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3654 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3655 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3656 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3657 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3658 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3659 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3660 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3661
3662 /* Disable interrupts */
3663 if (sc_if->sk_port == SK_PORT_A)
3664 sc->sk_intrmask &= ~SK_INTRS1;
3665 else
3666 sc->sk_intrmask &= ~SK_INTRS2;
3667 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3668
3669 SK_XM_READ_2(sc_if, XM_ISR);
3670 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3671
3672 /* Free RX and TX mbufs still in the queues. */
3673 for (i = 0; i < SK_RX_RING_CNT; i++) {
3674 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3675 if (rxd->rx_m != NULL) {
3676 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3677 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3678 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3679 rxd->rx_dmamap);
3680 m_freem(rxd->rx_m);
3681 rxd->rx_m = NULL;
3682 }
3683 }
3684 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3685 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3686 if (jrxd->rx_m != NULL) {
3687 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3688 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3689 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3690 jrxd->rx_dmamap);
3691 m_freem(jrxd->rx_m);
3692 jrxd->rx_m = NULL;
3693 }
3694 }
3695 for (i = 0; i < SK_TX_RING_CNT; i++) {
3696 txd = &sc_if->sk_cdata.sk_txdesc[i];
3697 if (txd->tx_m != NULL) {
3698 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3699 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3700 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3701 txd->tx_dmamap);
3702 m_freem(txd->tx_m);
3703 txd->tx_m = NULL;
3704 }
3705 }
3706
3707 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE));
3708
3709 return;
3710 }
3711
3712 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3713 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3714 {
3715 int error, value;
3716
3717 if (!arg1)
3718 return (EINVAL);
3719 value = *(int *)arg1;
3720 error = sysctl_handle_int(oidp, &value, 0, req);
3721 if (error || !req->newptr)
3722 return (error);
3723 if (value < low || value > high)
3724 return (EINVAL);
3725 *(int *)arg1 = value;
3726 return (0);
3727 }
3728
3729 static int
sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)3730 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3731 {
3732 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3733 }
3734