1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
5 *
6 * Copyright (c) 1997, 1998, 1999, 2000
7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Bill Paul.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
35 */
36 /*-
37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
38 *
39 * Permission to use, copy, modify, and distribute this software for any
40 * purpose with or without fee is hereby granted, provided that the above
41 * copyright notice and this permission notice appear in all copies.
42 *
43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50 */
51
52 #include <sys/cdefs.h>
53 /*
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
56 * References:
57 * The XaQti XMAC II datasheet,
58 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 *
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
64 *
65 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 *
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
70 */
71 /*
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
78 *
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
86 */
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/bus.h>
91 #include <sys/endian.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
100
101 #include <net/bpf.h>
102 #include <net/ethernet.h>
103 #include <net/if.h>
104 #include <net/if_var.h>
105 #include <net/if_arp.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/if_types.h>
109 #include <net/if_vlan_var.h>
110
111 #include <netinet/in.h>
112 #include <netinet/in_systm.h>
113 #include <netinet/ip.h>
114
115 #include <machine/bus.h>
116 #include <machine/in_cksum.h>
117 #include <machine/resource.h>
118 #include <sys/rman.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122 #include <dev/mii/brgphyreg.h>
123
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
126
127 #if 0
128 #define SK_USEIOSPACE
129 #endif
130
131 #include <dev/sk/if_skreg.h>
132 #include <dev/sk/xmaciireg.h>
133 #include <dev/sk/yukonreg.h>
134
135 MODULE_DEPEND(sk, pci, 1, 1, 1);
136 MODULE_DEPEND(sk, ether, 1, 1, 1);
137 MODULE_DEPEND(sk, miibus, 1, 1, 1);
138
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
141
142 static const struct sk_type sk_devs[] = {
143 {
144 VENDORID_SK,
145 DEVICEID_SK_V1,
146 "SysKonnect Gigabit Ethernet (V1.0)"
147 },
148 {
149 VENDORID_SK,
150 DEVICEID_SK_V2,
151 "SysKonnect Gigabit Ethernet (V2.0)"
152 },
153 {
154 VENDORID_MARVELL,
155 DEVICEID_SK_V2,
156 "Marvell Gigabit Ethernet"
157 },
158 {
159 VENDORID_MARVELL,
160 DEVICEID_BELKIN_5005,
161 "Belkin F5D5005 Gigabit Ethernet"
162 },
163 {
164 VENDORID_3COM,
165 DEVICEID_3COM_3C940,
166 "3Com 3C940 Gigabit Ethernet"
167 },
168 {
169 VENDORID_LINKSYS,
170 DEVICEID_LINKSYS_EG1032,
171 "Linksys EG1032 Gigabit Ethernet"
172 },
173 {
174 VENDORID_DLINK,
175 DEVICEID_DLINK_DGE530T_A1,
176 "D-Link DGE-530T Gigabit Ethernet"
177 },
178 {
179 VENDORID_DLINK,
180 DEVICEID_DLINK_DGE530T_B1,
181 "D-Link DGE-530T Gigabit Ethernet"
182 },
183 { 0, 0, NULL }
184 };
185
186 static int skc_probe(device_t);
187 static int skc_attach(device_t);
188 static void skc_child_deleted(device_t, device_t);
189 static int skc_detach(device_t);
190 static int skc_shutdown(device_t);
191 static int skc_suspend(device_t);
192 static int skc_resume(device_t);
193 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
194 static int sk_detach(device_t);
195 static int sk_probe(device_t);
196 static int sk_attach(device_t);
197 static void sk_tick(void *);
198 static void sk_yukon_tick(void *);
199 static void sk_intr(void *);
200 static void sk_intr_xmac(struct sk_if_softc *);
201 static void sk_intr_bcom(struct sk_if_softc *);
202 static void sk_intr_yukon(struct sk_if_softc *);
203 static __inline void sk_rxcksum(if_t, struct mbuf *, u_int32_t);
204 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
205 static void sk_rxeof(struct sk_if_softc *);
206 static void sk_jumbo_rxeof(struct sk_if_softc *);
207 static void sk_txeof(struct sk_if_softc *);
208 static void sk_txcksum(if_t, struct mbuf *, struct sk_tx_desc *);
209 static int sk_encap(struct sk_if_softc *, struct mbuf **);
210 static void sk_start(if_t);
211 static void sk_start_locked(if_t);
212 static int sk_ioctl(if_t, u_long, caddr_t);
213 static void sk_init(void *);
214 static void sk_init_locked(struct sk_if_softc *);
215 static void sk_init_xmac(struct sk_if_softc *);
216 static void sk_init_yukon(struct sk_if_softc *);
217 static void sk_stop(struct sk_if_softc *);
218 static void sk_watchdog(void *);
219 static int sk_ifmedia_upd(if_t);
220 static void sk_ifmedia_sts(if_t, struct ifmediareq *);
221 static void sk_reset(struct sk_softc *);
222 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
223 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
224 static int sk_newbuf(struct sk_if_softc *, int);
225 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
226 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
227 static int sk_dma_alloc(struct sk_if_softc *);
228 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
229 static void sk_dma_free(struct sk_if_softc *);
230 static void sk_dma_jumbo_free(struct sk_if_softc *);
231 static int sk_init_rx_ring(struct sk_if_softc *);
232 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
233 static void sk_init_tx_ring(struct sk_if_softc *);
234 static u_int32_t sk_win_read_4(struct sk_softc *, int);
235 static u_int16_t sk_win_read_2(struct sk_softc *, int);
236 static u_int8_t sk_win_read_1(struct sk_softc *, int);
237 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
238 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
239 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
240
241 static int sk_miibus_readreg(device_t, int, int);
242 static int sk_miibus_writereg(device_t, int, int, int);
243 static void sk_miibus_statchg(device_t);
244
245 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
246 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
247 int);
248 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
249
250 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
251 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
252 int);
253 static void sk_marv_miibus_statchg(struct sk_if_softc *);
254
255 static uint32_t sk_xmchash(const uint8_t *);
256 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
257 static void sk_rxfilter(struct sk_if_softc *);
258 static void sk_rxfilter_genesis(struct sk_if_softc *);
259 static void sk_rxfilter_yukon(struct sk_if_softc *);
260
261 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
262 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
263
264 /* Tunables. */
265 static int jumbo_disable = 0;
266 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
267
268 /*
269 * It seems that SK-NET GENESIS supports very simple checksum offload
270 * capability for Tx and I believe it can generate 0 checksum value for
271 * UDP packets in Tx as the hardware can't differenciate UDP packets from
272 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
273 * means sender didn't perforam checksum computation. For the safety I
274 * disabled UDP checksum offload capability at the moment.
275 */
276 #define SK_CSUM_FEATURES (CSUM_TCP)
277
278 /*
279 * Note that we have newbus methods for both the GEnesis controller
280 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
281 * the miibus code is a child of the XMACs. We need to do it this way
282 * so that the miibus drivers can access the PHY registers on the
283 * right PHY. It's not quite what I had in mind, but it's the only
284 * design that achieves the desired effect.
285 */
286 static device_method_t skc_methods[] = {
287 /* Device interface */
288 DEVMETHOD(device_probe, skc_probe),
289 DEVMETHOD(device_attach, skc_attach),
290 DEVMETHOD(device_detach, skc_detach),
291 DEVMETHOD(device_suspend, skc_suspend),
292 DEVMETHOD(device_resume, skc_resume),
293 DEVMETHOD(device_shutdown, skc_shutdown),
294
295 DEVMETHOD(bus_child_deleted, skc_child_deleted),
296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag),
297
298 DEVMETHOD_END
299 };
300
301 static driver_t skc_driver = {
302 "skc",
303 skc_methods,
304 sizeof(struct sk_softc)
305 };
306
307 static device_method_t sk_methods[] = {
308 /* Device interface */
309 DEVMETHOD(device_probe, sk_probe),
310 DEVMETHOD(device_attach, sk_attach),
311 DEVMETHOD(device_detach, sk_detach),
312 DEVMETHOD(device_shutdown, bus_generic_shutdown),
313
314 /* MII interface */
315 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
316 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
317 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
318
319 DEVMETHOD_END
320 };
321
322 static driver_t sk_driver = {
323 "sk",
324 sk_methods,
325 sizeof(struct sk_if_softc)
326 };
327
328 DRIVER_MODULE(skc, pci, skc_driver, NULL, NULL);
329 DRIVER_MODULE(sk, skc, sk_driver, NULL, NULL);
330 DRIVER_MODULE(miibus, sk, miibus_driver, NULL, NULL);
331
332 static struct resource_spec sk_res_spec_io[] = {
333 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
334 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
335 { -1, 0, 0 }
336 };
337
338 static struct resource_spec sk_res_spec_mem[] = {
339 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
340 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
341 { -1, 0, 0 }
342 };
343
344 #define SK_SETBIT(sc, reg, x) \
345 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
346
347 #define SK_CLRBIT(sc, reg, x) \
348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
349
350 #define SK_WIN_SETBIT_4(sc, reg, x) \
351 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
352
353 #define SK_WIN_CLRBIT_4(sc, reg, x) \
354 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
355
356 #define SK_WIN_SETBIT_2(sc, reg, x) \
357 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
358
359 #define SK_WIN_CLRBIT_2(sc, reg, x) \
360 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
361
362 static u_int32_t
sk_win_read_4(struct sk_softc * sc,int reg)363 sk_win_read_4(struct sk_softc *sc, int reg)
364 {
365 #ifdef SK_USEIOSPACE
366 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
367 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
368 #else
369 return(CSR_READ_4(sc, reg));
370 #endif
371 }
372
373 static u_int16_t
sk_win_read_2(struct sk_softc * sc,int reg)374 sk_win_read_2(struct sk_softc *sc, int reg)
375 {
376 #ifdef SK_USEIOSPACE
377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
378 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
379 #else
380 return(CSR_READ_2(sc, reg));
381 #endif
382 }
383
384 static u_int8_t
sk_win_read_1(struct sk_softc * sc,int reg)385 sk_win_read_1(struct sk_softc *sc, int reg)
386 {
387 #ifdef SK_USEIOSPACE
388 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
389 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
390 #else
391 return(CSR_READ_1(sc, reg));
392 #endif
393 }
394
395 static void
sk_win_write_4(struct sk_softc * sc,int reg,u_int32_t val)396 sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val)
397 {
398 #ifdef SK_USEIOSPACE
399 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
400 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
401 #else
402 CSR_WRITE_4(sc, reg, val);
403 #endif
404 return;
405 }
406
407 static void
sk_win_write_2(struct sk_softc * sc,int reg,u_int32_t val)408 sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val)
409 {
410 #ifdef SK_USEIOSPACE
411 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
412 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
413 #else
414 CSR_WRITE_2(sc, reg, val);
415 #endif
416 return;
417 }
418
419 static void
sk_win_write_1(struct sk_softc * sc,int reg,u_int32_t val)420 sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val)
421 {
422 #ifdef SK_USEIOSPACE
423 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
424 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
425 #else
426 CSR_WRITE_1(sc, reg, val);
427 #endif
428 return;
429 }
430
431 static int
sk_miibus_readreg(device_t dev,int phy,int reg)432 sk_miibus_readreg(device_t dev, int phy, int reg)
433 {
434 struct sk_if_softc *sc_if;
435 int v;
436
437 sc_if = device_get_softc(dev);
438
439 SK_IF_MII_LOCK(sc_if);
440 switch(sc_if->sk_softc->sk_type) {
441 case SK_GENESIS:
442 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
443 break;
444 case SK_YUKON:
445 case SK_YUKON_LITE:
446 case SK_YUKON_LP:
447 v = sk_marv_miibus_readreg(sc_if, phy, reg);
448 break;
449 default:
450 v = 0;
451 break;
452 }
453 SK_IF_MII_UNLOCK(sc_if);
454
455 return (v);
456 }
457
458 static int
sk_miibus_writereg(device_t dev,int phy,int reg,int val)459 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
460 {
461 struct sk_if_softc *sc_if;
462 int v;
463
464 sc_if = device_get_softc(dev);
465
466 SK_IF_MII_LOCK(sc_if);
467 switch(sc_if->sk_softc->sk_type) {
468 case SK_GENESIS:
469 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
470 break;
471 case SK_YUKON:
472 case SK_YUKON_LITE:
473 case SK_YUKON_LP:
474 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
475 break;
476 default:
477 v = 0;
478 break;
479 }
480 SK_IF_MII_UNLOCK(sc_if);
481
482 return (v);
483 }
484
485 static void
sk_miibus_statchg(device_t dev)486 sk_miibus_statchg(device_t dev)
487 {
488 struct sk_if_softc *sc_if;
489
490 sc_if = device_get_softc(dev);
491
492 SK_IF_MII_LOCK(sc_if);
493 switch(sc_if->sk_softc->sk_type) {
494 case SK_GENESIS:
495 sk_xmac_miibus_statchg(sc_if);
496 break;
497 case SK_YUKON:
498 case SK_YUKON_LITE:
499 case SK_YUKON_LP:
500 sk_marv_miibus_statchg(sc_if);
501 break;
502 }
503 SK_IF_MII_UNLOCK(sc_if);
504
505 return;
506 }
507
508 static int
sk_xmac_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)509 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
510 {
511 int i;
512
513 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
514 SK_XM_READ_2(sc_if, XM_PHY_DATA);
515 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
516 for (i = 0; i < SK_TIMEOUT; i++) {
517 DELAY(1);
518 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
519 XM_MMUCMD_PHYDATARDY)
520 break;
521 }
522
523 if (i == SK_TIMEOUT) {
524 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
525 return(0);
526 }
527 }
528 DELAY(1);
529 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
530
531 return(i);
532 }
533
534 static int
sk_xmac_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)535 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
536 {
537 int i;
538
539 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
540 for (i = 0; i < SK_TIMEOUT; i++) {
541 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
542 break;
543 }
544
545 if (i == SK_TIMEOUT) {
546 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
547 return (ETIMEDOUT);
548 }
549
550 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
551 for (i = 0; i < SK_TIMEOUT; i++) {
552 DELAY(1);
553 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
554 break;
555 }
556 if (i == SK_TIMEOUT)
557 if_printf(sc_if->sk_ifp, "phy write timed out\n");
558
559 return(0);
560 }
561
562 static void
sk_xmac_miibus_statchg(struct sk_if_softc * sc_if)563 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
564 {
565 struct mii_data *mii;
566
567 mii = device_get_softc(sc_if->sk_miibus);
568
569 /*
570 * If this is a GMII PHY, manually set the XMAC's
571 * duplex mode accordingly.
572 */
573 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
574 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
575 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
576 } else {
577 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
578 }
579 }
580 }
581
582 static int
sk_marv_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)583 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
584 {
585 u_int16_t val;
586 int i;
587
588 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
589 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
590 return(0);
591 }
592
593 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
594 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
595
596 for (i = 0; i < SK_TIMEOUT; i++) {
597 DELAY(1);
598 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
599 if (val & YU_SMICR_READ_VALID)
600 break;
601 }
602
603 if (i == SK_TIMEOUT) {
604 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
605 return(0);
606 }
607
608 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
609
610 return(val);
611 }
612
613 static int
sk_marv_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)614 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
615 {
616 int i;
617
618 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
619 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
620 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
621
622 for (i = 0; i < SK_TIMEOUT; i++) {
623 DELAY(1);
624 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
625 break;
626 }
627 if (i == SK_TIMEOUT)
628 if_printf(sc_if->sk_ifp, "phy write timeout\n");
629
630 return(0);
631 }
632
633 static void
sk_marv_miibus_statchg(struct sk_if_softc * sc_if)634 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
635 {
636 return;
637 }
638
639 #define HASH_BITS 6
640
641 static u_int32_t
sk_xmchash(const uint8_t * addr)642 sk_xmchash(const uint8_t *addr)
643 {
644 uint32_t crc;
645
646 /* Compute CRC for the address value. */
647 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
648
649 return (~crc & ((1 << HASH_BITS) - 1));
650 }
651
652 static void
sk_setfilt(struct sk_if_softc * sc_if,u_int16_t * addr,int slot)653 sk_setfilt(struct sk_if_softc *sc_if, u_int16_t *addr, int slot)
654 {
655 int base;
656
657 base = XM_RXFILT_ENTRY(slot);
658
659 SK_XM_WRITE_2(sc_if, base, addr[0]);
660 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
661 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
662
663 return;
664 }
665
666 static void
sk_rxfilter(struct sk_if_softc * sc_if)667 sk_rxfilter(struct sk_if_softc *sc_if)
668 {
669 struct sk_softc *sc;
670
671 SK_IF_LOCK_ASSERT(sc_if);
672
673 sc = sc_if->sk_softc;
674 if (sc->sk_type == SK_GENESIS)
675 sk_rxfilter_genesis(sc_if);
676 else
677 sk_rxfilter_yukon(sc_if);
678 }
679
680 struct sk_add_maddr_genesis_ctx {
681 struct sk_if_softc *sc_if;
682 uint32_t hashes[2];
683 uint32_t mode;
684 };
685
686 static u_int
sk_add_maddr_genesis(void * arg,struct sockaddr_dl * sdl,u_int cnt)687 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt)
688 {
689 struct sk_add_maddr_genesis_ctx *ctx = arg;
690 int h;
691
692 /*
693 * Program the first XM_RXFILT_MAX multicast groups
694 * into the perfect filter.
695 */
696 if (cnt + 1 < XM_RXFILT_MAX) {
697 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1);
698 ctx->mode |= XM_MODE_RX_USE_PERFECT;
699 return (1);
700 }
701 h = sk_xmchash((const uint8_t *)LLADDR(sdl));
702 if (h < 32)
703 ctx->hashes[0] |= (1 << h);
704 else
705 ctx->hashes[1] |= (1 << (h - 32));
706 ctx->mode |= XM_MODE_RX_USE_HASH;
707
708 return (1);
709 }
710
711 static void
sk_rxfilter_genesis(struct sk_if_softc * sc_if)712 sk_rxfilter_genesis(struct sk_if_softc *sc_if)
713 {
714 if_t ifp = sc_if->sk_ifp;
715 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } };
716 int i;
717 u_int16_t dummy[] = { 0, 0, 0 };
718
719 SK_IF_LOCK_ASSERT(sc_if);
720
721 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE);
722 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
723 XM_MODE_RX_USE_PERFECT);
724 /* First, zot all the existing perfect filters. */
725 for (i = 1; i < XM_RXFILT_MAX; i++)
726 sk_setfilt(sc_if, dummy, i);
727
728 /* Now program new ones. */
729 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
730 if (if_getflags(ifp) & IFF_ALLMULTI)
731 ctx.mode |= XM_MODE_RX_USE_HASH;
732 if (if_getflags(ifp) & IFF_PROMISC)
733 ctx.mode |= XM_MODE_RX_PROMISC;
734 ctx.hashes[0] = 0xFFFFFFFF;
735 ctx.hashes[1] = 0xFFFFFFFF;
736 } else
737 /* XXX want to maintain reverse semantics */
738 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx);
739
740 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode);
741 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]);
742 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]);
743 }
744
745 static u_int
sk_hash_maddr_yukon(void * arg,struct sockaddr_dl * sdl,u_int cnt)746 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt)
747 {
748 uint32_t crc, *hashes = arg;
749
750 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
751 /* Just want the 6 least significant bits. */
752 crc &= 0x3f;
753 /* Set the corresponding bit in the hash table. */
754 hashes[crc >> 5] |= 1 << (crc & 0x1f);
755
756 return (1);
757 }
758
759 static void
sk_rxfilter_yukon(struct sk_if_softc * sc_if)760 sk_rxfilter_yukon(struct sk_if_softc *sc_if)
761 {
762 if_t ifp;
763 uint32_t hashes[2] = { 0, 0 }, mode;
764
765 SK_IF_LOCK_ASSERT(sc_if);
766
767 ifp = sc_if->sk_ifp;
768 mode = SK_YU_READ_2(sc_if, YUKON_RCR);
769 if (if_getflags(ifp) & IFF_PROMISC)
770 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
771 else if (if_getflags(ifp) & IFF_ALLMULTI) {
772 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
773 hashes[0] = 0xFFFFFFFF;
774 hashes[1] = 0xFFFFFFFF;
775 } else {
776 mode |= YU_RCR_UFLEN;
777 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes);
778 if (hashes[0] != 0 || hashes[1] != 0)
779 mode |= YU_RCR_MUFLEN;
780 }
781
782 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
783 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
784 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
785 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
786 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
787 }
788
789 static int
sk_init_rx_ring(struct sk_if_softc * sc_if)790 sk_init_rx_ring(struct sk_if_softc *sc_if)
791 {
792 struct sk_ring_data *rd;
793 bus_addr_t addr;
794 u_int32_t csum_start;
795 int i;
796
797 sc_if->sk_cdata.sk_rx_cons = 0;
798
799 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
800 ETHER_HDR_LEN;
801 rd = &sc_if->sk_rdata;
802 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
803 for (i = 0; i < SK_RX_RING_CNT; i++) {
804 if (sk_newbuf(sc_if, i) != 0)
805 return (ENOBUFS);
806 if (i == (SK_RX_RING_CNT - 1))
807 addr = SK_RX_RING_ADDR(sc_if, 0);
808 else
809 addr = SK_RX_RING_ADDR(sc_if, i + 1);
810 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
811 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
812 }
813
814 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
815 sc_if->sk_cdata.sk_rx_ring_map,
816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
817
818 return(0);
819 }
820
821 static int
sk_init_jumbo_rx_ring(struct sk_if_softc * sc_if)822 sk_init_jumbo_rx_ring(struct sk_if_softc *sc_if)
823 {
824 struct sk_ring_data *rd;
825 bus_addr_t addr;
826 u_int32_t csum_start;
827 int i;
828
829 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
830
831 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
832 ETHER_HDR_LEN;
833 rd = &sc_if->sk_rdata;
834 bzero(rd->sk_jumbo_rx_ring,
835 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
836 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
837 if (sk_jumbo_newbuf(sc_if, i) != 0)
838 return (ENOBUFS);
839 if (i == (SK_JUMBO_RX_RING_CNT - 1))
840 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
841 else
842 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
843 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
844 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
845 }
846
847 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
848 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
849 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
850
851 return (0);
852 }
853
854 static void
sk_init_tx_ring(struct sk_if_softc * sc_if)855 sk_init_tx_ring(struct sk_if_softc *sc_if)
856 {
857 struct sk_ring_data *rd;
858 struct sk_txdesc *txd;
859 bus_addr_t addr;
860 int i;
861
862 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
863 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
864
865 sc_if->sk_cdata.sk_tx_prod = 0;
866 sc_if->sk_cdata.sk_tx_cons = 0;
867 sc_if->sk_cdata.sk_tx_cnt = 0;
868
869 rd = &sc_if->sk_rdata;
870 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
871 for (i = 0; i < SK_TX_RING_CNT; i++) {
872 if (i == (SK_TX_RING_CNT - 1))
873 addr = SK_TX_RING_ADDR(sc_if, 0);
874 else
875 addr = SK_TX_RING_ADDR(sc_if, i + 1);
876 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
877 txd = &sc_if->sk_cdata.sk_txdesc[i];
878 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
879 }
880
881 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
882 sc_if->sk_cdata.sk_tx_ring_map,
883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
884 }
885
886 static __inline void
sk_discard_rxbuf(struct sk_if_softc * sc_if,int idx)887 sk_discard_rxbuf(struct sk_if_softc *sc_if, int idx)
888 {
889 struct sk_rx_desc *r;
890 struct sk_rxdesc *rxd;
891 struct mbuf *m;
892
893 r = &sc_if->sk_rdata.sk_rx_ring[idx];
894 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
895 m = rxd->rx_m;
896 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
897 }
898
899 static __inline void
sk_discard_jumbo_rxbuf(struct sk_if_softc * sc_if,int idx)900 sk_discard_jumbo_rxbuf(struct sk_if_softc *sc_if, int idx)
901 {
902 struct sk_rx_desc *r;
903 struct sk_rxdesc *rxd;
904 struct mbuf *m;
905
906 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
907 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
908 m = rxd->rx_m;
909 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
910 }
911
912 static int
sk_newbuf(struct sk_if_softc * sc_if,int idx)913 sk_newbuf(struct sk_if_softc *sc_if, int idx)
914 {
915 struct sk_rx_desc *r;
916 struct sk_rxdesc *rxd;
917 struct mbuf *m;
918 bus_dma_segment_t segs[1];
919 bus_dmamap_t map;
920 int nsegs;
921
922 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
923 if (m == NULL)
924 return (ENOBUFS);
925 m->m_len = m->m_pkthdr.len = MCLBYTES;
926 m_adj(m, ETHER_ALIGN);
927
928 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
929 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
930 m_freem(m);
931 return (ENOBUFS);
932 }
933 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
934
935 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
936 if (rxd->rx_m != NULL) {
937 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
938 BUS_DMASYNC_POSTREAD);
939 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
940 }
941 map = rxd->rx_dmamap;
942 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
943 sc_if->sk_cdata.sk_rx_sparemap = map;
944 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
945 BUS_DMASYNC_PREREAD);
946 rxd->rx_m = m;
947 r = &sc_if->sk_rdata.sk_rx_ring[idx];
948 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
949 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
950 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
951
952 return (0);
953 }
954
955 static int
sk_jumbo_newbuf(struct sk_if_softc * sc_if,int idx)956 sk_jumbo_newbuf(struct sk_if_softc *sc_if, int idx)
957 {
958 struct sk_rx_desc *r;
959 struct sk_rxdesc *rxd;
960 struct mbuf *m;
961 bus_dma_segment_t segs[1];
962 bus_dmamap_t map;
963 int nsegs;
964
965 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
966 if (m == NULL)
967 return (ENOBUFS);
968 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
969 /*
970 * Adjust alignment so packet payload begins on a
971 * longword boundary. Mandatory for Alpha, useful on
972 * x86 too.
973 */
974 m_adj(m, ETHER_ALIGN);
975
976 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
977 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
978 m_freem(m);
979 return (ENOBUFS);
980 }
981 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
982
983 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
984 if (rxd->rx_m != NULL) {
985 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
986 BUS_DMASYNC_POSTREAD);
987 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
988 rxd->rx_dmamap);
989 }
990 map = rxd->rx_dmamap;
991 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
992 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
993 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
994 BUS_DMASYNC_PREREAD);
995 rxd->rx_m = m;
996 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
997 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
998 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
999 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1000
1001 return (0);
1002 }
1003
1004 /*
1005 * Set media options.
1006 */
1007 static int
sk_ifmedia_upd(if_t ifp)1008 sk_ifmedia_upd(if_t ifp)
1009 {
1010 struct sk_if_softc *sc_if = if_getsoftc(ifp);
1011 struct mii_data *mii;
1012
1013 mii = device_get_softc(sc_if->sk_miibus);
1014 sk_init(sc_if);
1015 mii_mediachg(mii);
1016
1017 return(0);
1018 }
1019
1020 /*
1021 * Report current media status.
1022 */
1023 static void
sk_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1024 sk_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1025 {
1026 struct sk_if_softc *sc_if;
1027 struct mii_data *mii;
1028
1029 sc_if = if_getsoftc(ifp);
1030 mii = device_get_softc(sc_if->sk_miibus);
1031
1032 mii_pollstat(mii);
1033 ifmr->ifm_active = mii->mii_media_active;
1034 ifmr->ifm_status = mii->mii_media_status;
1035
1036 return;
1037 }
1038
1039 static int
sk_ioctl(if_t ifp,u_long command,caddr_t data)1040 sk_ioctl(if_t ifp, u_long command, caddr_t data)
1041 {
1042 struct sk_if_softc *sc_if = if_getsoftc(ifp);
1043 struct ifreq *ifr = (struct ifreq *) data;
1044 int error, mask;
1045 struct mii_data *mii;
1046
1047 error = 0;
1048 switch(command) {
1049 case SIOCSIFMTU:
1050 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1051 error = EINVAL;
1052 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1053 if (sc_if->sk_jumbo_disable != 0 &&
1054 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1055 error = EINVAL;
1056 else {
1057 SK_IF_LOCK(sc_if);
1058 if_setmtu(ifp, ifr->ifr_mtu);
1059 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1060 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1061 sk_init_locked(sc_if);
1062 }
1063 SK_IF_UNLOCK(sc_if);
1064 }
1065 }
1066 break;
1067 case SIOCSIFFLAGS:
1068 SK_IF_LOCK(sc_if);
1069 if (if_getflags(ifp) & IFF_UP) {
1070 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1071 if ((if_getflags(ifp) ^ sc_if->sk_if_flags)
1072 & (IFF_PROMISC | IFF_ALLMULTI))
1073 sk_rxfilter(sc_if);
1074 } else
1075 sk_init_locked(sc_if);
1076 } else {
1077 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1078 sk_stop(sc_if);
1079 }
1080 sc_if->sk_if_flags = if_getflags(ifp);
1081 SK_IF_UNLOCK(sc_if);
1082 break;
1083 case SIOCADDMULTI:
1084 case SIOCDELMULTI:
1085 SK_IF_LOCK(sc_if);
1086 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1087 sk_rxfilter(sc_if);
1088 SK_IF_UNLOCK(sc_if);
1089 break;
1090 case SIOCGIFMEDIA:
1091 case SIOCSIFMEDIA:
1092 mii = device_get_softc(sc_if->sk_miibus);
1093 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1094 break;
1095 case SIOCSIFCAP:
1096 SK_IF_LOCK(sc_if);
1097 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1098 SK_IF_UNLOCK(sc_if);
1099 break;
1100 }
1101 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1102 if ((mask & IFCAP_TXCSUM) != 0 &&
1103 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
1104 if_togglecapenable(ifp, IFCAP_TXCSUM);
1105 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1106 if_sethwassistbits(ifp, SK_CSUM_FEATURES, 0);
1107 else
1108 if_sethwassistbits(ifp, 0, SK_CSUM_FEATURES);
1109 }
1110 if ((mask & IFCAP_RXCSUM) != 0 &&
1111 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0)
1112 if_togglecapenable(ifp, IFCAP_RXCSUM);
1113 SK_IF_UNLOCK(sc_if);
1114 break;
1115 default:
1116 error = ether_ioctl(ifp, command, data);
1117 break;
1118 }
1119
1120 return (error);
1121 }
1122
1123 /*
1124 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1125 * IDs against our list and return a device name if we find a match.
1126 */
1127 static int
skc_probe(device_t dev)1128 skc_probe(device_t dev)
1129 {
1130 const struct sk_type *t = sk_devs;
1131
1132 while(t->sk_name != NULL) {
1133 if ((pci_get_vendor(dev) == t->sk_vid) &&
1134 (pci_get_device(dev) == t->sk_did)) {
1135 /*
1136 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1137 * Rev. 3 is supported by re(4).
1138 */
1139 if ((t->sk_vid == VENDORID_LINKSYS) &&
1140 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1141 (pci_get_subdevice(dev) !=
1142 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1143 t++;
1144 continue;
1145 }
1146 device_set_desc(dev, t->sk_name);
1147 return (BUS_PROBE_DEFAULT);
1148 }
1149 t++;
1150 }
1151
1152 return(ENXIO);
1153 }
1154
1155 /*
1156 * Force the GEnesis into reset, then bring it out of reset.
1157 */
1158 static void
sk_reset(struct sk_softc * sc)1159 sk_reset(struct sk_softc *sc)
1160 {
1161
1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1164 if (SK_YUKON_FAMILY(sc->sk_type))
1165 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1166
1167 DELAY(1000);
1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1169 DELAY(2);
1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1171 if (SK_YUKON_FAMILY(sc->sk_type))
1172 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1173
1174 if (sc->sk_type == SK_GENESIS) {
1175 /* Configure packet arbiter */
1176 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1177 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1178 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1179 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1180 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1181 }
1182
1183 /* Enable RAM interface */
1184 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1185
1186 /*
1187 * Configure interrupt moderation. The moderation timer
1188 * defers interrupts specified in the interrupt moderation
1189 * timer mask based on the timeout specified in the interrupt
1190 * moderation timer init register. Each bit in the timer
1191 * register represents one tick, so to specify a timeout in
1192 * microseconds, we have to multiply by the correct number of
1193 * ticks-per-microsecond.
1194 */
1195 switch (sc->sk_type) {
1196 case SK_GENESIS:
1197 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1198 break;
1199 default:
1200 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1201 break;
1202 }
1203 if (bootverbose)
1204 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1205 sc->sk_int_mod);
1206 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1207 sc->sk_int_ticks));
1208 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1209 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1210 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1211
1212 return;
1213 }
1214
1215 static int
sk_probe(device_t dev)1216 sk_probe(device_t dev)
1217 {
1218 struct sk_softc *sc;
1219
1220 sc = device_get_softc(device_get_parent(dev));
1221
1222 /*
1223 * Not much to do here. We always know there will be
1224 * at least one XMAC present, and if there are two,
1225 * skc_attach() will create a second device instance
1226 * for us.
1227 */
1228 switch (sc->sk_type) {
1229 case SK_GENESIS:
1230 device_set_desc(dev, "XaQti Corp. XMAC II");
1231 break;
1232 case SK_YUKON:
1233 case SK_YUKON_LITE:
1234 case SK_YUKON_LP:
1235 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1236 break;
1237 }
1238
1239 return (BUS_PROBE_DEFAULT);
1240 }
1241
1242 /*
1243 * Each XMAC chip is attached as a separate logical IP interface.
1244 * Single port cards will have only one logical interface of course.
1245 */
1246 static int
sk_attach(device_t dev)1247 sk_attach(device_t dev)
1248 {
1249 struct sk_softc *sc;
1250 struct sk_if_softc *sc_if;
1251 if_t ifp;
1252 u_int32_t r;
1253 int error, i, phy, port;
1254 u_char eaddr[6];
1255 u_char inv_mac[] = {0, 0, 0, 0, 0, 0};
1256
1257 if (dev == NULL)
1258 return(EINVAL);
1259
1260 error = 0;
1261 sc_if = device_get_softc(dev);
1262 sc = device_get_softc(device_get_parent(dev));
1263 port = *(int *)device_get_ivars(dev);
1264
1265 sc_if->sk_if_dev = dev;
1266 sc_if->sk_port = port;
1267 sc_if->sk_softc = sc;
1268 sc->sk_if[port] = sc_if;
1269 if (port == SK_PORT_A)
1270 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1271 if (port == SK_PORT_B)
1272 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1273
1274 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1275 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1276
1277 if (sk_dma_alloc(sc_if) != 0) {
1278 error = ENOMEM;
1279 goto fail;
1280 }
1281 sk_dma_jumbo_alloc(sc_if);
1282
1283 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1284 if_setsoftc(ifp, sc_if);
1285 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1286 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1287 /*
1288 * SK_GENESIS has a bug in checksum offload - From linux.
1289 */
1290 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1291 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM);
1292 if_sethwassist(ifp, 0);
1293 } else {
1294 if_setcapabilities(ifp, 0);
1295 if_sethwassist(ifp, 0);
1296 }
1297 if_setcapenable(ifp, if_getcapabilities(ifp));
1298 /*
1299 * Some revision of Yukon controller generates corrupted
1300 * frame when TX checksum offloading is enabled. The
1301 * frame has a valid checksum value so payload might be
1302 * modified during TX checksum calculation. Disable TX
1303 * checksum offloading but give users chance to enable it
1304 * when they know their controller works without problems
1305 * with TX checksum offloading.
1306 */
1307 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
1308 if_setioctlfn(ifp, sk_ioctl);
1309 if_setstartfn(ifp, sk_start);
1310 if_setinitfn(ifp, sk_init);
1311 if_setsendqlen(ifp, SK_TX_RING_CNT - 1);
1312 if_setsendqready(ifp);
1313
1314 /*
1315 * Get station address for this interface. Note that
1316 * dual port cards actually come with three station
1317 * addresses: one for each port, plus an extra. The
1318 * extra one is used by the SysKonnect driver software
1319 * as a 'virtual' station address for when both ports
1320 * are operating in failover mode. Currently we don't
1321 * use this extra address.
1322 */
1323 SK_IF_LOCK(sc_if);
1324 for (i = 0; i < ETHER_ADDR_LEN; i++)
1325 eaddr[i] =
1326 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1327
1328 /* Verify whether the station address is invalid or not. */
1329 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1330 device_printf(sc_if->sk_if_dev,
1331 "Generating random ethernet address\n");
1332 r = arc4random();
1333 /*
1334 * Set OUI to convenient locally assigned address. 'b'
1335 * is 0x62, which has the locally assigned bit set, and
1336 * the broadcast/multicast bit clear.
1337 */
1338 eaddr[0] = 'b';
1339 eaddr[1] = 's';
1340 eaddr[2] = 'd';
1341 eaddr[3] = (r >> 16) & 0xff;
1342 eaddr[4] = (r >> 8) & 0xff;
1343 eaddr[5] = (r >> 0) & 0xff;
1344 }
1345 /*
1346 * Set up RAM buffer addresses. The NIC will have a certain
1347 * amount of SRAM on it, somewhere between 512K and 2MB. We
1348 * need to divide this up a) between the transmitter and
1349 * receiver and b) between the two XMACs, if this is a
1350 * dual port NIC. Our algotithm is to divide up the memory
1351 * evenly so that everyone gets a fair share.
1352 *
1353 * Just to be contrary, Yukon2 appears to have separate memory
1354 * for each MAC.
1355 */
1356 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1357 u_int32_t chunk, val;
1358
1359 chunk = sc->sk_ramsize / 2;
1360 val = sc->sk_rboff / sizeof(u_int64_t);
1361 sc_if->sk_rx_ramstart = val;
1362 val += (chunk / sizeof(u_int64_t));
1363 sc_if->sk_rx_ramend = val - 1;
1364 sc_if->sk_tx_ramstart = val;
1365 val += (chunk / sizeof(u_int64_t));
1366 sc_if->sk_tx_ramend = val - 1;
1367 } else {
1368 u_int32_t chunk, val;
1369
1370 chunk = sc->sk_ramsize / 4;
1371 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1372 sizeof(u_int64_t);
1373 sc_if->sk_rx_ramstart = val;
1374 val += (chunk / sizeof(u_int64_t));
1375 sc_if->sk_rx_ramend = val - 1;
1376 sc_if->sk_tx_ramstart = val;
1377 val += (chunk / sizeof(u_int64_t));
1378 sc_if->sk_tx_ramend = val - 1;
1379 }
1380
1381 /* Read and save PHY type and set PHY address */
1382 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1383 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1384 switch(sc_if->sk_phytype) {
1385 case SK_PHYTYPE_XMAC:
1386 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1387 break;
1388 case SK_PHYTYPE_BCOM:
1389 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1390 break;
1391 default:
1392 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1393 sc_if->sk_phytype);
1394 error = ENODEV;
1395 SK_IF_UNLOCK(sc_if);
1396 goto fail;
1397 }
1398 } else {
1399 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1400 sc->sk_pmd != 'S') {
1401 /* not initialized, punt */
1402 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1403 sc->sk_coppertype = 1;
1404 }
1405
1406 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1407
1408 if (!(sc->sk_coppertype))
1409 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1410 }
1411
1412 /*
1413 * Call MI attach routine. Can't hold locks when calling into ether_*.
1414 */
1415 SK_IF_UNLOCK(sc_if);
1416 ether_ifattach(ifp, eaddr);
1417 SK_IF_LOCK(sc_if);
1418
1419 /*
1420 * The hardware should be ready for VLAN_MTU by default:
1421 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1422 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1423 *
1424 */
1425 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1426 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
1427 /*
1428 * Tell the upper layer(s) we support long frames.
1429 * Must appear after the call to ether_ifattach() because
1430 * ether_ifattach() sets ifi_hdrlen to the default value.
1431 */
1432 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1433
1434 /*
1435 * Do miibus setup.
1436 */
1437 phy = MII_PHY_ANY;
1438 switch (sc->sk_type) {
1439 case SK_GENESIS:
1440 sk_init_xmac(sc_if);
1441 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1442 phy = 0;
1443 break;
1444 case SK_YUKON:
1445 case SK_YUKON_LITE:
1446 case SK_YUKON_LP:
1447 sk_init_yukon(sc_if);
1448 phy = 0;
1449 break;
1450 }
1451
1452 SK_IF_UNLOCK(sc_if);
1453 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1454 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1455 if (error != 0) {
1456 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1457 ether_ifdetach(ifp);
1458 goto fail;
1459 }
1460
1461 fail:
1462 if (error) {
1463 /* Access should be ok even though lock has been dropped */
1464 sc->sk_if[port] = NULL;
1465 sk_detach(dev);
1466 }
1467
1468 return(error);
1469 }
1470
1471 /*
1472 * Attach the interface. Allocate softc structures, do ifmedia
1473 * setup and ethernet/BPF attach.
1474 */
1475 static int
skc_attach(device_t dev)1476 skc_attach(device_t dev)
1477 {
1478 struct sk_softc *sc;
1479 int error = 0, *port;
1480 uint8_t skrs;
1481 const char *pname = NULL;
1482 char *revstr;
1483
1484 sc = device_get_softc(dev);
1485 sc->sk_dev = dev;
1486
1487 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1488 MTX_DEF);
1489 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1490 /*
1491 * Map control/status registers.
1492 */
1493 pci_enable_busmaster(dev);
1494
1495 /* Allocate resources */
1496 #ifdef SK_USEIOSPACE
1497 sc->sk_res_spec = sk_res_spec_io;
1498 #else
1499 sc->sk_res_spec = sk_res_spec_mem;
1500 #endif
1501 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1502 if (error) {
1503 if (sc->sk_res_spec == sk_res_spec_mem)
1504 sc->sk_res_spec = sk_res_spec_io;
1505 else
1506 sc->sk_res_spec = sk_res_spec_mem;
1507 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1508 if (error) {
1509 device_printf(dev, "couldn't allocate %s resources\n",
1510 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1511 "I/O");
1512 goto fail;
1513 }
1514 }
1515
1516 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1517 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1518
1519 /* Bail out if chip is not recognized. */
1520 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1521 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1522 sc->sk_type, sc->sk_rev);
1523 error = ENXIO;
1524 goto fail;
1525 }
1526
1527 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1528 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1529 OID_AUTO, "int_mod",
1530 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1531 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1532 "SK interrupt moderation");
1533
1534 /* Pull in device tunables. */
1535 sc->sk_int_mod = SK_IM_DEFAULT;
1536 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1537 "int_mod", &sc->sk_int_mod);
1538 if (error == 0) {
1539 if (sc->sk_int_mod < SK_IM_MIN ||
1540 sc->sk_int_mod > SK_IM_MAX) {
1541 device_printf(dev, "int_mod value out of range; "
1542 "using default: %d\n", SK_IM_DEFAULT);
1543 sc->sk_int_mod = SK_IM_DEFAULT;
1544 }
1545 }
1546
1547 /* Reset the adapter. */
1548 sk_reset(sc);
1549
1550 skrs = sk_win_read_1(sc, SK_EPROM0);
1551 if (sc->sk_type == SK_GENESIS) {
1552 /* Read and save RAM size and RAMbuffer offset */
1553 switch(skrs) {
1554 case SK_RAMSIZE_512K_64:
1555 sc->sk_ramsize = 0x80000;
1556 sc->sk_rboff = SK_RBOFF_0;
1557 break;
1558 case SK_RAMSIZE_1024K_64:
1559 sc->sk_ramsize = 0x100000;
1560 sc->sk_rboff = SK_RBOFF_80000;
1561 break;
1562 case SK_RAMSIZE_1024K_128:
1563 sc->sk_ramsize = 0x100000;
1564 sc->sk_rboff = SK_RBOFF_0;
1565 break;
1566 case SK_RAMSIZE_2048K_128:
1567 sc->sk_ramsize = 0x200000;
1568 sc->sk_rboff = SK_RBOFF_0;
1569 break;
1570 default:
1571 device_printf(dev, "unknown ram size: %d\n", skrs);
1572 error = ENXIO;
1573 goto fail;
1574 }
1575 } else { /* SK_YUKON_FAMILY */
1576 if (skrs == 0x00)
1577 sc->sk_ramsize = 0x20000;
1578 else
1579 sc->sk_ramsize = skrs * (1<<12);
1580 sc->sk_rboff = SK_RBOFF_0;
1581 }
1582
1583 /* Read and save physical media type */
1584 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1585
1586 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1587 sc->sk_coppertype = 1;
1588 else
1589 sc->sk_coppertype = 0;
1590
1591 /* Determine whether to name it with VPD PN or just make it up.
1592 * Marvell Yukon VPD PN seems to freqently be bogus. */
1593 switch (pci_get_device(dev)) {
1594 case DEVICEID_SK_V1:
1595 case DEVICEID_BELKIN_5005:
1596 case DEVICEID_3COM_3C940:
1597 case DEVICEID_LINKSYS_EG1032:
1598 case DEVICEID_DLINK_DGE530T_A1:
1599 case DEVICEID_DLINK_DGE530T_B1:
1600 /* Stay with VPD PN. */
1601 (void) pci_get_vpd_ident(dev, &pname);
1602 break;
1603 case DEVICEID_SK_V2:
1604 /* YUKON VPD PN might bear no resemblance to reality. */
1605 switch (sc->sk_type) {
1606 case SK_GENESIS:
1607 /* Stay with VPD PN. */
1608 (void) pci_get_vpd_ident(dev, &pname);
1609 break;
1610 case SK_YUKON:
1611 pname = "Marvell Yukon Gigabit Ethernet";
1612 break;
1613 case SK_YUKON_LITE:
1614 pname = "Marvell Yukon Lite Gigabit Ethernet";
1615 break;
1616 case SK_YUKON_LP:
1617 pname = "Marvell Yukon LP Gigabit Ethernet";
1618 break;
1619 default:
1620 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1621 break;
1622 }
1623
1624 /* Yukon Lite Rev. A0 needs special test. */
1625 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1626 u_int32_t far;
1627 u_int8_t testbyte;
1628
1629 /* Save flash address register before testing. */
1630 far = sk_win_read_4(sc, SK_EP_ADDR);
1631
1632 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1633 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1634
1635 if (testbyte != 0x00) {
1636 /* Yukon Lite Rev. A0 detected. */
1637 sc->sk_type = SK_YUKON_LITE;
1638 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1639 /* Restore flash address register. */
1640 sk_win_write_4(sc, SK_EP_ADDR, far);
1641 }
1642 }
1643 break;
1644 default:
1645 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1646 "chipver=%02x, rev=%x\n",
1647 pci_get_vendor(dev), pci_get_device(dev),
1648 sc->sk_type, sc->sk_rev);
1649 error = ENXIO;
1650 goto fail;
1651 }
1652
1653 if (sc->sk_type == SK_YUKON_LITE) {
1654 switch (sc->sk_rev) {
1655 case SK_YUKON_LITE_REV_A0:
1656 revstr = "A0";
1657 break;
1658 case SK_YUKON_LITE_REV_A1:
1659 revstr = "A1";
1660 break;
1661 case SK_YUKON_LITE_REV_A3:
1662 revstr = "A3";
1663 break;
1664 default:
1665 revstr = "";
1666 break;
1667 }
1668 } else {
1669 revstr = "";
1670 }
1671
1672 /* Announce the product name and more VPD data if there. */
1673 if (pname != NULL)
1674 device_printf(dev, "%s rev. %s(0x%x)\n",
1675 pname, revstr, sc->sk_rev);
1676
1677 if (bootverbose) {
1678 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1679 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1680 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1681 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1682 }
1683
1684 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", DEVICE_UNIT_ANY);
1685 if (sc->sk_devs[SK_PORT_A] == NULL) {
1686 device_printf(dev, "failed to add child for PORT_A\n");
1687 error = ENXIO;
1688 goto fail;
1689 }
1690 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1691 if (port == NULL) {
1692 device_printf(dev, "failed to allocate memory for "
1693 "ivars of PORT_A\n");
1694 error = ENXIO;
1695 goto fail;
1696 }
1697 *port = SK_PORT_A;
1698 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1699
1700 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1701 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", DEVICE_UNIT_ANY);
1702 if (sc->sk_devs[SK_PORT_B] == NULL) {
1703 device_printf(dev, "failed to add child for PORT_B\n");
1704 error = ENXIO;
1705 goto fail;
1706 }
1707 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1708 if (port == NULL) {
1709 device_printf(dev, "failed to allocate memory for "
1710 "ivars of PORT_B\n");
1711 error = ENXIO;
1712 goto fail;
1713 }
1714 *port = SK_PORT_B;
1715 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1716 }
1717
1718 /* Turn on the 'driver is loaded' LED. */
1719 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1720
1721 error = bus_generic_attach(dev);
1722 if (error) {
1723 device_printf(dev, "failed to attach port(s)\n");
1724 goto fail;
1725 }
1726
1727 /* Hook interrupt last to avoid having to lock softc */
1728 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1729 NULL, sk_intr, sc, &sc->sk_intrhand);
1730
1731 if (error) {
1732 device_printf(dev, "couldn't set up irq\n");
1733 goto fail;
1734 }
1735
1736 fail:
1737 if (error)
1738 skc_detach(dev);
1739
1740 return(error);
1741 }
1742
1743 static void
skc_child_deleted(device_t dev,device_t child)1744 skc_child_deleted(device_t dev, device_t child)
1745 {
1746 free(device_get_ivars(child), M_DEVBUF);
1747 }
1748
1749 /*
1750 * Shutdown hardware and free up resources. This can be called any
1751 * time after the mutex has been initialized. It is called in both
1752 * the error case in attach and the normal detach case so it needs
1753 * to be careful about only freeing resources that have actually been
1754 * allocated.
1755 */
1756 static int
sk_detach(device_t dev)1757 sk_detach(device_t dev)
1758 {
1759 struct sk_if_softc *sc_if;
1760 if_t ifp;
1761
1762 sc_if = device_get_softc(dev);
1763 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1764 ("sk mutex not initialized in sk_detach"));
1765 SK_IF_LOCK(sc_if);
1766
1767 ifp = sc_if->sk_ifp;
1768 /* These should only be active if attach_xmac succeeded */
1769 if (device_is_attached(dev)) {
1770 sk_stop(sc_if);
1771 /* Can't hold locks while calling detach */
1772 SK_IF_UNLOCK(sc_if);
1773 callout_drain(&sc_if->sk_tick_ch);
1774 callout_drain(&sc_if->sk_watchdog_ch);
1775 ether_ifdetach(ifp);
1776 SK_IF_LOCK(sc_if);
1777 }
1778 /*
1779 * We're generally called from skc_detach() which is using
1780 * device_delete_child() to get to here. It's already trashed
1781 * miibus for us, so don't do it here or we'll panic.
1782 */
1783 /*
1784 if (sc_if->sk_miibus != NULL)
1785 device_delete_child(dev, sc_if->sk_miibus);
1786 */
1787 bus_generic_detach(dev);
1788 sk_dma_jumbo_free(sc_if);
1789 sk_dma_free(sc_if);
1790 SK_IF_UNLOCK(sc_if);
1791 if (ifp)
1792 if_free(ifp);
1793
1794 return(0);
1795 }
1796
1797 static int
skc_detach(device_t dev)1798 skc_detach(device_t dev)
1799 {
1800 struct sk_softc *sc;
1801
1802 sc = device_get_softc(dev);
1803 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1804
1805 if (device_is_alive(dev)) {
1806 if (sc->sk_devs[SK_PORT_A] != NULL) {
1807 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1808 }
1809 if (sc->sk_devs[SK_PORT_B] != NULL) {
1810 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1811 }
1812 bus_generic_detach(dev);
1813 }
1814
1815 if (sc->sk_intrhand)
1816 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1817 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1818
1819 mtx_destroy(&sc->sk_mii_mtx);
1820 mtx_destroy(&sc->sk_mtx);
1821
1822 return(0);
1823 }
1824
1825 static bus_dma_tag_t
skc_get_dma_tag(device_t bus,device_t child __unused)1826 skc_get_dma_tag(device_t bus, device_t child __unused)
1827 {
1828
1829 return (bus_get_dma_tag(bus));
1830 }
1831
1832 struct sk_dmamap_arg {
1833 bus_addr_t sk_busaddr;
1834 };
1835
1836 static void
sk_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)1837 sk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1838 {
1839 struct sk_dmamap_arg *ctx;
1840
1841 if (error != 0)
1842 return;
1843
1844 ctx = arg;
1845 ctx->sk_busaddr = segs[0].ds_addr;
1846 }
1847
1848 /*
1849 * Allocate jumbo buffer storage. The SysKonnect adapters support
1850 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1851 * use them in their drivers. In order for us to use them, we need
1852 * large 9K receive buffers, however standard mbuf clusters are only
1853 * 2048 bytes in size. Consequently, we need to allocate and manage
1854 * our own jumbo buffer pool. Fortunately, this does not require an
1855 * excessive amount of additional code.
1856 */
1857 static int
sk_dma_alloc(struct sk_if_softc * sc_if)1858 sk_dma_alloc(struct sk_if_softc *sc_if)
1859 {
1860 struct sk_dmamap_arg ctx;
1861 struct sk_txdesc *txd;
1862 struct sk_rxdesc *rxd;
1863 int error, i;
1864
1865 /* create parent tag */
1866 /*
1867 * XXX
1868 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1869 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1870 * However bz@ reported that it does not work on amd64 with > 4GB
1871 * RAM. Until we have more clues of the breakage, disable DAC mode
1872 * by limiting DMA address to be in 32bit address space.
1873 */
1874 error = bus_dma_tag_create(
1875 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1876 1, 0, /* algnmnt, boundary */
1877 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1878 BUS_SPACE_MAXADDR, /* highaddr */
1879 NULL, NULL, /* filter, filterarg */
1880 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1881 0, /* nsegments */
1882 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1883 0, /* flags */
1884 NULL, NULL, /* lockfunc, lockarg */
1885 &sc_if->sk_cdata.sk_parent_tag);
1886 if (error != 0) {
1887 device_printf(sc_if->sk_if_dev,
1888 "failed to create parent DMA tag\n");
1889 goto fail;
1890 }
1891
1892 /* create tag for Tx ring */
1893 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1894 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1895 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1896 BUS_SPACE_MAXADDR, /* highaddr */
1897 NULL, NULL, /* filter, filterarg */
1898 SK_TX_RING_SZ, /* maxsize */
1899 1, /* nsegments */
1900 SK_TX_RING_SZ, /* maxsegsize */
1901 0, /* flags */
1902 NULL, NULL, /* lockfunc, lockarg */
1903 &sc_if->sk_cdata.sk_tx_ring_tag);
1904 if (error != 0) {
1905 device_printf(sc_if->sk_if_dev,
1906 "failed to allocate Tx ring DMA tag\n");
1907 goto fail;
1908 }
1909
1910 /* create tag for Rx ring */
1911 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1912 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1913 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1914 BUS_SPACE_MAXADDR, /* highaddr */
1915 NULL, NULL, /* filter, filterarg */
1916 SK_RX_RING_SZ, /* maxsize */
1917 1, /* nsegments */
1918 SK_RX_RING_SZ, /* maxsegsize */
1919 0, /* flags */
1920 NULL, NULL, /* lockfunc, lockarg */
1921 &sc_if->sk_cdata.sk_rx_ring_tag);
1922 if (error != 0) {
1923 device_printf(sc_if->sk_if_dev,
1924 "failed to allocate Rx ring DMA tag\n");
1925 goto fail;
1926 }
1927
1928 /* create tag for Tx buffers */
1929 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1930 1, 0, /* algnmnt, boundary */
1931 BUS_SPACE_MAXADDR, /* lowaddr */
1932 BUS_SPACE_MAXADDR, /* highaddr */
1933 NULL, NULL, /* filter, filterarg */
1934 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
1935 SK_MAXTXSEGS, /* nsegments */
1936 MCLBYTES, /* maxsegsize */
1937 0, /* flags */
1938 NULL, NULL, /* lockfunc, lockarg */
1939 &sc_if->sk_cdata.sk_tx_tag);
1940 if (error != 0) {
1941 device_printf(sc_if->sk_if_dev,
1942 "failed to allocate Tx DMA tag\n");
1943 goto fail;
1944 }
1945
1946 /* create tag for Rx buffers */
1947 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1948 1, 0, /* algnmnt, boundary */
1949 BUS_SPACE_MAXADDR, /* lowaddr */
1950 BUS_SPACE_MAXADDR, /* highaddr */
1951 NULL, NULL, /* filter, filterarg */
1952 MCLBYTES, /* maxsize */
1953 1, /* nsegments */
1954 MCLBYTES, /* maxsegsize */
1955 0, /* flags */
1956 NULL, NULL, /* lockfunc, lockarg */
1957 &sc_if->sk_cdata.sk_rx_tag);
1958 if (error != 0) {
1959 device_printf(sc_if->sk_if_dev,
1960 "failed to allocate Rx DMA tag\n");
1961 goto fail;
1962 }
1963
1964 /* allocate DMA'able memory and load the DMA map for Tx ring */
1965 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
1966 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
1967 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
1968 if (error != 0) {
1969 device_printf(sc_if->sk_if_dev,
1970 "failed to allocate DMA'able memory for Tx ring\n");
1971 goto fail;
1972 }
1973
1974 ctx.sk_busaddr = 0;
1975 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
1976 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
1977 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1978 if (error != 0) {
1979 device_printf(sc_if->sk_if_dev,
1980 "failed to load DMA'able memory for Tx ring\n");
1981 goto fail;
1982 }
1983 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
1984
1985 /* allocate DMA'able memory and load the DMA map for Rx ring */
1986 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
1987 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
1988 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
1989 if (error != 0) {
1990 device_printf(sc_if->sk_if_dev,
1991 "failed to allocate DMA'able memory for Rx ring\n");
1992 goto fail;
1993 }
1994
1995 ctx.sk_busaddr = 0;
1996 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
1997 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
1998 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1999 if (error != 0) {
2000 device_printf(sc_if->sk_if_dev,
2001 "failed to load DMA'able memory for Rx ring\n");
2002 goto fail;
2003 }
2004 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2005
2006 /* create DMA maps for Tx buffers */
2007 for (i = 0; i < SK_TX_RING_CNT; i++) {
2008 txd = &sc_if->sk_cdata.sk_txdesc[i];
2009 txd->tx_m = NULL;
2010 txd->tx_dmamap = NULL;
2011 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2012 &txd->tx_dmamap);
2013 if (error != 0) {
2014 device_printf(sc_if->sk_if_dev,
2015 "failed to create Tx dmamap\n");
2016 goto fail;
2017 }
2018 }
2019
2020 /* create DMA maps for Rx buffers */
2021 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2022 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2023 device_printf(sc_if->sk_if_dev,
2024 "failed to create spare Rx dmamap\n");
2025 goto fail;
2026 }
2027 for (i = 0; i < SK_RX_RING_CNT; i++) {
2028 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2029 rxd->rx_m = NULL;
2030 rxd->rx_dmamap = NULL;
2031 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2032 &rxd->rx_dmamap);
2033 if (error != 0) {
2034 device_printf(sc_if->sk_if_dev,
2035 "failed to create Rx dmamap\n");
2036 goto fail;
2037 }
2038 }
2039
2040 fail:
2041 return (error);
2042 }
2043
2044 static int
sk_dma_jumbo_alloc(struct sk_if_softc * sc_if)2045 sk_dma_jumbo_alloc(struct sk_if_softc *sc_if)
2046 {
2047 struct sk_dmamap_arg ctx;
2048 struct sk_rxdesc *jrxd;
2049 int error, i;
2050
2051 if (jumbo_disable != 0) {
2052 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2053 sc_if->sk_jumbo_disable = 1;
2054 return (0);
2055 }
2056 /* create tag for jumbo Rx ring */
2057 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2058 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2059 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2060 BUS_SPACE_MAXADDR, /* highaddr */
2061 NULL, NULL, /* filter, filterarg */
2062 SK_JUMBO_RX_RING_SZ, /* maxsize */
2063 1, /* nsegments */
2064 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2065 0, /* flags */
2066 NULL, NULL, /* lockfunc, lockarg */
2067 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2068 if (error != 0) {
2069 device_printf(sc_if->sk_if_dev,
2070 "failed to allocate jumbo Rx ring DMA tag\n");
2071 goto jumbo_fail;
2072 }
2073
2074 /* create tag for jumbo Rx buffers */
2075 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2076 1, 0, /* algnmnt, boundary */
2077 BUS_SPACE_MAXADDR, /* lowaddr */
2078 BUS_SPACE_MAXADDR, /* highaddr */
2079 NULL, NULL, /* filter, filterarg */
2080 MJUM9BYTES, /* maxsize */
2081 1, /* nsegments */
2082 MJUM9BYTES, /* maxsegsize */
2083 0, /* flags */
2084 NULL, NULL, /* lockfunc, lockarg */
2085 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2086 if (error != 0) {
2087 device_printf(sc_if->sk_if_dev,
2088 "failed to allocate jumbo Rx DMA tag\n");
2089 goto jumbo_fail;
2090 }
2091
2092 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2093 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2094 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2095 BUS_DMA_COHERENT | BUS_DMA_ZERO,
2096 &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2097 if (error != 0) {
2098 device_printf(sc_if->sk_if_dev,
2099 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2100 goto jumbo_fail;
2101 }
2102
2103 ctx.sk_busaddr = 0;
2104 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2105 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2106 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2107 &ctx, BUS_DMA_NOWAIT);
2108 if (error != 0) {
2109 device_printf(sc_if->sk_if_dev,
2110 "failed to load DMA'able memory for jumbo Rx ring\n");
2111 goto jumbo_fail;
2112 }
2113 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2114
2115 /* create DMA maps for jumbo Rx buffers */
2116 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2117 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2118 device_printf(sc_if->sk_if_dev,
2119 "failed to create spare jumbo Rx dmamap\n");
2120 goto jumbo_fail;
2121 }
2122 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2123 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2124 jrxd->rx_m = NULL;
2125 jrxd->rx_dmamap = NULL;
2126 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2127 &jrxd->rx_dmamap);
2128 if (error != 0) {
2129 device_printf(sc_if->sk_if_dev,
2130 "failed to create jumbo Rx dmamap\n");
2131 goto jumbo_fail;
2132 }
2133 }
2134
2135 return (0);
2136
2137 jumbo_fail:
2138 sk_dma_jumbo_free(sc_if);
2139 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2140 "resource shortage\n");
2141 sc_if->sk_jumbo_disable = 1;
2142 return (0);
2143 }
2144
2145 static void
sk_dma_free(struct sk_if_softc * sc_if)2146 sk_dma_free(struct sk_if_softc *sc_if)
2147 {
2148 struct sk_txdesc *txd;
2149 struct sk_rxdesc *rxd;
2150 int i;
2151
2152 /* Tx ring */
2153 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2154 if (sc_if->sk_rdata.sk_tx_ring_paddr)
2155 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2156 sc_if->sk_cdata.sk_tx_ring_map);
2157 if (sc_if->sk_rdata.sk_tx_ring)
2158 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2159 sc_if->sk_rdata.sk_tx_ring,
2160 sc_if->sk_cdata.sk_tx_ring_map);
2161 sc_if->sk_rdata.sk_tx_ring = NULL;
2162 sc_if->sk_rdata.sk_tx_ring_paddr = 0;
2163 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2164 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2165 }
2166 /* Rx ring */
2167 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2168 if (sc_if->sk_rdata.sk_rx_ring_paddr)
2169 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2170 sc_if->sk_cdata.sk_rx_ring_map);
2171 if (sc_if->sk_rdata.sk_rx_ring)
2172 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2173 sc_if->sk_rdata.sk_rx_ring,
2174 sc_if->sk_cdata.sk_rx_ring_map);
2175 sc_if->sk_rdata.sk_rx_ring = NULL;
2176 sc_if->sk_rdata.sk_rx_ring_paddr = 0;
2177 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2178 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2179 }
2180 /* Tx buffers */
2181 if (sc_if->sk_cdata.sk_tx_tag) {
2182 for (i = 0; i < SK_TX_RING_CNT; i++) {
2183 txd = &sc_if->sk_cdata.sk_txdesc[i];
2184 if (txd->tx_dmamap) {
2185 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2186 txd->tx_dmamap);
2187 txd->tx_dmamap = NULL;
2188 }
2189 }
2190 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2191 sc_if->sk_cdata.sk_tx_tag = NULL;
2192 }
2193 /* Rx buffers */
2194 if (sc_if->sk_cdata.sk_rx_tag) {
2195 for (i = 0; i < SK_RX_RING_CNT; i++) {
2196 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2197 if (rxd->rx_dmamap) {
2198 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2199 rxd->rx_dmamap);
2200 rxd->rx_dmamap = NULL;
2201 }
2202 }
2203 if (sc_if->sk_cdata.sk_rx_sparemap) {
2204 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2205 sc_if->sk_cdata.sk_rx_sparemap);
2206 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2207 }
2208 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2209 sc_if->sk_cdata.sk_rx_tag = NULL;
2210 }
2211
2212 if (sc_if->sk_cdata.sk_parent_tag) {
2213 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2214 sc_if->sk_cdata.sk_parent_tag = NULL;
2215 }
2216 }
2217
2218 static void
sk_dma_jumbo_free(struct sk_if_softc * sc_if)2219 sk_dma_jumbo_free(struct sk_if_softc *sc_if)
2220 {
2221 struct sk_rxdesc *jrxd;
2222 int i;
2223
2224 /* jumbo Rx ring */
2225 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2226 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr)
2227 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2228 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2229 if (sc_if->sk_rdata.sk_jumbo_rx_ring)
2230 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2231 sc_if->sk_rdata.sk_jumbo_rx_ring,
2232 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2233 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2234 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0;
2235 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2236 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2237 }
2238
2239 /* jumbo Rx buffers */
2240 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2241 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2242 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2243 if (jrxd->rx_dmamap) {
2244 bus_dmamap_destroy(
2245 sc_if->sk_cdata.sk_jumbo_rx_tag,
2246 jrxd->rx_dmamap);
2247 jrxd->rx_dmamap = NULL;
2248 }
2249 }
2250 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2251 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2252 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2253 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2254 }
2255 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2256 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2257 }
2258 }
2259
2260 static void
sk_txcksum(if_t ifp,struct mbuf * m,struct sk_tx_desc * f)2261 sk_txcksum(if_t ifp, struct mbuf *m, struct sk_tx_desc *f)
2262 {
2263 struct ip *ip;
2264 u_int16_t offset;
2265 u_int8_t *p;
2266
2267 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2268 for(; m && m->m_len == 0; m = m->m_next)
2269 ;
2270 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2271 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2272 /* checksum may be corrupted */
2273 goto sendit;
2274 }
2275 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2276 if (m->m_len != ETHER_HDR_LEN) {
2277 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2278 __func__);
2279 /* checksum may be corrupted */
2280 goto sendit;
2281 }
2282 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2283 ;
2284 if (m == NULL) {
2285 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2286 /* checksum may be corrupted */
2287 goto sendit;
2288 }
2289 ip = mtod(m, struct ip *);
2290 } else {
2291 p = mtod(m, u_int8_t *);
2292 p += ETHER_HDR_LEN;
2293 ip = (struct ip *)p;
2294 }
2295 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2296
2297 sendit:
2298 f->sk_csum_startval = 0;
2299 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2300 (offset << 16));
2301 }
2302
2303 static int
sk_encap(struct sk_if_softc * sc_if,struct mbuf ** m_head)2304 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head)
2305 {
2306 struct sk_txdesc *txd;
2307 struct sk_tx_desc *f = NULL;
2308 struct mbuf *m;
2309 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2310 u_int32_t cflags, frag, si, sk_ctl;
2311 int error, i, nseg;
2312
2313 SK_IF_LOCK_ASSERT(sc_if);
2314
2315 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2316 return (ENOBUFS);
2317
2318 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2319 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2320 if (error == EFBIG) {
2321 m = m_defrag(*m_head, M_NOWAIT);
2322 if (m == NULL) {
2323 m_freem(*m_head);
2324 *m_head = NULL;
2325 return (ENOMEM);
2326 }
2327 *m_head = m;
2328 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2329 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2330 if (error != 0) {
2331 m_freem(*m_head);
2332 *m_head = NULL;
2333 return (error);
2334 }
2335 } else if (error != 0)
2336 return (error);
2337 if (nseg == 0) {
2338 m_freem(*m_head);
2339 *m_head = NULL;
2340 return (EIO);
2341 }
2342 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2343 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2344 return (ENOBUFS);
2345 }
2346
2347 m = *m_head;
2348 if ((m->m_pkthdr.csum_flags & if_gethwassist(sc_if->sk_ifp)) != 0)
2349 cflags = SK_OPCODE_CSUM;
2350 else
2351 cflags = SK_OPCODE_DEFAULT;
2352 si = frag = sc_if->sk_cdata.sk_tx_prod;
2353 for (i = 0; i < nseg; i++) {
2354 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2355 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2356 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2357 sk_ctl = txsegs[i].ds_len | cflags;
2358 if (i == 0) {
2359 if (cflags == SK_OPCODE_CSUM)
2360 sk_txcksum(sc_if->sk_ifp, m, f);
2361 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2362 } else
2363 sk_ctl |= SK_TXCTL_OWN;
2364 f->sk_ctl = htole32(sk_ctl);
2365 sc_if->sk_cdata.sk_tx_cnt++;
2366 SK_INC(frag, SK_TX_RING_CNT);
2367 }
2368 sc_if->sk_cdata.sk_tx_prod = frag;
2369
2370 /* set EOF on the last descriptor */
2371 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2372 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2373 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2374
2375 /* turn the first descriptor ownership to NIC */
2376 f = &sc_if->sk_rdata.sk_tx_ring[si];
2377 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2378
2379 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2380 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2381 txd->tx_m = m;
2382
2383 /* sync descriptors */
2384 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2385 BUS_DMASYNC_PREWRITE);
2386 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2387 sc_if->sk_cdata.sk_tx_ring_map,
2388 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2389
2390 return (0);
2391 }
2392
2393 static void
sk_start(if_t ifp)2394 sk_start(if_t ifp)
2395 {
2396 struct sk_if_softc *sc_if;
2397
2398 sc_if = if_getsoftc(ifp);
2399
2400 SK_IF_LOCK(sc_if);
2401 sk_start_locked(ifp);
2402 SK_IF_UNLOCK(sc_if);
2403
2404 return;
2405 }
2406
2407 static void
sk_start_locked(if_t ifp)2408 sk_start_locked(if_t ifp)
2409 {
2410 struct sk_softc *sc;
2411 struct sk_if_softc *sc_if;
2412 struct mbuf *m_head;
2413 int enq;
2414
2415 sc_if = if_getsoftc(ifp);
2416 sc = sc_if->sk_softc;
2417
2418 SK_IF_LOCK_ASSERT(sc_if);
2419
2420 for (enq = 0; !if_sendq_empty(ifp) &&
2421 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2422 m_head = if_dequeue(ifp);
2423 if (m_head == NULL)
2424 break;
2425
2426 /*
2427 * Pack the data into the transmit ring. If we
2428 * don't have room, set the OACTIVE flag and wait
2429 * for the NIC to drain the ring.
2430 */
2431 if (sk_encap(sc_if, &m_head)) {
2432 if (m_head == NULL)
2433 break;
2434 if_sendq_prepend(ifp, m_head);
2435 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2436 break;
2437 }
2438
2439 enq++;
2440 /*
2441 * If there's a BPF listener, bounce a copy of this frame
2442 * to him.
2443 */
2444 BPF_MTAP(ifp, m_head);
2445 }
2446
2447 if (enq > 0) {
2448 /* Transmit */
2449 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2450
2451 /* Set a timeout in case the chip goes out to lunch. */
2452 sc_if->sk_watchdog_timer = 5;
2453 }
2454 }
2455
2456 static void
sk_watchdog(void * arg)2457 sk_watchdog(void *arg)
2458 {
2459 struct sk_if_softc *sc_if;
2460 if_t ifp;
2461
2462 ifp = arg;
2463 sc_if = if_getsoftc(ifp);
2464
2465 SK_IF_LOCK_ASSERT(sc_if);
2466
2467 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2468 goto done;
2469
2470 /*
2471 * Reclaim first as there is a possibility of losing Tx completion
2472 * interrupts.
2473 */
2474 sk_txeof(sc_if);
2475 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2476 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2477 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2478 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2479 sk_init_locked(sc_if);
2480 }
2481
2482 done:
2483 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2484
2485 return;
2486 }
2487
2488 static int
skc_shutdown(device_t dev)2489 skc_shutdown(device_t dev)
2490 {
2491 struct sk_softc *sc;
2492
2493 sc = device_get_softc(dev);
2494 SK_LOCK(sc);
2495
2496 /* Turn off the 'driver is loaded' LED. */
2497 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2498
2499 /*
2500 * Reset the GEnesis controller. Doing this should also
2501 * assert the resets on the attached XMAC(s).
2502 */
2503 sk_reset(sc);
2504 SK_UNLOCK(sc);
2505
2506 return (0);
2507 }
2508
2509 static int
skc_suspend(device_t dev)2510 skc_suspend(device_t dev)
2511 {
2512 struct sk_softc *sc;
2513 struct sk_if_softc *sc_if0, *sc_if1;
2514 if_t ifp0 = NULL, ifp1 = NULL;
2515
2516 sc = device_get_softc(dev);
2517
2518 SK_LOCK(sc);
2519
2520 sc_if0 = sc->sk_if[SK_PORT_A];
2521 sc_if1 = sc->sk_if[SK_PORT_B];
2522 if (sc_if0 != NULL)
2523 ifp0 = sc_if0->sk_ifp;
2524 if (sc_if1 != NULL)
2525 ifp1 = sc_if1->sk_ifp;
2526 if (ifp0 != NULL)
2527 sk_stop(sc_if0);
2528 if (ifp1 != NULL)
2529 sk_stop(sc_if1);
2530 sc->sk_suspended = 1;
2531
2532 SK_UNLOCK(sc);
2533
2534 return (0);
2535 }
2536
2537 static int
skc_resume(device_t dev)2538 skc_resume(device_t dev)
2539 {
2540 struct sk_softc *sc;
2541 struct sk_if_softc *sc_if0, *sc_if1;
2542 if_t ifp0 = NULL, ifp1 = NULL;
2543
2544 sc = device_get_softc(dev);
2545
2546 SK_LOCK(sc);
2547
2548 sc_if0 = sc->sk_if[SK_PORT_A];
2549 sc_if1 = sc->sk_if[SK_PORT_B];
2550 if (sc_if0 != NULL)
2551 ifp0 = sc_if0->sk_ifp;
2552 if (sc_if1 != NULL)
2553 ifp1 = sc_if1->sk_ifp;
2554 if (ifp0 != NULL && if_getflags(ifp0) & IFF_UP)
2555 sk_init_locked(sc_if0);
2556 if (ifp1 != NULL && if_getflags(ifp1) & IFF_UP)
2557 sk_init_locked(sc_if1);
2558 sc->sk_suspended = 0;
2559
2560 SK_UNLOCK(sc);
2561
2562 return (0);
2563 }
2564
2565 /*
2566 * According to the data sheet from SK-NET GENESIS the hardware can compute
2567 * two Rx checksums at the same time(Each checksum start position is
2568 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2569 * does not work at least on my Yukon hardware. I tried every possible ways
2570 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2571 * checksum offload was disabled at the moment and only IP checksum offload
2572 * was enabled.
2573 * As normal IP header size is 20 bytes I can't expect it would give an
2574 * increase in throughput. However it seems it doesn't hurt performance in
2575 * my testing. If there is a more detailed information for checksum secret
2576 * of the hardware in question please contact yongari@FreeBSD.org to add
2577 * TCP/UDP checksum offload support.
2578 */
2579 static __inline void
sk_rxcksum(if_t ifp,struct mbuf * m,u_int32_t csum)2580 sk_rxcksum(if_t ifp, struct mbuf *m, u_int32_t csum)
2581 {
2582 struct ether_header *eh;
2583 struct ip *ip;
2584 int32_t hlen, len, pktlen;
2585 u_int16_t csum1, csum2, ipcsum;
2586
2587 pktlen = m->m_pkthdr.len;
2588 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2589 return;
2590 eh = mtod(m, struct ether_header *);
2591 if (eh->ether_type != htons(ETHERTYPE_IP))
2592 return;
2593 ip = (struct ip *)(eh + 1);
2594 if (ip->ip_v != IPVERSION)
2595 return;
2596 hlen = ip->ip_hl << 2;
2597 pktlen -= sizeof(struct ether_header);
2598 if (hlen < sizeof(struct ip))
2599 return;
2600 if (ntohs(ip->ip_len) < hlen)
2601 return;
2602 if (ntohs(ip->ip_len) != pktlen)
2603 return;
2604
2605 csum1 = htons(csum & 0xffff);
2606 csum2 = htons((csum >> 16) & 0xffff);
2607 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2608 /* checksum fixup for IP options */
2609 len = hlen - sizeof(struct ip);
2610 if (len > 0) {
2611 /*
2612 * If the second checksum value is correct we can compute IP
2613 * checksum with simple math. Unfortunately the second checksum
2614 * value is wrong so we can't verify the checksum from the
2615 * value(It seems there is some magic here to get correct
2616 * value). If the second checksum value is correct it also
2617 * means we can get TCP/UDP checksum) here. However, it still
2618 * needs pseudo header checksum calculation due to hardware
2619 * limitations.
2620 */
2621 return;
2622 }
2623 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2624 if (ipcsum == 0xffff)
2625 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2626 }
2627
2628 static __inline int
sk_rxvalid(struct sk_softc * sc,u_int32_t stat,u_int32_t len)2629 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
2630 {
2631
2632 if (sc->sk_type == SK_GENESIS) {
2633 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2634 XM_RXSTAT_BYTES(stat) != len)
2635 return (0);
2636 } else {
2637 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2638 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2639 YU_RXSTAT_JABBER)) != 0 ||
2640 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2641 YU_RXSTAT_BYTES(stat) != len)
2642 return (0);
2643 }
2644
2645 return (1);
2646 }
2647
2648 static void
sk_rxeof(struct sk_if_softc * sc_if)2649 sk_rxeof(struct sk_if_softc *sc_if)
2650 {
2651 struct sk_softc *sc;
2652 struct mbuf *m;
2653 if_t ifp;
2654 struct sk_rx_desc *cur_rx;
2655 struct sk_rxdesc *rxd;
2656 int cons, prog;
2657 u_int32_t csum, rxstat, sk_ctl;
2658
2659 sc = sc_if->sk_softc;
2660 ifp = sc_if->sk_ifp;
2661
2662 SK_IF_LOCK_ASSERT(sc_if);
2663
2664 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2665 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2666
2667 prog = 0;
2668 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2669 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2670 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2671 sk_ctl = le32toh(cur_rx->sk_ctl);
2672 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2673 break;
2674 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2675 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2676
2677 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2678 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2679 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2680 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2681 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2682 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2683 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2684 sk_discard_rxbuf(sc_if, cons);
2685 continue;
2686 }
2687
2688 m = rxd->rx_m;
2689 csum = le32toh(cur_rx->sk_csum);
2690 if (sk_newbuf(sc_if, cons) != 0) {
2691 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2692 /* reuse old buffer */
2693 sk_discard_rxbuf(sc_if, cons);
2694 continue;
2695 }
2696 m->m_pkthdr.rcvif = ifp;
2697 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2698 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2699 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2700 sk_rxcksum(ifp, m, csum);
2701 SK_IF_UNLOCK(sc_if);
2702 if_input(ifp, m);
2703 SK_IF_LOCK(sc_if);
2704 }
2705
2706 if (prog > 0) {
2707 sc_if->sk_cdata.sk_rx_cons = cons;
2708 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2709 sc_if->sk_cdata.sk_rx_ring_map,
2710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2711 }
2712 }
2713
2714 static void
sk_jumbo_rxeof(struct sk_if_softc * sc_if)2715 sk_jumbo_rxeof(struct sk_if_softc *sc_if)
2716 {
2717 struct sk_softc *sc;
2718 struct mbuf *m;
2719 if_t ifp;
2720 struct sk_rx_desc *cur_rx;
2721 struct sk_rxdesc *jrxd;
2722 int cons, prog;
2723 u_int32_t csum, rxstat, sk_ctl;
2724
2725 sc = sc_if->sk_softc;
2726 ifp = sc_if->sk_ifp;
2727
2728 SK_IF_LOCK_ASSERT(sc_if);
2729
2730 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2731 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2732
2733 prog = 0;
2734 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2735 prog < SK_JUMBO_RX_RING_CNT;
2736 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2737 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2738 sk_ctl = le32toh(cur_rx->sk_ctl);
2739 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2740 break;
2741 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2742 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2743
2744 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2745 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2746 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2747 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2748 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2749 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2750 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2751 sk_discard_jumbo_rxbuf(sc_if, cons);
2752 continue;
2753 }
2754
2755 m = jrxd->rx_m;
2756 csum = le32toh(cur_rx->sk_csum);
2757 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2758 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2759 /* reuse old buffer */
2760 sk_discard_jumbo_rxbuf(sc_if, cons);
2761 continue;
2762 }
2763 m->m_pkthdr.rcvif = ifp;
2764 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2765 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2766 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2767 sk_rxcksum(ifp, m, csum);
2768 SK_IF_UNLOCK(sc_if);
2769 if_input(ifp, m);
2770 SK_IF_LOCK(sc_if);
2771 }
2772
2773 if (prog > 0) {
2774 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2775 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2776 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2778 }
2779 }
2780
2781 static void
sk_txeof(struct sk_if_softc * sc_if)2782 sk_txeof(struct sk_if_softc *sc_if)
2783 {
2784 struct sk_txdesc *txd;
2785 struct sk_tx_desc *cur_tx;
2786 if_t ifp;
2787 u_int32_t idx, sk_ctl;
2788
2789 ifp = sc_if->sk_ifp;
2790
2791 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2792 if (txd == NULL)
2793 return;
2794 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2795 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2796 /*
2797 * Go through our tx ring and free mbufs for those
2798 * frames that have been sent.
2799 */
2800 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2801 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2802 break;
2803 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2804 sk_ctl = le32toh(cur_tx->sk_ctl);
2805 if (sk_ctl & SK_TXCTL_OWN)
2806 break;
2807 sc_if->sk_cdata.sk_tx_cnt--;
2808 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2809 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2810 continue;
2811 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2812 BUS_DMASYNC_POSTWRITE);
2813 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2814
2815 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2816 m_freem(txd->tx_m);
2817 txd->tx_m = NULL;
2818 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2819 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2820 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2821 }
2822 sc_if->sk_cdata.sk_tx_cons = idx;
2823 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2824
2825 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2826 sc_if->sk_cdata.sk_tx_ring_map,
2827 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2828 }
2829
2830 static void
sk_tick(void * xsc_if)2831 sk_tick(void *xsc_if)
2832 {
2833 struct sk_if_softc *sc_if;
2834 struct mii_data *mii;
2835 if_t ifp;
2836 int i;
2837
2838 sc_if = xsc_if;
2839 ifp = sc_if->sk_ifp;
2840 mii = device_get_softc(sc_if->sk_miibus);
2841
2842 if (!(if_getflags(ifp) & IFF_UP))
2843 return;
2844
2845 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2846 sk_intr_bcom(sc_if);
2847 return;
2848 }
2849
2850 /*
2851 * According to SysKonnect, the correct way to verify that
2852 * the link has come back up is to poll bit 0 of the GPIO
2853 * register three times. This pin has the signal from the
2854 * link_sync pin connected to it; if we read the same link
2855 * state 3 times in a row, we know the link is up.
2856 */
2857 for (i = 0; i < 3; i++) {
2858 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2859 break;
2860 }
2861
2862 if (i != 3) {
2863 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2864 return;
2865 }
2866
2867 /* Turn the GP0 interrupt back on. */
2868 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2869 SK_XM_READ_2(sc_if, XM_ISR);
2870 mii_tick(mii);
2871 callout_stop(&sc_if->sk_tick_ch);
2872 }
2873
2874 static void
sk_yukon_tick(void * xsc_if)2875 sk_yukon_tick(void *xsc_if)
2876 {
2877 struct sk_if_softc *sc_if;
2878 struct mii_data *mii;
2879
2880 sc_if = xsc_if;
2881 mii = device_get_softc(sc_if->sk_miibus);
2882
2883 mii_tick(mii);
2884 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2885 }
2886
2887 static void
sk_intr_bcom(struct sk_if_softc * sc_if)2888 sk_intr_bcom(struct sk_if_softc *sc_if)
2889 {
2890 struct mii_data *mii;
2891 if_t ifp;
2892 int status;
2893 mii = device_get_softc(sc_if->sk_miibus);
2894 ifp = sc_if->sk_ifp;
2895
2896 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2897
2898 /*
2899 * Read the PHY interrupt register to make sure
2900 * we clear any pending interrupts.
2901 */
2902 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2903
2904 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
2905 sk_init_xmac(sc_if);
2906 return;
2907 }
2908
2909 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2910 int lstat;
2911 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2912 BRGPHY_MII_AUXSTS);
2913
2914 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2915 mii_mediachg(mii);
2916 /* Turn off the link LED. */
2917 SK_IF_WRITE_1(sc_if, 0,
2918 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2919 sc_if->sk_link = 0;
2920 } else if (status & BRGPHY_ISR_LNK_CHG) {
2921 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2922 BRGPHY_MII_IMR, 0xFF00);
2923 mii_tick(mii);
2924 sc_if->sk_link = 1;
2925 /* Turn on the link LED. */
2926 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2927 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2928 SK_LINKLED_BLINK_OFF);
2929 } else {
2930 mii_tick(mii);
2931 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2932 }
2933 }
2934
2935 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2936
2937 return;
2938 }
2939
2940 static void
sk_intr_xmac(struct sk_if_softc * sc_if)2941 sk_intr_xmac(struct sk_if_softc *sc_if)
2942 {
2943 u_int16_t status;
2944
2945 status = SK_XM_READ_2(sc_if, XM_ISR);
2946
2947 /*
2948 * Link has gone down. Start MII tick timeout to
2949 * watch for link resync.
2950 */
2951 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2952 if (status & XM_ISR_GP0_SET) {
2953 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2954 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2955 }
2956
2957 if (status & XM_ISR_AUTONEG_DONE) {
2958 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2959 }
2960 }
2961
2962 if (status & XM_IMR_TX_UNDERRUN)
2963 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2964
2965 if (status & XM_IMR_RX_OVERRUN)
2966 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2967
2968 status = SK_XM_READ_2(sc_if, XM_ISR);
2969
2970 return;
2971 }
2972
2973 static void
sk_intr_yukon(struct sk_if_softc * sc_if)2974 sk_intr_yukon(struct sk_if_softc *sc_if)
2975 {
2976 u_int8_t status;
2977
2978 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2979 /* RX overrun */
2980 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2981 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2982 SK_RFCTL_RX_FIFO_OVER);
2983 }
2984 /* TX underrun */
2985 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2986 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2987 SK_TFCTL_TX_FIFO_UNDER);
2988 }
2989 }
2990
2991 static void
sk_intr(void * xsc)2992 sk_intr(void *xsc)
2993 {
2994 struct sk_softc *sc = xsc;
2995 struct sk_if_softc *sc_if0, *sc_if1;
2996 if_t ifp0 = NULL, ifp1 = NULL;
2997 u_int32_t status;
2998
2999 SK_LOCK(sc);
3000
3001 status = CSR_READ_4(sc, SK_ISSR);
3002 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3003 goto done_locked;
3004
3005 sc_if0 = sc->sk_if[SK_PORT_A];
3006 sc_if1 = sc->sk_if[SK_PORT_B];
3007
3008 if (sc_if0 != NULL)
3009 ifp0 = sc_if0->sk_ifp;
3010 if (sc_if1 != NULL)
3011 ifp1 = sc_if1->sk_ifp;
3012
3013 for (; (status &= sc->sk_intrmask) != 0;) {
3014 /* Handle receive interrupts first. */
3015 if (status & SK_ISR_RX1_EOF) {
3016 if (if_getmtu(ifp0) > SK_MAX_FRAMELEN)
3017 sk_jumbo_rxeof(sc_if0);
3018 else
3019 sk_rxeof(sc_if0);
3020 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3021 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3022 }
3023 if (status & SK_ISR_RX2_EOF) {
3024 if (if_getflags(ifp1) > SK_MAX_FRAMELEN)
3025 sk_jumbo_rxeof(sc_if1);
3026 else
3027 sk_rxeof(sc_if1);
3028 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3029 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3030 }
3031
3032 /* Then transmit interrupts. */
3033 if (status & SK_ISR_TX1_S_EOF) {
3034 sk_txeof(sc_if0);
3035 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3036 }
3037 if (status & SK_ISR_TX2_S_EOF) {
3038 sk_txeof(sc_if1);
3039 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3040 }
3041
3042 /* Then MAC interrupts. */
3043 if (status & SK_ISR_MAC1 &&
3044 if_getdrvflags(ifp0) & IFF_DRV_RUNNING) {
3045 if (sc->sk_type == SK_GENESIS)
3046 sk_intr_xmac(sc_if0);
3047 else
3048 sk_intr_yukon(sc_if0);
3049 }
3050
3051 if (status & SK_ISR_MAC2 &&
3052 if_getdrvflags(ifp1) & IFF_DRV_RUNNING) {
3053 if (sc->sk_type == SK_GENESIS)
3054 sk_intr_xmac(sc_if1);
3055 else
3056 sk_intr_yukon(sc_if1);
3057 }
3058
3059 if (status & SK_ISR_EXTERNAL_REG) {
3060 if (ifp0 != NULL &&
3061 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3062 sk_intr_bcom(sc_if0);
3063 if (ifp1 != NULL &&
3064 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3065 sk_intr_bcom(sc_if1);
3066 }
3067 status = CSR_READ_4(sc, SK_ISSR);
3068 }
3069
3070 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3071
3072 if (ifp0 != NULL && !if_sendq_empty(ifp0))
3073 sk_start_locked(ifp0);
3074 if (ifp1 != NULL && !if_sendq_empty(ifp1))
3075 sk_start_locked(ifp1);
3076
3077 done_locked:
3078 SK_UNLOCK(sc);
3079 }
3080
3081 static void
sk_init_xmac(struct sk_if_softc * sc_if)3082 sk_init_xmac(struct sk_if_softc *sc_if)
3083 {
3084 struct sk_softc *sc;
3085 if_t ifp;
3086 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3087 static const struct sk_bcom_hack bhack[] = {
3088 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3089 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3090 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3091 { 0, 0 } };
3092
3093 SK_IF_LOCK_ASSERT(sc_if);
3094
3095 sc = sc_if->sk_softc;
3096 ifp = sc_if->sk_ifp;
3097
3098 /* Unreset the XMAC. */
3099 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3100 DELAY(1000);
3101
3102 /* Reset the XMAC's internal state. */
3103 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3104
3105 /* Save the XMAC II revision */
3106 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3107
3108 /*
3109 * Perform additional initialization for external PHYs,
3110 * namely for the 1000baseTX cards that use the XMAC's
3111 * GMII mode.
3112 */
3113 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3114 int i = 0;
3115 u_int32_t val;
3116
3117 /* Take PHY out of reset. */
3118 val = sk_win_read_4(sc, SK_GPIO);
3119 if (sc_if->sk_port == SK_PORT_A)
3120 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3121 else
3122 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3123 sk_win_write_4(sc, SK_GPIO, val);
3124
3125 /* Enable GMII mode on the XMAC. */
3126 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3127
3128 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3129 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3130 DELAY(10000);
3131 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3132 BRGPHY_MII_IMR, 0xFFF0);
3133
3134 /*
3135 * Early versions of the BCM5400 apparently have
3136 * a bug that requires them to have their reserved
3137 * registers initialized to some magic values. I don't
3138 * know what the numbers do, I'm just the messenger.
3139 */
3140 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3141 == 0x6041) {
3142 while(bhack[i].reg) {
3143 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3144 bhack[i].reg, bhack[i].val);
3145 i++;
3146 }
3147 }
3148 }
3149
3150 /* Set station address */
3151 bcopy(if_getlladdr(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3152 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3153 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3154 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3155 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3156
3157 if (if_getflags(ifp) & IFF_BROADCAST) {
3158 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3159 } else {
3160 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3161 }
3162
3163 /* We don't need the FCS appended to the packet. */
3164 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3165
3166 /* We want short frames padded to 60 bytes. */
3167 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3168
3169 /*
3170 * Enable the reception of all error frames. This is is
3171 * a necessary evil due to the design of the XMAC. The
3172 * XMAC's receive FIFO is only 8K in size, however jumbo
3173 * frames can be up to 9000 bytes in length. When bad
3174 * frame filtering is enabled, the XMAC's RX FIFO operates
3175 * in 'store and forward' mode. For this to work, the
3176 * entire frame has to fit into the FIFO, but that means
3177 * that jumbo frames larger than 8192 bytes will be
3178 * truncated. Disabling all bad frame filtering causes
3179 * the RX FIFO to operate in streaming mode, in which
3180 * case the XMAC will start transferring frames out of the
3181 * RX FIFO as soon as the FIFO threshold is reached.
3182 */
3183 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) {
3184 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3185 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3186 XM_MODE_RX_INRANGELEN);
3187 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3188 } else
3189 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3190
3191 /*
3192 * Bump up the transmit threshold. This helps hold off transmit
3193 * underruns when we're blasting traffic from both ports at once.
3194 */
3195 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3196
3197 /* Set Rx filter */
3198 sk_rxfilter_genesis(sc_if);
3199
3200 /* Clear and enable interrupts */
3201 SK_XM_READ_2(sc_if, XM_ISR);
3202 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3203 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3204 else
3205 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3206
3207 /* Configure MAC arbiter */
3208 switch(sc_if->sk_xmac_rev) {
3209 case XM_XMAC_REV_B2:
3210 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3211 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3212 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3213 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3214 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3215 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3216 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3217 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3218 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3219 break;
3220 case XM_XMAC_REV_C1:
3221 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3222 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3223 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3224 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3225 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3226 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3227 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3228 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3229 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3230 break;
3231 default:
3232 break;
3233 }
3234 sk_win_write_2(sc, SK_MACARB_CTL,
3235 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3236
3237 sc_if->sk_link = 1;
3238
3239 return;
3240 }
3241
3242 static void
sk_init_yukon(struct sk_if_softc * sc_if)3243 sk_init_yukon(struct sk_if_softc *sc_if)
3244 {
3245 u_int32_t phy, v;
3246 u_int16_t reg;
3247 struct sk_softc *sc;
3248 if_t ifp;
3249 u_int8_t *eaddr;
3250 int i;
3251
3252 SK_IF_LOCK_ASSERT(sc_if);
3253
3254 sc = sc_if->sk_softc;
3255 ifp = sc_if->sk_ifp;
3256
3257 if (sc->sk_type == SK_YUKON_LITE &&
3258 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3259 /*
3260 * Workaround code for COMA mode, set PHY reset.
3261 * Otherwise it will not correctly take chip out of
3262 * powerdown (coma)
3263 */
3264 v = sk_win_read_4(sc, SK_GPIO);
3265 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3266 sk_win_write_4(sc, SK_GPIO, v);
3267 }
3268
3269 /* GMAC and GPHY Reset */
3270 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3271 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3272 DELAY(1000);
3273
3274 if (sc->sk_type == SK_YUKON_LITE &&
3275 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3276 /*
3277 * Workaround code for COMA mode, clear PHY reset
3278 */
3279 v = sk_win_read_4(sc, SK_GPIO);
3280 v |= SK_GPIO_DIR9;
3281 v &= ~SK_GPIO_DAT9;
3282 sk_win_write_4(sc, SK_GPIO, v);
3283 }
3284
3285 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3286 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3287
3288 if (sc->sk_coppertype)
3289 phy |= SK_GPHY_COPPER;
3290 else
3291 phy |= SK_GPHY_FIBER;
3292
3293 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3294 DELAY(1000);
3295 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3296 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3297 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3298
3299 /* unused read of the interrupt source register */
3300 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3301
3302 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3303
3304 /* MIB Counter Clear Mode set */
3305 reg |= YU_PAR_MIB_CLR;
3306 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3307
3308 /* MIB Counter Clear Mode clear */
3309 reg &= ~YU_PAR_MIB_CLR;
3310 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3311
3312 /* receive control reg */
3313 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3314
3315 /* transmit parameter register */
3316 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3317 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3318
3319 /* serial mode register */
3320 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3321 if (if_getmtu(ifp) > SK_MAX_FRAMELEN)
3322 reg |= YU_SMR_MFL_JUMBO;
3323 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3324
3325 /* Setup Yukon's station address */
3326 eaddr = if_getlladdr(sc_if->sk_ifp);
3327 for (i = 0; i < 3; i++)
3328 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3329 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3330 /* Set GMAC source address of flow control. */
3331 for (i = 0; i < 3; i++)
3332 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3333 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3334 /* Set GMAC virtual address. */
3335 for (i = 0; i < 3; i++)
3336 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3337 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3338
3339 /* Set Rx filter */
3340 sk_rxfilter_yukon(sc_if);
3341
3342 /* enable interrupt mask for counter overflows */
3343 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3344 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3345 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3346
3347 /* Configure RX MAC FIFO Flush Mask */
3348 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3349 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3350 YU_RXSTAT_JABBER;
3351 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3352
3353 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3354 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3355 v = SK_TFCTL_OPERATION_ON;
3356 else
3357 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3358 /* Configure RX MAC FIFO */
3359 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3360 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3361
3362 /* Increase flush threshould to 64 bytes */
3363 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3364 SK_RFCTL_FIFO_THRESHOLD + 1);
3365
3366 /* Configure TX MAC FIFO */
3367 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3368 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3369 }
3370
3371 /*
3372 * Note that to properly initialize any part of the GEnesis chip,
3373 * you first have to take it out of reset mode.
3374 */
3375 static void
sk_init(void * xsc)3376 sk_init(void *xsc)
3377 {
3378 struct sk_if_softc *sc_if = xsc;
3379
3380 SK_IF_LOCK(sc_if);
3381 sk_init_locked(sc_if);
3382 SK_IF_UNLOCK(sc_if);
3383
3384 return;
3385 }
3386
3387 static void
sk_init_locked(struct sk_if_softc * sc_if)3388 sk_init_locked(struct sk_if_softc *sc_if)
3389 {
3390 struct sk_softc *sc;
3391 if_t ifp;
3392 struct mii_data *mii;
3393 u_int16_t reg;
3394 u_int32_t imr;
3395 int error;
3396
3397 SK_IF_LOCK_ASSERT(sc_if);
3398
3399 ifp = sc_if->sk_ifp;
3400 sc = sc_if->sk_softc;
3401 mii = device_get_softc(sc_if->sk_miibus);
3402
3403 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3404 return;
3405
3406 /* Cancel pending I/O and free all RX/TX buffers. */
3407 sk_stop(sc_if);
3408
3409 if (sc->sk_type == SK_GENESIS) {
3410 /* Configure LINK_SYNC LED */
3411 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3412 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3413 SK_LINKLED_LINKSYNC_ON);
3414
3415 /* Configure RX LED */
3416 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3417 SK_RXLEDCTL_COUNTER_START);
3418
3419 /* Configure TX LED */
3420 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3421 SK_TXLEDCTL_COUNTER_START);
3422 }
3423
3424 /*
3425 * Configure descriptor poll timer
3426 *
3427 * SK-NET GENESIS data sheet says that possibility of losing Start
3428 * transmit command due to CPU/cache related interim storage problems
3429 * under certain conditions. The document recommends a polling
3430 * mechanism to send a Start transmit command to initiate transfer
3431 * of ready descriptors regulary. To cope with this issue sk(4) now
3432 * enables descriptor poll timer to initiate descriptor processing
3433 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3434 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3435 * command instead of waiting for next descriptor polling time.
3436 * The same rule may apply to Rx side too but it seems that is not
3437 * needed at the moment.
3438 * Since sk(4) uses descriptor polling as a last resort there is no
3439 * need to set smaller polling time than maximum allowable one.
3440 */
3441 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3442
3443 /* Configure I2C registers */
3444
3445 /* Configure XMAC(s) */
3446 switch (sc->sk_type) {
3447 case SK_GENESIS:
3448 sk_init_xmac(sc_if);
3449 break;
3450 case SK_YUKON:
3451 case SK_YUKON_LITE:
3452 case SK_YUKON_LP:
3453 sk_init_yukon(sc_if);
3454 break;
3455 }
3456 mii_mediachg(mii);
3457
3458 if (sc->sk_type == SK_GENESIS) {
3459 /* Configure MAC FIFOs */
3460 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3461 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3462 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3463
3464 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3465 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3466 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3467 }
3468
3469 /* Configure transmit arbiter(s) */
3470 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3471 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3472
3473 /* Configure RAMbuffers */
3474 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3475 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3476 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3477 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3478 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3479 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3480
3481 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3482 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3483 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3484 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3485 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3486 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3487 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3488
3489 /* Configure BMUs */
3490 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3491 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) {
3492 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3493 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3494 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3495 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3496 } else {
3497 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3498 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3499 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3500 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3501 }
3502
3503 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3504 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3505 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3506 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3507 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3508
3509 /* Init descriptors */
3510 if (if_getmtu(ifp) > SK_MAX_FRAMELEN)
3511 error = sk_init_jumbo_rx_ring(sc_if);
3512 else
3513 error = sk_init_rx_ring(sc_if);
3514 if (error != 0) {
3515 device_printf(sc_if->sk_if_dev,
3516 "initialization failed: no memory for rx buffers\n");
3517 sk_stop(sc_if);
3518 return;
3519 }
3520 sk_init_tx_ring(sc_if);
3521
3522 /* Set interrupt moderation if changed via sysctl. */
3523 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3524 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3525 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3526 sc->sk_int_ticks));
3527 if (bootverbose)
3528 device_printf(sc_if->sk_if_dev,
3529 "interrupt moderation is %d us.\n",
3530 sc->sk_int_mod);
3531 }
3532
3533 /* Configure interrupt handling */
3534 CSR_READ_4(sc, SK_ISSR);
3535 if (sc_if->sk_port == SK_PORT_A)
3536 sc->sk_intrmask |= SK_INTRS1;
3537 else
3538 sc->sk_intrmask |= SK_INTRS2;
3539
3540 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3541
3542 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3543
3544 /* Start BMUs. */
3545 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3546
3547 switch(sc->sk_type) {
3548 case SK_GENESIS:
3549 /* Enable XMACs TX and RX state machines */
3550 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3551 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3552 break;
3553 case SK_YUKON:
3554 case SK_YUKON_LITE:
3555 case SK_YUKON_LP:
3556 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3557 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3558 #if 0
3559 /* XXX disable 100Mbps and full duplex mode? */
3560 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3561 #endif
3562 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3563 }
3564
3565 /* Activate descriptor polling timer */
3566 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3567 /* start transfer of Tx descriptors */
3568 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3569
3570 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3571 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3572
3573 switch (sc->sk_type) {
3574 case SK_YUKON:
3575 case SK_YUKON_LITE:
3576 case SK_YUKON_LP:
3577 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3578 break;
3579 }
3580
3581 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3582
3583 return;
3584 }
3585
3586 static void
sk_stop(struct sk_if_softc * sc_if)3587 sk_stop(struct sk_if_softc *sc_if)
3588 {
3589 int i;
3590 struct sk_softc *sc;
3591 struct sk_txdesc *txd;
3592 struct sk_rxdesc *rxd;
3593 struct sk_rxdesc *jrxd;
3594 if_t ifp;
3595 u_int32_t val;
3596
3597 SK_IF_LOCK_ASSERT(sc_if);
3598 sc = sc_if->sk_softc;
3599 ifp = sc_if->sk_ifp;
3600
3601 callout_stop(&sc_if->sk_tick_ch);
3602 callout_stop(&sc_if->sk_watchdog_ch);
3603
3604 /* stop Tx descriptor polling timer */
3605 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3606 /* stop transfer of Tx descriptors */
3607 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3608 for (i = 0; i < SK_TIMEOUT; i++) {
3609 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3610 if ((val & SK_TXBMU_TX_STOP) == 0)
3611 break;
3612 DELAY(1);
3613 }
3614 if (i == SK_TIMEOUT)
3615 device_printf(sc_if->sk_if_dev,
3616 "can not stop transfer of Tx descriptor\n");
3617 /* stop transfer of Rx descriptors */
3618 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3619 for (i = 0; i < SK_TIMEOUT; i++) {
3620 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3621 if ((val & SK_RXBMU_RX_STOP) == 0)
3622 break;
3623 DELAY(1);
3624 }
3625 if (i == SK_TIMEOUT)
3626 device_printf(sc_if->sk_if_dev,
3627 "can not stop transfer of Rx descriptor\n");
3628
3629 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3630 /* Put PHY back into reset. */
3631 val = sk_win_read_4(sc, SK_GPIO);
3632 if (sc_if->sk_port == SK_PORT_A) {
3633 val |= SK_GPIO_DIR0;
3634 val &= ~SK_GPIO_DAT0;
3635 } else {
3636 val |= SK_GPIO_DIR2;
3637 val &= ~SK_GPIO_DAT2;
3638 }
3639 sk_win_write_4(sc, SK_GPIO, val);
3640 }
3641
3642 /* Turn off various components of this interface. */
3643 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3644 switch (sc->sk_type) {
3645 case SK_GENESIS:
3646 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3647 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3648 break;
3649 case SK_YUKON:
3650 case SK_YUKON_LITE:
3651 case SK_YUKON_LP:
3652 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3653 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3654 break;
3655 }
3656 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3657 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3658 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3659 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3660 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3661 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3662 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3663 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3664 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3665
3666 /* Disable interrupts */
3667 if (sc_if->sk_port == SK_PORT_A)
3668 sc->sk_intrmask &= ~SK_INTRS1;
3669 else
3670 sc->sk_intrmask &= ~SK_INTRS2;
3671 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3672
3673 SK_XM_READ_2(sc_if, XM_ISR);
3674 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3675
3676 /* Free RX and TX mbufs still in the queues. */
3677 for (i = 0; i < SK_RX_RING_CNT; i++) {
3678 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3679 if (rxd->rx_m != NULL) {
3680 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3681 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3682 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3683 rxd->rx_dmamap);
3684 m_freem(rxd->rx_m);
3685 rxd->rx_m = NULL;
3686 }
3687 }
3688 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3689 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3690 if (jrxd->rx_m != NULL) {
3691 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3692 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3693 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3694 jrxd->rx_dmamap);
3695 m_freem(jrxd->rx_m);
3696 jrxd->rx_m = NULL;
3697 }
3698 }
3699 for (i = 0; i < SK_TX_RING_CNT; i++) {
3700 txd = &sc_if->sk_cdata.sk_txdesc[i];
3701 if (txd->tx_m != NULL) {
3702 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3703 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3704 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3705 txd->tx_dmamap);
3706 m_freem(txd->tx_m);
3707 txd->tx_m = NULL;
3708 }
3709 }
3710
3711 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE));
3712
3713 return;
3714 }
3715
3716 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3717 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3718 {
3719 int error, value;
3720
3721 if (!arg1)
3722 return (EINVAL);
3723 value = *(int *)arg1;
3724 error = sysctl_handle_int(oidp, &value, 0, req);
3725 if (error || !req->newptr)
3726 return (error);
3727 if (value < low || value > high)
3728 return (EINVAL);
3729 *(int *)arg1 = value;
3730 return (0);
3731 }
3732
3733 static int
sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)3734 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3735 {
3736 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3737 }
3738