1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
31 */
32
33 #include <sys/cdefs.h>
34 #include "efx.h"
35 #include "efx_impl.h"
36
37 #if EFSYS_OPT_SIENA
38
39 void
siena_sram_init(__in efx_nic_t * enp)40 siena_sram_init(
41 __in efx_nic_t *enp)
42 {
43 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
44 efx_oword_t oword;
45 uint32_t rx_base, tx_base;
46
47 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
48 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
49
50 rx_base = encp->enc_buftbl_limit;
51 tx_base = rx_base + (encp->enc_rxq_limit *
52 EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
53
54 /* Initialize the transmit descriptor cache */
55 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
56 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
57
58 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
59 EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
60
61 /* Initialize the receive descriptor cache */
62 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
63 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
64
65 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
66 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
67
68 /* Set receive descriptor pre-fetch low water mark */
69 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
70 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
71
72 /* Set the event queue to use for SRAM updates */
73 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
74 EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
75 }
76
77 #if EFSYS_OPT_DIAG
78
79 __checkReturn efx_rc_t
siena_sram_test(__in efx_nic_t * enp,__in efx_sram_pattern_fn_t func)80 siena_sram_test(
81 __in efx_nic_t *enp,
82 __in efx_sram_pattern_fn_t func)
83 {
84 efx_oword_t oword;
85 efx_qword_t qword;
86 efx_qword_t verify;
87 size_t rows;
88 unsigned int wptr;
89 unsigned int rptr;
90 efx_rc_t rc;
91
92 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
93
94 /* Reconfigure into HALF buffer table mode */
95 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
96 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
97
98 /*
99 * Move the descriptor caches up to the top of SRAM, and test
100 * all of SRAM below them. We only miss out one row here.
101 */
102 rows = SIENA_SRAM_ROWS - 1;
103 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
104 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
105
106 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
107 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
108
109 /*
110 * Write the pattern through BUF_HALF_TBL. Write
111 * in 64 entry batches, waiting 1us in between each batch
112 * to guarantee not to overflow the SRAM fifo
113 */
114 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
115 func(wptr, B_FALSE, &qword);
116 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
117
118 if ((wptr - rptr) < 64 && wptr < rows - 1)
119 continue;
120
121 EFSYS_SPIN(1);
122
123 for (; rptr <= wptr; ++rptr) {
124 func(rptr, B_FALSE, &qword);
125 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
126 &verify);
127
128 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
129 rc = EFAULT;
130 goto fail1;
131 }
132 }
133 }
134
135 /* And do the same negated */
136 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
137 func(wptr, B_TRUE, &qword);
138 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
139
140 if ((wptr - rptr) < 64 && wptr < rows - 1)
141 continue;
142
143 EFSYS_SPIN(1);
144
145 for (; rptr <= wptr; ++rptr) {
146 func(rptr, B_TRUE, &qword);
147 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
148 &verify);
149
150 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
151 rc = EFAULT;
152 goto fail2;
153 }
154 }
155 }
156
157 /* Restore back to FULL buffer table mode */
158 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
159 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
160
161 /*
162 * We don't need to reconfigure SRAM again because the API
163 * requires efx_nic_fini() to be called after an sram test.
164 */
165 return (0);
166
167 fail2:
168 EFSYS_PROBE(fail2);
169 fail1:
170 EFSYS_PROBE1(fail1, efx_rc_t, rc);
171
172 /* Restore back to FULL buffer table mode */
173 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
174 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
175
176 return (rc);
177 }
178
179 #endif /* EFSYS_OPT_DIAG */
180
181 #endif /* EFSYS_OPT_SIENA */
182