1 /* 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #ifndef _SYS_SIENA_FLASH_H 32 #define _SYS_SIENA_FLASH_H 33 34 #pragma pack(1) 35 36 /* Fixed locations near the start of flash (which may be in the internal PHY 37 * firmware header) point to the boot header. 38 * 39 * - parsed by MC boot ROM and firmware 40 * - reserved (but not parsed) by PHY firmware 41 * - opaque to driver 42 */ 43 44 #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20) 45 46 #define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */ 47 #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */ 48 49 #define SIENA_MC_BOOT_HDR_LEN (0x200) 50 51 #define SIENA_MC_BOOT_MAGIC (0x51E4A001) 52 #define SIENA_MC_BOOT_VERSION (1) 53 54 55 /*Structures supporting an arbitrary number of binary blobs in the flash image 56 intended to house code and tables for the satellite cpus*/ 57 /*thanks to random.org for:*/ 58 #define BLOBS_HEADER_MAGIC (0xBDA3BBD4) 59 #define BLOB_HEADER_MAGIC (0xA1478A91) 60 61 typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */ 62 efx_dword_t magic; 63 efx_dword_t no_of_blobs; 64 } blobs_hdr_t; 65 66 typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ 67 efx_dword_t magic; 68 efx_dword_t cpu_type; 69 efx_dword_t build_variant; 70 efx_dword_t offset; 71 efx_dword_t length; 72 efx_dword_t checksum; 73 } blob_hdr_t; 74 75 #define BLOB_CPU_TYPE_TXDI_TEXT (0) 76 #define BLOB_CPU_TYPE_RXDI_TEXT (1) 77 #define BLOB_CPU_TYPE_TXDP_TEXT (2) 78 #define BLOB_CPU_TYPE_RXDP_TEXT (3) 79 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4) 80 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5) 81 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6) 82 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7) 83 #define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8) 84 #define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9) 85 #define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10) 86 #define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11) 87 #define BLOB_CPU_TYPE_RXDI_VTBL0 (12) 88 #define BLOB_CPU_TYPE_TXDI_VTBL0 (13) 89 #define BLOB_CPU_TYPE_RXDI_VTBL1 (14) 90 #define BLOB_CPU_TYPE_TXDI_VTBL1 (15) 91 #define BLOB_CPU_TYPE_DUMPSPEC (32) 92 #define BLOB_CPU_TYPE_MC_XIP (33) 93 94 #define BLOB_CPU_TYPE_INVALID (31) 95 96 /* 97 * The upper four bits of the CPU type field specify the compression 98 * algorithm used for this blob. 99 */ 100 #define BLOB_COMPRESSION_MASK (0xf0000000) 101 #define BLOB_CPU_TYPE_MASK (0x0fffffff) 102 103 #define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */ 104 #define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */ 105 106 typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ 107 efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ 108 efx_word_t hdr_version; /* this structure definition is version 1 */ 109 efx_byte_t board_type; 110 efx_byte_t firmware_version_a; 111 efx_byte_t firmware_version_b; 112 efx_byte_t firmware_version_c; 113 efx_word_t checksum; /* of whole header area + firmware image */ 114 efx_word_t firmware_version_d; 115 efx_byte_t mcfw_subtype; 116 efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */ 117 efx_dword_t firmware_text_offset; /* offset to firmware .text */ 118 efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ 119 efx_dword_t firmware_data_offset; /* offset to firmware .data */ 120 efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ 121 efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ 122 efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ 123 efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */ 124 efx_dword_t reserved_c[7]; /* (set to 0) */ 125 } siena_mc_boot_hdr_t; 126 127 #define SIENA_MC_BOOT_HDR_PADDING \ 128 (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t)) 129 130 #define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555) 131 #define SIENA_MC_STATIC_CONFIG_VERSION (0) 132 133 typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 134 efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */ 135 efx_word_t length; /* of header area (i.e. not including VPD) */ 136 efx_byte_t version; 137 efx_byte_t csum; /* over header area (i.e. not including VPD) */ 138 efx_dword_t static_vpd_offset; 139 efx_dword_t static_vpd_length; 140 efx_dword_t capabilities; 141 efx_byte_t mac_addr_base[6]; 142 efx_byte_t green_mode_cal; /* Green mode calibration result */ 143 efx_byte_t green_mode_valid; /* Whether cal holds a valid value */ 144 efx_word_t mac_addr_count; 145 efx_word_t mac_addr_stride; 146 efx_word_t calibrated_vref; /* Vref as measured during production */ 147 efx_word_t adc_vref; /* Vref as read by ADC */ 148 efx_dword_t reserved2[1]; /* (write as zero) */ 149 efx_dword_t num_dbi_items; 150 struct { 151 efx_word_t addr; 152 efx_word_t byte_enables; 153 efx_dword_t value; 154 } dbi[]; 155 } siena_mc_static_config_hdr_t; 156 157 #define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD) 158 #define SIENA_MC_DYNAMIC_CONFIG_VERSION (0) 159 160 typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */ 161 efx_dword_t fw_subtype; 162 efx_word_t version_w; 163 efx_word_t version_x; 164 efx_word_t version_y; 165 efx_word_t version_z; 166 } siena_mc_fw_version_t; 167 168 typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 169 efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */ 170 efx_word_t length; /* of header area (i.e. not including VPD) */ 171 efx_byte_t version; 172 efx_byte_t csum; /* over header area (i.e. not including VPD) */ 173 efx_dword_t dynamic_vpd_offset; 174 efx_dword_t dynamic_vpd_length; 175 efx_dword_t num_fw_version_items; 176 siena_mc_fw_version_t fw_version[]; 177 } siena_mc_dynamic_config_hdr_t; 178 179 #define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */ 180 181 #define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */ 182 #define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */ 183 184 typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */ 185 efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */ 186 union { 187 struct { 188 efx_dword_t len1; /* length of first image */ 189 efx_dword_t len2; /* length of second image */ 190 efx_dword_t off1; /* offset of first byte to edit to combine images */ 191 efx_dword_t off2; /* offset of second byte to edit to combine images */ 192 efx_word_t infoblk0_off;/* infoblk offset */ 193 efx_word_t infoblk1_off;/* infoblk offset */ 194 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 195 efx_byte_t reserved[7];/* (set to 0) */ 196 } v1; 197 struct { 198 efx_dword_t len1; /* length of first image */ 199 efx_dword_t len2; /* length of second image */ 200 efx_dword_t off1; /* offset of first byte to edit to combine images */ 201 efx_dword_t off2; /* offset of second byte to edit to combine images */ 202 efx_word_t infoblk_off;/* infoblk start offset */ 203 efx_word_t infoblk_count;/* infoblk count */ 204 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 205 efx_byte_t reserved[7];/* (set to 0) */ 206 } v2; 207 } data; 208 } siena_mc_combo_rom_hdr_t; 209 210 #pragma pack() 211 212 #endif /* _SYS_SIENA_FLASH_H */ 213