1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw89_ 7 #endif 8 9 #include <linux/ip.h> 10 #include <linux/udp.h> 11 12 #include "cam.h" 13 #include "chan.h" 14 #include "coex.h" 15 #include "core.h" 16 #include "efuse.h" 17 #include "fw.h" 18 #include "mac.h" 19 #include "phy.h" 20 #include "ps.h" 21 #include "reg.h" 22 #include "sar.h" 23 #include "ser.h" 24 #include "txrx.h" 25 #include "util.h" 26 #include "wow.h" 27 28 static bool rtw89_disable_ps_mode; 29 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 30 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 31 32 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 33 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 34 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 36 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 37 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 38 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 39 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 40 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 41 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 42 43 static struct ieee80211_channel rtw89_channels_2ghz[] = { 44 RTW89_DEF_CHAN_2G(2412, 1), 45 RTW89_DEF_CHAN_2G(2417, 2), 46 RTW89_DEF_CHAN_2G(2422, 3), 47 RTW89_DEF_CHAN_2G(2427, 4), 48 RTW89_DEF_CHAN_2G(2432, 5), 49 RTW89_DEF_CHAN_2G(2437, 6), 50 RTW89_DEF_CHAN_2G(2442, 7), 51 RTW89_DEF_CHAN_2G(2447, 8), 52 RTW89_DEF_CHAN_2G(2452, 9), 53 RTW89_DEF_CHAN_2G(2457, 10), 54 RTW89_DEF_CHAN_2G(2462, 11), 55 RTW89_DEF_CHAN_2G(2467, 12), 56 RTW89_DEF_CHAN_2G(2472, 13), 57 RTW89_DEF_CHAN_2G(2484, 14), 58 }; 59 60 static struct ieee80211_channel rtw89_channels_5ghz[] = { 61 RTW89_DEF_CHAN_5G(5180, 36), 62 RTW89_DEF_CHAN_5G(5200, 40), 63 RTW89_DEF_CHAN_5G(5220, 44), 64 RTW89_DEF_CHAN_5G(5240, 48), 65 RTW89_DEF_CHAN_5G(5260, 52), 66 RTW89_DEF_CHAN_5G(5280, 56), 67 RTW89_DEF_CHAN_5G(5300, 60), 68 RTW89_DEF_CHAN_5G(5320, 64), 69 RTW89_DEF_CHAN_5G(5500, 100), 70 RTW89_DEF_CHAN_5G(5520, 104), 71 RTW89_DEF_CHAN_5G(5540, 108), 72 RTW89_DEF_CHAN_5G(5560, 112), 73 RTW89_DEF_CHAN_5G(5580, 116), 74 RTW89_DEF_CHAN_5G(5600, 120), 75 RTW89_DEF_CHAN_5G(5620, 124), 76 RTW89_DEF_CHAN_5G(5640, 128), 77 RTW89_DEF_CHAN_5G(5660, 132), 78 RTW89_DEF_CHAN_5G(5680, 136), 79 RTW89_DEF_CHAN_5G(5700, 140), 80 RTW89_DEF_CHAN_5G(5720, 144), 81 RTW89_DEF_CHAN_5G(5745, 149), 82 RTW89_DEF_CHAN_5G(5765, 153), 83 RTW89_DEF_CHAN_5G(5785, 157), 84 RTW89_DEF_CHAN_5G(5805, 161), 85 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 86 RTW89_DEF_CHAN_5G(5845, 169), 87 RTW89_DEF_CHAN_5G(5865, 173), 88 RTW89_DEF_CHAN_5G(5885, 177), 89 }; 90 91 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 92 ARRAY_SIZE(rtw89_channels_5ghz)); 93 94 static struct ieee80211_channel rtw89_channels_6ghz[] = { 95 RTW89_DEF_CHAN_6G(5955, 1), 96 RTW89_DEF_CHAN_6G(5975, 5), 97 RTW89_DEF_CHAN_6G(5995, 9), 98 RTW89_DEF_CHAN_6G(6015, 13), 99 RTW89_DEF_CHAN_6G(6035, 17), 100 RTW89_DEF_CHAN_6G(6055, 21), 101 RTW89_DEF_CHAN_6G(6075, 25), 102 RTW89_DEF_CHAN_6G(6095, 29), 103 RTW89_DEF_CHAN_6G(6115, 33), 104 RTW89_DEF_CHAN_6G(6135, 37), 105 RTW89_DEF_CHAN_6G(6155, 41), 106 RTW89_DEF_CHAN_6G(6175, 45), 107 RTW89_DEF_CHAN_6G(6195, 49), 108 RTW89_DEF_CHAN_6G(6215, 53), 109 RTW89_DEF_CHAN_6G(6235, 57), 110 RTW89_DEF_CHAN_6G(6255, 61), 111 RTW89_DEF_CHAN_6G(6275, 65), 112 RTW89_DEF_CHAN_6G(6295, 69), 113 RTW89_DEF_CHAN_6G(6315, 73), 114 RTW89_DEF_CHAN_6G(6335, 77), 115 RTW89_DEF_CHAN_6G(6355, 81), 116 RTW89_DEF_CHAN_6G(6375, 85), 117 RTW89_DEF_CHAN_6G(6395, 89), 118 RTW89_DEF_CHAN_6G(6415, 93), 119 RTW89_DEF_CHAN_6G(6435, 97), 120 RTW89_DEF_CHAN_6G(6455, 101), 121 RTW89_DEF_CHAN_6G(6475, 105), 122 RTW89_DEF_CHAN_6G(6495, 109), 123 RTW89_DEF_CHAN_6G(6515, 113), 124 RTW89_DEF_CHAN_6G(6535, 117), 125 RTW89_DEF_CHAN_6G(6555, 121), 126 RTW89_DEF_CHAN_6G(6575, 125), 127 RTW89_DEF_CHAN_6G(6595, 129), 128 RTW89_DEF_CHAN_6G(6615, 133), 129 RTW89_DEF_CHAN_6G(6635, 137), 130 RTW89_DEF_CHAN_6G(6655, 141), 131 RTW89_DEF_CHAN_6G(6675, 145), 132 RTW89_DEF_CHAN_6G(6695, 149), 133 RTW89_DEF_CHAN_6G(6715, 153), 134 RTW89_DEF_CHAN_6G(6735, 157), 135 RTW89_DEF_CHAN_6G(6755, 161), 136 RTW89_DEF_CHAN_6G(6775, 165), 137 RTW89_DEF_CHAN_6G(6795, 169), 138 RTW89_DEF_CHAN_6G(6815, 173), 139 RTW89_DEF_CHAN_6G(6835, 177), 140 RTW89_DEF_CHAN_6G(6855, 181), 141 RTW89_DEF_CHAN_6G(6875, 185), 142 RTW89_DEF_CHAN_6G(6895, 189), 143 RTW89_DEF_CHAN_6G(6915, 193), 144 RTW89_DEF_CHAN_6G(6935, 197), 145 RTW89_DEF_CHAN_6G(6955, 201), 146 RTW89_DEF_CHAN_6G(6975, 205), 147 RTW89_DEF_CHAN_6G(6995, 209), 148 RTW89_DEF_CHAN_6G(7015, 213), 149 RTW89_DEF_CHAN_6G(7035, 217), 150 RTW89_DEF_CHAN_6G(7055, 221), 151 RTW89_DEF_CHAN_6G(7075, 225), 152 RTW89_DEF_CHAN_6G(7095, 229), 153 RTW89_DEF_CHAN_6G(7115, 233), 154 }; 155 156 static struct ieee80211_rate rtw89_bitrates[] = { 157 { .bitrate = 10, .hw_value = 0x00, }, 158 { .bitrate = 20, .hw_value = 0x01, }, 159 { .bitrate = 55, .hw_value = 0x02, }, 160 { .bitrate = 110, .hw_value = 0x03, }, 161 { .bitrate = 60, .hw_value = 0x04, }, 162 { .bitrate = 90, .hw_value = 0x05, }, 163 { .bitrate = 120, .hw_value = 0x06, }, 164 { .bitrate = 180, .hw_value = 0x07, }, 165 { .bitrate = 240, .hw_value = 0x08, }, 166 { .bitrate = 360, .hw_value = 0x09, }, 167 { .bitrate = 480, .hw_value = 0x0a, }, 168 { .bitrate = 540, .hw_value = 0x0b, }, 169 }; 170 171 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 172 { 173 .max = 1, 174 .types = BIT(NL80211_IFTYPE_STATION), 175 }, 176 { 177 .max = 1, 178 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 179 BIT(NL80211_IFTYPE_P2P_GO) | 180 BIT(NL80211_IFTYPE_AP), 181 }, 182 }; 183 184 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 185 { 186 .max = 1, 187 .types = BIT(NL80211_IFTYPE_STATION), 188 }, 189 { 190 .max = 1, 191 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 192 BIT(NL80211_IFTYPE_P2P_GO), 193 }, 194 }; 195 196 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 197 { 198 .limits = rtw89_iface_limits, 199 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 200 .max_interfaces = 2, 201 .num_different_channels = 1, 202 }, 203 { 204 .limits = rtw89_iface_limits_mcc, 205 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 206 .max_interfaces = 2, 207 .num_different_channels = 2, 208 }, 209 }; 210 211 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 212 { 213 struct ieee80211_rate rate; 214 215 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 216 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 217 return false; 218 } 219 220 rate = rtw89_bitrates[rpt_rate]; 221 *bitrate = rate.bitrate; 222 223 return true; 224 } 225 226 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 227 .band = NL80211_BAND_2GHZ, 228 .channels = rtw89_channels_2ghz, 229 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 230 .bitrates = rtw89_bitrates, 231 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 232 .ht_cap = {0}, 233 .vht_cap = {0}, 234 }; 235 236 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 237 .band = NL80211_BAND_5GHZ, 238 .channels = rtw89_channels_5ghz, 239 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 240 241 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 242 .bitrates = rtw89_bitrates + 4, 243 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 244 .ht_cap = {0}, 245 .vht_cap = {0}, 246 }; 247 248 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 249 .band = NL80211_BAND_6GHZ, 250 .channels = rtw89_channels_6ghz, 251 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 252 253 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 254 .bitrates = rtw89_bitrates + 4, 255 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 256 }; 257 258 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 259 struct rtw89_traffic_stats *stats, 260 struct sk_buff *skb, bool tx) 261 { 262 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 263 264 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 265 rtw89_wow_parse_akm(rtwdev, skb); 266 267 if (!ieee80211_is_data(hdr->frame_control)) 268 return; 269 270 if (is_broadcast_ether_addr(hdr->addr1) || 271 is_multicast_ether_addr(hdr->addr1)) 272 return; 273 274 if (tx) { 275 stats->tx_cnt++; 276 stats->tx_unicast += skb->len; 277 } else { 278 stats->rx_cnt++; 279 stats->rx_unicast += skb->len; 280 } 281 } 282 283 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 284 { 285 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 286 NL80211_CHAN_NO_HT); 287 } 288 289 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 290 struct rtw89_chan *chan) 291 { 292 struct ieee80211_channel *channel = chandef->chan; 293 enum nl80211_chan_width width = chandef->width; 294 u32 primary_freq, center_freq; 295 u8 center_chan; 296 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 297 u32 offset; 298 u8 band; 299 300 center_chan = channel->hw_value; 301 primary_freq = channel->center_freq; 302 center_freq = chandef->center_freq1; 303 304 switch (width) { 305 case NL80211_CHAN_WIDTH_20_NOHT: 306 case NL80211_CHAN_WIDTH_20: 307 bandwidth = RTW89_CHANNEL_WIDTH_20; 308 break; 309 case NL80211_CHAN_WIDTH_40: 310 bandwidth = RTW89_CHANNEL_WIDTH_40; 311 if (primary_freq > center_freq) { 312 center_chan -= 2; 313 } else { 314 center_chan += 2; 315 } 316 break; 317 case NL80211_CHAN_WIDTH_80: 318 case NL80211_CHAN_WIDTH_160: 319 bandwidth = nl_to_rtw89_bandwidth(width); 320 if (primary_freq > center_freq) { 321 offset = (primary_freq - center_freq - 10) / 20; 322 center_chan -= 2 + offset * 4; 323 } else { 324 offset = (center_freq - primary_freq - 10) / 20; 325 center_chan += 2 + offset * 4; 326 } 327 break; 328 default: 329 center_chan = 0; 330 break; 331 } 332 333 switch (channel->band) { 334 default: 335 case NL80211_BAND_2GHZ: 336 band = RTW89_BAND_2G; 337 break; 338 case NL80211_BAND_5GHZ: 339 band = RTW89_BAND_5G; 340 break; 341 case NL80211_BAND_6GHZ: 342 band = RTW89_BAND_6G; 343 break; 344 } 345 346 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 347 } 348 349 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 350 { 351 struct rtw89_hal *hal = &rtwdev->hal; 352 const struct rtw89_chip_info *chip = rtwdev->chip; 353 const struct rtw89_chan *chan; 354 enum rtw89_sub_entity_idx sub_entity_idx; 355 enum rtw89_sub_entity_idx roc_idx; 356 enum rtw89_phy_idx phy_idx; 357 enum rtw89_entity_mode mode; 358 bool entity_active; 359 360 entity_active = rtw89_get_entity_state(rtwdev); 361 if (!entity_active) 362 return; 363 364 mode = rtw89_get_entity_mode(rtwdev); 365 switch (mode) { 366 case RTW89_ENTITY_MODE_SCC: 367 case RTW89_ENTITY_MODE_MCC: 368 sub_entity_idx = RTW89_SUB_ENTITY_0; 369 break; 370 case RTW89_ENTITY_MODE_MCC_PREPARE: 371 sub_entity_idx = RTW89_SUB_ENTITY_1; 372 break; 373 default: 374 WARN(1, "Invalid ent mode: %d\n", mode); 375 return; 376 } 377 378 roc_idx = atomic_read(&hal->roc_entity_idx); 379 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 380 sub_entity_idx = roc_idx; 381 382 phy_idx = RTW89_PHY_0; 383 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 384 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 385 } 386 387 int rtw89_set_channel(struct rtw89_dev *rtwdev) 388 { 389 struct rtw89_hal *hal = &rtwdev->hal; 390 const struct rtw89_chip_info *chip = rtwdev->chip; 391 const struct rtw89_chan_rcd *chan_rcd; 392 const struct rtw89_chan *chan; 393 enum rtw89_sub_entity_idx sub_entity_idx; 394 enum rtw89_sub_entity_idx roc_idx; 395 enum rtw89_mac_idx mac_idx; 396 enum rtw89_phy_idx phy_idx; 397 struct rtw89_channel_help_params bak; 398 enum rtw89_entity_mode mode; 399 bool entity_active; 400 401 entity_active = rtw89_get_entity_state(rtwdev); 402 403 mode = rtw89_entity_recalc(rtwdev); 404 switch (mode) { 405 case RTW89_ENTITY_MODE_SCC: 406 case RTW89_ENTITY_MODE_MCC: 407 sub_entity_idx = RTW89_SUB_ENTITY_0; 408 break; 409 case RTW89_ENTITY_MODE_MCC_PREPARE: 410 sub_entity_idx = RTW89_SUB_ENTITY_1; 411 break; 412 default: 413 WARN(1, "Invalid ent mode: %d\n", mode); 414 return -EINVAL; 415 } 416 417 roc_idx = atomic_read(&hal->roc_entity_idx); 418 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 419 sub_entity_idx = roc_idx; 420 421 mac_idx = RTW89_MAC_0; 422 phy_idx = RTW89_PHY_0; 423 424 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 425 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 426 427 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 428 429 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 430 431 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 432 433 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 434 435 if (!entity_active || chan_rcd->band_changed) { 436 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 437 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 438 } 439 440 rtw89_set_entity_state(rtwdev, true); 441 return 0; 442 } 443 444 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 445 struct rtw89_chan *chan) 446 { 447 const struct cfg80211_chan_def *chandef; 448 449 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 450 rtw89_get_channel_params(chandef, chan); 451 } 452 453 static enum rtw89_core_tx_type 454 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 455 struct sk_buff *skb) 456 { 457 struct ieee80211_hdr *hdr = (void *)skb->data; 458 __le16 fc = hdr->frame_control; 459 460 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 461 return RTW89_CORE_TX_TYPE_MGMT; 462 463 return RTW89_CORE_TX_TYPE_DATA; 464 } 465 466 static void 467 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 468 struct rtw89_core_tx_request *tx_req, 469 enum btc_pkt_type pkt_type) 470 { 471 struct ieee80211_sta *sta = tx_req->sta; 472 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 473 struct sk_buff *skb = tx_req->skb; 474 struct rtw89_sta *rtwsta; 475 u8 ampdu_num; 476 u8 tid; 477 478 if (pkt_type == PACKET_EAPOL) { 479 desc_info->bk = true; 480 return; 481 } 482 483 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 484 return; 485 486 if (!sta) { 487 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 488 return; 489 } 490 491 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 492 rtwsta = (struct rtw89_sta *)sta->drv_priv; 493 494 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 495 rtwsta->ampdu_params[tid].agg_num : 496 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 497 498 desc_info->agg_en = true; 499 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 500 desc_info->ampdu_num = ampdu_num; 501 } 502 503 static void 504 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 505 struct rtw89_core_tx_request *tx_req) 506 { 507 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 508 const struct rtw89_chip_info *chip = rtwdev->chip; 509 const struct rtw89_sec_cam_entry *sec_cam; 510 struct ieee80211_tx_info *info; 511 struct ieee80211_key_conf *key; 512 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 513 struct sk_buff *skb = tx_req->skb; 514 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 515 u8 sec_cam_idx; 516 u64 pn64; 517 518 info = IEEE80211_SKB_CB(skb); 519 key = info->control.hw_key; 520 sec_cam_idx = key->hw_key_idx; 521 sec_cam = cam_info->sec_entries[sec_cam_idx]; 522 if (!sec_cam) { 523 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 524 return; 525 } 526 527 switch (key->cipher) { 528 case WLAN_CIPHER_SUITE_WEP40: 529 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 530 break; 531 case WLAN_CIPHER_SUITE_WEP104: 532 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 533 break; 534 case WLAN_CIPHER_SUITE_TKIP: 535 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 536 break; 537 case WLAN_CIPHER_SUITE_CCMP: 538 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 539 break; 540 case WLAN_CIPHER_SUITE_CCMP_256: 541 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 542 break; 543 case WLAN_CIPHER_SUITE_GCMP: 544 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 545 break; 546 case WLAN_CIPHER_SUITE_GCMP_256: 547 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 548 break; 549 default: 550 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 551 return; 552 } 553 554 desc_info->sec_en = true; 555 desc_info->sec_keyid = key->keyidx; 556 desc_info->sec_type = sec_type; 557 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 558 559 if (!chip->hw_sec_hdr) 560 return; 561 562 pn64 = atomic64_inc_return(&key->tx_pn); 563 desc_info->sec_seq[0] = pn64; 564 desc_info->sec_seq[1] = pn64 >> 8; 565 desc_info->sec_seq[2] = pn64 >> 16; 566 desc_info->sec_seq[3] = pn64 >> 24; 567 desc_info->sec_seq[4] = pn64 >> 32; 568 desc_info->sec_seq[5] = pn64 >> 40; 569 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 570 } 571 572 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 573 struct rtw89_core_tx_request *tx_req, 574 const struct rtw89_chan *chan) 575 { 576 struct sk_buff *skb = tx_req->skb; 577 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 578 struct ieee80211_vif *vif = tx_info->control.vif; 579 u16 lowest_rate; 580 581 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 582 (vif && vif->p2p)) 583 lowest_rate = RTW89_HW_RATE_OFDM6; 584 else if (chan->band_type == RTW89_BAND_2G) 585 lowest_rate = RTW89_HW_RATE_CCK1; 586 else 587 lowest_rate = RTW89_HW_RATE_OFDM6; 588 589 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 590 return lowest_rate; 591 592 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 593 } 594 595 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 596 struct rtw89_core_tx_request *tx_req) 597 { 598 struct ieee80211_vif *vif = tx_req->vif; 599 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 600 struct ieee80211_sta *sta = tx_req->sta; 601 struct rtw89_sta *rtwsta; 602 603 if (!sta) 604 return rtwvif->mac_id; 605 606 rtwsta = (struct rtw89_sta *)sta->drv_priv; 607 return rtwsta->mac_id; 608 } 609 610 static void 611 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 612 struct rtw89_core_tx_request *tx_req) 613 { 614 struct ieee80211_vif *vif = tx_req->vif; 615 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 616 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 617 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 618 rtwvif->sub_entity_idx); 619 u8 qsel, ch_dma; 620 621 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 622 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 623 624 desc_info->qsel = qsel; 625 desc_info->ch_dma = ch_dma; 626 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 627 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 628 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 629 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 630 631 /* fixed data rate for mgmt frames */ 632 desc_info->en_wd_info = true; 633 desc_info->use_rate = true; 634 desc_info->dis_data_fb = true; 635 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 636 637 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 638 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 639 desc_info->data_rate, chan->channel, chan->band_type, 640 chan->band_width); 641 } 642 643 static void 644 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 645 struct rtw89_core_tx_request *tx_req) 646 { 647 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 648 649 desc_info->is_bmc = false; 650 desc_info->wd_page = false; 651 desc_info->ch_dma = RTW89_DMA_H2C; 652 } 653 654 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 655 const struct rtw89_chan *chan) 656 { 657 static const u8 rtw89_bandwidth_to_om[] = { 658 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 659 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 660 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 661 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 662 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 663 }; 664 const struct rtw89_chip_info *chip = rtwdev->chip; 665 struct rtw89_hal *hal = &rtwdev->hal; 666 u8 om_bandwidth; 667 668 if (!chip->dis_2g_40m_ul_ofdma || 669 chan->band_type != RTW89_BAND_2G || 670 chan->band_width != RTW89_CHANNEL_WIDTH_40) 671 return; 672 673 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 674 rtw89_bandwidth_to_om[chan->band_width] : 0; 675 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 676 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 677 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 678 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 679 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 680 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 681 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 682 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 683 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 684 } 685 686 static bool 687 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 688 struct rtw89_core_tx_request *tx_req, 689 enum btc_pkt_type pkt_type) 690 { 691 struct ieee80211_sta *sta = tx_req->sta; 692 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 693 struct sk_buff *skb = tx_req->skb; 694 struct ieee80211_hdr *hdr = (void *)skb->data; 695 __le16 fc = hdr->frame_control; 696 697 /* AP IOT issue with EAPoL, ARP and DHCP */ 698 if (pkt_type < PACKET_MAX) 699 return false; 700 701 if (!sta || !sta->deflink.he_cap.has_he) 702 return false; 703 704 if (!ieee80211_is_data_qos(fc)) 705 return false; 706 707 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 708 return false; 709 710 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 711 return false; 712 713 return true; 714 } 715 716 static void 717 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 718 struct rtw89_core_tx_request *tx_req) 719 { 720 struct ieee80211_sta *sta = tx_req->sta; 721 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 722 struct sk_buff *skb = tx_req->skb; 723 struct ieee80211_hdr *hdr = (void *)skb->data; 724 __le16 fc = hdr->frame_control; 725 void *data; 726 __le32 *htc; 727 u8 *qc; 728 int hdr_len; 729 730 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 731 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 732 #if defined(__linux__) 733 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 734 #elif defined(__FreeBSD__) 735 memmove(data, (u8 *)data + IEEE80211_HT_CTL_LEN, hdr_len); 736 #endif 737 738 hdr = data; 739 #if defined(__linux__) 740 htc = data + hdr_len; 741 #elif defined(__FreeBSD__) 742 htc = (__le32 *)((u8 *)data + hdr_len); 743 #endif 744 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 745 *htc = rtwsta->htc_template ? rtwsta->htc_template : 746 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 747 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 748 749 #if defined(__linux__) 750 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 751 #elif defined(__FreeBSD__) 752 qc = (u8 *)data + hdr_len - IEEE80211_QOS_CTL_LEN; 753 #endif 754 qc[0] |= IEEE80211_QOS_CTL_EOSP; 755 } 756 757 static void 758 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 759 struct rtw89_core_tx_request *tx_req, 760 enum btc_pkt_type pkt_type) 761 { 762 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 763 struct ieee80211_vif *vif = tx_req->vif; 764 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 765 766 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 767 goto desc_bk; 768 769 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 770 771 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 772 desc_info->a_ctrl_bsr = true; 773 774 desc_bk: 775 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 776 return; 777 778 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 779 desc_info->bk = true; 780 } 781 782 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 783 struct rtw89_core_tx_request *tx_req) 784 { 785 struct ieee80211_vif *vif = tx_req->vif; 786 struct ieee80211_sta *sta = tx_req->sta; 787 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 788 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 789 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 790 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 791 u16 lowest_rate; 792 793 if (rate_pattern->enable) 794 return rate_pattern->rate; 795 796 if (vif->p2p) 797 lowest_rate = RTW89_HW_RATE_OFDM6; 798 else if (chan->band_type == RTW89_BAND_2G) 799 lowest_rate = RTW89_HW_RATE_CCK1; 800 else 801 lowest_rate = RTW89_HW_RATE_OFDM6; 802 803 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 804 return lowest_rate; 805 806 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 807 } 808 809 static void 810 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 811 struct rtw89_core_tx_request *tx_req) 812 { 813 struct ieee80211_vif *vif = tx_req->vif; 814 struct ieee80211_sta *sta = tx_req->sta; 815 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 816 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 817 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 818 struct sk_buff *skb = tx_req->skb; 819 u8 tid, tid_indicate; 820 u8 qsel, ch_dma; 821 822 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 823 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 824 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 825 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 826 827 desc_info->ch_dma = ch_dma; 828 desc_info->tid_indicate = tid_indicate; 829 desc_info->qsel = qsel; 830 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 831 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 832 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 833 desc_info->stbc = rtwsta ? rtwsta->ra.stbc_cap : false; 834 desc_info->ldpc = rtwsta ? rtwsta->ra.ldpc_cap : false; 835 836 /* enable wd_info for AMPDU */ 837 desc_info->en_wd_info = true; 838 839 if (IEEE80211_SKB_CB(skb)->control.hw_key) 840 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 841 842 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 843 } 844 845 static enum btc_pkt_type 846 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 847 struct rtw89_core_tx_request *tx_req) 848 { 849 struct sk_buff *skb = tx_req->skb; 850 struct udphdr *udphdr; 851 852 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 853 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 854 return PACKET_EAPOL; 855 } 856 857 if (skb->protocol == htons(ETH_P_ARP)) { 858 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 859 return PACKET_ARP; 860 } 861 862 if (skb->protocol == htons(ETH_P_IP) && 863 ip_hdr(skb)->protocol == IPPROTO_UDP) { 864 udphdr = udp_hdr(skb); 865 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 866 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 867 skb->len > 282) { 868 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 869 return PACKET_DHCP; 870 } 871 } 872 873 if (skb->protocol == htons(ETH_P_IP) && 874 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 875 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 876 return PACKET_ICMP; 877 } 878 879 return PACKET_MAX; 880 } 881 882 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 883 struct rtw89_tx_desc_info *desc_info, 884 struct sk_buff *skb) 885 { 886 struct ieee80211_hdr *hdr = (void *)skb->data; 887 __le16 fc = hdr->frame_control; 888 889 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 890 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 891 } 892 893 static void 894 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 895 struct rtw89_core_tx_request *tx_req) 896 { 897 const struct rtw89_chip_info *chip = rtwdev->chip; 898 899 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 900 return; 901 902 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 903 return; 904 905 if (chip->chip_id != RTL8852C && 906 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 907 return; 908 909 rtw89_mac_notify_wake(rtwdev); 910 } 911 912 static void 913 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 914 struct rtw89_core_tx_request *tx_req) 915 { 916 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 917 struct sk_buff *skb = tx_req->skb; 918 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 919 struct ieee80211_hdr *hdr = (void *)skb->data; 920 enum rtw89_core_tx_type tx_type; 921 enum btc_pkt_type pkt_type; 922 bool is_bmc; 923 u16 seq; 924 925 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 926 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 927 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 928 tx_req->tx_type = tx_type; 929 } 930 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 931 is_multicast_ether_addr(hdr->addr1)); 932 933 desc_info->seq = seq; 934 desc_info->pkt_size = skb->len; 935 desc_info->is_bmc = is_bmc; 936 desc_info->wd_page = true; 937 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 938 939 switch (tx_req->tx_type) { 940 case RTW89_CORE_TX_TYPE_MGMT: 941 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 942 break; 943 case RTW89_CORE_TX_TYPE_DATA: 944 rtw89_core_tx_update_data_info(rtwdev, tx_req); 945 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 946 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 947 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 948 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 949 break; 950 case RTW89_CORE_TX_TYPE_FWCMD: 951 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 952 break; 953 } 954 } 955 956 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 957 { 958 u8 ch_dma; 959 960 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 961 962 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 963 } 964 965 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 966 int qsel, unsigned int timeout) 967 { 968 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 969 struct rtw89_tx_wait_info *wait; 970 unsigned long time_left; 971 int ret = 0; 972 973 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 974 if (!wait) { 975 rtw89_core_tx_kick_off(rtwdev, qsel); 976 return 0; 977 } 978 979 init_completion(&wait->completion); 980 rcu_assign_pointer(skb_data->wait, wait); 981 982 rtw89_core_tx_kick_off(rtwdev, qsel); 983 time_left = wait_for_completion_timeout(&wait->completion, 984 msecs_to_jiffies(timeout)); 985 if (time_left == 0) 986 ret = -ETIMEDOUT; 987 else if (!wait->tx_done) 988 ret = -EAGAIN; 989 990 rcu_assign_pointer(skb_data->wait, NULL); 991 kfree_rcu(wait, rcu_head); 992 993 return ret; 994 } 995 996 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 997 struct sk_buff *skb, bool fwdl) 998 { 999 struct rtw89_core_tx_request tx_req = {0}; 1000 u32 cnt; 1001 int ret; 1002 1003 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1004 rtw89_debug(rtwdev, RTW89_DBG_FW, 1005 "ignore h2c due to power is off with firmware state=%d\n", 1006 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1007 dev_kfree_skb(skb); 1008 return 0; 1009 } 1010 1011 tx_req.skb = skb; 1012 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1013 if (fwdl) 1014 tx_req.desc_info.fw_dl = true; 1015 1016 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1017 1018 if (!fwdl) 1019 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1020 1021 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1022 if (cnt == 0) { 1023 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1024 return -ENOSPC; 1025 } 1026 1027 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1028 if (ret) { 1029 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1030 return ret; 1031 } 1032 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1033 1034 return 0; 1035 } 1036 1037 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1038 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1039 { 1040 struct rtw89_core_tx_request tx_req = {0}; 1041 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1042 int ret; 1043 1044 tx_req.skb = skb; 1045 tx_req.sta = sta; 1046 tx_req.vif = vif; 1047 1048 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1049 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1050 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1051 rtw89_core_tx_wake(rtwdev, &tx_req); 1052 1053 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1054 if (ret) { 1055 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1056 return ret; 1057 } 1058 1059 if (qsel) 1060 *qsel = tx_req.desc_info.qsel; 1061 1062 return 0; 1063 } 1064 1065 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1066 { 1067 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1068 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1069 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1070 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1071 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1072 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1073 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1074 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1075 1076 return cpu_to_le32(dword); 1077 } 1078 1079 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1080 { 1081 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1082 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1083 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1084 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1085 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1086 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1087 1088 return cpu_to_le32(dword); 1089 } 1090 1091 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1092 { 1093 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1094 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1095 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1096 1097 return cpu_to_le32(dword); 1098 } 1099 1100 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1101 { 1102 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1103 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1104 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1105 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 1110 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1113 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1114 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1115 1116 return cpu_to_le32(dword); 1117 } 1118 1119 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1120 { 1121 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1122 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1123 1124 return cpu_to_le32(dword); 1125 } 1126 1127 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1128 { 1129 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1130 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1131 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1132 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1133 1134 return cpu_to_le32(dword); 1135 } 1136 1137 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1138 { 1139 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1140 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1141 1142 return cpu_to_le32(dword); 1143 } 1144 1145 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1146 { 1147 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1148 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1149 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1150 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1151 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1152 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1153 1154 return cpu_to_le32(dword); 1155 } 1156 1157 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1158 { 1159 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1160 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1161 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1162 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1163 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1164 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1165 1166 return cpu_to_le32(dword); 1167 } 1168 1169 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1170 { 1171 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1172 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1173 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1174 desc_info->data_retry_lowest_rate); 1175 1176 return cpu_to_le32(dword); 1177 } 1178 1179 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1180 { 1181 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1182 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1183 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1184 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1185 1186 return cpu_to_le32(dword); 1187 } 1188 1189 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1190 { 1191 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1192 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1193 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1194 1195 return cpu_to_le32(dword); 1196 } 1197 1198 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1199 { 1200 bool rts_en = !desc_info->is_bmc; 1201 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1202 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1203 1204 return cpu_to_le32(dword); 1205 } 1206 1207 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1208 struct rtw89_tx_desc_info *desc_info, 1209 void *txdesc) 1210 { 1211 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1212 struct rtw89_txwd_info *txwd_info; 1213 1214 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1215 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1216 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1217 1218 if (!desc_info->en_wd_info) 1219 return; 1220 1221 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1222 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1223 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1224 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1225 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1226 1227 } 1228 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1229 1230 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1231 struct rtw89_tx_desc_info *desc_info, 1232 void *txdesc) 1233 { 1234 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1235 struct rtw89_txwd_info *txwd_info; 1236 1237 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1238 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1239 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1240 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1241 if (desc_info->sec_en) { 1242 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1243 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1244 } 1245 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1246 1247 if (!desc_info->en_wd_info) 1248 return; 1249 1250 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1251 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1252 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1253 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1254 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1255 } 1256 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1257 1258 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1259 { 1260 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1261 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1262 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1263 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1264 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1265 1266 return cpu_to_le32(dword); 1267 } 1268 1269 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1270 { 1271 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1272 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1273 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1274 1275 return cpu_to_le32(dword); 1276 } 1277 1278 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1279 { 1280 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1281 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1282 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1283 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1284 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1285 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1286 1287 return cpu_to_le32(dword); 1288 } 1289 1290 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1291 { 1292 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1293 1294 return cpu_to_le32(dword); 1295 } 1296 1297 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1298 { 1299 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1300 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1301 1302 return cpu_to_le32(dword); 1303 } 1304 1305 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1306 { 1307 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1308 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1309 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1310 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1311 1312 return cpu_to_le32(dword); 1313 } 1314 1315 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1316 { 1317 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1318 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1319 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1320 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1321 1322 return cpu_to_le32(dword); 1323 } 1324 1325 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1326 { 1327 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1328 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1329 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1330 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1331 1332 return cpu_to_le32(dword); 1333 } 1334 1335 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1336 { 1337 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1338 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1339 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1340 desc_info->data_retry_lowest_rate); 1341 1342 return cpu_to_le32(dword); 1343 } 1344 1345 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1346 { 1347 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1348 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1349 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1350 1351 return cpu_to_le32(dword); 1352 } 1353 1354 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1355 { 1356 bool rts_en = !desc_info->is_bmc; 1357 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1358 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1359 1360 return cpu_to_le32(dword); 1361 } 1362 1363 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1364 struct rtw89_tx_desc_info *desc_info, 1365 void *txdesc) 1366 { 1367 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1368 struct rtw89_txwd_info_v2 *txwd_info; 1369 1370 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1371 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1372 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1373 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1374 if (desc_info->sec_en) { 1375 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1376 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1377 } 1378 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1379 1380 if (!desc_info->en_wd_info) 1381 return; 1382 1383 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1384 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1385 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1386 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1387 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1388 } 1389 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1390 1391 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1392 { 1393 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1394 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1395 RTW89_CORE_RX_TYPE_FWDL : 1396 RTW89_CORE_RX_TYPE_H2C); 1397 1398 return cpu_to_le32(dword); 1399 } 1400 1401 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1402 struct rtw89_tx_desc_info *desc_info, 1403 void *txdesc) 1404 { 1405 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1406 1407 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1408 } 1409 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1410 1411 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1412 { 1413 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1414 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1415 RTW89_CORE_RX_TYPE_FWDL : 1416 RTW89_CORE_RX_TYPE_H2C); 1417 1418 return cpu_to_le32(dword); 1419 } 1420 1421 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1422 struct rtw89_tx_desc_info *desc_info, 1423 void *txdesc) 1424 { 1425 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1426 1427 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1428 } 1429 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1430 1431 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1432 struct sk_buff *skb, 1433 struct rtw89_rx_phy_ppdu *phy_ppdu) 1434 { 1435 const struct rtw89_chip_info *chip = rtwdev->chip; 1436 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1437 const struct rtw89_rxinfo_user *user; 1438 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1439 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1440 bool rx_cnt_valid = false; 1441 bool invalid = false; 1442 u8 plcp_size = 0; 1443 u8 *phy_sts; 1444 u8 usr_num; 1445 int i; 1446 1447 if (chip_gen == RTW89_CHIP_BE) { 1448 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1449 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1450 } 1451 1452 if (invalid) 1453 return -EINVAL; 1454 1455 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1456 if (chip_gen == RTW89_CHIP_BE) { 1457 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1458 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1459 } else { 1460 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1461 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1462 } 1463 if (usr_num > chip->ppdu_max_usr) { 1464 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1465 usr_num); 1466 return -EINVAL; 1467 } 1468 1469 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware, 1470 * so update mac_id by rxinfo_user[].mac_id. 1471 */ 1472 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) { 1473 user = &rxinfo->user[i]; 1474 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1475 continue; 1476 1477 phy_ppdu->mac_id = 1478 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1479 break; 1480 } 1481 1482 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1483 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1484 /* 8-byte alignment */ 1485 if (usr_num & BIT(0)) 1486 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1487 if (rx_cnt_valid) 1488 phy_sts += rx_cnt_size; 1489 phy_sts += plcp_size; 1490 1491 if (phy_sts > skb->data + skb->len) 1492 return -EINVAL; 1493 1494 phy_ppdu->buf = phy_sts; 1495 phy_ppdu->len = skb->data + skb->len - phy_sts; 1496 1497 return 0; 1498 } 1499 1500 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1501 struct ieee80211_sta *sta) 1502 { 1503 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1504 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1505 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1506 struct rtw89_hal *hal = &rtwdev->hal; 1507 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1508 u8 ant_pos = U8_MAX; 1509 u8 evm_pos = 0; 1510 int i; 1511 1512 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1513 return; 1514 1515 if (hal->ant_diversity && hal->antenna_rx) { 1516 ant_pos = __ffs(hal->antenna_rx); 1517 evm_pos = ant_pos; 1518 } 1519 1520 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1521 1522 if (ant_pos < ant_num) { 1523 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1524 } else { 1525 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1526 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1527 } 1528 1529 if (phy_ppdu->ofdm.has) { 1530 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1531 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1532 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1533 } 1534 } 1535 1536 #define VAR_LEN 0xff 1537 #define VAR_LEN_UNIT 8 1538 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1539 const struct rtw89_phy_sts_iehdr *iehdr) 1540 { 1541 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1542 [RTW89_CHIP_AX] = { 1543 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1544 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1545 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1546 }, 1547 [RTW89_CHIP_BE] = { 1548 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1549 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1550 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1551 }, 1552 }; 1553 const u8 *physts_ie_len_tab; 1554 u16 ie_len; 1555 u8 ie; 1556 1557 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1558 1559 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1560 if (physts_ie_len_tab[ie] != VAR_LEN) 1561 ie_len = physts_ie_len_tab[ie]; 1562 else 1563 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1564 1565 return ie_len; 1566 } 1567 1568 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1569 const struct rtw89_phy_sts_iehdr *iehdr, 1570 struct rtw89_rx_phy_ppdu *phy_ppdu) 1571 { 1572 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1573 s16 cfo; 1574 u32 t; 1575 1576 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1577 1578 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1579 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1580 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1581 } 1582 1583 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1584 return; 1585 1586 if (!phy_ppdu->to_self) 1587 return; 1588 1589 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1590 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1591 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1592 phy_ppdu->ofdm.has = true; 1593 1594 /* sign conversion for S(12,2) */ 1595 if (rtwdev->chip->cfo_src_fd) { 1596 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1597 cfo = sign_extend32(t, 11); 1598 } else { 1599 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1600 cfo = sign_extend32(t, 11); 1601 } 1602 1603 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1604 } 1605 1606 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1607 const struct rtw89_phy_sts_iehdr *iehdr, 1608 struct rtw89_rx_phy_ppdu *phy_ppdu) 1609 { 1610 u8 ie; 1611 1612 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1613 1614 switch (ie) { 1615 case RTW89_PHYSTS_IE01_CMN_OFDM: 1616 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1617 break; 1618 default: 1619 break; 1620 } 1621 1622 return 0; 1623 } 1624 1625 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1626 { 1627 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1628 u8 *rssi = phy_ppdu->rssi; 1629 1630 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1631 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1632 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1633 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1634 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1635 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1636 } 1637 1638 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1639 struct rtw89_rx_phy_ppdu *phy_ppdu) 1640 { 1641 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1642 u32 len_from_header; 1643 bool physts_valid; 1644 1645 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1646 if (!physts_valid) 1647 return -EINVAL; 1648 1649 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1650 1651 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1652 len_from_header += PHY_STS_HDR_LEN; 1653 1654 if (len_from_header != phy_ppdu->len) { 1655 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1656 return -EINVAL; 1657 } 1658 rtw89_core_update_phy_ppdu(phy_ppdu); 1659 1660 return 0; 1661 } 1662 1663 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1664 struct rtw89_rx_phy_ppdu *phy_ppdu) 1665 { 1666 u16 ie_len; 1667 #if defined(__linux__) 1668 void *pos, *end; 1669 #elif defined(__FreeBSD__) 1670 u8 *pos, *end; 1671 #endif 1672 1673 /* mark invalid reports and bypass them */ 1674 if (phy_ppdu->ie < RTW89_CCK_PKT) 1675 return -EINVAL; 1676 1677 #if defined(__linux__) 1678 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1679 end = phy_ppdu->buf + phy_ppdu->len; 1680 #elif defined(__FreeBSD__) 1681 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1682 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1683 #endif 1684 while (pos < end) { 1685 #if defined(__linux__) 1686 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1687 #elif defined(__FreeBSD__) 1688 const struct rtw89_phy_sts_iehdr *iehdr = (void *)pos; 1689 #endif 1690 1691 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1692 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1693 pos += ie_len; 1694 if (pos > end || ie_len == 0) { 1695 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1696 "phy status parse failed\n"); 1697 return -EINVAL; 1698 } 1699 } 1700 1701 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1702 1703 return 0; 1704 } 1705 1706 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1707 struct rtw89_rx_phy_ppdu *phy_ppdu) 1708 { 1709 int ret; 1710 1711 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1712 if (ret) 1713 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1714 else 1715 phy_ppdu->valid = true; 1716 1717 ieee80211_iterate_stations_atomic(rtwdev->hw, 1718 rtw89_core_rx_process_phy_ppdu_iter, 1719 phy_ppdu); 1720 } 1721 1722 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1723 u8 desc_info_gi, 1724 bool rx_status, bool eht) 1725 { 1726 switch (desc_info_gi) { 1727 case RTW89_GILTF_SGI_4XHE08: 1728 case RTW89_GILTF_2XHE08: 1729 case RTW89_GILTF_1XHE08: 1730 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1731 NL80211_RATE_INFO_HE_GI_0_8; 1732 case RTW89_GILTF_2XHE16: 1733 case RTW89_GILTF_1XHE16: 1734 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1735 NL80211_RATE_INFO_HE_GI_1_6; 1736 case RTW89_GILTF_LGI_4XHE32: 1737 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1738 NL80211_RATE_INFO_HE_GI_3_2; 1739 default: 1740 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1741 if (rx_status) 1742 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1743 NL80211_RATE_INFO_HE_GI_3_2; 1744 return U8_MAX; 1745 } 1746 } 1747 1748 static 1749 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1750 bool eht) 1751 { 1752 if (eht) 1753 return status->eht.gi == gi_ltf; 1754 1755 return status->he_gi == gi_ltf; 1756 } 1757 1758 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1759 struct rtw89_rx_desc_info *desc_info, 1760 struct ieee80211_rx_status *status) 1761 { 1762 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1763 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1764 bool eht = false; 1765 u16 data_rate; 1766 bool ret; 1767 1768 data_rate = desc_info->data_rate; 1769 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1770 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1771 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1772 /* rate_idx is still hardware value here */ 1773 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1774 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1775 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1776 data_rate_mode == DATA_RATE_MODE_HE || 1777 data_rate_mode == DATA_RATE_MODE_EHT) { 1778 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1779 } else { 1780 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1781 } 1782 1783 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1784 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1785 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1786 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1787 status->rate_idx == rate_idx && 1788 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1789 status->bw == bw; 1790 1791 return ret; 1792 } 1793 1794 struct rtw89_vif_rx_stats_iter_data { 1795 struct rtw89_dev *rtwdev; 1796 struct rtw89_rx_phy_ppdu *phy_ppdu; 1797 struct rtw89_rx_desc_info *desc_info; 1798 struct sk_buff *skb; 1799 const u8 *bssid; 1800 }; 1801 1802 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1803 struct ieee80211_vif *vif, 1804 struct sk_buff *skb) 1805 { 1806 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1807 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1808 u8 *pos, *end, type, tf_bw; 1809 u16 aid, tf_rua; 1810 1811 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1812 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1813 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1814 return; 1815 1816 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1817 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1818 return; 1819 1820 end = (u8 *)tf + skb->len; 1821 pos = tf->variable; 1822 1823 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1824 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1825 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1826 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1827 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1828 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1829 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1830 tf_rua, tf_bw); 1831 1832 if (aid == RTW89_TF_PAD) 1833 break; 1834 1835 if (aid == vif->cfg.aid) { 1836 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1837 1838 rtwvif->stats.rx_tf_acc++; 1839 rtwdev->stats.rx_tf_acc++; 1840 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1841 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1842 rtwvif->pwr_diff_en = true; 1843 break; 1844 } 1845 1846 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1847 } 1848 } 1849 1850 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1851 { 1852 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1853 cancel_6ghz_probe_work); 1854 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1855 struct rtw89_pktofld_info *info; 1856 1857 mutex_lock(&rtwdev->mutex); 1858 1859 if (!rtwdev->scanning) 1860 goto out; 1861 1862 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1863 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1864 continue; 1865 1866 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1867 1868 /* Don't delete/free info from pkt_list at this moment. Let it 1869 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1870 * since if during scanning, pkt_list is accessed in bottom half. 1871 */ 1872 } 1873 1874 out: 1875 mutex_unlock(&rtwdev->mutex); 1876 } 1877 1878 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1879 struct sk_buff *skb) 1880 { 1881 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1882 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1883 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1884 struct rtw89_pktofld_info *info; 1885 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1886 bool queue_work = false; 1887 1888 if (rx_status->band != NL80211_BAND_6GHZ) 1889 return; 1890 1891 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1892 1893 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1894 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1895 info->cancel = true; 1896 queue_work = true; 1897 continue; 1898 } 1899 1900 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1901 continue; 1902 1903 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1904 info->cancel = true; 1905 queue_work = true; 1906 } 1907 } 1908 1909 if (queue_work) 1910 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1911 } 1912 1913 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif *rtwvif, 1914 struct ieee80211_hdr *hdr, size_t len) 1915 { 1916 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 1917 1918 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 1919 return; 1920 1921 WRITE_ONCE(rtwvif->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 1922 } 1923 1924 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1925 struct ieee80211_vif *vif) 1926 { 1927 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1928 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1929 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1930 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1931 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1932 struct sk_buff *skb = iter_data->skb; 1933 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1934 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1935 const u8 *bssid = iter_data->bssid; 1936 1937 if (rtwdev->scanning && 1938 (ieee80211_is_beacon(hdr->frame_control) || 1939 ieee80211_is_probe_resp(hdr->frame_control))) 1940 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1941 1942 if (!vif->bss_conf.bssid) 1943 return; 1944 1945 if (ieee80211_is_trigger(hdr->frame_control)) { 1946 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1947 return; 1948 } 1949 1950 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1951 return; 1952 1953 if (ieee80211_is_beacon(hdr->frame_control)) { 1954 if (vif->type == NL80211_IFTYPE_STATION && 1955 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 1956 rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len); 1957 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1958 } 1959 pkt_stat->beacon_nr++; 1960 } 1961 1962 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1963 return; 1964 1965 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1966 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1967 1968 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1969 } 1970 1971 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1972 struct rtw89_rx_phy_ppdu *phy_ppdu, 1973 struct rtw89_rx_desc_info *desc_info, 1974 struct sk_buff *skb) 1975 { 1976 struct rtw89_vif_rx_stats_iter_data iter_data; 1977 1978 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1979 1980 iter_data.rtwdev = rtwdev; 1981 iter_data.phy_ppdu = phy_ppdu; 1982 iter_data.desc_info = desc_info; 1983 iter_data.skb = skb; 1984 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1985 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1986 } 1987 1988 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1989 struct ieee80211_rx_status *status) 1990 { 1991 const struct rtw89_chan_rcd *rcd = 1992 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1993 u16 chan = rcd->prev_primary_channel; 1994 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1995 1996 if (status->band != NL80211_BAND_2GHZ && 1997 status->encoding == RX_ENC_LEGACY && 1998 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1999 status->freq = ieee80211_channel_to_frequency(chan, band); 2000 status->band = band; 2001 } 2002 } 2003 2004 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2005 { 2006 if (rx_status->band == NL80211_BAND_2GHZ || 2007 rx_status->encoding != RX_ENC_LEGACY) 2008 return; 2009 2010 /* Some control frames' freq(ACKs in this case) are reported wrong due 2011 * to FW notify timing, set to lowest rate to prevent overflow. 2012 */ 2013 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2014 rx_status->rate_idx = 0; 2015 return; 2016 } 2017 2018 /* No 4 CCK rates for non-2G */ 2019 rx_status->rate_idx -= 4; 2020 } 2021 2022 static 2023 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2024 struct ieee80211_rx_status *rx_status, 2025 struct rtw89_rx_phy_ppdu *phy_ppdu) 2026 { 2027 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2028 return; 2029 2030 if (!phy_ppdu) 2031 return; 2032 2033 if (phy_ppdu->ldpc) 2034 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2035 if (phy_ppdu->stbc) 2036 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2037 } 2038 2039 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2040 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2041 [RATE_INFO_BW_5] = U8_MAX, 2042 [RATE_INFO_BW_10] = U8_MAX, 2043 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2044 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2045 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2046 [RATE_INFO_BW_HE_RU] = U8_MAX, 2047 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2048 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2049 }; 2050 2051 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2052 struct sk_buff *skb, 2053 struct ieee80211_rx_status *rx_status) 2054 { 2055 struct ieee80211_radiotap_eht_usig *usig; 2056 struct ieee80211_radiotap_eht *eht; 2057 struct ieee80211_radiotap_tlv *tlv; 2058 int eht_len = struct_size(eht, user_info, 1); 2059 int usig_len = sizeof(*usig); 2060 int len; 2061 u8 bw; 2062 2063 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2064 sizeof(*tlv) + ALIGN(usig_len, 4); 2065 2066 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2067 skb_reset_mac_header(skb); 2068 2069 /* EHT */ 2070 tlv = skb_push(skb, len); 2071 memset(tlv, 0, len); 2072 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2073 tlv->len = cpu_to_le16(eht_len); 2074 2075 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2076 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2077 eht->data[0] = 2078 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2079 2080 eht->user_info[0] = 2081 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2082 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2083 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2084 eht->user_info[0] |= 2085 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2086 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2087 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2088 eht->user_info[0] |= 2089 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2090 2091 /* U-SIG */ 2092 #if defined(__linux__) 2093 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2094 #elif defined(__FreeBSD__) 2095 tlv = (void *)((u8 *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4)); 2096 #endif 2097 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2098 tlv->len = cpu_to_le16(usig_len); 2099 2100 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2101 return; 2102 2103 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2104 if (bw == U8_MAX) 2105 return; 2106 2107 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2108 usig->common = 2109 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2110 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2111 } 2112 2113 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2114 struct sk_buff *skb, 2115 struct ieee80211_rx_status *rx_status) 2116 { 2117 static const struct ieee80211_radiotap_he known_he = { 2118 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2119 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2120 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2121 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2122 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2123 }; 2124 struct ieee80211_radiotap_he *he; 2125 2126 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2127 return; 2128 2129 if (rx_status->encoding == RX_ENC_HE) { 2130 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2131 he = skb_push(skb, sizeof(*he)); 2132 *he = known_he; 2133 } else if (rx_status->encoding == RX_ENC_EHT) { 2134 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2135 } 2136 } 2137 2138 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2139 struct rtw89_rx_phy_ppdu *phy_ppdu, 2140 struct rtw89_rx_desc_info *desc_info, 2141 struct sk_buff *skb_ppdu, 2142 struct ieee80211_rx_status *rx_status) 2143 { 2144 struct napi_struct *napi = &rtwdev->napi; 2145 2146 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2147 if (unlikely(!napi_is_scheduled(napi))) 2148 napi = NULL; 2149 2150 rtw89_core_hw_to_sband_rate(rx_status); 2151 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2152 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2153 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2154 /* In low power mode, it does RX in thread context. */ 2155 local_bh_disable(); 2156 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2157 local_bh_enable(); 2158 rtwdev->napi_budget_countdown--; 2159 } 2160 2161 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2162 struct rtw89_rx_phy_ppdu *phy_ppdu, 2163 struct rtw89_rx_desc_info *desc_info, 2164 struct sk_buff *skb) 2165 { 2166 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2167 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2168 struct sk_buff *skb_ppdu = NULL, *tmp; 2169 struct ieee80211_rx_status *rx_status; 2170 2171 if (curr > RTW89_MAX_PPDU_CNT) 2172 return; 2173 2174 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2175 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2176 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2177 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2178 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2179 rtw89_correct_cck_chan(rtwdev, rx_status); 2180 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2181 } 2182 } 2183 2184 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2185 struct rtw89_rx_desc_info *desc_info, 2186 struct sk_buff *skb) 2187 { 2188 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2189 .len = skb->len, 2190 .to_self = desc_info->addr1_match, 2191 .rate = desc_info->data_rate, 2192 .mac_id = desc_info->mac_id}; 2193 int ret; 2194 2195 if (desc_info->mac_info_valid) { 2196 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2197 if (ret) 2198 goto out; 2199 } 2200 2201 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2202 if (ret) 2203 goto out; 2204 2205 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2206 2207 out: 2208 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2209 dev_kfree_skb_any(skb); 2210 } 2211 2212 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2213 struct rtw89_rx_desc_info *desc_info, 2214 struct sk_buff *skb) 2215 { 2216 switch (desc_info->pkt_type) { 2217 case RTW89_CORE_RX_TYPE_C2H: 2218 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2219 break; 2220 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2221 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2222 break; 2223 default: 2224 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2225 desc_info->pkt_type); 2226 dev_kfree_skb_any(skb); 2227 break; 2228 } 2229 } 2230 2231 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2232 struct rtw89_rx_desc_info *desc_info, 2233 u8 *data, u32 data_offset) 2234 { 2235 const struct rtw89_chip_info *chip = rtwdev->chip; 2236 struct rtw89_rxdesc_short *rxd_s; 2237 struct rtw89_rxdesc_long *rxd_l; 2238 u8 shift_len, drv_info_len; 2239 2240 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2241 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2242 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2243 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2244 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2245 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2246 if (chip->chip_id == RTL8852C) 2247 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2248 else 2249 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2250 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2251 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2252 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2253 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2254 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2255 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2256 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2257 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2258 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2259 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2260 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2261 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2262 2263 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2264 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2265 desc_info->offset = data_offset + shift_len + drv_info_len; 2266 if (desc_info->long_rxdesc) 2267 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2268 else 2269 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2270 desc_info->ready = true; 2271 2272 if (!desc_info->long_rxdesc) 2273 return; 2274 2275 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2276 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2277 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2278 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2279 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2280 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2281 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2282 } 2283 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2284 2285 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2286 struct rtw89_rx_desc_info *desc_info, 2287 u8 *data, u32 data_offset) 2288 { 2289 struct rtw89_rxdesc_short_v2 *rxd_s; 2290 struct rtw89_rxdesc_long_v2 *rxd_l; 2291 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2292 2293 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2294 2295 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2296 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2297 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2298 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2299 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2300 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2301 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2302 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2303 desc_info->mac_info_valid = true; 2304 2305 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2306 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2307 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2308 2309 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2310 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2311 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2312 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2313 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2314 2315 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2316 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2317 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2318 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2319 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2320 2321 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2322 2323 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2324 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2325 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2326 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2327 desc_info->offset = data_offset + shift_len + drv_info_len + 2328 phy_rtp_len + hdr_cnv_len; 2329 2330 if (desc_info->long_rxdesc) 2331 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2332 else 2333 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2334 desc_info->ready = true; 2335 2336 if (!desc_info->long_rxdesc) 2337 return; 2338 2339 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2340 2341 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2342 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2343 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2344 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2345 2346 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2347 } 2348 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2349 2350 struct rtw89_core_iter_rx_status { 2351 struct rtw89_dev *rtwdev; 2352 struct ieee80211_rx_status *rx_status; 2353 struct rtw89_rx_desc_info *desc_info; 2354 u8 mac_id; 2355 }; 2356 2357 static 2358 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2359 { 2360 struct rtw89_core_iter_rx_status *iter_data = 2361 (struct rtw89_core_iter_rx_status *)data; 2362 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2363 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2364 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2365 u8 mac_id = iter_data->mac_id; 2366 2367 if (mac_id != rtwsta->mac_id) 2368 return; 2369 2370 rtwsta->rx_status = *rx_status; 2371 rtwsta->rx_hw_rate = desc_info->data_rate; 2372 } 2373 2374 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2375 struct rtw89_rx_desc_info *desc_info, 2376 struct ieee80211_rx_status *rx_status) 2377 { 2378 struct rtw89_core_iter_rx_status iter_data; 2379 2380 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2381 return; 2382 2383 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2384 return; 2385 2386 iter_data.rtwdev = rtwdev; 2387 iter_data.rx_status = rx_status; 2388 iter_data.desc_info = desc_info; 2389 iter_data.mac_id = desc_info->mac_id; 2390 ieee80211_iterate_stations_atomic(rtwdev->hw, 2391 rtw89_core_stats_sta_rx_status_iter, 2392 &iter_data); 2393 } 2394 2395 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2396 struct rtw89_rx_desc_info *desc_info, 2397 struct ieee80211_rx_status *rx_status) 2398 { 2399 const struct cfg80211_chan_def *chandef = 2400 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 2401 u16 data_rate; 2402 u8 data_rate_mode; 2403 bool eht = false; 2404 u8 gi; 2405 2406 /* currently using single PHY */ 2407 rx_status->freq = chandef->chan->center_freq; 2408 rx_status->band = chandef->chan->band; 2409 2410 if (rtwdev->scanning && 2411 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2412 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2413 u8 chan = cur->primary_channel; 2414 u8 band = cur->band_type; 2415 enum nl80211_band nl_band; 2416 2417 nl_band = rtw89_hw_to_nl80211_band(band); 2418 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2419 rx_status->band = nl_band; 2420 } 2421 2422 if (desc_info->icv_err || desc_info->crc32_err) 2423 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2424 2425 if (desc_info->hw_dec && 2426 !(desc_info->sw_dec || desc_info->icv_err)) 2427 rx_status->flag |= RX_FLAG_DECRYPTED; 2428 2429 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2430 2431 data_rate = desc_info->data_rate; 2432 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2433 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2434 rx_status->encoding = RX_ENC_LEGACY; 2435 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2436 /* convert rate_idx after we get the correct band */ 2437 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2438 rx_status->encoding = RX_ENC_HT; 2439 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2440 if (desc_info->gi_ltf) 2441 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2442 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2443 rx_status->encoding = RX_ENC_VHT; 2444 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2445 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2446 if (desc_info->gi_ltf) 2447 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2448 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2449 rx_status->encoding = RX_ENC_HE; 2450 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2451 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2452 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2453 rx_status->encoding = RX_ENC_EHT; 2454 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2455 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2456 eht = true; 2457 } else { 2458 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2459 } 2460 2461 /* he_gi is used to match ppdu, so we always fill it. */ 2462 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2463 if (eht) 2464 rx_status->eht.gi = gi; 2465 else 2466 rx_status->he_gi = gi; 2467 rx_status->flag |= RX_FLAG_MACTIME_START; 2468 rx_status->mactime = desc_info->free_run_cnt; 2469 2470 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2471 } 2472 2473 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2474 { 2475 const struct rtw89_chip_info *chip = rtwdev->chip; 2476 2477 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2478 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2479 return RTW89_PS_MODE_NONE; 2480 2481 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2482 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2483 return RTW89_PS_MODE_PWR_GATED; 2484 2485 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2486 return RTW89_PS_MODE_CLK_GATED; 2487 2488 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2489 return RTW89_PS_MODE_RFOFF; 2490 2491 return RTW89_PS_MODE_NONE; 2492 } 2493 2494 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2495 struct rtw89_rx_desc_info *desc_info) 2496 { 2497 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2498 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2499 struct ieee80211_rx_status *rx_status; 2500 struct sk_buff *skb_ppdu, *tmp; 2501 2502 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2503 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2504 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2505 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2506 } 2507 } 2508 2509 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2510 struct rtw89_rx_desc_info *desc_info, 2511 struct sk_buff *skb) 2512 { 2513 struct ieee80211_rx_status *rx_status; 2514 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2515 u8 ppdu_cnt = desc_info->ppdu_cnt; 2516 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2517 2518 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2519 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2520 return; 2521 } 2522 2523 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2524 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2525 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2526 } 2527 2528 rx_status = IEEE80211_SKB_RXCB(skb); 2529 memset(rx_status, 0, sizeof(*rx_status)); 2530 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2531 if (desc_info->long_rxdesc && 2532 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2533 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2534 else 2535 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2536 } 2537 EXPORT_SYMBOL(rtw89_core_rx); 2538 2539 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2540 { 2541 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2542 return; 2543 2544 napi_enable(&rtwdev->napi); 2545 } 2546 EXPORT_SYMBOL(rtw89_core_napi_start); 2547 2548 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2549 { 2550 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2551 return; 2552 2553 napi_synchronize(&rtwdev->napi); 2554 napi_disable(&rtwdev->napi); 2555 } 2556 EXPORT_SYMBOL(rtw89_core_napi_stop); 2557 2558 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2559 { 2560 rtwdev->netdev = alloc_netdev_dummy(0); 2561 if (!rtwdev->netdev) 2562 return -ENOMEM; 2563 2564 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2565 rtwdev->hci.ops->napi_poll); 2566 return 0; 2567 } 2568 EXPORT_SYMBOL(rtw89_core_napi_init); 2569 2570 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2571 { 2572 rtw89_core_napi_stop(rtwdev); 2573 netif_napi_del(&rtwdev->napi); 2574 free_netdev(rtwdev->netdev); 2575 } 2576 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2577 2578 static void rtw89_core_ba_work(struct work_struct *work) 2579 { 2580 struct rtw89_dev *rtwdev = 2581 container_of(work, struct rtw89_dev, ba_work); 2582 struct rtw89_txq *rtwtxq, *tmp; 2583 int ret; 2584 2585 spin_lock_bh(&rtwdev->ba_lock); 2586 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2587 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2588 struct ieee80211_sta *sta = txq->sta; 2589 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2590 u8 tid = txq->tid; 2591 2592 if (!sta) { 2593 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2594 goto skip_ba_work; 2595 } 2596 2597 if (rtwsta->disassoc) { 2598 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2599 "cannot start BA with disassoc sta\n"); 2600 goto skip_ba_work; 2601 } 2602 2603 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2604 if (ret) { 2605 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2606 "failed to setup BA session for %pM:%2d: %d\n", 2607 sta->addr, tid, ret); 2608 if (ret == -EINVAL) 2609 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2610 } 2611 skip_ba_work: 2612 list_del_init(&rtwtxq->list); 2613 } 2614 spin_unlock_bh(&rtwdev->ba_lock); 2615 } 2616 2617 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2618 struct ieee80211_sta *sta) 2619 { 2620 struct rtw89_txq *rtwtxq, *tmp; 2621 2622 spin_lock_bh(&rtwdev->ba_lock); 2623 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2624 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2625 2626 if (sta == txq->sta) 2627 list_del_init(&rtwtxq->list); 2628 } 2629 spin_unlock_bh(&rtwdev->ba_lock); 2630 } 2631 2632 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2633 struct ieee80211_sta *sta) 2634 { 2635 struct rtw89_txq *rtwtxq, *tmp; 2636 2637 spin_lock_bh(&rtwdev->ba_lock); 2638 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2639 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2640 2641 if (sta == txq->sta) { 2642 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2643 list_del_init(&rtwtxq->list); 2644 } 2645 } 2646 spin_unlock_bh(&rtwdev->ba_lock); 2647 } 2648 2649 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2650 struct ieee80211_sta *sta) 2651 { 2652 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2653 struct sk_buff *skb, *tmp; 2654 2655 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2656 skb_unlink(skb, &rtwsta->roc_queue); 2657 dev_kfree_skb_any(skb); 2658 } 2659 } 2660 2661 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2662 struct rtw89_txq *rtwtxq) 2663 { 2664 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2665 struct ieee80211_sta *sta = txq->sta; 2666 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2667 2668 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2669 return; 2670 2671 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2672 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2673 return; 2674 2675 spin_lock_bh(&rtwdev->ba_lock); 2676 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2677 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2678 spin_unlock_bh(&rtwdev->ba_lock); 2679 2680 ieee80211_stop_tx_ba_session(sta, txq->tid); 2681 cancel_delayed_work(&rtwdev->forbid_ba_work); 2682 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2683 RTW89_FORBID_BA_TIMER); 2684 } 2685 2686 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2687 struct rtw89_txq *rtwtxq, 2688 struct sk_buff *skb) 2689 { 2690 struct ieee80211_hw *hw = rtwdev->hw; 2691 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2692 struct ieee80211_sta *sta = txq->sta; 2693 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2694 2695 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2696 return; 2697 2698 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2699 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2700 return; 2701 } 2702 2703 if (unlikely(!sta)) 2704 return; 2705 2706 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2707 return; 2708 2709 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2710 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2711 return; 2712 } 2713 2714 spin_lock_bh(&rtwdev->ba_lock); 2715 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2716 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2717 ieee80211_queue_work(hw, &rtwdev->ba_work); 2718 } 2719 spin_unlock_bh(&rtwdev->ba_lock); 2720 } 2721 2722 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2723 struct rtw89_txq *rtwtxq, 2724 unsigned long frame_cnt, 2725 unsigned long byte_cnt) 2726 { 2727 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2728 struct ieee80211_vif *vif = txq->vif; 2729 struct ieee80211_sta *sta = txq->sta; 2730 struct sk_buff *skb; 2731 unsigned long i; 2732 int ret; 2733 2734 rcu_read_lock(); 2735 for (i = 0; i < frame_cnt; i++) { 2736 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2737 if (!skb) { 2738 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2739 goto out; 2740 } 2741 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2742 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2743 if (ret) { 2744 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2745 ieee80211_free_txskb(rtwdev->hw, skb); 2746 break; 2747 } 2748 } 2749 out: 2750 rcu_read_unlock(); 2751 } 2752 2753 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2754 { 2755 u8 qsel, ch_dma; 2756 2757 qsel = rtw89_core_get_qsel(rtwdev, tid); 2758 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2759 2760 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2761 } 2762 2763 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2764 struct ieee80211_txq *txq, 2765 unsigned long *frame_cnt, 2766 bool *sched_txq, bool *reinvoke) 2767 { 2768 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2769 struct ieee80211_sta *sta = txq->sta; 2770 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2771 2772 if (!sta || rtwsta->max_agg_wait <= 0) 2773 return false; 2774 2775 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2776 return false; 2777 2778 if (*frame_cnt > 1) { 2779 *frame_cnt -= 1; 2780 *sched_txq = true; 2781 *reinvoke = true; 2782 rtwtxq->wait_cnt = 1; 2783 return false; 2784 } 2785 2786 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2787 *reinvoke = true; 2788 rtwtxq->wait_cnt++; 2789 return true; 2790 } 2791 2792 rtwtxq->wait_cnt = 0; 2793 return false; 2794 } 2795 2796 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2797 { 2798 struct ieee80211_hw *hw = rtwdev->hw; 2799 struct ieee80211_txq *txq; 2800 struct rtw89_vif *rtwvif; 2801 struct rtw89_txq *rtwtxq; 2802 unsigned long frame_cnt; 2803 unsigned long byte_cnt; 2804 u32 tx_resource; 2805 bool sched_txq; 2806 2807 ieee80211_txq_schedule_start(hw, ac); 2808 while ((txq = ieee80211_next_txq(hw, ac))) { 2809 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2810 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2811 2812 if (rtwvif->offchan) { 2813 ieee80211_return_txq(hw, txq, true); 2814 continue; 2815 } 2816 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2817 sched_txq = false; 2818 2819 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2820 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2821 ieee80211_return_txq(hw, txq, true); 2822 continue; 2823 } 2824 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2825 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2826 ieee80211_return_txq(hw, txq, sched_txq); 2827 if (frame_cnt != 0) 2828 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2829 2830 /* bound of tx_resource could get stuck due to burst traffic */ 2831 if (frame_cnt == tx_resource) 2832 *reinvoke = true; 2833 } 2834 ieee80211_txq_schedule_end(hw, ac); 2835 } 2836 2837 static void rtw89_ips_work(struct work_struct *work) 2838 { 2839 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2840 ips_work); 2841 mutex_lock(&rtwdev->mutex); 2842 rtw89_enter_ips_by_hwflags(rtwdev); 2843 mutex_unlock(&rtwdev->mutex); 2844 } 2845 2846 static void rtw89_core_txq_work(struct work_struct *w) 2847 { 2848 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2849 bool reinvoke = false; 2850 u8 ac; 2851 2852 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2853 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2854 2855 if (reinvoke) { 2856 /* reinvoke to process the last frame */ 2857 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2858 } 2859 } 2860 2861 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2862 { 2863 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2864 txq_reinvoke_work.work); 2865 2866 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2867 } 2868 2869 static void rtw89_forbid_ba_work(struct work_struct *w) 2870 { 2871 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2872 forbid_ba_work.work); 2873 struct rtw89_txq *rtwtxq, *tmp; 2874 2875 spin_lock_bh(&rtwdev->ba_lock); 2876 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2877 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2878 list_del_init(&rtwtxq->list); 2879 } 2880 spin_unlock_bh(&rtwdev->ba_lock); 2881 } 2882 2883 static void rtw89_core_sta_pending_tx_iter(void *data, 2884 struct ieee80211_sta *sta) 2885 { 2886 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2887 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2888 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2889 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2890 struct sk_buff *skb, *tmp; 2891 int qsel, ret; 2892 2893 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2894 return; 2895 2896 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2897 return; 2898 2899 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2900 skb_unlink(skb, &rtwsta->roc_queue); 2901 2902 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2903 if (ret) { 2904 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2905 dev_kfree_skb_any(skb); 2906 } else { 2907 rtw89_core_tx_kick_off(rtwdev, qsel); 2908 } 2909 } 2910 } 2911 2912 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2913 struct rtw89_vif *rtwvif) 2914 { 2915 ieee80211_iterate_stations_atomic(rtwdev->hw, 2916 rtw89_core_sta_pending_tx_iter, 2917 rtwvif); 2918 } 2919 2920 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2921 struct rtw89_vif *rtwvif, bool qos, bool ps) 2922 { 2923 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2924 struct ieee80211_sta *sta; 2925 struct ieee80211_hdr *hdr; 2926 struct sk_buff *skb; 2927 int ret, qsel; 2928 2929 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2930 return 0; 2931 2932 rcu_read_lock(); 2933 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2934 if (!sta) { 2935 ret = -EINVAL; 2936 goto out; 2937 } 2938 2939 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2940 if (!skb) { 2941 ret = -ENOMEM; 2942 goto out; 2943 } 2944 2945 hdr = (struct ieee80211_hdr *)skb->data; 2946 if (ps) 2947 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2948 2949 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2950 if (ret) { 2951 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2952 dev_kfree_skb_any(skb); 2953 goto out; 2954 } 2955 2956 rcu_read_unlock(); 2957 2958 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2959 RTW89_ROC_TX_TIMEOUT); 2960 out: 2961 rcu_read_unlock(); 2962 2963 return ret; 2964 } 2965 2966 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2967 { 2968 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2969 struct ieee80211_hw *hw = rtwdev->hw; 2970 struct rtw89_roc *roc = &rtwvif->roc; 2971 struct cfg80211_chan_def roc_chan; 2972 struct rtw89_vif *tmp; 2973 int ret; 2974 2975 lockdep_assert_held(&rtwdev->mutex); 2976 2977 rtw89_leave_ips_by_hwflags(rtwdev); 2978 rtw89_leave_lps(rtwdev); 2979 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2980 2981 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2982 if (ret) 2983 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2984 "roc send null-1 failed: %d\n", ret); 2985 2986 rtw89_for_each_rtwvif(rtwdev, tmp) 2987 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2988 tmp->offchan = true; 2989 2990 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2991 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2992 rtw89_set_channel(rtwdev); 2993 rtw89_write32_clr(rtwdev, 2994 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2995 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2996 2997 ieee80211_ready_on_channel(hw); 2998 cancel_delayed_work(&rtwvif->roc.roc_work); 2999 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 3000 msecs_to_jiffies(rtwvif->roc.duration)); 3001 } 3002 3003 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3004 { 3005 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3006 struct ieee80211_hw *hw = rtwdev->hw; 3007 struct rtw89_roc *roc = &rtwvif->roc; 3008 struct rtw89_vif *tmp; 3009 int ret; 3010 3011 lockdep_assert_held(&rtwdev->mutex); 3012 3013 ieee80211_remain_on_channel_expired(hw); 3014 3015 rtw89_leave_ips_by_hwflags(rtwdev); 3016 rtw89_leave_lps(rtwdev); 3017 3018 rtw89_write32_mask(rtwdev, 3019 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 3020 B_AX_RX_FLTR_CFG_MASK, 3021 rtwdev->hal.rx_fltr); 3022 3023 roc->state = RTW89_ROC_IDLE; 3024 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 3025 rtw89_chanctx_proceed(rtwdev); 3026 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 3027 if (ret) 3028 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3029 "roc send null-0 failed: %d\n", ret); 3030 3031 rtw89_for_each_rtwvif(rtwdev, tmp) 3032 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 3033 tmp->offchan = false; 3034 3035 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 3036 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3037 3038 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3039 ieee80211_queue_delayed_work(hw, &roc->roc_work, 3040 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3041 } 3042 3043 void rtw89_roc_work(struct work_struct *work) 3044 { 3045 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3046 roc.roc_work.work); 3047 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3048 struct rtw89_roc *roc = &rtwvif->roc; 3049 3050 mutex_lock(&rtwdev->mutex); 3051 3052 switch (roc->state) { 3053 case RTW89_ROC_IDLE: 3054 rtw89_enter_ips_by_hwflags(rtwdev); 3055 break; 3056 case RTW89_ROC_MGMT: 3057 case RTW89_ROC_NORMAL: 3058 rtw89_roc_end(rtwdev, rtwvif); 3059 break; 3060 default: 3061 break; 3062 } 3063 3064 mutex_unlock(&rtwdev->mutex); 3065 } 3066 3067 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3068 u32 throughput, u64 cnt) 3069 { 3070 if (cnt < 100) 3071 return RTW89_TFC_IDLE; 3072 if (throughput > 50) 3073 return RTW89_TFC_HIGH; 3074 if (throughput > 10) 3075 return RTW89_TFC_MID; 3076 if (throughput > 2) 3077 return RTW89_TFC_LOW; 3078 return RTW89_TFC_ULTRA_LOW; 3079 } 3080 3081 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3082 struct rtw89_traffic_stats *stats) 3083 { 3084 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3085 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3086 3087 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3088 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3089 3090 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3091 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3092 3093 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3094 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3095 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3096 stats->tx_cnt); 3097 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3098 stats->rx_cnt); 3099 stats->tx_avg_len = stats->tx_cnt ? 3100 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3101 stats->rx_avg_len = stats->rx_cnt ? 3102 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3103 3104 stats->tx_unicast = 0; 3105 stats->rx_unicast = 0; 3106 stats->tx_cnt = 0; 3107 stats->rx_cnt = 0; 3108 stats->rx_tf_periodic = stats->rx_tf_acc; 3109 stats->rx_tf_acc = 0; 3110 3111 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3112 return true; 3113 3114 return false; 3115 } 3116 3117 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3118 { 3119 struct rtw89_vif *rtwvif; 3120 bool tfc_changed; 3121 3122 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3123 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3124 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3125 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3126 } 3127 3128 return tfc_changed; 3129 } 3130 3131 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3132 { 3133 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3134 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3135 rtwvif->tdls_peer) 3136 return; 3137 3138 if (rtwvif->offchan) 3139 return; 3140 3141 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3142 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3143 rtw89_enter_lps(rtwdev, rtwvif, true); 3144 } 3145 3146 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3147 { 3148 struct rtw89_vif *rtwvif; 3149 3150 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3151 rtw89_vif_enter_lps(rtwdev, rtwvif); 3152 } 3153 3154 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3155 { 3156 enum rtw89_entity_mode mode; 3157 3158 mode = rtw89_get_entity_mode(rtwdev); 3159 if (mode == RTW89_ENTITY_MODE_MCC) 3160 return; 3161 3162 rtw89_chip_rfk_track(rtwdev); 3163 } 3164 3165 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3166 { 3167 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3168 3169 if (mode == RTW89_ENTITY_MODE_MCC) 3170 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3171 else 3172 rtw89_process_p2p_ps(rtwdev, vif); 3173 } 3174 3175 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3176 struct rtw89_traffic_stats *stats) 3177 { 3178 stats->tx_unicast = 0; 3179 stats->rx_unicast = 0; 3180 stats->tx_cnt = 0; 3181 stats->rx_cnt = 0; 3182 ewma_tp_init(&stats->tx_ewma_tp); 3183 ewma_tp_init(&stats->rx_ewma_tp); 3184 } 3185 3186 static void rtw89_track_work(struct work_struct *work) 3187 { 3188 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3189 track_work.work); 3190 bool tfc_changed; 3191 3192 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3193 return; 3194 3195 mutex_lock(&rtwdev->mutex); 3196 3197 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3198 goto out; 3199 3200 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3201 RTW89_TRACK_WORK_PERIOD); 3202 3203 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3204 if (rtwdev->scanning) 3205 goto out; 3206 3207 rtw89_leave_lps(rtwdev); 3208 3209 if (tfc_changed) { 3210 rtw89_hci_recalc_int_mit(rtwdev); 3211 rtw89_btc_ntfy_wl_sta(rtwdev); 3212 } 3213 rtw89_mac_bf_monitor_track(rtwdev); 3214 rtw89_phy_stat_track(rtwdev); 3215 rtw89_phy_env_monitor_track(rtwdev); 3216 rtw89_phy_dig(rtwdev); 3217 rtw89_core_rfk_track(rtwdev); 3218 rtw89_phy_ra_update(rtwdev); 3219 rtw89_phy_cfo_track(rtwdev); 3220 rtw89_phy_tx_path_div_track(rtwdev); 3221 rtw89_phy_antdiv_track(rtwdev); 3222 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3223 rtw89_phy_edcca_track(rtwdev); 3224 rtw89_tas_track(rtwdev); 3225 rtw89_chanctx_track(rtwdev); 3226 3227 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3228 rtw89_enter_lps_track(rtwdev); 3229 3230 out: 3231 mutex_unlock(&rtwdev->mutex); 3232 } 3233 3234 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3235 { 3236 unsigned long bit; 3237 3238 bit = find_first_zero_bit(addr, size); 3239 if (bit < size) 3240 set_bit(bit, addr); 3241 3242 return bit; 3243 } 3244 3245 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3246 { 3247 clear_bit(bit, addr); 3248 } 3249 3250 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3251 { 3252 bitmap_zero(addr, nbits); 3253 } 3254 3255 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3256 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3257 { 3258 const struct rtw89_chip_info *chip = rtwdev->chip; 3259 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3260 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3261 u8 idx; 3262 int i; 3263 3264 lockdep_assert_held(&rtwdev->mutex); 3265 3266 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3267 if (idx == chip->bacam_num) { 3268 /* allocate a static BA CAM to tid=0/5, so replace the existing 3269 * one if BA CAM is full. Hardware will process the original tid 3270 * automatically. 3271 */ 3272 if (tid != 0 && tid != 5) 3273 return -ENOSPC; 3274 3275 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3276 tmp = &cam_info->ba_cam_entry[i]; 3277 if (tmp->tid == 0 || tmp->tid == 5) 3278 continue; 3279 3280 idx = i; 3281 entry = tmp; 3282 list_del(&entry->list); 3283 break; 3284 } 3285 3286 if (!entry) 3287 return -ENOSPC; 3288 } else { 3289 entry = &cam_info->ba_cam_entry[idx]; 3290 } 3291 3292 entry->tid = tid; 3293 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3294 3295 *cam_idx = idx; 3296 3297 return 0; 3298 } 3299 3300 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3301 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3302 { 3303 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3304 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3305 u8 idx; 3306 3307 lockdep_assert_held(&rtwdev->mutex); 3308 3309 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3310 if (entry->tid != tid) 3311 continue; 3312 3313 idx = entry - cam_info->ba_cam_entry; 3314 list_del(&entry->list); 3315 3316 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3317 *cam_idx = idx; 3318 return 0; 3319 } 3320 3321 return -ENOENT; 3322 } 3323 3324 #define RTW89_TYPE_MAPPING(_type) \ 3325 case NL80211_IFTYPE_ ## _type: \ 3326 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3327 break 3328 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3329 { 3330 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3331 3332 switch (vif->type) { 3333 case NL80211_IFTYPE_STATION: 3334 if (vif->p2p) 3335 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3336 else 3337 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3338 break; 3339 case NL80211_IFTYPE_AP: 3340 if (vif->p2p) 3341 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3342 else 3343 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3344 break; 3345 RTW89_TYPE_MAPPING(ADHOC); 3346 RTW89_TYPE_MAPPING(MONITOR); 3347 RTW89_TYPE_MAPPING(MESH_POINT); 3348 default: 3349 WARN_ON(1); 3350 break; 3351 } 3352 3353 switch (vif->type) { 3354 case NL80211_IFTYPE_AP: 3355 case NL80211_IFTYPE_MESH_POINT: 3356 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3357 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3358 break; 3359 case NL80211_IFTYPE_ADHOC: 3360 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3361 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3362 break; 3363 case NL80211_IFTYPE_STATION: 3364 if (assoc) { 3365 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3366 rtwvif->trigger = vif->bss_conf.he_support; 3367 } else { 3368 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3369 rtwvif->trigger = false; 3370 } 3371 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3372 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3373 break; 3374 case NL80211_IFTYPE_MONITOR: 3375 break; 3376 default: 3377 WARN_ON(1); 3378 break; 3379 } 3380 } 3381 3382 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3383 struct ieee80211_vif *vif, 3384 struct ieee80211_sta *sta) 3385 { 3386 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3387 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3388 struct rtw89_hal *hal = &rtwdev->hal; 3389 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3390 int i; 3391 int ret; 3392 3393 rtwsta->rtwdev = rtwdev; 3394 rtwsta->rtwvif = rtwvif; 3395 rtwsta->prev_rssi = 0; 3396 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3397 skb_queue_head_init(&rtwsta->roc_queue); 3398 3399 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3400 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3401 3402 ewma_rssi_init(&rtwsta->avg_rssi); 3403 ewma_snr_init(&rtwsta->avg_snr); 3404 for (i = 0; i < ant_num; i++) { 3405 ewma_rssi_init(&rtwsta->rssi[i]); 3406 ewma_evm_init(&rtwsta->evm_min[i]); 3407 ewma_evm_init(&rtwsta->evm_max[i]); 3408 } 3409 3410 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3411 /* for station mode, assign the mac_id from itself */ 3412 rtwsta->mac_id = rtwvif->mac_id; 3413 3414 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 3415 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif, true); 3416 if (ret) 3417 return ret; 3418 3419 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3420 BTC_ROLE_MSTS_STA_CONN_START); 3421 rtw89_chip_rfk_channel(rtwdev); 3422 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3423 rtwsta->mac_id = rtw89_acquire_mac_id(rtwdev); 3424 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3425 return -ENOSPC; 3426 3427 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3428 if (ret) { 3429 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3430 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3431 return ret; 3432 } 3433 3434 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3435 RTW89_ROLE_CREATE); 3436 if (ret) { 3437 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3438 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3439 return ret; 3440 } 3441 3442 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 3443 if (ret) 3444 return ret; 3445 3446 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 3447 if (ret) 3448 return ret; 3449 3450 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3451 } 3452 3453 return 0; 3454 } 3455 3456 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3457 struct ieee80211_vif *vif, 3458 struct ieee80211_sta *sta) 3459 { 3460 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3461 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3462 3463 if (vif->type == NL80211_IFTYPE_STATION) 3464 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3465 3466 rtwdev->total_sta_assoc--; 3467 if (sta->tdls) 3468 rtwvif->tdls_peer--; 3469 rtwsta->disassoc = true; 3470 3471 return 0; 3472 } 3473 3474 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3475 struct ieee80211_vif *vif, 3476 struct ieee80211_sta *sta) 3477 { 3478 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3479 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3480 int ret; 3481 3482 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3483 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3484 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3485 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3486 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3487 3488 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3489 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3490 if (sta->tdls) 3491 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3492 3493 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3494 rtw89_vif_type_mapping(vif, false); 3495 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3496 } 3497 3498 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3499 if (ret) { 3500 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3501 return ret; 3502 } 3503 3504 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3505 if (ret) { 3506 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3507 return ret; 3508 } 3509 3510 /* update cam aid mac_id net_type */ 3511 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3512 if (ret) { 3513 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3514 return ret; 3515 } 3516 3517 return ret; 3518 } 3519 3520 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3521 struct ieee80211_vif *vif, 3522 struct ieee80211_sta *sta) 3523 { 3524 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3525 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3526 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3527 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3528 rtwvif->sub_entity_idx); 3529 int ret; 3530 3531 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3532 if (sta->tdls) { 3533 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3534 if (ret) { 3535 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3536 return ret; 3537 } 3538 } 3539 3540 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3541 if (ret) { 3542 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3543 return ret; 3544 } 3545 } 3546 3547 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3548 if (ret) { 3549 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3550 return ret; 3551 } 3552 3553 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3554 if (ret) { 3555 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3556 return ret; 3557 } 3558 3559 /* update cam aid mac_id net_type */ 3560 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3561 if (ret) { 3562 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3563 return ret; 3564 } 3565 3566 rtwdev->total_sta_assoc++; 3567 if (sta->tdls) 3568 rtwvif->tdls_peer++; 3569 rtw89_phy_ra_assoc(rtwdev, sta); 3570 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3571 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3572 3573 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3574 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3575 3576 if (bss_conf->he_support && 3577 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3578 rtwsta->er_cap = true; 3579 3580 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3581 BTC_ROLE_MSTS_STA_CONN_END); 3582 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3583 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3584 3585 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3586 if (ret) { 3587 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3588 return ret; 3589 } 3590 3591 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 3592 } 3593 3594 return ret; 3595 } 3596 3597 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3598 struct ieee80211_vif *vif, 3599 struct ieee80211_sta *sta) 3600 { 3601 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3602 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3603 int ret; 3604 3605 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3606 rtw89_reg_6ghz_recalc(rtwdev, rtwvif, false); 3607 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3608 BTC_ROLE_MSTS_STA_DIS_CONN); 3609 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3610 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3611 3612 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3613 RTW89_ROLE_REMOVE); 3614 if (ret) { 3615 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3616 return ret; 3617 } 3618 3619 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3620 } 3621 3622 return 0; 3623 } 3624 3625 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3626 struct ieee80211_sta *sta, 3627 struct cfg80211_tid_cfg *tid_conf) 3628 { 3629 struct ieee80211_txq *txq; 3630 struct rtw89_txq *rtwtxq; 3631 u32 mask = tid_conf->mask; 3632 u8 tids = tid_conf->tids; 3633 int tids_nbit = BITS_PER_BYTE; 3634 int i; 3635 3636 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3637 if (!tids) 3638 break; 3639 3640 if (!(tids & BIT(0))) 3641 continue; 3642 3643 txq = sta->txq[i]; 3644 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3645 3646 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3647 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3648 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3649 } else { 3650 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3651 ieee80211_stop_tx_ba_session(sta, txq->tid); 3652 spin_lock_bh(&rtwdev->ba_lock); 3653 list_del_init(&rtwtxq->list); 3654 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3655 spin_unlock_bh(&rtwdev->ba_lock); 3656 } 3657 } 3658 3659 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3660 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3661 sta->max_amsdu_subframes = 0; 3662 else 3663 sta->max_amsdu_subframes = 1; 3664 } 3665 } 3666 } 3667 3668 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3669 struct ieee80211_sta *sta, 3670 struct cfg80211_tid_config *tid_config) 3671 { 3672 int i; 3673 3674 for (i = 0; i < tid_config->n_tid_conf; i++) 3675 _rtw89_core_set_tid_config(rtwdev, sta, 3676 &tid_config->tid_conf[i]); 3677 } 3678 3679 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3680 struct ieee80211_sta_ht_cap *ht_cap) 3681 { 3682 static const __le16 highest[RF_PATH_MAX] = { 3683 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3684 }; 3685 struct rtw89_hal *hal = &rtwdev->hal; 3686 u8 nss = hal->rx_nss; 3687 int i; 3688 3689 ht_cap->ht_supported = true; 3690 ht_cap->cap = 0; 3691 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3692 IEEE80211_HT_CAP_MAX_AMSDU | 3693 IEEE80211_HT_CAP_TX_STBC | 3694 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3695 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3696 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3697 IEEE80211_HT_CAP_DSSSCCK40 | 3698 IEEE80211_HT_CAP_SGI_40; 3699 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3700 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3701 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3702 for (i = 0; i < nss; i++) 3703 ht_cap->mcs.rx_mask[i] = 0xFF; 3704 ht_cap->mcs.rx_mask[4] = 0x01; 3705 ht_cap->mcs.rx_highest = highest[nss - 1]; 3706 } 3707 3708 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3709 struct ieee80211_sta_vht_cap *vht_cap) 3710 { 3711 static const __le16 highest_bw80[RF_PATH_MAX] = { 3712 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3713 }; 3714 static const __le16 highest_bw160[RF_PATH_MAX] = { 3715 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3716 }; 3717 const struct rtw89_chip_info *chip = rtwdev->chip; 3718 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 3719 highest_bw160 : highest_bw80; 3720 struct rtw89_hal *hal = &rtwdev->hal; 3721 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3722 u8 sts_cap = 3; 3723 int i; 3724 3725 for (i = 0; i < 8; i++) { 3726 if (i < hal->tx_nss) 3727 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3728 else 3729 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3730 if (i < hal->rx_nss) 3731 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3732 else 3733 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3734 } 3735 3736 vht_cap->vht_supported = true; 3737 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3738 IEEE80211_VHT_CAP_SHORT_GI_80 | 3739 IEEE80211_VHT_CAP_RXSTBC_1 | 3740 IEEE80211_VHT_CAP_HTC_VHT | 3741 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3742 0; 3743 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3744 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3745 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3746 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3747 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3748 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3749 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3750 IEEE80211_VHT_CAP_SHORT_GI_160; 3751 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3752 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3753 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3754 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3755 3756 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 3757 vht_cap->vht_mcs.tx_highest |= 3758 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 3759 } 3760 3761 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3762 enum nl80211_band band, 3763 enum nl80211_iftype iftype, 3764 struct ieee80211_sband_iftype_data *iftype_data) 3765 { 3766 const struct rtw89_chip_info *chip = rtwdev->chip; 3767 struct rtw89_hal *hal = &rtwdev->hal; 3768 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3769 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3770 struct ieee80211_sta_he_cap *he_cap; 3771 int nss = hal->rx_nss; 3772 u8 *mac_cap_info; 3773 u8 *phy_cap_info; 3774 u16 mcs_map = 0; 3775 int i; 3776 3777 for (i = 0; i < 8; i++) { 3778 if (i < nss) 3779 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3780 else 3781 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3782 } 3783 3784 he_cap = &iftype_data->he_cap; 3785 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3786 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3787 3788 he_cap->has_he = true; 3789 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3790 if (iftype == NL80211_IFTYPE_STATION) 3791 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3792 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3793 IEEE80211_HE_MAC_CAP2_BSR; 3794 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3795 if (iftype == NL80211_IFTYPE_AP) 3796 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3797 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3798 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3799 if (iftype == NL80211_IFTYPE_STATION) 3800 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3801 if (band == NL80211_BAND_2GHZ) { 3802 phy_cap_info[0] = 3803 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3804 } else { 3805 phy_cap_info[0] = 3806 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3807 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3808 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3809 } 3810 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3811 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3812 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3813 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3814 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3815 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3816 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3817 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3818 if (iftype == NL80211_IFTYPE_STATION) 3819 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3820 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3821 if (iftype == NL80211_IFTYPE_AP) 3822 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3823 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3824 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3825 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3826 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3827 phy_cap_info[5] = no_ng16 ? 0 : 3828 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3829 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3830 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3831 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3832 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3833 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3834 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3835 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3836 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3837 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3838 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3839 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3840 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3841 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3842 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3843 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3844 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3845 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3846 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3847 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3848 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3849 if (iftype == NL80211_IFTYPE_STATION) 3850 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3851 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3852 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3853 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 3854 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3855 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3856 } 3857 3858 if (band == NL80211_BAND_6GHZ) { 3859 __le16 capa; 3860 3861 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3862 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3863 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3864 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3865 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3866 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3867 iftype_data->he_6ghz_capa.capa = capa; 3868 } 3869 } 3870 3871 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 3872 enum nl80211_band band, 3873 enum nl80211_iftype iftype, 3874 struct ieee80211_sband_iftype_data *iftype_data) 3875 { 3876 const struct rtw89_chip_info *chip = rtwdev->chip; 3877 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 3878 struct ieee80211_eht_mcs_nss_supp *eht_nss; 3879 struct ieee80211_sta_eht_cap *eht_cap; 3880 struct rtw89_hal *hal = &rtwdev->hal; 3881 bool support_320mhz = false; 3882 int sts = 8; 3883 u8 val; 3884 3885 if (chip->chip_gen == RTW89_CHIP_AX) 3886 return; 3887 3888 if (band == NL80211_BAND_6GHZ && 3889 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 3890 support_320mhz = true; 3891 3892 eht_cap = &iftype_data->eht_cap; 3893 eht_cap_elem = &eht_cap->eht_cap_elem; 3894 eht_nss = &eht_cap->eht_mcs_nss_supp; 3895 3896 eht_cap->has_eht = true; 3897 3898 eht_cap_elem->mac_cap_info[0] = 3899 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 3900 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 3901 eht_cap_elem->mac_cap_info[1] = 0; 3902 3903 eht_cap_elem->phy_cap_info[0] = 3904 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 3905 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 3906 if (support_320mhz) 3907 eht_cap_elem->phy_cap_info[0] |= 3908 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 3909 3910 eht_cap_elem->phy_cap_info[0] |= 3911 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 3912 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 3913 eht_cap_elem->phy_cap_info[1] = 3914 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 3915 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 3916 u8_encode_bits(sts - 1, 3917 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 3918 if (support_320mhz) 3919 eht_cap_elem->phy_cap_info[1] |= 3920 u8_encode_bits(sts - 1, 3921 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 3922 3923 eht_cap_elem->phy_cap_info[2] = 0; 3924 3925 eht_cap_elem->phy_cap_info[3] = 3926 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 3927 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 3928 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 3929 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 3930 3931 eht_cap_elem->phy_cap_info[4] = 3932 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 3933 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 3934 3935 eht_cap_elem->phy_cap_info[5] = 3936 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 3937 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 3938 3939 eht_cap_elem->phy_cap_info[6] = 0; 3940 eht_cap_elem->phy_cap_info[7] = 0; 3941 eht_cap_elem->phy_cap_info[8] = 0; 3942 3943 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 3944 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 3945 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 3946 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 3947 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 3948 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 3949 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 3950 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 3951 if (support_320mhz) { 3952 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 3953 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 3954 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 3955 } 3956 } 3957 3958 #define RTW89_SBAND_IFTYPES_NR 2 3959 3960 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 3961 enum nl80211_band band, 3962 struct ieee80211_supported_band *sband) 3963 { 3964 struct ieee80211_sband_iftype_data *iftype_data; 3965 enum nl80211_iftype iftype; 3966 int idx = 0; 3967 3968 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3969 if (!iftype_data) 3970 return; 3971 3972 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 3973 switch (iftype) { 3974 case NL80211_IFTYPE_STATION: 3975 case NL80211_IFTYPE_AP: 3976 break; 3977 default: 3978 continue; 3979 } 3980 3981 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3982 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3983 break; 3984 } 3985 3986 iftype_data[idx].types_mask = BIT(iftype); 3987 3988 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 3989 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 3990 3991 idx++; 3992 } 3993 3994 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3995 } 3996 3997 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3998 { 3999 struct ieee80211_hw *hw = rtwdev->hw; 4000 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 4001 struct ieee80211_supported_band *sband_6ghz = NULL; 4002 u32 size = sizeof(struct ieee80211_supported_band); 4003 u8 support_bands = rtwdev->chip->support_bands; 4004 4005 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4006 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 4007 if (!sband_2ghz) 4008 goto err; 4009 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 4010 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 4011 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 4012 } 4013 4014 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4015 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 4016 if (!sband_5ghz) 4017 goto err; 4018 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 4019 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 4020 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 4021 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 4022 } 4023 4024 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4025 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 4026 if (!sband_6ghz) 4027 goto err; 4028 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 4029 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 4030 } 4031 4032 return 0; 4033 4034 err: 4035 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4036 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4037 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4038 if (sband_2ghz) 4039 kfree((__force void *)sband_2ghz->iftype_data); 4040 if (sband_5ghz) 4041 kfree((__force void *)sband_5ghz->iftype_data); 4042 if (sband_6ghz) 4043 kfree((__force void *)sband_6ghz->iftype_data); 4044 kfree(sband_2ghz); 4045 kfree(sband_5ghz); 4046 kfree(sband_6ghz); 4047 return -ENOMEM; 4048 } 4049 4050 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 4051 { 4052 struct ieee80211_hw *hw = rtwdev->hw; 4053 4054 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 4055 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 4056 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 4057 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 4058 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 4059 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 4060 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 4061 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 4062 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 4063 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4064 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4065 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4066 } 4067 4068 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4069 { 4070 int i; 4071 4072 for (i = 0; i < RTW89_PHY_MAX; i++) 4073 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4074 for (i = 0; i < RTW89_PHY_MAX; i++) 4075 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4076 } 4077 4078 void rtw89_core_update_beacon_work(struct work_struct *work) 4079 { 4080 struct rtw89_dev *rtwdev; 4081 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4082 update_beacon_work); 4083 4084 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 4085 return; 4086 4087 rtwdev = rtwvif->rtwdev; 4088 mutex_lock(&rtwdev->mutex); 4089 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif); 4090 mutex_unlock(&rtwdev->mutex); 4091 } 4092 4093 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4094 { 4095 struct completion *cmpl = &wait->completion; 4096 unsigned long time_left; 4097 unsigned int cur; 4098 4099 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4100 if (cur != RTW89_WAIT_COND_IDLE) 4101 return -EBUSY; 4102 4103 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4104 if (time_left == 0) { 4105 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4106 return -ETIMEDOUT; 4107 } 4108 4109 if (wait->data.err) 4110 return -EFAULT; 4111 4112 return 0; 4113 } 4114 4115 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4116 const struct rtw89_completion_data *data) 4117 { 4118 unsigned int cur; 4119 4120 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4121 if (cur != cond) 4122 return; 4123 4124 wait->data = *data; 4125 complete(&wait->completion); 4126 } 4127 4128 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4129 { 4130 u16 bt_req_len; 4131 4132 switch (event) { 4133 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4134 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4135 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4136 "coex updates BT req len to %d TU\n", bt_req_len); 4137 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4138 break; 4139 default: 4140 if (event < NUM_OF_RTW89_BTC_HMSG) 4141 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4142 "unhandled BTC HMSG event: %d\n", event); 4143 else 4144 rtw89_warn(rtwdev, 4145 "unrecognized BTC HMSG event: %d\n", event); 4146 break; 4147 } 4148 } 4149 4150 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4151 { 4152 const struct dmi_system_id *match; 4153 enum rtw89_quirks quirk; 4154 4155 if (!quirks) 4156 return; 4157 4158 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4159 quirk = (uintptr_t)match->driver_data; 4160 if (quirk >= NUM_OF_RTW89_QUIRKS) 4161 continue; 4162 4163 set_bit(quirk, rtwdev->quirks); 4164 } 4165 } 4166 EXPORT_SYMBOL(rtw89_check_quirks); 4167 4168 int rtw89_core_start(struct rtw89_dev *rtwdev) 4169 { 4170 int ret; 4171 4172 ret = rtw89_mac_init(rtwdev); 4173 if (ret) { 4174 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4175 return ret; 4176 } 4177 4178 rtw89_btc_ntfy_poweron(rtwdev); 4179 4180 /* efuse process */ 4181 4182 /* pre-config BB/RF, BB reset/RFC reset */ 4183 ret = rtw89_chip_reset_bb_rf(rtwdev); 4184 if (ret) 4185 return ret; 4186 4187 rtw89_phy_init_bb_reg(rtwdev); 4188 rtw89_chip_bb_postinit(rtwdev); 4189 rtw89_phy_init_rf_reg(rtwdev, false); 4190 4191 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4192 4193 rtw89_phy_dm_init(rtwdev); 4194 4195 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 4196 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 4197 4198 rtw89_tas_reset(rtwdev); 4199 4200 ret = rtw89_hci_start(rtwdev); 4201 if (ret) { 4202 rtw89_err(rtwdev, "failed to start hci\n"); 4203 return ret; 4204 } 4205 4206 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4207 RTW89_TRACK_WORK_PERIOD); 4208 4209 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4210 4211 rtw89_chip_rfk_init_late(rtwdev); 4212 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4213 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4214 rtw89_fw_h2c_init_ba_cam(rtwdev); 4215 4216 return 0; 4217 } 4218 4219 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4220 { 4221 struct rtw89_btc *btc = &rtwdev->btc; 4222 4223 /* Prvent to stop twice; enter_ips and ops_stop */ 4224 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4225 return; 4226 4227 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4228 4229 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4230 4231 mutex_unlock(&rtwdev->mutex); 4232 4233 cancel_work_sync(&rtwdev->c2h_work); 4234 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4235 cancel_work_sync(&btc->eapol_notify_work); 4236 cancel_work_sync(&btc->arp_notify_work); 4237 cancel_work_sync(&btc->dhcp_notify_work); 4238 cancel_work_sync(&btc->icmp_notify_work); 4239 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4240 cancel_delayed_work_sync(&rtwdev->track_work); 4241 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4242 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4243 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4244 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4245 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4246 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4247 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4248 4249 mutex_lock(&rtwdev->mutex); 4250 4251 rtw89_btc_ntfy_poweroff(rtwdev); 4252 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4253 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4254 rtw89_hci_stop(rtwdev); 4255 rtw89_hci_deinit(rtwdev); 4256 rtw89_mac_pwr_off(rtwdev); 4257 rtw89_hci_reset(rtwdev); 4258 } 4259 4260 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4261 { 4262 const struct rtw89_chip_info *chip = rtwdev->chip; 4263 u8 mac_id_num = chip->support_macid_num; 4264 u8 mac_id; 4265 4266 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4267 if (mac_id == mac_id_num) 4268 return RTW89_MAX_MAC_ID_NUM; 4269 4270 set_bit(mac_id, rtwdev->mac_id_map); 4271 return mac_id; 4272 } 4273 4274 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4275 { 4276 clear_bit(mac_id, rtwdev->mac_id_map); 4277 } 4278 4279 int rtw89_core_init(struct rtw89_dev *rtwdev) 4280 { 4281 struct rtw89_btc *btc = &rtwdev->btc; 4282 u8 band; 4283 4284 INIT_LIST_HEAD(&rtwdev->ba_list); 4285 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4286 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4287 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4288 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4289 if (!(rtwdev->chip->support_bands & BIT(band))) 4290 continue; 4291 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4292 } 4293 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4294 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4295 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4296 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4297 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4298 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4299 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4300 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4301 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4302 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4303 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4304 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4305 if (!rtwdev->txq_wq) 4306 return -ENOMEM; 4307 spin_lock_init(&rtwdev->ba_lock); 4308 spin_lock_init(&rtwdev->rpwm_lock); 4309 mutex_init(&rtwdev->mutex); 4310 mutex_init(&rtwdev->rf_mutex); 4311 rtwdev->total_sta_assoc = 0; 4312 4313 rtw89_init_wait(&rtwdev->mcc.wait); 4314 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4315 4316 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4317 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4318 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4319 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4320 4321 skb_queue_head_init(&rtwdev->c2h_queue); 4322 rtw89_core_ppdu_sts_init(rtwdev); 4323 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4324 4325 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4326 rtwdev->dbcc_en = false; 4327 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4328 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4329 4330 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4331 rtwdev->dbcc_en = true; 4332 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4333 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4334 } 4335 4336 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4337 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4338 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4339 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4340 4341 init_completion(&rtwdev->fw.req.completion); 4342 init_completion(&rtwdev->rfk_wait.completion); 4343 4344 schedule_work(&rtwdev->load_firmware_work); 4345 4346 rtw89_ser_init(rtwdev); 4347 rtw89_entity_init(rtwdev); 4348 rtw89_tas_init(rtwdev); 4349 4350 return 0; 4351 } 4352 EXPORT_SYMBOL(rtw89_core_init); 4353 4354 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4355 { 4356 rtw89_ser_deinit(rtwdev); 4357 rtw89_unload_firmware(rtwdev); 4358 rtw89_fw_free_all_early_h2c(rtwdev); 4359 4360 destroy_workqueue(rtwdev->txq_wq); 4361 mutex_destroy(&rtwdev->rf_mutex); 4362 mutex_destroy(&rtwdev->mutex); 4363 } 4364 EXPORT_SYMBOL(rtw89_core_deinit); 4365 4366 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4367 const u8 *mac_addr, bool hw_scan) 4368 { 4369 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4370 rtwvif->sub_entity_idx); 4371 4372 rtwdev->scanning = true; 4373 rtw89_leave_lps(rtwdev); 4374 if (hw_scan) 4375 rtw89_leave_ips_by_hwflags(rtwdev); 4376 4377 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4378 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4379 rtw89_chip_rfk_scan(rtwdev, true); 4380 rtw89_hci_recalc_int_mit(rtwdev); 4381 rtw89_phy_config_edcca(rtwdev, true); 4382 4383 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4384 } 4385 4386 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4387 struct ieee80211_vif *vif, bool hw_scan) 4388 { 4389 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4390 4391 if (!rtwvif) 4392 return; 4393 4394 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4395 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4396 4397 rtw89_chip_rfk_scan(rtwdev, false); 4398 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4399 rtw89_phy_config_edcca(rtwdev, false); 4400 4401 rtwdev->scanning = false; 4402 rtwdev->dig.bypass_dig = true; 4403 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4404 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4405 } 4406 4407 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4408 { 4409 const struct rtw89_chip_info *chip = rtwdev->chip; 4410 int ret; 4411 u8 val; 4412 u8 cv; 4413 4414 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4415 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4416 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4417 cv = CHIP_CAV; 4418 else 4419 cv = CHIP_CBV; 4420 } 4421 4422 rtwdev->hal.cv = cv; 4423 4424 if (rtw89_is_rtl885xb(rtwdev)) { 4425 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4426 if (ret) 4427 return; 4428 4429 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4430 } 4431 } 4432 4433 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4434 { 4435 rtwdev->hal.support_cckpd = 4436 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4437 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4438 rtwdev->hal.support_igi = 4439 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4440 } 4441 4442 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4443 { 4444 const struct rtw89_chip_info *chip = rtwdev->chip; 4445 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4446 struct rtw89_efuse *efuse = &rtwdev->efuse; 4447 const struct rtw89_rfe_parms *sel; 4448 u8 rfe_type = efuse->rfe_type; 4449 4450 if (!conf) { 4451 sel = chip->dflt_parms; 4452 goto out; 4453 } 4454 4455 while (conf->rfe_parms) { 4456 if (rfe_type == conf->rfe_type) { 4457 sel = conf->rfe_parms; 4458 goto out; 4459 } 4460 conf++; 4461 } 4462 4463 sel = chip->dflt_parms; 4464 4465 out: 4466 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4467 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4468 } 4469 4470 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4471 { 4472 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4473 int ret; 4474 4475 ret = rtw89_mac_partial_init(rtwdev, false); 4476 if (ret) 4477 return ret; 4478 4479 ret = mac->parse_efuse_map(rtwdev); 4480 if (ret) 4481 return ret; 4482 4483 ret = mac->parse_phycap_map(rtwdev); 4484 if (ret) 4485 return ret; 4486 4487 ret = rtw89_mac_setup_phycap(rtwdev); 4488 if (ret) 4489 return ret; 4490 4491 rtw89_core_setup_phycap(rtwdev); 4492 4493 rtw89_hci_mac_pre_deinit(rtwdev); 4494 4495 rtw89_mac_pwr_off(rtwdev); 4496 4497 return 0; 4498 } 4499 4500 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4501 { 4502 rtw89_chip_fem_setup(rtwdev); 4503 4504 return 0; 4505 } 4506 4507 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4508 { 4509 int ret; 4510 4511 rtw89_read_chip_ver(rtwdev); 4512 4513 ret = rtw89_wait_firmware_completion(rtwdev); 4514 if (ret) { 4515 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4516 return ret; 4517 } 4518 4519 ret = rtw89_fw_recognize(rtwdev); 4520 if (ret) { 4521 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4522 return ret; 4523 } 4524 4525 ret = rtw89_chip_efuse_info_setup(rtwdev); 4526 if (ret) 4527 return ret; 4528 4529 ret = rtw89_fw_recognize_elements(rtwdev); 4530 if (ret) { 4531 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4532 return ret; 4533 } 4534 4535 ret = rtw89_chip_board_info_setup(rtwdev); 4536 if (ret) 4537 return ret; 4538 4539 rtw89_core_setup_rfe_parms(rtwdev); 4540 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4541 4542 return 0; 4543 } 4544 EXPORT_SYMBOL(rtw89_chip_info_setup); 4545 4546 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4547 { 4548 const struct rtw89_chip_info *chip = rtwdev->chip; 4549 struct ieee80211_hw *hw = rtwdev->hw; 4550 struct rtw89_efuse *efuse = &rtwdev->efuse; 4551 struct rtw89_hal *hal = &rtwdev->hal; 4552 int ret; 4553 int tx_headroom = IEEE80211_HT_CTL_LEN; 4554 4555 hw->vif_data_size = sizeof(struct rtw89_vif); 4556 hw->sta_data_size = sizeof(struct rtw89_sta); 4557 hw->txq_data_size = sizeof(struct rtw89_txq); 4558 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4559 4560 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4561 4562 hw->extra_tx_headroom = tx_headroom; 4563 hw->queues = IEEE80211_NUM_ACS; 4564 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4565 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4566 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4567 4568 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 4569 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 4570 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 4571 4572 ieee80211_hw_set(hw, SIGNAL_DBM); 4573 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4574 ieee80211_hw_set(hw, MFP_CAPABLE); 4575 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4576 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4577 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4578 ieee80211_hw_set(hw, TX_AMSDU); 4579 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4580 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4581 ieee80211_hw_set(hw, SUPPORTS_PS); 4582 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4583 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4584 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4585 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4586 4587 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4588 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 4589 4590 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4591 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4592 4593 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4594 BIT(NL80211_IFTYPE_AP) | 4595 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4596 BIT(NL80211_IFTYPE_P2P_GO); 4597 4598 if (hal->ant_diversity) { 4599 hw->wiphy->available_antennas_tx = 0x3; 4600 hw->wiphy->available_antennas_rx = 0x3; 4601 } else { 4602 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4603 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4604 } 4605 4606 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4607 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4608 WIPHY_FLAG_AP_UAPSD | 4609 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 4610 4611 if (!chip->support_rnr) 4612 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4613 4614 if (chip->chip_gen == RTW89_CHIP_BE) 4615 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 4616 4617 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4618 4619 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4620 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4621 4622 #ifdef CONFIG_PM 4623 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4624 #endif 4625 4626 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4627 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4628 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4629 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4630 hw->wiphy->max_remain_on_channel_duration = 1000; 4631 4632 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4633 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 4634 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 4635 4636 ret = rtw89_core_set_supported_band(rtwdev); 4637 if (ret) { 4638 rtw89_err(rtwdev, "failed to set supported band\n"); 4639 return ret; 4640 } 4641 4642 ret = rtw89_regd_setup(rtwdev); 4643 if (ret) { 4644 rtw89_err(rtwdev, "failed to set up regd\n"); 4645 goto err_free_supported_band; 4646 } 4647 4648 hw->wiphy->sar_capa = &rtw89_sar_capa; 4649 4650 ret = ieee80211_register_hw(hw); 4651 if (ret) { 4652 rtw89_err(rtwdev, "failed to register hw\n"); 4653 goto err_free_supported_band; 4654 } 4655 4656 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4657 if (ret) { 4658 rtw89_err(rtwdev, "failed to init regd\n"); 4659 goto err_unregister_hw; 4660 } 4661 4662 return 0; 4663 4664 err_unregister_hw: 4665 ieee80211_unregister_hw(hw); 4666 err_free_supported_band: 4667 rtw89_core_clr_supported_band(rtwdev); 4668 4669 return ret; 4670 } 4671 4672 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4673 { 4674 struct ieee80211_hw *hw = rtwdev->hw; 4675 4676 ieee80211_unregister_hw(hw); 4677 rtw89_core_clr_supported_band(rtwdev); 4678 } 4679 4680 int rtw89_core_register(struct rtw89_dev *rtwdev) 4681 { 4682 int ret; 4683 4684 ret = rtw89_core_register_hw(rtwdev); 4685 if (ret) { 4686 rtw89_err(rtwdev, "failed to register core hw\n"); 4687 return ret; 4688 } 4689 4690 rtw89_debugfs_init(rtwdev); 4691 4692 return 0; 4693 } 4694 EXPORT_SYMBOL(rtw89_core_register); 4695 4696 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4697 { 4698 rtw89_core_unregister_hw(rtwdev); 4699 } 4700 EXPORT_SYMBOL(rtw89_core_unregister); 4701 4702 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4703 u32 bus_data_size, 4704 const struct rtw89_chip_info *chip) 4705 { 4706 struct rtw89_fw_info early_fw = {}; 4707 const struct firmware *firmware; 4708 struct ieee80211_hw *hw; 4709 struct rtw89_dev *rtwdev; 4710 struct ieee80211_ops *ops; 4711 u32 driver_data_size; 4712 int fw_format = -1; 4713 bool no_chanctx; 4714 4715 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4716 4717 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4718 if (!ops) 4719 goto err; 4720 4721 no_chanctx = chip->support_chanctx_num == 0 || 4722 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4723 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4724 4725 if (no_chanctx) { 4726 ops->add_chanctx = ieee80211_emulate_add_chanctx; 4727 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 4728 ops->change_chanctx = ieee80211_emulate_change_chanctx; 4729 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 4730 ops->assign_vif_chanctx = NULL; 4731 ops->unassign_vif_chanctx = NULL; 4732 ops->remain_on_channel = NULL; 4733 ops->cancel_remain_on_channel = NULL; 4734 } 4735 4736 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4737 hw = ieee80211_alloc_hw(driver_data_size, ops); 4738 if (!hw) 4739 goto err; 4740 4741 hw->wiphy->iface_combinations = rtw89_iface_combs; 4742 4743 if (no_chanctx || chip->support_chanctx_num == 1) 4744 hw->wiphy->n_iface_combinations = 1; 4745 else 4746 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4747 4748 rtwdev = hw->priv; 4749 rtwdev->hw = hw; 4750 rtwdev->dev = device; 4751 rtwdev->ops = ops; 4752 rtwdev->chip = chip; 4753 rtwdev->fw.req.firmware = firmware; 4754 rtwdev->fw.fw_format = fw_format; 4755 4756 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4757 no_chanctx ? "without" : "with"); 4758 4759 return rtwdev; 4760 4761 err: 4762 kfree(ops); 4763 release_firmware(firmware); 4764 return NULL; 4765 } 4766 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4767 4768 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4769 { 4770 kfree(rtwdev->ops); 4771 kfree(rtwdev->rfe_data); 4772 release_firmware(rtwdev->fw.req.firmware); 4773 ieee80211_free_hw(rtwdev->hw); 4774 } 4775 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4776 4777 MODULE_AUTHOR("Realtek Corporation"); 4778 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4779 MODULE_LICENSE("Dual BSD/GPL"); 4780