xref: /linux/drivers/net/can/rcar/rcar_canfd.c (revision 5fc31936081919a8572a3d644f3fbb258038f337)
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
3  *
4  * Copyright (C) 2015 Renesas Electronics Corp.
5  */
6 
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8  *  - CAN FD only mode
9  *  - Classical CAN (CAN 2.0) only mode
10  *
11  * This driver puts the controller in CAN FD only mode by default. In this
12  * mode, the controller acts as a CAN FD node that can also interoperate with
13  * CAN 2.0 nodes.
14  *
15  * To switch the controller to Classical CAN (CAN 2.0) only mode, add
16  * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
17  * also required to switch modes.
18  *
19  * Note: The h/w manual register naming convention is clumsy and not acceptable
20  * to use as it is in the driver. However, those names are added as comments
21  * wherever it is modified to a readable name.
22  */
23 
24 #include <linux/bitmap.h>
25 #include <linux/bitops.h>
26 #include <linux/can/dev.h>
27 #include <linux/clk.h>
28 #include <linux/errno.h>
29 #include <linux/ethtool.h>
30 #include <linux/interrupt.h>
31 #include <linux/iopoll.h>
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/netdevice.h>
36 #include <linux/of.h>
37 #include <linux/phy/phy.h>
38 #include <linux/platform_device.h>
39 #include <linux/reset.h>
40 #include <linux/types.h>
41 
42 #define RCANFD_DRV_NAME			"rcar_canfd"
43 
44 /* Global register bits */
45 
46 /* RSCFDnCFDGRMCFG */
47 #define RCANFD_GRMCFG_RCMC		BIT(0)
48 
49 /* RSCFDnCFDGCFG / RSCFDnGCFG */
50 #define RCANFD_GCFG_EEFE		BIT(6)
51 #define RCANFD_GCFG_CMPOC		BIT(5)	/* CAN FD only */
52 #define RCANFD_GCFG_DCS			BIT(4)
53 #define RCANFD_GCFG_DCE			BIT(1)
54 #define RCANFD_GCFG_TPRI		BIT(0)
55 
56 /* RSCFDnCFDGCTR / RSCFDnGCTR */
57 #define RCANFD_GCTR_TSRST		BIT(16)
58 #define RCANFD_GCTR_CFMPOFIE		BIT(11)	/* CAN FD only */
59 #define RCANFD_GCTR_THLEIE		BIT(10)
60 #define RCANFD_GCTR_MEIE		BIT(9)
61 #define RCANFD_GCTR_DEIE		BIT(8)
62 #define RCANFD_GCTR_GSLPR		BIT(2)
63 #define RCANFD_GCTR_GMDC_MASK		(0x3)
64 #define RCANFD_GCTR_GMDC_GOPM		(0x0)
65 #define RCANFD_GCTR_GMDC_GRESET		(0x1)
66 #define RCANFD_GCTR_GMDC_GTEST		(0x2)
67 
68 /* RSCFDnCFDGSTS / RSCFDnGSTS */
69 #define RCANFD_GSTS_GRAMINIT		BIT(3)
70 #define RCANFD_GSTS_GSLPSTS		BIT(2)
71 #define RCANFD_GSTS_GHLTSTS		BIT(1)
72 #define RCANFD_GSTS_GRSTSTS		BIT(0)
73 /* Non-operational status */
74 #define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
75 
76 /* RSCFDnCFDGERFL / RSCFDnGERFL */
77 #define RCANFD_GERFL_EEF0_7		GENMASK(23, 16)
78 #define RCANFD_GERFL_EEF(ch)		BIT(16 + (ch))
79 #define RCANFD_GERFL_CMPOF		BIT(3)	/* CAN FD only */
80 #define RCANFD_GERFL_THLES		BIT(2)
81 #define RCANFD_GERFL_MES		BIT(1)
82 #define RCANFD_GERFL_DEF		BIT(0)
83 
84 #define RCANFD_GERFL_ERR(gpriv, x) \
85 	((x) & (reg_gen4(gpriv, RCANFD_GERFL_EEF0_7, \
86 			 RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
87 		RCANFD_GERFL_MES | \
88 		((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
89 
90 /* AFL Rx rules registers */
91 
92 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
93 #define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
94 	(((x) & reg_gen4(gpriv, 0x1ff, 0xff)) << \
95 	 (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
96 
97 #define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
98 	(((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
99 	 reg_gen4(gpriv, 0x1ff, 0xff))
100 
101 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
102 #define RCANFD_GAFLECTR_AFLDAE		BIT(8)
103 #define RCANFD_GAFLECTR_AFLPN(gpriv, x)	((x) & reg_gen4(gpriv, 0x7f, 0x1f))
104 
105 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
106 #define RCANFD_GAFLID_GAFLLB		BIT(29)
107 
108 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
109 #define RCANFD_GAFLP1_GAFLFDP(x)	(1 << (x))
110 
111 /* Channel register bits */
112 
113 /* RSCFDnCmCFG - Classical CAN only */
114 #define RCANFD_CFG_SJW(x)		(((x) & 0x3) << 24)
115 #define RCANFD_CFG_TSEG2(x)		(((x) & 0x7) << 20)
116 #define RCANFD_CFG_TSEG1(x)		(((x) & 0xf) << 16)
117 #define RCANFD_CFG_BRP(x)		(((x) & 0x3ff) << 0)
118 
119 /* RSCFDnCFDCmNCFG - CAN FD only */
120 #define RCANFD_NCFG_NTSEG2(gpriv, x) \
121 	(((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
122 
123 #define RCANFD_NCFG_NTSEG1(gpriv, x) \
124 	(((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
125 
126 #define RCANFD_NCFG_NSJW(gpriv, x) \
127 	(((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
128 
129 #define RCANFD_NCFG_NBRP(x)		(((x) & 0x3ff) << 0)
130 
131 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
132 #define RCANFD_CCTR_CTME		BIT(24)
133 #define RCANFD_CCTR_ERRD		BIT(23)
134 #define RCANFD_CCTR_BOM_MASK		(0x3 << 21)
135 #define RCANFD_CCTR_BOM_ISO		(0x0 << 21)
136 #define RCANFD_CCTR_BOM_BENTRY		(0x1 << 21)
137 #define RCANFD_CCTR_BOM_BEND		(0x2 << 21)
138 #define RCANFD_CCTR_TDCVFIE		BIT(19)
139 #define RCANFD_CCTR_SOCOIE		BIT(18)
140 #define RCANFD_CCTR_EOCOIE		BIT(17)
141 #define RCANFD_CCTR_TAIE		BIT(16)
142 #define RCANFD_CCTR_ALIE		BIT(15)
143 #define RCANFD_CCTR_BLIE		BIT(14)
144 #define RCANFD_CCTR_OLIE		BIT(13)
145 #define RCANFD_CCTR_BORIE		BIT(12)
146 #define RCANFD_CCTR_BOEIE		BIT(11)
147 #define RCANFD_CCTR_EPIE		BIT(10)
148 #define RCANFD_CCTR_EWIE		BIT(9)
149 #define RCANFD_CCTR_BEIE		BIT(8)
150 #define RCANFD_CCTR_CSLPR		BIT(2)
151 #define RCANFD_CCTR_CHMDC_MASK		(0x3)
152 #define RCANFD_CCTR_CHDMC_COPM		(0x0)
153 #define RCANFD_CCTR_CHDMC_CRESET	(0x1)
154 #define RCANFD_CCTR_CHDMC_CHLT		(0x2)
155 
156 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
157 #define RCANFD_CSTS_COMSTS		BIT(7)
158 #define RCANFD_CSTS_RECSTS		BIT(6)
159 #define RCANFD_CSTS_TRMSTS		BIT(5)
160 #define RCANFD_CSTS_BOSTS		BIT(4)
161 #define RCANFD_CSTS_EPSTS		BIT(3)
162 #define RCANFD_CSTS_SLPSTS		BIT(2)
163 #define RCANFD_CSTS_HLTSTS		BIT(1)
164 #define RCANFD_CSTS_CRSTSTS		BIT(0)
165 
166 #define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
167 #define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
168 
169 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
170 #define RCANFD_CERFL_ADERR		BIT(14)
171 #define RCANFD_CERFL_B0ERR		BIT(13)
172 #define RCANFD_CERFL_B1ERR		BIT(12)
173 #define RCANFD_CERFL_CERR		BIT(11)
174 #define RCANFD_CERFL_AERR		BIT(10)
175 #define RCANFD_CERFL_FERR		BIT(9)
176 #define RCANFD_CERFL_SERR		BIT(8)
177 #define RCANFD_CERFL_ALF		BIT(7)
178 #define RCANFD_CERFL_BLF		BIT(6)
179 #define RCANFD_CERFL_OVLF		BIT(5)
180 #define RCANFD_CERFL_BORF		BIT(4)
181 #define RCANFD_CERFL_BOEF		BIT(3)
182 #define RCANFD_CERFL_EPF		BIT(2)
183 #define RCANFD_CERFL_EWF		BIT(1)
184 #define RCANFD_CERFL_BEF		BIT(0)
185 
186 #define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
187 
188 /* RSCFDnCFDCmDCFG */
189 #define RCANFD_DCFG_DSJW(gpriv, x)	(((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
190 
191 #define RCANFD_DCFG_DTSEG2(gpriv, x) \
192 	(((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
193 
194 #define RCANFD_DCFG_DTSEG1(gpriv, x) \
195 	(((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
196 
197 #define RCANFD_DCFG_DBRP(x)		(((x) & 0xff) << 0)
198 
199 /* RSCFDnCFDCmFDCFG */
200 #define RCANFD_GEN4_FDCFG_CLOE		BIT(30)
201 #define RCANFD_GEN4_FDCFG_FDOE		BIT(28)
202 #define RCANFD_FDCFG_TDCE		BIT(9)
203 #define RCANFD_FDCFG_TDCOC		BIT(8)
204 #define RCANFD_FDCFG_TDCO(x)		(((x) & 0x7f) >> 16)
205 
206 /* RSCFDnCFDRFCCx */
207 #define RCANFD_RFCC_RFIM		BIT(12)
208 #define RCANFD_RFCC_RFDC(x)		(((x) & 0x7) << 8)
209 #define RCANFD_RFCC_RFPLS(x)		(((x) & 0x7) << 4)
210 #define RCANFD_RFCC_RFIE		BIT(1)
211 #define RCANFD_RFCC_RFE			BIT(0)
212 
213 /* RSCFDnCFDRFSTSx */
214 #define RCANFD_RFSTS_RFIF		BIT(3)
215 #define RCANFD_RFSTS_RFMLT		BIT(2)
216 #define RCANFD_RFSTS_RFFLL		BIT(1)
217 #define RCANFD_RFSTS_RFEMP		BIT(0)
218 
219 /* RSCFDnCFDRFIDx */
220 #define RCANFD_RFID_RFIDE		BIT(31)
221 #define RCANFD_RFID_RFRTR		BIT(30)
222 
223 /* RSCFDnCFDRFPTRx */
224 #define RCANFD_RFPTR_RFDLC(x)		(((x) >> 28) & 0xf)
225 #define RCANFD_RFPTR_RFPTR(x)		(((x) >> 16) & 0xfff)
226 #define RCANFD_RFPTR_RFTS(x)		(((x) >> 0) & 0xffff)
227 
228 /* RSCFDnCFDRFFDSTSx */
229 #define RCANFD_RFFDSTS_RFFDF		BIT(2)
230 #define RCANFD_RFFDSTS_RFBRS		BIT(1)
231 #define RCANFD_RFFDSTS_RFESI		BIT(0)
232 
233 /* Common FIFO bits */
234 
235 /* RSCFDnCFDCFCCk */
236 #define RCANFD_CFCC_CFTML(gpriv, x)	\
237 	(((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
238 #define RCANFD_CFCC_CFM(gpriv, x)	(((x) & 0x3) << reg_gen4(gpriv,  8, 16))
239 #define RCANFD_CFCC_CFIM		BIT(12)
240 #define RCANFD_CFCC_CFDC(gpriv, x)	(((x) & 0x7) << reg_gen4(gpriv, 21,  8))
241 #define RCANFD_CFCC_CFPLS(x)		(((x) & 0x7) << 4)
242 #define RCANFD_CFCC_CFTXIE		BIT(2)
243 #define RCANFD_CFCC_CFE			BIT(0)
244 
245 /* RSCFDnCFDCFSTSk */
246 #define RCANFD_CFSTS_CFMC(x)		(((x) >> 8) & 0xff)
247 #define RCANFD_CFSTS_CFTXIF		BIT(4)
248 #define RCANFD_CFSTS_CFMLT		BIT(2)
249 #define RCANFD_CFSTS_CFFLL		BIT(1)
250 #define RCANFD_CFSTS_CFEMP		BIT(0)
251 
252 /* RSCFDnCFDCFIDk */
253 #define RCANFD_CFID_CFIDE		BIT(31)
254 #define RCANFD_CFID_CFRTR		BIT(30)
255 #define RCANFD_CFID_CFID_MASK(x)	((x) & 0x1fffffff)
256 
257 /* RSCFDnCFDCFPTRk */
258 #define RCANFD_CFPTR_CFDLC(x)		(((x) & 0xf) << 28)
259 #define RCANFD_CFPTR_CFPTR(x)		(((x) & 0xfff) << 16)
260 #define RCANFD_CFPTR_CFTS(x)		(((x) & 0xff) << 0)
261 
262 /* RSCFDnCFDCFFDCSTSk */
263 #define RCANFD_CFFDCSTS_CFFDF		BIT(2)
264 #define RCANFD_CFFDCSTS_CFBRS		BIT(1)
265 #define RCANFD_CFFDCSTS_CFESI		BIT(0)
266 
267 /* This controller supports either Classical CAN only mode or CAN FD only mode.
268  * These modes are supported in two separate set of register maps & names.
269  * However, some of the register offsets are common for both modes. Those
270  * offsets are listed below as Common registers.
271  *
272  * The CAN FD only mode specific registers & Classical CAN only mode specific
273  * registers are listed separately. Their register names starts with
274  * RCANFD_F_xxx & RCANFD_C_xxx respectively.
275  */
276 
277 /* Common registers */
278 
279 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
280 #define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
281 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
282 #define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
283 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
284 #define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
285 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
286 #define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
287 
288 /* RSCFDnCFDGCFG / RSCFDnGCFG */
289 #define RCANFD_GCFG			(0x0084)
290 /* RSCFDnCFDGCTR / RSCFDnGCTR */
291 #define RCANFD_GCTR			(0x0088)
292 /* RSCFDnCFDGCTS / RSCFDnGCTS */
293 #define RCANFD_GSTS			(0x008c)
294 /* RSCFDnCFDGERFL / RSCFDnGERFL */
295 #define RCANFD_GERFL			(0x0090)
296 /* RSCFDnCFDGTSC / RSCFDnGTSC */
297 #define RCANFD_GTSC			(0x0094)
298 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
299 #define RCANFD_GAFLECTR			(0x0098)
300 /* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
301 #define RCANFD_GAFLCFG(ch)		(0x009c + (0x04 * ((ch) / 2)))
302 /* RSCFDnCFDRMNB / RSCFDnRMNB */
303 #define RCANFD_RMNB			(0x00a4)
304 /* RSCFDnCFDRMND / RSCFDnRMND */
305 #define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
306 
307 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
308 #define RCANFD_RFCC(gpriv, x)		(reg_gen4(gpriv, 0x00c0, 0x00b8) + (0x04 * (x)))
309 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
310 #define RCANFD_RFSTS(gpriv, x)		(RCANFD_RFCC(gpriv, x) + 0x20)
311 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
312 #define RCANFD_RFPCTR(gpriv, x)		(RCANFD_RFCC(gpriv, x) + 0x40)
313 
314 /* Common FIFO Control registers */
315 
316 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
317 #define RCANFD_CFCC(gpriv, ch, idx) \
318 	(reg_gen4(gpriv, 0x0120, 0x0118) + (0x0c * (ch)) + (0x04 * (idx)))
319 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
320 #define RCANFD_CFSTS(gpriv, ch, idx) \
321 	(reg_gen4(gpriv, 0x01e0, 0x0178) + (0x0c * (ch)) + (0x04 * (idx)))
322 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
323 #define RCANFD_CFPCTR(gpriv, ch, idx) \
324 	(reg_gen4(gpriv, 0x0240, 0x01d8) + (0x0c * (ch)) + (0x04 * (idx)))
325 
326 /* RSCFDnCFDFESTS / RSCFDnFESTS */
327 #define RCANFD_FESTS			(0x0238)
328 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
329 #define RCANFD_FFSTS			(0x023c)
330 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
331 #define RCANFD_FMSTS			(0x0240)
332 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
333 #define RCANFD_RFISTS			(0x0244)
334 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
335 #define RCANFD_CFRISTS			(0x0248)
336 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
337 #define RCANFD_CFTISTS			(0x024c)
338 
339 /* RSCFDnCFDTMCp / RSCFDnTMCp */
340 #define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
341 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
342 #define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
343 
344 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
345 #define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
346 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
347 #define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
348 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
349 #define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
350 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
351 #define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
352 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
353 #define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
354 
355 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
356 #define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
357 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
358 #define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
359 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
360 #define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
361 
362 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
363 #define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
364 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
365 #define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
366 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
367 #define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
368 
369 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
370 #define RCANFD_GTINTSTS0		(0x0460)
371 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
372 #define RCANFD_GTINTSTS1		(0x0464)
373 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
374 #define RCANFD_GTSTCFG			(0x0468)
375 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
376 #define RCANFD_GTSTCTR			(0x046c)
377 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
378 #define RCANFD_GLOCKK			(0x047c)
379 /* RSCFDnCFDGRMCFG */
380 #define RCANFD_GRMCFG			(0x04fc)
381 
382 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
383 #define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
384 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
385 #define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
386 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
387 #define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
388 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
389 #define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
390 
391 /* Classical CAN only mode register map */
392 
393 /* RSCFDnGAFLXXXj offset */
394 #define RCANFD_C_GAFL_OFFSET		(0x0500)
395 
396 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
397 #define RCANFD_C_RMID(q)		(0x0600 + (0x10 * (q)))
398 #define RCANFD_C_RMPTR(q)		(0x0604 + (0x10 * (q)))
399 #define RCANFD_C_RMDF0(q)		(0x0608 + (0x10 * (q)))
400 #define RCANFD_C_RMDF1(q)		(0x060c + (0x10 * (q)))
401 
402 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
403 #define RCANFD_C_RFOFFSET	(0x0e00)
404 #define RCANFD_C_RFID(x)	(RCANFD_C_RFOFFSET + (0x10 * (x)))
405 #define RCANFD_C_RFPTR(x)	(RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
406 #define RCANFD_C_RFDF(x, df) \
407 		(RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
408 
409 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
410 #define RCANFD_C_CFOFFSET		(0x0e80)
411 
412 #define RCANFD_C_CFID(ch, idx) \
413 	(RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
414 
415 #define RCANFD_C_CFPTR(ch, idx)	\
416 	(RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
417 
418 #define RCANFD_C_CFDF(ch, idx, df) \
419 	(RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
420 
421 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
422 #define RCANFD_C_TMID(p)		(0x1000 + (0x10 * (p)))
423 #define RCANFD_C_TMPTR(p)		(0x1004 + (0x10 * (p)))
424 #define RCANFD_C_TMDF0(p)		(0x1008 + (0x10 * (p)))
425 #define RCANFD_C_TMDF1(p)		(0x100c + (0x10 * (p)))
426 
427 /* RSCFDnTHLACCm */
428 #define RCANFD_C_THLACC(m)		(0x1800 + (0x04 * (m)))
429 /* RSCFDnRPGACCr */
430 #define RCANFD_C_RPGACC(r)		(0x1900 + (0x04 * (r)))
431 
432 /* R-Car Gen4 Classical and CAN FD mode specific register map */
433 #define RCANFD_GEN4_FDCFG(m)		(0x1404 + (0x20 * (m)))
434 
435 #define RCANFD_GEN4_GAFL_OFFSET		(0x1800)
436 
437 /* CAN FD mode specific register map */
438 
439 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
440 #define RCANFD_F_DCFG(gpriv, m)		(reg_gen4(gpriv, 0x1400, 0x0500) + (0x20 * (m)))
441 #define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
442 #define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
443 #define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
444 #define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
445 
446 /* RSCFDnCFDGAFLXXXj offset */
447 #define RCANFD_F_GAFL_OFFSET		(0x1000)
448 
449 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
450 #define RCANFD_F_RMID(q)		(0x2000 + (0x20 * (q)))
451 #define RCANFD_F_RMPTR(q)		(0x2004 + (0x20 * (q)))
452 #define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x20 * (q)))
453 #define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
454 
455 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
456 #define RCANFD_F_RFOFFSET(gpriv)	reg_gen4(gpriv, 0x6000, 0x3000)
457 #define RCANFD_F_RFID(gpriv, x)		(RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
458 #define RCANFD_F_RFPTR(gpriv, x)	(RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
459 #define RCANFD_F_RFFDSTS(gpriv, x)	(RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
460 #define RCANFD_F_RFDF(gpriv, x, df) \
461 	(RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
462 
463 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
464 #define RCANFD_F_CFOFFSET(gpriv)	reg_gen4(gpriv, 0x6400, 0x3400)
465 
466 #define RCANFD_F_CFID(gpriv, ch, idx) \
467 	(RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
468 
469 #define RCANFD_F_CFPTR(gpriv, ch, idx) \
470 	(RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
471 
472 #define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
473 	(RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
474 
475 #define RCANFD_F_CFDF(gpriv, ch, idx, df) \
476 	(RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
477 	 (0x04 * (df)))
478 
479 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
480 #define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
481 #define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
482 #define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
483 #define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
484 
485 /* RSCFDnCFDTHLACCm */
486 #define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
487 /* RSCFDnCFDRPGACCr */
488 #define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
489 
490 /* Constants */
491 #define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
492 #define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
493 
494 #define RCANFD_NUM_CHANNELS		8	/* Eight channels max */
495 #define RCANFD_CHANNELS_MASK		BIT((RCANFD_NUM_CHANNELS) - 1)
496 
497 #define RCANFD_GAFL_PAGENUM(entry)	((entry) / 16)
498 #define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
499 
500 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
501  * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
502  * number is added to RFFIFO index.
503  */
504 #define RCANFD_RFFIFO_IDX		0
505 
506 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
507  * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
508  */
509 #define RCANFD_CFFIFO_IDX		0
510 
511 struct rcar_canfd_global;
512 
513 struct rcar_canfd_hw_info {
514 	u8 max_channels;
515 	u8 postdiv;
516 	/* hardware features */
517 	unsigned shared_global_irqs:1;	/* Has shared global irqs */
518 	unsigned multi_channel_irqs:1;	/* Has multiple channel irqs */
519 };
520 
521 /* Channel priv data */
522 struct rcar_canfd_channel {
523 	struct can_priv can;			/* Must be the first member */
524 	struct net_device *ndev;
525 	struct rcar_canfd_global *gpriv;	/* Controller reference */
526 	void __iomem *base;			/* Register base address */
527 	struct phy *transceiver;		/* Optional transceiver */
528 	struct napi_struct napi;
529 	u32 tx_head;				/* Incremented on xmit */
530 	u32 tx_tail;				/* Incremented on xmit done */
531 	u32 channel;				/* Channel number */
532 	spinlock_t tx_lock;			/* To protect tx path */
533 };
534 
535 /* Global priv data */
536 struct rcar_canfd_global {
537 	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
538 	void __iomem *base;		/* Register base address */
539 	struct platform_device *pdev;	/* Respective platform device */
540 	struct clk *clkp;		/* Peripheral clock */
541 	struct clk *can_clk;		/* fCAN clock */
542 	unsigned long channels_mask;	/* Enabled channels mask */
543 	bool extclk;			/* CANFD or Ext clock */
544 	bool fdmode;			/* CAN FD or Classical CAN only mode */
545 	struct reset_control *rstc1;
546 	struct reset_control *rstc2;
547 	const struct rcar_canfd_hw_info *info;
548 };
549 
550 /* CAN FD mode nominal rate constants */
551 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
552 	.name = RCANFD_DRV_NAME,
553 	.tseg1_min = 2,
554 	.tseg1_max = 128,
555 	.tseg2_min = 2,
556 	.tseg2_max = 32,
557 	.sjw_max = 32,
558 	.brp_min = 1,
559 	.brp_max = 1024,
560 	.brp_inc = 1,
561 };
562 
563 /* CAN FD mode data rate constants */
564 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
565 	.name = RCANFD_DRV_NAME,
566 	.tseg1_min = 2,
567 	.tseg1_max = 16,
568 	.tseg2_min = 2,
569 	.tseg2_max = 8,
570 	.sjw_max = 8,
571 	.brp_min = 1,
572 	.brp_max = 256,
573 	.brp_inc = 1,
574 };
575 
576 /* Classical CAN mode bitrate constants */
577 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
578 	.name = RCANFD_DRV_NAME,
579 	.tseg1_min = 4,
580 	.tseg1_max = 16,
581 	.tseg2_min = 2,
582 	.tseg2_max = 8,
583 	.sjw_max = 4,
584 	.brp_min = 1,
585 	.brp_max = 1024,
586 	.brp_inc = 1,
587 };
588 
589 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
590 	.max_channels = 2,
591 	.postdiv = 2,
592 	.shared_global_irqs = 1,
593 };
594 
595 static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
596 	.max_channels = 8,
597 	.postdiv = 2,
598 	.shared_global_irqs = 1,
599 };
600 
601 static const struct rcar_canfd_hw_info rzg2l_hw_info = {
602 	.max_channels = 2,
603 	.postdiv = 1,
604 	.multi_channel_irqs = 1,
605 };
606 
607 /* Helper functions */
is_gen4(struct rcar_canfd_global * gpriv)608 static inline bool is_gen4(struct rcar_canfd_global *gpriv)
609 {
610 	return gpriv->info == &rcar_gen4_hw_info;
611 }
612 
reg_gen4(struct rcar_canfd_global * gpriv,u32 gen4,u32 not_gen4)613 static inline u32 reg_gen4(struct rcar_canfd_global *gpriv,
614 			   u32 gen4, u32 not_gen4)
615 {
616 	return is_gen4(gpriv) ? gen4 : not_gen4;
617 }
618 
rcar_canfd_update(u32 mask,u32 val,u32 __iomem * reg)619 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
620 {
621 	u32 data = readl(reg);
622 
623 	data &= ~mask;
624 	data |= (val & mask);
625 	writel(data, reg);
626 }
627 
rcar_canfd_read(void __iomem * base,u32 offset)628 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
629 {
630 	return readl(base + offset);
631 }
632 
rcar_canfd_write(void __iomem * base,u32 offset,u32 val)633 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
634 {
635 	writel(val, base + offset);
636 }
637 
rcar_canfd_set_bit(void __iomem * base,u32 reg,u32 val)638 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
639 {
640 	rcar_canfd_update(val, val, base + reg);
641 }
642 
rcar_canfd_clear_bit(void __iomem * base,u32 reg,u32 val)643 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
644 {
645 	rcar_canfd_update(val, 0, base + reg);
646 }
647 
rcar_canfd_update_bit(void __iomem * base,u32 reg,u32 mask,u32 val)648 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
649 				  u32 mask, u32 val)
650 {
651 	rcar_canfd_update(mask, val, base + reg);
652 }
653 
rcar_canfd_get_data(struct rcar_canfd_channel * priv,struct canfd_frame * cf,u32 off)654 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
655 				struct canfd_frame *cf, u32 off)
656 {
657 	u32 i, lwords;
658 
659 	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
660 	for (i = 0; i < lwords; i++)
661 		*((u32 *)cf->data + i) =
662 			rcar_canfd_read(priv->base, off + i * sizeof(u32));
663 }
664 
rcar_canfd_put_data(struct rcar_canfd_channel * priv,struct canfd_frame * cf,u32 off)665 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
666 				struct canfd_frame *cf, u32 off)
667 {
668 	u32 i, lwords;
669 
670 	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
671 	for (i = 0; i < lwords; i++)
672 		rcar_canfd_write(priv->base, off + i * sizeof(u32),
673 				 *((u32 *)cf->data + i));
674 }
675 
rcar_canfd_tx_failure_cleanup(struct net_device * ndev)676 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
677 {
678 	u32 i;
679 
680 	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
681 		can_free_echo_skb(ndev, i, NULL);
682 }
683 
rcar_canfd_set_mode(struct rcar_canfd_global * gpriv)684 static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
685 {
686 	if (is_gen4(gpriv)) {
687 		u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
688 					    : RCANFD_GEN4_FDCFG_CLOE;
689 
690 		for_each_set_bit(ch, &gpriv->channels_mask,
691 				 gpriv->info->max_channels)
692 			rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
693 					   val);
694 	} else {
695 		if (gpriv->fdmode)
696 			rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
697 					   RCANFD_GRMCFG_RCMC);
698 		else
699 			rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
700 					     RCANFD_GRMCFG_RCMC);
701 	}
702 }
703 
rcar_canfd_reset_controller(struct rcar_canfd_global * gpriv)704 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
705 {
706 	u32 sts, ch;
707 	int err;
708 
709 	/* Check RAMINIT flag as CAN RAM initialization takes place
710 	 * after the MCU reset
711 	 */
712 	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
713 				 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
714 	if (err) {
715 		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
716 		return err;
717 	}
718 
719 	/* Transition to Global Reset mode */
720 	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
721 	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
722 			      RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
723 
724 	/* Ensure Global reset mode */
725 	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
726 				 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
727 	if (err) {
728 		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
729 		return err;
730 	}
731 
732 	/* Reset Global error flags */
733 	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
734 
735 	/* Set the controller into appropriate mode */
736 	rcar_canfd_set_mode(gpriv);
737 
738 	/* Transition all Channels to reset mode */
739 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
740 		rcar_canfd_clear_bit(gpriv->base,
741 				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
742 
743 		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
744 				      RCANFD_CCTR_CHMDC_MASK,
745 				      RCANFD_CCTR_CHDMC_CRESET);
746 
747 		/* Ensure Channel reset mode */
748 		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
749 					 (sts & RCANFD_CSTS_CRSTSTS),
750 					 2, 500000);
751 		if (err) {
752 			dev_dbg(&gpriv->pdev->dev,
753 				"channel %u reset failed\n", ch);
754 			return err;
755 		}
756 	}
757 	return 0;
758 }
759 
rcar_canfd_configure_controller(struct rcar_canfd_global * gpriv)760 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
761 {
762 	u32 cfg, ch;
763 
764 	/* Global configuration settings */
765 
766 	/* ECC Error flag Enable */
767 	cfg = RCANFD_GCFG_EEFE;
768 
769 	if (gpriv->fdmode)
770 		/* Truncate payload to configured message size RFPLS */
771 		cfg |= RCANFD_GCFG_CMPOC;
772 
773 	/* Set External Clock if selected */
774 	if (gpriv->extclk)
775 		cfg |= RCANFD_GCFG_DCS;
776 
777 	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
778 
779 	/* Channel configuration settings */
780 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
781 		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
782 				   RCANFD_CCTR_ERRD);
783 		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
784 				      RCANFD_CCTR_BOM_MASK,
785 				      RCANFD_CCTR_BOM_BENTRY);
786 	}
787 }
788 
rcar_canfd_configure_afl_rules(struct rcar_canfd_global * gpriv,u32 ch,u32 rule_entry)789 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
790 					   u32 ch, u32 rule_entry)
791 {
792 	int offset, page, num_rules = RCANFD_CHANNEL_NUMRULES;
793 	u32 rule_entry_index = rule_entry % 16;
794 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
795 
796 	/* Enable write access to entry */
797 	page = RCANFD_GAFL_PAGENUM(rule_entry);
798 	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
799 			   (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
800 			    RCANFD_GAFLECTR_AFLDAE));
801 
802 	/* Write number of rules for channel */
803 	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
804 			   RCANFD_GAFLCFG_SETRNC(gpriv, ch, num_rules));
805 	if (is_gen4(gpriv))
806 		offset = RCANFD_GEN4_GAFL_OFFSET;
807 	else if (gpriv->fdmode)
808 		offset = RCANFD_F_GAFL_OFFSET;
809 	else
810 		offset = RCANFD_C_GAFL_OFFSET;
811 
812 	/* Accept all IDs */
813 	rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, rule_entry_index), 0);
814 	/* IDE or RTR is not considered for matching */
815 	rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, rule_entry_index), 0);
816 	/* Any data length accepted */
817 	rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, rule_entry_index), 0);
818 	/* Place the msg in corresponding Rx FIFO entry */
819 	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, rule_entry_index),
820 			   RCANFD_GAFLP1_GAFLFDP(ridx));
821 
822 	/* Disable write access to page */
823 	rcar_canfd_clear_bit(gpriv->base,
824 			     RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
825 }
826 
rcar_canfd_configure_rx(struct rcar_canfd_global * gpriv,u32 ch)827 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
828 {
829 	/* Rx FIFO is used for reception */
830 	u32 cfg;
831 	u16 rfdc, rfpls;
832 
833 	/* Select Rx FIFO based on channel */
834 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
835 
836 	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
837 	if (gpriv->fdmode)
838 		rfpls = 7;	/* b111 - Max 64 bytes payload */
839 	else
840 		rfpls = 0;	/* b000 - Max 8 bytes payload */
841 
842 	cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
843 		RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
844 	rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
845 }
846 
rcar_canfd_configure_tx(struct rcar_canfd_global * gpriv,u32 ch)847 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
848 {
849 	/* Tx/Rx(Common) FIFO configured in Tx mode is
850 	 * used for transmission
851 	 *
852 	 * Each channel has 3 Common FIFO dedicated to them.
853 	 * Use the 1st (index 0) out of 3
854 	 */
855 	u32 cfg;
856 	u16 cftml, cfm, cfdc, cfpls;
857 
858 	cftml = 0;		/* 0th buffer */
859 	cfm = 1;		/* b01 - Transmit mode */
860 	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
861 	if (gpriv->fdmode)
862 		cfpls = 7;	/* b111 - Max 64 bytes payload */
863 	else
864 		cfpls = 0;	/* b000 - Max 8 bytes payload */
865 
866 	cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
867 		RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
868 		RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
869 	rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
870 
871 	if (gpriv->fdmode)
872 		/* Clear FD mode specific control/status register */
873 		rcar_canfd_write(gpriv->base,
874 				 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
875 }
876 
rcar_canfd_enable_global_interrupts(struct rcar_canfd_global * gpriv)877 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
878 {
879 	u32 ctr;
880 
881 	/* Clear any stray error interrupt flags */
882 	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
883 
884 	/* Global interrupts setup */
885 	ctr = RCANFD_GCTR_MEIE;
886 	if (gpriv->fdmode)
887 		ctr |= RCANFD_GCTR_CFMPOFIE;
888 
889 	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
890 }
891 
rcar_canfd_disable_global_interrupts(struct rcar_canfd_global * gpriv)892 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
893 						 *gpriv)
894 {
895 	/* Disable all interrupts */
896 	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
897 
898 	/* Clear any stray error interrupt flags */
899 	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
900 }
901 
rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel * priv)902 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
903 						 *priv)
904 {
905 	u32 ctr, ch = priv->channel;
906 
907 	/* Clear any stray error flags */
908 	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
909 
910 	/* Channel interrupts setup */
911 	ctr = (RCANFD_CCTR_TAIE |
912 	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
913 	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
914 	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
915 	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
916 	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
917 }
918 
rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel * priv)919 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
920 						  *priv)
921 {
922 	u32 ctr, ch = priv->channel;
923 
924 	ctr = (RCANFD_CCTR_TAIE |
925 	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
926 	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
927 	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
928 	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
929 	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
930 
931 	/* Clear any stray error flags */
932 	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
933 }
934 
rcar_canfd_global_error(struct net_device * ndev)935 static void rcar_canfd_global_error(struct net_device *ndev)
936 {
937 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
938 	struct rcar_canfd_global *gpriv = priv->gpriv;
939 	struct net_device_stats *stats = &ndev->stats;
940 	u32 ch = priv->channel;
941 	u32 gerfl, sts;
942 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
943 
944 	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
945 	if (gerfl & RCANFD_GERFL_EEF(ch)) {
946 		netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
947 		stats->tx_dropped++;
948 	}
949 	if (gerfl & RCANFD_GERFL_MES) {
950 		sts = rcar_canfd_read(priv->base,
951 				      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
952 		if (sts & RCANFD_CFSTS_CFMLT) {
953 			netdev_dbg(ndev, "Tx Message Lost flag\n");
954 			stats->tx_dropped++;
955 			rcar_canfd_write(priv->base,
956 					 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
957 					 sts & ~RCANFD_CFSTS_CFMLT);
958 		}
959 
960 		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
961 		if (sts & RCANFD_RFSTS_RFMLT) {
962 			netdev_dbg(ndev, "Rx Message Lost flag\n");
963 			stats->rx_dropped++;
964 			rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
965 					 sts & ~RCANFD_RFSTS_RFMLT);
966 		}
967 	}
968 	if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
969 		/* Message Lost flag will be set for respective channel
970 		 * when this condition happens with counters and flags
971 		 * already updated.
972 		 */
973 		netdev_dbg(ndev, "global payload overflow interrupt\n");
974 	}
975 
976 	/* Clear all global error interrupts. Only affected channels bits
977 	 * get cleared
978 	 */
979 	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
980 }
981 
rcar_canfd_error(struct net_device * ndev,u32 cerfl,u16 txerr,u16 rxerr)982 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
983 			     u16 txerr, u16 rxerr)
984 {
985 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
986 	struct net_device_stats *stats = &ndev->stats;
987 	struct can_frame *cf;
988 	struct sk_buff *skb;
989 	u32 ch = priv->channel;
990 
991 	netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
992 
993 	/* Propagate the error condition to the CAN stack */
994 	skb = alloc_can_err_skb(ndev, &cf);
995 	if (!skb) {
996 		stats->rx_dropped++;
997 		return;
998 	}
999 
1000 	/* Channel error interrupts */
1001 	if (cerfl & RCANFD_CERFL_BEF) {
1002 		netdev_dbg(ndev, "Bus error\n");
1003 		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1004 		cf->data[2] = CAN_ERR_PROT_UNSPEC;
1005 		priv->can.can_stats.bus_error++;
1006 	}
1007 	if (cerfl & RCANFD_CERFL_ADERR) {
1008 		netdev_dbg(ndev, "ACK Delimiter Error\n");
1009 		stats->tx_errors++;
1010 		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1011 	}
1012 	if (cerfl & RCANFD_CERFL_B0ERR) {
1013 		netdev_dbg(ndev, "Bit Error (dominant)\n");
1014 		stats->tx_errors++;
1015 		cf->data[2] |= CAN_ERR_PROT_BIT0;
1016 	}
1017 	if (cerfl & RCANFD_CERFL_B1ERR) {
1018 		netdev_dbg(ndev, "Bit Error (recessive)\n");
1019 		stats->tx_errors++;
1020 		cf->data[2] |= CAN_ERR_PROT_BIT1;
1021 	}
1022 	if (cerfl & RCANFD_CERFL_CERR) {
1023 		netdev_dbg(ndev, "CRC Error\n");
1024 		stats->rx_errors++;
1025 		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1026 	}
1027 	if (cerfl & RCANFD_CERFL_AERR) {
1028 		netdev_dbg(ndev, "ACK Error\n");
1029 		stats->tx_errors++;
1030 		cf->can_id |= CAN_ERR_ACK;
1031 		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1032 	}
1033 	if (cerfl & RCANFD_CERFL_FERR) {
1034 		netdev_dbg(ndev, "Form Error\n");
1035 		stats->rx_errors++;
1036 		cf->data[2] |= CAN_ERR_PROT_FORM;
1037 	}
1038 	if (cerfl & RCANFD_CERFL_SERR) {
1039 		netdev_dbg(ndev, "Stuff Error\n");
1040 		stats->rx_errors++;
1041 		cf->data[2] |= CAN_ERR_PROT_STUFF;
1042 	}
1043 	if (cerfl & RCANFD_CERFL_ALF) {
1044 		netdev_dbg(ndev, "Arbitration lost Error\n");
1045 		priv->can.can_stats.arbitration_lost++;
1046 		cf->can_id |= CAN_ERR_LOSTARB;
1047 		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1048 	}
1049 	if (cerfl & RCANFD_CERFL_BLF) {
1050 		netdev_dbg(ndev, "Bus Lock Error\n");
1051 		stats->rx_errors++;
1052 		cf->can_id |= CAN_ERR_BUSERROR;
1053 	}
1054 	if (cerfl & RCANFD_CERFL_EWF) {
1055 		netdev_dbg(ndev, "Error warning interrupt\n");
1056 		priv->can.state = CAN_STATE_ERROR_WARNING;
1057 		priv->can.can_stats.error_warning++;
1058 		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1059 		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1060 			CAN_ERR_CRTL_RX_WARNING;
1061 		cf->data[6] = txerr;
1062 		cf->data[7] = rxerr;
1063 	}
1064 	if (cerfl & RCANFD_CERFL_EPF) {
1065 		netdev_dbg(ndev, "Error passive interrupt\n");
1066 		priv->can.state = CAN_STATE_ERROR_PASSIVE;
1067 		priv->can.can_stats.error_passive++;
1068 		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1069 		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1070 			CAN_ERR_CRTL_RX_PASSIVE;
1071 		cf->data[6] = txerr;
1072 		cf->data[7] = rxerr;
1073 	}
1074 	if (cerfl & RCANFD_CERFL_BOEF) {
1075 		netdev_dbg(ndev, "Bus-off entry interrupt\n");
1076 		rcar_canfd_tx_failure_cleanup(ndev);
1077 		priv->can.state = CAN_STATE_BUS_OFF;
1078 		priv->can.can_stats.bus_off++;
1079 		can_bus_off(ndev);
1080 		cf->can_id |= CAN_ERR_BUSOFF;
1081 	}
1082 	if (cerfl & RCANFD_CERFL_OVLF) {
1083 		netdev_dbg(ndev,
1084 			   "Overload Frame Transmission error interrupt\n");
1085 		stats->tx_errors++;
1086 		cf->can_id |= CAN_ERR_PROT;
1087 		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1088 	}
1089 
1090 	/* Clear channel error interrupts that are handled */
1091 	rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1092 			 RCANFD_CERFL_ERR(~cerfl));
1093 	netif_rx(skb);
1094 }
1095 
rcar_canfd_tx_done(struct net_device * ndev)1096 static void rcar_canfd_tx_done(struct net_device *ndev)
1097 {
1098 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1099 	struct rcar_canfd_global *gpriv = priv->gpriv;
1100 	struct net_device_stats *stats = &ndev->stats;
1101 	u32 sts;
1102 	unsigned long flags;
1103 	u32 ch = priv->channel;
1104 
1105 	do {
1106 		u8 unsent, sent;
1107 
1108 		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1109 		stats->tx_packets++;
1110 		stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1111 
1112 		spin_lock_irqsave(&priv->tx_lock, flags);
1113 		priv->tx_tail++;
1114 		sts = rcar_canfd_read(priv->base,
1115 				      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1116 		unsent = RCANFD_CFSTS_CFMC(sts);
1117 
1118 		/* Wake producer only when there is room */
1119 		if (unsent != RCANFD_FIFO_DEPTH)
1120 			netif_wake_queue(ndev);
1121 
1122 		if (priv->tx_head - priv->tx_tail <= unsent) {
1123 			spin_unlock_irqrestore(&priv->tx_lock, flags);
1124 			break;
1125 		}
1126 		spin_unlock_irqrestore(&priv->tx_lock, flags);
1127 
1128 	} while (1);
1129 
1130 	/* Clear interrupt */
1131 	rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1132 			 sts & ~RCANFD_CFSTS_CFTXIF);
1133 }
1134 
rcar_canfd_handle_global_err(struct rcar_canfd_global * gpriv,u32 ch)1135 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1136 {
1137 	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1138 	struct net_device *ndev = priv->ndev;
1139 	u32 gerfl;
1140 
1141 	/* Handle global error interrupts */
1142 	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1143 	if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1144 		rcar_canfd_global_error(ndev);
1145 }
1146 
rcar_canfd_global_err_interrupt(int irq,void * dev_id)1147 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1148 {
1149 	struct rcar_canfd_global *gpriv = dev_id;
1150 	u32 ch;
1151 
1152 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1153 		rcar_canfd_handle_global_err(gpriv, ch);
1154 
1155 	return IRQ_HANDLED;
1156 }
1157 
rcar_canfd_handle_global_receive(struct rcar_canfd_global * gpriv,u32 ch)1158 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1159 {
1160 	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1161 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1162 	u32 sts, cc;
1163 
1164 	/* Handle Rx interrupts */
1165 	sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1166 	cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1167 	if (likely(sts & RCANFD_RFSTS_RFIF &&
1168 		   cc & RCANFD_RFCC_RFIE)) {
1169 		if (napi_schedule_prep(&priv->napi)) {
1170 			/* Disable Rx FIFO interrupts */
1171 			rcar_canfd_clear_bit(priv->base,
1172 					     RCANFD_RFCC(gpriv, ridx),
1173 					     RCANFD_RFCC_RFIE);
1174 			__napi_schedule(&priv->napi);
1175 		}
1176 	}
1177 }
1178 
rcar_canfd_global_receive_fifo_interrupt(int irq,void * dev_id)1179 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1180 {
1181 	struct rcar_canfd_global *gpriv = dev_id;
1182 	u32 ch;
1183 
1184 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1185 		rcar_canfd_handle_global_receive(gpriv, ch);
1186 
1187 	return IRQ_HANDLED;
1188 }
1189 
rcar_canfd_global_interrupt(int irq,void * dev_id)1190 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1191 {
1192 	struct rcar_canfd_global *gpriv = dev_id;
1193 	u32 ch;
1194 
1195 	/* Global error interrupts still indicate a condition specific
1196 	 * to a channel. RxFIFO interrupt is a global interrupt.
1197 	 */
1198 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1199 		rcar_canfd_handle_global_err(gpriv, ch);
1200 		rcar_canfd_handle_global_receive(gpriv, ch);
1201 	}
1202 	return IRQ_HANDLED;
1203 }
1204 
rcar_canfd_state_change(struct net_device * ndev,u16 txerr,u16 rxerr)1205 static void rcar_canfd_state_change(struct net_device *ndev,
1206 				    u16 txerr, u16 rxerr)
1207 {
1208 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1209 	struct net_device_stats *stats = &ndev->stats;
1210 	enum can_state rx_state, tx_state, state = priv->can.state;
1211 	struct can_frame *cf;
1212 	struct sk_buff *skb;
1213 
1214 	/* Handle transition from error to normal states */
1215 	if (txerr < 96 && rxerr < 96)
1216 		state = CAN_STATE_ERROR_ACTIVE;
1217 	else if (txerr < 128 && rxerr < 128)
1218 		state = CAN_STATE_ERROR_WARNING;
1219 
1220 	if (state != priv->can.state) {
1221 		netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1222 			   state, priv->can.state, txerr, rxerr);
1223 		skb = alloc_can_err_skb(ndev, &cf);
1224 		if (!skb) {
1225 			stats->rx_dropped++;
1226 			return;
1227 		}
1228 		tx_state = txerr >= rxerr ? state : 0;
1229 		rx_state = txerr <= rxerr ? state : 0;
1230 
1231 		can_change_state(ndev, cf, tx_state, rx_state);
1232 		netif_rx(skb);
1233 	}
1234 }
1235 
rcar_canfd_handle_channel_tx(struct rcar_canfd_global * gpriv,u32 ch)1236 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1237 {
1238 	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1239 	struct net_device *ndev = priv->ndev;
1240 	u32 sts;
1241 
1242 	/* Handle Tx interrupts */
1243 	sts = rcar_canfd_read(priv->base,
1244 			      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1245 	if (likely(sts & RCANFD_CFSTS_CFTXIF))
1246 		rcar_canfd_tx_done(ndev);
1247 }
1248 
rcar_canfd_channel_tx_interrupt(int irq,void * dev_id)1249 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1250 {
1251 	struct rcar_canfd_channel *priv = dev_id;
1252 
1253 	rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1254 
1255 	return IRQ_HANDLED;
1256 }
1257 
rcar_canfd_handle_channel_err(struct rcar_canfd_global * gpriv,u32 ch)1258 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1259 {
1260 	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1261 	struct net_device *ndev = priv->ndev;
1262 	u16 txerr, rxerr;
1263 	u32 sts, cerfl;
1264 
1265 	/* Handle channel error interrupts */
1266 	cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1267 	sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1268 	txerr = RCANFD_CSTS_TECCNT(sts);
1269 	rxerr = RCANFD_CSTS_RECCNT(sts);
1270 	if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1271 		rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1272 
1273 	/* Handle state change to lower states */
1274 	if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1275 		     priv->can.state != CAN_STATE_BUS_OFF))
1276 		rcar_canfd_state_change(ndev, txerr, rxerr);
1277 }
1278 
rcar_canfd_channel_err_interrupt(int irq,void * dev_id)1279 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1280 {
1281 	struct rcar_canfd_channel *priv = dev_id;
1282 
1283 	rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1284 
1285 	return IRQ_HANDLED;
1286 }
1287 
rcar_canfd_channel_interrupt(int irq,void * dev_id)1288 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1289 {
1290 	struct rcar_canfd_global *gpriv = dev_id;
1291 	u32 ch;
1292 
1293 	/* Common FIFO is a per channel resource */
1294 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1295 		rcar_canfd_handle_channel_err(gpriv, ch);
1296 		rcar_canfd_handle_channel_tx(gpriv, ch);
1297 	}
1298 
1299 	return IRQ_HANDLED;
1300 }
1301 
rcar_canfd_set_bittiming(struct net_device * dev)1302 static void rcar_canfd_set_bittiming(struct net_device *dev)
1303 {
1304 	struct rcar_canfd_channel *priv = netdev_priv(dev);
1305 	struct rcar_canfd_global *gpriv = priv->gpriv;
1306 	const struct can_bittiming *bt = &priv->can.bittiming;
1307 	const struct can_bittiming *dbt = &priv->can.data_bittiming;
1308 	u16 brp, sjw, tseg1, tseg2;
1309 	u32 cfg;
1310 	u32 ch = priv->channel;
1311 
1312 	/* Nominal bit timing settings */
1313 	brp = bt->brp - 1;
1314 	sjw = bt->sjw - 1;
1315 	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1316 	tseg2 = bt->phase_seg2 - 1;
1317 
1318 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1319 		/* CAN FD only mode */
1320 		cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
1321 		       RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1322 
1323 		rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1324 		netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1325 			   brp, sjw, tseg1, tseg2);
1326 
1327 		/* Data bit timing settings */
1328 		brp = dbt->brp - 1;
1329 		sjw = dbt->sjw - 1;
1330 		tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1331 		tseg2 = dbt->phase_seg2 - 1;
1332 
1333 		cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
1334 		       RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
1335 
1336 		rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
1337 		netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1338 			   brp, sjw, tseg1, tseg2);
1339 	} else {
1340 		/* Classical CAN only mode */
1341 		if (is_gen4(gpriv)) {
1342 			cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) |
1343 			       RCANFD_NCFG_NBRP(brp) |
1344 			       RCANFD_NCFG_NSJW(gpriv, sjw) |
1345 			       RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1346 		} else {
1347 			cfg = (RCANFD_CFG_TSEG1(tseg1) |
1348 			       RCANFD_CFG_BRP(brp) |
1349 			       RCANFD_CFG_SJW(sjw) |
1350 			       RCANFD_CFG_TSEG2(tseg2));
1351 		}
1352 
1353 		rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1354 		netdev_dbg(priv->ndev,
1355 			   "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1356 			   brp, sjw, tseg1, tseg2);
1357 	}
1358 }
1359 
rcar_canfd_start(struct net_device * ndev)1360 static int rcar_canfd_start(struct net_device *ndev)
1361 {
1362 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1363 	struct rcar_canfd_global *gpriv = priv->gpriv;
1364 	int err = -EOPNOTSUPP;
1365 	u32 sts, ch = priv->channel;
1366 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1367 
1368 	rcar_canfd_set_bittiming(ndev);
1369 
1370 	rcar_canfd_enable_channel_interrupts(priv);
1371 
1372 	/* Set channel to Operational mode */
1373 	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1374 			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1375 
1376 	/* Verify channel mode change */
1377 	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1378 				 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1379 	if (err) {
1380 		netdev_err(ndev, "channel %u communication state failed\n", ch);
1381 		goto fail_mode_change;
1382 	}
1383 
1384 	/* Enable Common & Rx FIFO */
1385 	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1386 			   RCANFD_CFCC_CFE);
1387 	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1388 
1389 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1390 	return 0;
1391 
1392 fail_mode_change:
1393 	rcar_canfd_disable_channel_interrupts(priv);
1394 	return err;
1395 }
1396 
rcar_canfd_open(struct net_device * ndev)1397 static int rcar_canfd_open(struct net_device *ndev)
1398 {
1399 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1400 	struct rcar_canfd_global *gpriv = priv->gpriv;
1401 	int err;
1402 
1403 	err = phy_power_on(priv->transceiver);
1404 	if (err) {
1405 		netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err));
1406 		return err;
1407 	}
1408 
1409 	/* Peripheral clock is already enabled in probe */
1410 	err = clk_prepare_enable(gpriv->can_clk);
1411 	if (err) {
1412 		netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err));
1413 		goto out_phy;
1414 	}
1415 
1416 	err = open_candev(ndev);
1417 	if (err) {
1418 		netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err));
1419 		goto out_can_clock;
1420 	}
1421 
1422 	napi_enable(&priv->napi);
1423 	err = rcar_canfd_start(ndev);
1424 	if (err)
1425 		goto out_close;
1426 	netif_start_queue(ndev);
1427 	return 0;
1428 out_close:
1429 	napi_disable(&priv->napi);
1430 	close_candev(ndev);
1431 out_can_clock:
1432 	clk_disable_unprepare(gpriv->can_clk);
1433 out_phy:
1434 	phy_power_off(priv->transceiver);
1435 	return err;
1436 }
1437 
rcar_canfd_stop(struct net_device * ndev)1438 static void rcar_canfd_stop(struct net_device *ndev)
1439 {
1440 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1441 	struct rcar_canfd_global *gpriv = priv->gpriv;
1442 	int err;
1443 	u32 sts, ch = priv->channel;
1444 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1445 
1446 	/* Transition to channel reset mode  */
1447 	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1448 			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1449 
1450 	/* Check Channel reset mode */
1451 	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1452 				 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1453 	if (err)
1454 		netdev_err(ndev, "channel %u reset failed\n", ch);
1455 
1456 	rcar_canfd_disable_channel_interrupts(priv);
1457 
1458 	/* Disable Common & Rx FIFO */
1459 	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1460 			     RCANFD_CFCC_CFE);
1461 	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1462 
1463 	/* Set the state as STOPPED */
1464 	priv->can.state = CAN_STATE_STOPPED;
1465 }
1466 
rcar_canfd_close(struct net_device * ndev)1467 static int rcar_canfd_close(struct net_device *ndev)
1468 {
1469 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1470 	struct rcar_canfd_global *gpriv = priv->gpriv;
1471 
1472 	netif_stop_queue(ndev);
1473 	rcar_canfd_stop(ndev);
1474 	napi_disable(&priv->napi);
1475 	clk_disable_unprepare(gpriv->can_clk);
1476 	close_candev(ndev);
1477 	phy_power_off(priv->transceiver);
1478 	return 0;
1479 }
1480 
rcar_canfd_start_xmit(struct sk_buff * skb,struct net_device * ndev)1481 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1482 					 struct net_device *ndev)
1483 {
1484 	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1485 	struct rcar_canfd_global *gpriv = priv->gpriv;
1486 	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1487 	u32 sts = 0, id, dlc;
1488 	unsigned long flags;
1489 	u32 ch = priv->channel;
1490 
1491 	if (can_dev_dropped_skb(ndev, skb))
1492 		return NETDEV_TX_OK;
1493 
1494 	if (cf->can_id & CAN_EFF_FLAG) {
1495 		id = cf->can_id & CAN_EFF_MASK;
1496 		id |= RCANFD_CFID_CFIDE;
1497 	} else {
1498 		id = cf->can_id & CAN_SFF_MASK;
1499 	}
1500 
1501 	if (cf->can_id & CAN_RTR_FLAG)
1502 		id |= RCANFD_CFID_CFRTR;
1503 
1504 	dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1505 
1506 	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1507 		rcar_canfd_write(priv->base,
1508 				 RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1509 		rcar_canfd_write(priv->base,
1510 				 RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1511 
1512 		if (can_is_canfd_skb(skb)) {
1513 			/* CAN FD frame format */
1514 			sts |= RCANFD_CFFDCSTS_CFFDF;
1515 			if (cf->flags & CANFD_BRS)
1516 				sts |= RCANFD_CFFDCSTS_CFBRS;
1517 
1518 			if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1519 				sts |= RCANFD_CFFDCSTS_CFESI;
1520 		}
1521 
1522 		rcar_canfd_write(priv->base,
1523 				 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1524 
1525 		rcar_canfd_put_data(priv, cf,
1526 				    RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1527 	} else {
1528 		rcar_canfd_write(priv->base,
1529 				 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1530 		rcar_canfd_write(priv->base,
1531 				 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1532 		rcar_canfd_put_data(priv, cf,
1533 				    RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1534 	}
1535 
1536 	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1537 
1538 	spin_lock_irqsave(&priv->tx_lock, flags);
1539 	priv->tx_head++;
1540 
1541 	/* Stop the queue if we've filled all FIFO entries */
1542 	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1543 		netif_stop_queue(ndev);
1544 
1545 	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
1546 	 * pointer for the Common FIFO
1547 	 */
1548 	rcar_canfd_write(priv->base,
1549 			 RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1550 
1551 	spin_unlock_irqrestore(&priv->tx_lock, flags);
1552 	return NETDEV_TX_OK;
1553 }
1554 
rcar_canfd_rx_pkt(struct rcar_canfd_channel * priv)1555 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1556 {
1557 	struct net_device_stats *stats = &priv->ndev->stats;
1558 	struct rcar_canfd_global *gpriv = priv->gpriv;
1559 	struct canfd_frame *cf;
1560 	struct sk_buff *skb;
1561 	u32 sts = 0, id, dlc;
1562 	u32 ch = priv->channel;
1563 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1564 
1565 	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1566 		id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1567 		dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1568 
1569 		sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1570 
1571 		if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1572 		    sts & RCANFD_RFFDSTS_RFFDF)
1573 			skb = alloc_canfd_skb(priv->ndev, &cf);
1574 		else
1575 			skb = alloc_can_skb(priv->ndev,
1576 					    (struct can_frame **)&cf);
1577 	} else {
1578 		id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1579 		dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1580 		skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1581 	}
1582 
1583 	if (!skb) {
1584 		stats->rx_dropped++;
1585 		return;
1586 	}
1587 
1588 	if (id & RCANFD_RFID_RFIDE)
1589 		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1590 	else
1591 		cf->can_id = id & CAN_SFF_MASK;
1592 
1593 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1594 		if (sts & RCANFD_RFFDSTS_RFFDF)
1595 			cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1596 		else
1597 			cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1598 
1599 		if (sts & RCANFD_RFFDSTS_RFESI) {
1600 			cf->flags |= CANFD_ESI;
1601 			netdev_dbg(priv->ndev, "ESI Error\n");
1602 		}
1603 
1604 		if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1605 			cf->can_id |= CAN_RTR_FLAG;
1606 		} else {
1607 			if (sts & RCANFD_RFFDSTS_RFBRS)
1608 				cf->flags |= CANFD_BRS;
1609 
1610 			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1611 		}
1612 	} else {
1613 		cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1614 		if (id & RCANFD_RFID_RFRTR)
1615 			cf->can_id |= CAN_RTR_FLAG;
1616 		else if (is_gen4(gpriv))
1617 			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1618 		else
1619 			rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1620 	}
1621 
1622 	/* Write 0xff to RFPC to increment the CPU-side
1623 	 * pointer of the Rx FIFO
1624 	 */
1625 	rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1626 
1627 	if (!(cf->can_id & CAN_RTR_FLAG))
1628 		stats->rx_bytes += cf->len;
1629 	stats->rx_packets++;
1630 	netif_receive_skb(skb);
1631 }
1632 
rcar_canfd_rx_poll(struct napi_struct * napi,int quota)1633 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1634 {
1635 	struct rcar_canfd_channel *priv =
1636 		container_of(napi, struct rcar_canfd_channel, napi);
1637 	struct rcar_canfd_global *gpriv = priv->gpriv;
1638 	int num_pkts;
1639 	u32 sts;
1640 	u32 ch = priv->channel;
1641 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1642 
1643 	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1644 		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1645 		/* Check FIFO empty condition */
1646 		if (sts & RCANFD_RFSTS_RFEMP)
1647 			break;
1648 
1649 		rcar_canfd_rx_pkt(priv);
1650 
1651 		/* Clear interrupt bit */
1652 		if (sts & RCANFD_RFSTS_RFIF)
1653 			rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1654 					 sts & ~RCANFD_RFSTS_RFIF);
1655 	}
1656 
1657 	/* All packets processed */
1658 	if (num_pkts < quota) {
1659 		if (napi_complete_done(napi, num_pkts)) {
1660 			/* Enable Rx FIFO interrupts */
1661 			rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1662 					   RCANFD_RFCC_RFIE);
1663 		}
1664 	}
1665 	return num_pkts;
1666 }
1667 
rcar_canfd_do_set_mode(struct net_device * ndev,enum can_mode mode)1668 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1669 {
1670 	int err;
1671 
1672 	switch (mode) {
1673 	case CAN_MODE_START:
1674 		err = rcar_canfd_start(ndev);
1675 		if (err)
1676 			return err;
1677 		netif_wake_queue(ndev);
1678 		return 0;
1679 	default:
1680 		return -EOPNOTSUPP;
1681 	}
1682 }
1683 
rcar_canfd_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)1684 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1685 				       struct can_berr_counter *bec)
1686 {
1687 	struct rcar_canfd_channel *priv = netdev_priv(dev);
1688 	u32 val, ch = priv->channel;
1689 
1690 	/* Peripheral clock is already enabled in probe */
1691 	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1692 	bec->txerr = RCANFD_CSTS_TECCNT(val);
1693 	bec->rxerr = RCANFD_CSTS_RECCNT(val);
1694 	return 0;
1695 }
1696 
1697 static const struct net_device_ops rcar_canfd_netdev_ops = {
1698 	.ndo_open = rcar_canfd_open,
1699 	.ndo_stop = rcar_canfd_close,
1700 	.ndo_start_xmit = rcar_canfd_start_xmit,
1701 	.ndo_change_mtu = can_change_mtu,
1702 };
1703 
1704 static const struct ethtool_ops rcar_canfd_ethtool_ops = {
1705 	.get_ts_info = ethtool_op_get_ts_info,
1706 };
1707 
rcar_canfd_channel_probe(struct rcar_canfd_global * gpriv,u32 ch,u32 fcan_freq,struct phy * transceiver)1708 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1709 				    u32 fcan_freq, struct phy *transceiver)
1710 {
1711 	const struct rcar_canfd_hw_info *info = gpriv->info;
1712 	struct platform_device *pdev = gpriv->pdev;
1713 	struct device *dev = &pdev->dev;
1714 	struct rcar_canfd_channel *priv;
1715 	struct net_device *ndev;
1716 	int err = -ENODEV;
1717 
1718 	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1719 	if (!ndev)
1720 		return -ENOMEM;
1721 
1722 	priv = netdev_priv(ndev);
1723 
1724 	ndev->netdev_ops = &rcar_canfd_netdev_ops;
1725 	ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1726 	ndev->flags |= IFF_ECHO;
1727 	priv->ndev = ndev;
1728 	priv->base = gpriv->base;
1729 	priv->transceiver = transceiver;
1730 	priv->channel = ch;
1731 	priv->gpriv = gpriv;
1732 	if (transceiver)
1733 		priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1734 	priv->can.clock.freq = fcan_freq;
1735 	dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1736 
1737 	if (info->multi_channel_irqs) {
1738 		char *irq_name;
1739 		int err_irq;
1740 		int tx_irq;
1741 
1742 		err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1743 		if (err_irq < 0) {
1744 			err = err_irq;
1745 			goto fail;
1746 		}
1747 
1748 		tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1749 		if (tx_irq < 0) {
1750 			err = tx_irq;
1751 			goto fail;
1752 		}
1753 
1754 		irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1755 					  ch);
1756 		if (!irq_name) {
1757 			err = -ENOMEM;
1758 			goto fail;
1759 		}
1760 		err = devm_request_irq(dev, err_irq,
1761 				       rcar_canfd_channel_err_interrupt, 0,
1762 				       irq_name, priv);
1763 		if (err) {
1764 			dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n",
1765 				err_irq, ERR_PTR(err));
1766 			goto fail;
1767 		}
1768 		irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1769 					  ch);
1770 		if (!irq_name) {
1771 			err = -ENOMEM;
1772 			goto fail;
1773 		}
1774 		err = devm_request_irq(dev, tx_irq,
1775 				       rcar_canfd_channel_tx_interrupt, 0,
1776 				       irq_name, priv);
1777 		if (err) {
1778 			dev_err(dev, "devm_request_irq Tx %d failed: %pe\n",
1779 				tx_irq, ERR_PTR(err));
1780 			goto fail;
1781 		}
1782 	}
1783 
1784 	if (gpriv->fdmode) {
1785 		priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1786 		priv->can.data_bittiming_const =
1787 			&rcar_canfd_data_bittiming_const;
1788 
1789 		/* Controller starts in CAN FD only mode */
1790 		err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1791 		if (err)
1792 			goto fail;
1793 		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1794 	} else {
1795 		/* Controller starts in Classical CAN only mode */
1796 		priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1797 		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1798 	}
1799 
1800 	priv->can.do_set_mode = rcar_canfd_do_set_mode;
1801 	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1802 	SET_NETDEV_DEV(ndev, dev);
1803 
1804 	netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1805 			      RCANFD_NAPI_WEIGHT);
1806 	spin_lock_init(&priv->tx_lock);
1807 	gpriv->ch[priv->channel] = priv;
1808 	err = register_candev(ndev);
1809 	if (err) {
1810 		dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err));
1811 		goto fail_candev;
1812 	}
1813 	dev_info(dev, "device registered (channel %u)\n", priv->channel);
1814 	return 0;
1815 
1816 fail_candev:
1817 	netif_napi_del(&priv->napi);
1818 fail:
1819 	free_candev(ndev);
1820 	return err;
1821 }
1822 
rcar_canfd_channel_remove(struct rcar_canfd_global * gpriv,u32 ch)1823 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1824 {
1825 	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1826 
1827 	if (priv) {
1828 		unregister_candev(priv->ndev);
1829 		netif_napi_del(&priv->napi);
1830 		free_candev(priv->ndev);
1831 	}
1832 }
1833 
rcar_canfd_probe(struct platform_device * pdev)1834 static int rcar_canfd_probe(struct platform_device *pdev)
1835 {
1836 	struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, };
1837 	const struct rcar_canfd_hw_info *info;
1838 	struct device *dev = &pdev->dev;
1839 	void __iomem *addr;
1840 	u32 sts, ch, fcan_freq;
1841 	struct rcar_canfd_global *gpriv;
1842 	struct device_node *of_child;
1843 	unsigned long channels_mask = 0;
1844 	int err, ch_irq, g_irq;
1845 	int g_err_irq, g_recc_irq;
1846 	u32 rule_entry = 0;
1847 	bool fdmode = true;			/* CAN FD only mode - default */
1848 	char name[9] = "channelX";
1849 	int i;
1850 
1851 	info = of_device_get_match_data(dev);
1852 
1853 	if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
1854 		fdmode = false;			/* Classical CAN only mode */
1855 
1856 	for (i = 0; i < info->max_channels; ++i) {
1857 		name[7] = '0' + i;
1858 		of_child = of_get_child_by_name(dev->of_node, name);
1859 		if (of_child && of_device_is_available(of_child)) {
1860 			channels_mask |= BIT(i);
1861 			transceivers[i] = devm_of_phy_optional_get(dev,
1862 							of_child, NULL);
1863 		}
1864 		of_node_put(of_child);
1865 		if (IS_ERR(transceivers[i]))
1866 			return PTR_ERR(transceivers[i]);
1867 	}
1868 
1869 	if (info->shared_global_irqs) {
1870 		ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1871 		if (ch_irq < 0) {
1872 			/* For backward compatibility get irq by index */
1873 			ch_irq = platform_get_irq(pdev, 0);
1874 			if (ch_irq < 0)
1875 				return ch_irq;
1876 		}
1877 
1878 		g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1879 		if (g_irq < 0) {
1880 			/* For backward compatibility get irq by index */
1881 			g_irq = platform_get_irq(pdev, 1);
1882 			if (g_irq < 0)
1883 				return g_irq;
1884 		}
1885 	} else {
1886 		g_err_irq = platform_get_irq_byname(pdev, "g_err");
1887 		if (g_err_irq < 0)
1888 			return g_err_irq;
1889 
1890 		g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1891 		if (g_recc_irq < 0)
1892 			return g_recc_irq;
1893 	}
1894 
1895 	/* Global controller context */
1896 	gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL);
1897 	if (!gpriv)
1898 		return -ENOMEM;
1899 
1900 	gpriv->pdev = pdev;
1901 	gpriv->channels_mask = channels_mask;
1902 	gpriv->fdmode = fdmode;
1903 	gpriv->info = info;
1904 
1905 	gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
1906 	if (IS_ERR(gpriv->rstc1))
1907 		return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
1908 				     "failed to get rstp_n\n");
1909 
1910 	gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
1911 	if (IS_ERR(gpriv->rstc2))
1912 		return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
1913 				     "failed to get rstc_n\n");
1914 
1915 	/* Peripheral clock */
1916 	gpriv->clkp = devm_clk_get(dev, "fck");
1917 	if (IS_ERR(gpriv->clkp))
1918 		return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
1919 				     "cannot get peripheral clock\n");
1920 
1921 	/* fCAN clock: Pick External clock. If not available fallback to
1922 	 * CANFD clock
1923 	 */
1924 	gpriv->can_clk = devm_clk_get(dev, "can_clk");
1925 	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1926 		gpriv->can_clk = devm_clk_get(dev, "canfd");
1927 		if (IS_ERR(gpriv->can_clk))
1928 			return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
1929 					     "cannot get canfd clock\n");
1930 
1931 		/* CANFD clock may be further divided within the IP */
1932 		fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv;
1933 	} else {
1934 		fcan_freq = clk_get_rate(gpriv->can_clk);
1935 		gpriv->extclk = true;
1936 	}
1937 
1938 	addr = devm_platform_ioremap_resource(pdev, 0);
1939 	if (IS_ERR(addr)) {
1940 		err = PTR_ERR(addr);
1941 		goto fail_dev;
1942 	}
1943 	gpriv->base = addr;
1944 
1945 	/* Request IRQ that's common for both channels */
1946 	if (info->shared_global_irqs) {
1947 		err = devm_request_irq(dev, ch_irq,
1948 				       rcar_canfd_channel_interrupt, 0,
1949 				       "canfd.ch_int", gpriv);
1950 		if (err) {
1951 			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1952 				ch_irq, ERR_PTR(err));
1953 			goto fail_dev;
1954 		}
1955 
1956 		err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt,
1957 				       0, "canfd.g_int", gpriv);
1958 		if (err) {
1959 			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1960 				g_irq, ERR_PTR(err));
1961 			goto fail_dev;
1962 		}
1963 	} else {
1964 		err = devm_request_irq(dev, g_recc_irq,
1965 				       rcar_canfd_global_receive_fifo_interrupt, 0,
1966 				       "canfd.g_recc", gpriv);
1967 
1968 		if (err) {
1969 			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1970 				g_recc_irq, ERR_PTR(err));
1971 			goto fail_dev;
1972 		}
1973 
1974 		err = devm_request_irq(dev, g_err_irq,
1975 				       rcar_canfd_global_err_interrupt, 0,
1976 				       "canfd.g_err", gpriv);
1977 		if (err) {
1978 			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1979 				g_err_irq, ERR_PTR(err));
1980 			goto fail_dev;
1981 		}
1982 	}
1983 
1984 	err = reset_control_reset(gpriv->rstc1);
1985 	if (err)
1986 		goto fail_dev;
1987 	err = reset_control_reset(gpriv->rstc2);
1988 	if (err) {
1989 		reset_control_assert(gpriv->rstc1);
1990 		goto fail_dev;
1991 	}
1992 
1993 	/* Enable peripheral clock for register access */
1994 	err = clk_prepare_enable(gpriv->clkp);
1995 	if (err) {
1996 		dev_err(dev, "failed to enable peripheral clock: %pe\n",
1997 			ERR_PTR(err));
1998 		goto fail_reset;
1999 	}
2000 
2001 	err = rcar_canfd_reset_controller(gpriv);
2002 	if (err) {
2003 		dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
2004 		goto fail_clk;
2005 	}
2006 
2007 	/* Controller in Global reset & Channel reset mode */
2008 	rcar_canfd_configure_controller(gpriv);
2009 
2010 	/* Configure per channel attributes */
2011 	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2012 		/* Configure Channel's Rx fifo */
2013 		rcar_canfd_configure_rx(gpriv, ch);
2014 
2015 		/* Configure Channel's Tx (Common) fifo */
2016 		rcar_canfd_configure_tx(gpriv, ch);
2017 
2018 		/* Configure receive rules */
2019 		rcar_canfd_configure_afl_rules(gpriv, ch, rule_entry);
2020 		rule_entry += RCANFD_CHANNEL_NUMRULES;
2021 	}
2022 
2023 	/* Configure common interrupts */
2024 	rcar_canfd_enable_global_interrupts(gpriv);
2025 
2026 	/* Start Global operation mode */
2027 	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2028 			      RCANFD_GCTR_GMDC_GOPM);
2029 
2030 	/* Verify mode change */
2031 	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2032 				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2033 	if (err) {
2034 		dev_err(dev, "global operational mode failed\n");
2035 		goto fail_mode;
2036 	}
2037 
2038 	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2039 		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq,
2040 					       transceivers[ch]);
2041 		if (err)
2042 			goto fail_channel;
2043 	}
2044 
2045 	platform_set_drvdata(pdev, gpriv);
2046 	dev_info(dev, "global operational state (%s clk, %s mode)\n",
2047 		 gpriv->extclk ? "ext" : "canfd",
2048 		 gpriv->fdmode ? "fd" : "classical");
2049 	return 0;
2050 
2051 fail_channel:
2052 	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2053 		rcar_canfd_channel_remove(gpriv, ch);
2054 fail_mode:
2055 	rcar_canfd_disable_global_interrupts(gpriv);
2056 fail_clk:
2057 	clk_disable_unprepare(gpriv->clkp);
2058 fail_reset:
2059 	reset_control_assert(gpriv->rstc1);
2060 	reset_control_assert(gpriv->rstc2);
2061 fail_dev:
2062 	return err;
2063 }
2064 
rcar_canfd_remove(struct platform_device * pdev)2065 static void rcar_canfd_remove(struct platform_device *pdev)
2066 {
2067 	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2068 	u32 ch;
2069 
2070 	rcar_canfd_reset_controller(gpriv);
2071 	rcar_canfd_disable_global_interrupts(gpriv);
2072 
2073 	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2074 		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2075 		rcar_canfd_channel_remove(gpriv, ch);
2076 	}
2077 
2078 	/* Enter global sleep mode */
2079 	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2080 	clk_disable_unprepare(gpriv->clkp);
2081 	reset_control_assert(gpriv->rstc1);
2082 	reset_control_assert(gpriv->rstc2);
2083 }
2084 
rcar_canfd_suspend(struct device * dev)2085 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2086 {
2087 	return 0;
2088 }
2089 
rcar_canfd_resume(struct device * dev)2090 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2091 {
2092 	return 0;
2093 }
2094 
2095 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2096 			 rcar_canfd_resume);
2097 
2098 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2099 	{ .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2100 	{ .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2101 	{ .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2102 	{ .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2103 	{ }
2104 };
2105 
2106 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2107 
2108 static struct platform_driver rcar_canfd_driver = {
2109 	.driver = {
2110 		.name = RCANFD_DRV_NAME,
2111 		.of_match_table = of_match_ptr(rcar_canfd_of_table),
2112 		.pm = &rcar_canfd_pm_ops,
2113 	},
2114 	.probe = rcar_canfd_probe,
2115 	.remove = rcar_canfd_remove,
2116 };
2117 
2118 module_platform_driver(rcar_canfd_driver);
2119 
2120 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
2121 MODULE_LICENSE("GPL");
2122 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2123 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
2124