1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2008-2010 Nikolay Denev <ndenev@gmail.com>
5 * Copyright (c) 2007-2008 Alexander Pohoyda <alexander.pohoyda@gmx.net>
6 * Copyright (c) 1997, 1998, 1999
7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Bill Paul.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR
28 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
35 * OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 /*
40 * SiS 190/191 PCI Ethernet NIC driver.
41 *
42 * Adapted to SiS 190 NIC by Alexander Pohoyda based on the original
43 * SiS 900 driver by Bill Paul, using SiS 190/191 Solaris driver by
44 * Masayuki Murayama and SiS 190/191 GNU/Linux driver by K.M. Liu
45 * <kmliu@sis.com>. Thanks to Pyun YongHyeon <pyunyh@gmail.com> for
46 * review and very useful comments.
47 *
48 * Adapted to SiS 191 NIC by Nikolay Denev with further ideas from the
49 * Linux and Solaris drivers.
50 */
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/bus.h>
55 #include <sys/endian.h>
56 #include <sys/kernel.h>
57 #include <sys/lock.h>
58 #include <sys/malloc.h>
59 #include <sys/mbuf.h>
60 #include <sys/module.h>
61 #include <sys/mutex.h>
62 #include <sys/rman.h>
63 #include <sys/socket.h>
64 #include <sys/sockio.h>
65
66 #include <net/bpf.h>
67 #include <net/if.h>
68 #include <net/if_var.h>
69 #include <net/if_arp.h>
70 #include <net/ethernet.h>
71 #include <net/if_dl.h>
72 #include <net/if_media.h>
73 #include <net/if_types.h>
74 #include <net/if_vlan_var.h>
75
76 #include <netinet/in.h>
77 #include <netinet/in_systm.h>
78 #include <netinet/ip.h>
79 #include <netinet/tcp.h>
80
81 #include <machine/bus.h>
82 #include <machine/in_cksum.h>
83
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
86
87 #include <dev/pci/pcireg.h>
88 #include <dev/pci/pcivar.h>
89
90 #include <dev/sge/if_sgereg.h>
91
92 MODULE_DEPEND(sge, pci, 1, 1, 1);
93 MODULE_DEPEND(sge, ether, 1, 1, 1);
94 MODULE_DEPEND(sge, miibus, 1, 1, 1);
95
96 /* "device miibus0" required. See GENERIC if you get errors here. */
97 #include "miibus_if.h"
98
99 /*
100 * Various supported device vendors/types and their names.
101 */
102 static struct sge_type sge_devs[] = {
103 { SIS_VENDORID, SIS_DEVICEID_190, "SiS190 Fast Ethernet" },
104 { SIS_VENDORID, SIS_DEVICEID_191, "SiS191 Fast/Gigabit Ethernet" },
105 { 0, 0, NULL }
106 };
107
108 static int sge_probe(device_t);
109 static int sge_attach(device_t);
110 static int sge_detach(device_t);
111 static int sge_shutdown(device_t);
112 static int sge_suspend(device_t);
113 static int sge_resume(device_t);
114
115 static int sge_miibus_readreg(device_t, int, int);
116 static int sge_miibus_writereg(device_t, int, int, int);
117 static void sge_miibus_statchg(device_t);
118
119 static int sge_newbuf(struct sge_softc *, int);
120 static int sge_encap(struct sge_softc *, struct mbuf **);
121 static __inline void
122 sge_discard_rxbuf(struct sge_softc *, int);
123 static void sge_rxeof(struct sge_softc *);
124 static void sge_txeof(struct sge_softc *);
125 static void sge_intr(void *);
126 static void sge_tick(void *);
127 static void sge_start(if_t);
128 static void sge_start_locked(if_t);
129 static int sge_ioctl(if_t, u_long, caddr_t);
130 static void sge_init(void *);
131 static void sge_init_locked(struct sge_softc *);
132 static void sge_stop(struct sge_softc *);
133 static void sge_watchdog(struct sge_softc *);
134 static int sge_ifmedia_upd(if_t);
135 static void sge_ifmedia_sts(if_t, struct ifmediareq *);
136
137 static int sge_get_mac_addr_apc(struct sge_softc *, uint8_t *);
138 static int sge_get_mac_addr_eeprom(struct sge_softc *, uint8_t *);
139 static uint16_t sge_read_eeprom(struct sge_softc *, int);
140
141 static void sge_rxfilter(struct sge_softc *);
142 static void sge_setvlan(struct sge_softc *);
143 static void sge_reset(struct sge_softc *);
144 static int sge_list_rx_init(struct sge_softc *);
145 static int sge_list_rx_free(struct sge_softc *);
146 static int sge_list_tx_init(struct sge_softc *);
147 static int sge_list_tx_free(struct sge_softc *);
148
149 static int sge_dma_alloc(struct sge_softc *);
150 static void sge_dma_free(struct sge_softc *);
151 static void sge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
152
153 static device_method_t sge_methods[] = {
154 /* Device interface */
155 DEVMETHOD(device_probe, sge_probe),
156 DEVMETHOD(device_attach, sge_attach),
157 DEVMETHOD(device_detach, sge_detach),
158 DEVMETHOD(device_suspend, sge_suspend),
159 DEVMETHOD(device_resume, sge_resume),
160 DEVMETHOD(device_shutdown, sge_shutdown),
161
162 /* MII interface */
163 DEVMETHOD(miibus_readreg, sge_miibus_readreg),
164 DEVMETHOD(miibus_writereg, sge_miibus_writereg),
165 DEVMETHOD(miibus_statchg, sge_miibus_statchg),
166
167 DEVMETHOD_END
168 };
169
170 static driver_t sge_driver = {
171 "sge", sge_methods, sizeof(struct sge_softc)
172 };
173
174 DRIVER_MODULE(sge, pci, sge_driver, 0, 0);
175 DRIVER_MODULE(miibus, sge, miibus_driver, 0, 0);
176
177 /*
178 * Register space access macros.
179 */
180 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val)
181 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)
182 #define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val)
183
184 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg)
185 #define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg)
186 #define CSR_READ_1(sc, reg) bus_read_1(sc->sge_res, reg)
187
188 /* Define to show Tx/Rx error status. */
189 #undef SGE_SHOW_ERRORS
190
191 #define SGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
192
193 static void
sge_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)194 sge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
195 {
196 bus_addr_t *p;
197
198 if (error != 0)
199 return;
200 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
201 p = arg;
202 *p = segs->ds_addr;
203 }
204
205 /*
206 * Read a sequence of words from the EEPROM.
207 */
208 static uint16_t
sge_read_eeprom(struct sge_softc * sc,int offset)209 sge_read_eeprom(struct sge_softc *sc, int offset)
210 {
211 uint32_t val;
212 int i;
213
214 KASSERT(offset <= EI_OFFSET, ("EEPROM offset too big"));
215 CSR_WRITE_4(sc, ROMInterface,
216 EI_REQ | EI_OP_RD | (offset << EI_OFFSET_SHIFT));
217 DELAY(500);
218 for (i = 0; i < SGE_TIMEOUT; i++) {
219 val = CSR_READ_4(sc, ROMInterface);
220 if ((val & EI_REQ) == 0)
221 break;
222 DELAY(100);
223 }
224 if (i == SGE_TIMEOUT) {
225 device_printf(sc->sge_dev,
226 "EEPROM read timeout : 0x%08x\n", val);
227 return (0xffff);
228 }
229
230 return ((val & EI_DATA) >> EI_DATA_SHIFT);
231 }
232
233 static int
sge_get_mac_addr_eeprom(struct sge_softc * sc,uint8_t * dest)234 sge_get_mac_addr_eeprom(struct sge_softc *sc, uint8_t *dest)
235 {
236 uint16_t val;
237 int i;
238
239 val = sge_read_eeprom(sc, EEPROMSignature);
240 if (val == 0xffff || val == 0) {
241 device_printf(sc->sge_dev,
242 "invalid EEPROM signature : 0x%04x\n", val);
243 return (EINVAL);
244 }
245
246 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
247 val = sge_read_eeprom(sc, EEPROMMACAddr + i / 2);
248 dest[i + 0] = (uint8_t)val;
249 dest[i + 1] = (uint8_t)(val >> 8);
250 }
251
252 if ((sge_read_eeprom(sc, EEPROMInfo) & 0x80) != 0)
253 sc->sge_flags |= SGE_FLAG_RGMII;
254 return (0);
255 }
256
257 /*
258 * For SiS96x, APC CMOS RAM is used to store ethernet address.
259 * APC CMOS RAM is accessed through ISA bridge.
260 */
261 static int
sge_get_mac_addr_apc(struct sge_softc * sc,uint8_t * dest)262 sge_get_mac_addr_apc(struct sge_softc *sc, uint8_t *dest)
263 {
264 #if defined(__amd64__) || defined(__i386__)
265 devclass_t pci;
266 device_t bus, dev = NULL;
267 device_t *kids;
268 struct apc_tbl {
269 uint16_t vid;
270 uint16_t did;
271 } *tp, apc_tbls[] = {
272 { SIS_VENDORID, 0x0965 },
273 { SIS_VENDORID, 0x0966 },
274 { SIS_VENDORID, 0x0968 }
275 };
276 uint8_t reg;
277 int busnum, i, j, numkids;
278
279 pci = devclass_find("pci");
280 for (busnum = 0; busnum < devclass_get_maxunit(pci); busnum++) {
281 bus = devclass_get_device(pci, busnum);
282 if (!bus)
283 continue;
284 if (device_get_children(bus, &kids, &numkids) != 0)
285 continue;
286 for (i = 0; i < numkids; i++) {
287 dev = kids[i];
288 if (pci_get_class(dev) == PCIC_BRIDGE &&
289 pci_get_subclass(dev) == PCIS_BRIDGE_ISA) {
290 tp = apc_tbls;
291 for (j = 0; j < nitems(apc_tbls); j++) {
292 if (pci_get_vendor(dev) == tp->vid &&
293 pci_get_device(dev) == tp->did) {
294 free(kids, M_TEMP);
295 goto apc_found;
296 }
297 tp++;
298 }
299 }
300 }
301 free(kids, M_TEMP);
302 }
303 device_printf(sc->sge_dev, "couldn't find PCI-ISA bridge\n");
304 return (EINVAL);
305 apc_found:
306 /* Enable port 0x78 and 0x79 to access APC registers. */
307 reg = pci_read_config(dev, 0x48, 1);
308 pci_write_config(dev, 0x48, reg & ~0x02, 1);
309 DELAY(50);
310 pci_read_config(dev, 0x48, 1);
311 /* Read stored ethernet address. */
312 for (i = 0; i < ETHER_ADDR_LEN; i++) {
313 outb(0x78, 0x09 + i);
314 dest[i] = inb(0x79);
315 }
316 outb(0x78, 0x12);
317 if ((inb(0x79) & 0x80) != 0)
318 sc->sge_flags |= SGE_FLAG_RGMII;
319 /* Restore access to APC registers. */
320 pci_write_config(dev, 0x48, reg, 1);
321
322 return (0);
323 #else
324 return (EINVAL);
325 #endif
326 }
327
328 static int
sge_miibus_readreg(device_t dev,int phy,int reg)329 sge_miibus_readreg(device_t dev, int phy, int reg)
330 {
331 struct sge_softc *sc;
332 uint32_t val;
333 int i;
334
335 sc = device_get_softc(dev);
336 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
337 (reg << GMI_REG_SHIFT) | GMI_OP_RD | GMI_REQ);
338 DELAY(10);
339 for (i = 0; i < SGE_TIMEOUT; i++) {
340 val = CSR_READ_4(sc, GMIIControl);
341 if ((val & GMI_REQ) == 0)
342 break;
343 DELAY(10);
344 }
345 if (i == SGE_TIMEOUT) {
346 device_printf(sc->sge_dev, "PHY read timeout : %d\n", reg);
347 return (0);
348 }
349 return ((val & GMI_DATA) >> GMI_DATA_SHIFT);
350 }
351
352 static int
sge_miibus_writereg(device_t dev,int phy,int reg,int data)353 sge_miibus_writereg(device_t dev, int phy, int reg, int data)
354 {
355 struct sge_softc *sc;
356 uint32_t val;
357 int i;
358
359 sc = device_get_softc(dev);
360 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
361 (reg << GMI_REG_SHIFT) | (data << GMI_DATA_SHIFT) |
362 GMI_OP_WR | GMI_REQ);
363 DELAY(10);
364 for (i = 0; i < SGE_TIMEOUT; i++) {
365 val = CSR_READ_4(sc, GMIIControl);
366 if ((val & GMI_REQ) == 0)
367 break;
368 DELAY(10);
369 }
370 if (i == SGE_TIMEOUT)
371 device_printf(sc->sge_dev, "PHY write timeout : %d\n", reg);
372 return (0);
373 }
374
375 static void
sge_miibus_statchg(device_t dev)376 sge_miibus_statchg(device_t dev)
377 {
378 struct sge_softc *sc;
379 struct mii_data *mii;
380 if_t ifp;
381 uint32_t ctl, speed;
382
383 sc = device_get_softc(dev);
384 mii = device_get_softc(sc->sge_miibus);
385 ifp = sc->sge_ifp;
386 if (mii == NULL || ifp == NULL ||
387 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
388 return;
389 speed = 0;
390 sc->sge_flags &= ~SGE_FLAG_LINK;
391 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
392 (IFM_ACTIVE | IFM_AVALID)) {
393 switch (IFM_SUBTYPE(mii->mii_media_active)) {
394 case IFM_10_T:
395 sc->sge_flags |= SGE_FLAG_LINK;
396 speed = SC_SPEED_10;
397 break;
398 case IFM_100_TX:
399 sc->sge_flags |= SGE_FLAG_LINK;
400 speed = SC_SPEED_100;
401 break;
402 case IFM_1000_T:
403 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0) {
404 sc->sge_flags |= SGE_FLAG_LINK;
405 speed = SC_SPEED_1000;
406 }
407 break;
408 default:
409 break;
410 }
411 }
412 if ((sc->sge_flags & SGE_FLAG_LINK) == 0)
413 return;
414 /* Reprogram MAC to resolved speed/duplex/flow-control parameters. */
415 ctl = CSR_READ_4(sc, StationControl);
416 ctl &= ~(0x0f000000 | SC_FDX | SC_SPEED_MASK);
417 if (speed == SC_SPEED_1000) {
418 ctl |= 0x07000000;
419 sc->sge_flags |= SGE_FLAG_SPEED_1000;
420 } else {
421 ctl |= 0x04000000;
422 sc->sge_flags &= ~SGE_FLAG_SPEED_1000;
423 }
424 #ifdef notyet
425 if ((sc->sge_flags & SGE_FLAG_GMII) != 0)
426 ctl |= 0x03000000;
427 #endif
428 ctl |= speed;
429 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
430 ctl |= SC_FDX;
431 sc->sge_flags |= SGE_FLAG_FDX;
432 } else
433 sc->sge_flags &= ~SGE_FLAG_FDX;
434 CSR_WRITE_4(sc, StationControl, ctl);
435 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0) {
436 CSR_WRITE_4(sc, RGMIIDelay, 0x0441);
437 CSR_WRITE_4(sc, RGMIIDelay, 0x0440);
438 }
439 }
440
441 static u_int
sge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int count)442 sge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count)
443 {
444 uint32_t crc, *hashes = arg;
445
446 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
447 hashes[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
448
449 return (1);
450 }
451
452 static void
sge_rxfilter(struct sge_softc * sc)453 sge_rxfilter(struct sge_softc *sc)
454 {
455 if_t ifp;
456 uint32_t hashes[2];
457 uint16_t rxfilt;
458
459 SGE_LOCK_ASSERT(sc);
460
461 ifp = sc->sge_ifp;
462 rxfilt = CSR_READ_2(sc, RxMacControl);
463 rxfilt &= ~(AcceptBroadcast | AcceptAllPhys | AcceptMulticast);
464 rxfilt |= AcceptMyPhys;
465 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
466 rxfilt |= AcceptBroadcast;
467 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
468 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
469 rxfilt |= AcceptAllPhys;
470 rxfilt |= AcceptMulticast;
471 hashes[0] = 0xFFFFFFFF;
472 hashes[1] = 0xFFFFFFFF;
473 } else {
474 rxfilt |= AcceptMulticast;
475 hashes[0] = hashes[1] = 0;
476 /* Now program new ones. */
477 if_foreach_llmaddr(ifp, sge_hash_maddr, hashes);
478 }
479 CSR_WRITE_2(sc, RxMacControl, rxfilt);
480 CSR_WRITE_4(sc, RxHashTable, hashes[0]);
481 CSR_WRITE_4(sc, RxHashTable2, hashes[1]);
482 }
483
484 static void
sge_setvlan(struct sge_softc * sc)485 sge_setvlan(struct sge_softc *sc)
486 {
487 if_t ifp;
488 uint16_t rxfilt;
489
490 SGE_LOCK_ASSERT(sc);
491
492 ifp = sc->sge_ifp;
493 if ((if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
494 return;
495 rxfilt = CSR_READ_2(sc, RxMacControl);
496 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
497 rxfilt |= RXMAC_STRIP_VLAN;
498 else
499 rxfilt &= ~RXMAC_STRIP_VLAN;
500 CSR_WRITE_2(sc, RxMacControl, rxfilt);
501 }
502
503 static void
sge_reset(struct sge_softc * sc)504 sge_reset(struct sge_softc *sc)
505 {
506
507 CSR_WRITE_4(sc, IntrMask, 0);
508 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
509
510 /* Soft reset. */
511 CSR_WRITE_4(sc, IntrControl, 0x8000);
512 CSR_READ_4(sc, IntrControl);
513 DELAY(100);
514 CSR_WRITE_4(sc, IntrControl, 0);
515 /* Stop MAC. */
516 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
517 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
518
519 CSR_WRITE_4(sc, IntrMask, 0);
520 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
521
522 CSR_WRITE_4(sc, GMIIControl, 0);
523 }
524
525 /*
526 * Probe for an SiS chip. Check the PCI vendor and device
527 * IDs against our list and return a device name if we find a match.
528 */
529 static int
sge_probe(device_t dev)530 sge_probe(device_t dev)
531 {
532 struct sge_type *t;
533
534 t = sge_devs;
535 while (t->sge_name != NULL) {
536 if ((pci_get_vendor(dev) == t->sge_vid) &&
537 (pci_get_device(dev) == t->sge_did)) {
538 device_set_desc(dev, t->sge_name);
539 return (BUS_PROBE_DEFAULT);
540 }
541 t++;
542 }
543
544 return (ENXIO);
545 }
546
547 /*
548 * Attach the interface. Allocate softc structures, do ifmedia
549 * setup and ethernet/BPF attach.
550 */
551 static int
sge_attach(device_t dev)552 sge_attach(device_t dev)
553 {
554 struct sge_softc *sc;
555 if_t ifp;
556 uint8_t eaddr[ETHER_ADDR_LEN];
557 int error = 0, rid;
558
559 sc = device_get_softc(dev);
560 sc->sge_dev = dev;
561
562 mtx_init(&sc->sge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
563 MTX_DEF);
564 callout_init_mtx(&sc->sge_stat_ch, &sc->sge_mtx, 0);
565
566 /*
567 * Map control/status registers.
568 */
569 pci_enable_busmaster(dev);
570
571 /* Allocate resources. */
572 sc->sge_res_id = PCIR_BAR(0);
573 sc->sge_res_type = SYS_RES_MEMORY;
574 sc->sge_res = bus_alloc_resource_any(dev, sc->sge_res_type,
575 &sc->sge_res_id, RF_ACTIVE);
576 if (sc->sge_res == NULL) {
577 device_printf(dev, "couldn't allocate resource\n");
578 error = ENXIO;
579 goto fail;
580 }
581
582 rid = 0;
583 sc->sge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
584 RF_SHAREABLE | RF_ACTIVE);
585 if (sc->sge_irq == NULL) {
586 device_printf(dev, "couldn't allocate IRQ resources\n");
587 error = ENXIO;
588 goto fail;
589 }
590 sc->sge_rev = pci_get_revid(dev);
591 if (pci_get_device(dev) == SIS_DEVICEID_190)
592 sc->sge_flags |= SGE_FLAG_FASTETHER | SGE_FLAG_SIS190;
593 /* Reset the adapter. */
594 sge_reset(sc);
595
596 /* Get MAC address from the EEPROM. */
597 if ((pci_read_config(dev, 0x73, 1) & 0x01) != 0)
598 sge_get_mac_addr_apc(sc, eaddr);
599 else
600 sge_get_mac_addr_eeprom(sc, eaddr);
601
602 if ((error = sge_dma_alloc(sc)) != 0)
603 goto fail;
604
605 ifp = sc->sge_ifp = if_alloc(IFT_ETHER);
606 if_setsoftc(ifp, sc);
607 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
608 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
609 if_setioctlfn(ifp, sge_ioctl);
610 if_setstartfn(ifp, sge_start);
611 if_setinitfn(ifp, sge_init);
612 if_setsendqlen(ifp, SGE_TX_RING_CNT - 1);
613 if_setsendqready(ifp);
614 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM | IFCAP_TSO4);
615 if_sethwassist(ifp, SGE_CSUM_FEATURES | CSUM_TSO);
616 if_setcapenable(ifp, if_getcapabilities(ifp));
617 /*
618 * Do MII setup.
619 */
620 error = mii_attach(dev, &sc->sge_miibus, ifp, sge_ifmedia_upd,
621 sge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
622 if (error != 0) {
623 device_printf(dev, "attaching PHYs failed\n");
624 goto fail;
625 }
626
627 /*
628 * Call MI attach routine.
629 */
630 ether_ifattach(ifp, eaddr);
631
632 /* VLAN setup. */
633 if_setcapabilities(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM |
634 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU);
635 if_setcapenable(ifp, if_getcapabilities(ifp));
636 /* Tell the upper layer(s) we support long frames. */
637 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
638
639 /* Hook interrupt last to avoid having to lock softc */
640 error = bus_setup_intr(dev, sc->sge_irq, INTR_TYPE_NET | INTR_MPSAFE,
641 NULL, sge_intr, sc, &sc->sge_intrhand);
642 if (error) {
643 device_printf(dev, "couldn't set up irq\n");
644 ether_ifdetach(ifp);
645 goto fail;
646 }
647
648 fail:
649 if (error)
650 sge_detach(dev);
651
652 return (error);
653 }
654
655 /*
656 * Shutdown hardware and free up resources. This can be called any
657 * time after the mutex has been initialized. It is called in both
658 * the error case in attach and the normal detach case so it needs
659 * to be careful about only freeing resources that have actually been
660 * allocated.
661 */
662 static int
sge_detach(device_t dev)663 sge_detach(device_t dev)
664 {
665 struct sge_softc *sc;
666 if_t ifp;
667
668 sc = device_get_softc(dev);
669 ifp = sc->sge_ifp;
670 /* These should only be active if attach succeeded. */
671 if (device_is_attached(dev)) {
672 ether_ifdetach(ifp);
673 SGE_LOCK(sc);
674 sge_stop(sc);
675 SGE_UNLOCK(sc);
676 callout_drain(&sc->sge_stat_ch);
677 }
678 if (sc->sge_miibus)
679 device_delete_child(dev, sc->sge_miibus);
680 bus_generic_detach(dev);
681
682 if (sc->sge_intrhand)
683 bus_teardown_intr(dev, sc->sge_irq, sc->sge_intrhand);
684 if (sc->sge_irq)
685 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sge_irq);
686 if (sc->sge_res)
687 bus_release_resource(dev, sc->sge_res_type, sc->sge_res_id,
688 sc->sge_res);
689 if (ifp)
690 if_free(ifp);
691 sge_dma_free(sc);
692 mtx_destroy(&sc->sge_mtx);
693
694 return (0);
695 }
696
697 /*
698 * Stop all chip I/O so that the kernel's probe routines don't
699 * get confused by errant DMAs when rebooting.
700 */
701 static int
sge_shutdown(device_t dev)702 sge_shutdown(device_t dev)
703 {
704 struct sge_softc *sc;
705
706 sc = device_get_softc(dev);
707 SGE_LOCK(sc);
708 sge_stop(sc);
709 SGE_UNLOCK(sc);
710 return (0);
711 }
712
713 static int
sge_suspend(device_t dev)714 sge_suspend(device_t dev)
715 {
716 struct sge_softc *sc;
717 if_t ifp;
718
719 sc = device_get_softc(dev);
720 SGE_LOCK(sc);
721 ifp = sc->sge_ifp;
722 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
723 sge_stop(sc);
724 SGE_UNLOCK(sc);
725 return (0);
726 }
727
728 static int
sge_resume(device_t dev)729 sge_resume(device_t dev)
730 {
731 struct sge_softc *sc;
732 if_t ifp;
733
734 sc = device_get_softc(dev);
735 SGE_LOCK(sc);
736 ifp = sc->sge_ifp;
737 if ((if_getflags(ifp) & IFF_UP) != 0)
738 sge_init_locked(sc);
739 SGE_UNLOCK(sc);
740 return (0);
741 }
742
743 static int
sge_dma_alloc(struct sge_softc * sc)744 sge_dma_alloc(struct sge_softc *sc)
745 {
746 struct sge_chain_data *cd;
747 struct sge_list_data *ld;
748 struct sge_rxdesc *rxd;
749 struct sge_txdesc *txd;
750 int error, i;
751
752 cd = &sc->sge_cdata;
753 ld = &sc->sge_ldata;
754 error = bus_dma_tag_create(bus_get_dma_tag(sc->sge_dev),
755 1, 0, /* alignment, boundary */
756 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
757 BUS_SPACE_MAXADDR, /* highaddr */
758 NULL, NULL, /* filter, filterarg */
759 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
760 1, /* nsegments */
761 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
762 0, /* flags */
763 NULL, /* lockfunc */
764 NULL, /* lockarg */
765 &cd->sge_tag);
766 if (error != 0) {
767 device_printf(sc->sge_dev,
768 "could not create parent DMA tag.\n");
769 goto fail;
770 }
771
772 /* RX descriptor ring */
773 error = bus_dma_tag_create(cd->sge_tag,
774 SGE_DESC_ALIGN, 0, /* alignment, boundary */
775 BUS_SPACE_MAXADDR, /* lowaddr */
776 BUS_SPACE_MAXADDR, /* highaddr */
777 NULL, NULL, /* filter, filterarg */
778 SGE_RX_RING_SZ, 1, /* maxsize,nsegments */
779 SGE_RX_RING_SZ, /* maxsegsize */
780 0, /* flags */
781 NULL, /* lockfunc */
782 NULL, /* lockarg */
783 &cd->sge_rx_tag);
784 if (error != 0) {
785 device_printf(sc->sge_dev,
786 "could not create Rx ring DMA tag.\n");
787 goto fail;
788 }
789 /* Allocate DMA'able memory and load DMA map for RX ring. */
790 error = bus_dmamem_alloc(cd->sge_rx_tag, (void **)&ld->sge_rx_ring,
791 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
792 &cd->sge_rx_dmamap);
793 if (error != 0) {
794 device_printf(sc->sge_dev,
795 "could not allocate DMA'able memory for Rx ring.\n");
796 goto fail;
797 }
798 error = bus_dmamap_load(cd->sge_rx_tag, cd->sge_rx_dmamap,
799 ld->sge_rx_ring, SGE_RX_RING_SZ, sge_dma_map_addr,
800 &ld->sge_rx_paddr, BUS_DMA_NOWAIT);
801 if (error != 0) {
802 device_printf(sc->sge_dev,
803 "could not load DMA'able memory for Rx ring.\n");
804 }
805
806 /* TX descriptor ring */
807 error = bus_dma_tag_create(cd->sge_tag,
808 SGE_DESC_ALIGN, 0, /* alignment, boundary */
809 BUS_SPACE_MAXADDR, /* lowaddr */
810 BUS_SPACE_MAXADDR, /* highaddr */
811 NULL, NULL, /* filter, filterarg */
812 SGE_TX_RING_SZ, 1, /* maxsize,nsegments */
813 SGE_TX_RING_SZ, /* maxsegsize */
814 0, /* flags */
815 NULL, /* lockfunc */
816 NULL, /* lockarg */
817 &cd->sge_tx_tag);
818 if (error != 0) {
819 device_printf(sc->sge_dev,
820 "could not create Rx ring DMA tag.\n");
821 goto fail;
822 }
823 /* Allocate DMA'able memory and load DMA map for TX ring. */
824 error = bus_dmamem_alloc(cd->sge_tx_tag, (void **)&ld->sge_tx_ring,
825 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
826 &cd->sge_tx_dmamap);
827 if (error != 0) {
828 device_printf(sc->sge_dev,
829 "could not allocate DMA'able memory for Tx ring.\n");
830 goto fail;
831 }
832 error = bus_dmamap_load(cd->sge_tx_tag, cd->sge_tx_dmamap,
833 ld->sge_tx_ring, SGE_TX_RING_SZ, sge_dma_map_addr,
834 &ld->sge_tx_paddr, BUS_DMA_NOWAIT);
835 if (error != 0) {
836 device_printf(sc->sge_dev,
837 "could not load DMA'able memory for Rx ring.\n");
838 goto fail;
839 }
840
841 /* Create DMA tag for Tx buffers. */
842 error = bus_dma_tag_create(cd->sge_tag, 1, 0, BUS_SPACE_MAXADDR,
843 BUS_SPACE_MAXADDR, NULL, NULL, SGE_TSO_MAXSIZE, SGE_MAXTXSEGS,
844 SGE_TSO_MAXSEGSIZE, 0, NULL, NULL, &cd->sge_txmbuf_tag);
845 if (error != 0) {
846 device_printf(sc->sge_dev,
847 "could not create Tx mbuf DMA tag.\n");
848 goto fail;
849 }
850
851 /* Create DMA tag for Rx buffers. */
852 error = bus_dma_tag_create(cd->sge_tag, SGE_RX_BUF_ALIGN, 0,
853 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
854 MCLBYTES, 0, NULL, NULL, &cd->sge_rxmbuf_tag);
855 if (error != 0) {
856 device_printf(sc->sge_dev,
857 "could not create Rx mbuf DMA tag.\n");
858 goto fail;
859 }
860
861 /* Create DMA maps for Tx buffers. */
862 for (i = 0; i < SGE_TX_RING_CNT; i++) {
863 txd = &cd->sge_txdesc[i];
864 txd->tx_m = NULL;
865 txd->tx_dmamap = NULL;
866 txd->tx_ndesc = 0;
867 error = bus_dmamap_create(cd->sge_txmbuf_tag, 0,
868 &txd->tx_dmamap);
869 if (error != 0) {
870 device_printf(sc->sge_dev,
871 "could not create Tx DMA map.\n");
872 goto fail;
873 }
874 }
875 /* Create spare DMA map for Rx buffer. */
876 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0, &cd->sge_rx_spare_map);
877 if (error != 0) {
878 device_printf(sc->sge_dev,
879 "could not create spare Rx DMA map.\n");
880 goto fail;
881 }
882 /* Create DMA maps for Rx buffers. */
883 for (i = 0; i < SGE_RX_RING_CNT; i++) {
884 rxd = &cd->sge_rxdesc[i];
885 rxd->rx_m = NULL;
886 rxd->rx_dmamap = NULL;
887 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0,
888 &rxd->rx_dmamap);
889 if (error) {
890 device_printf(sc->sge_dev,
891 "could not create Rx DMA map.\n");
892 goto fail;
893 }
894 }
895 fail:
896 return (error);
897 }
898
899 static void
sge_dma_free(struct sge_softc * sc)900 sge_dma_free(struct sge_softc *sc)
901 {
902 struct sge_chain_data *cd;
903 struct sge_list_data *ld;
904 struct sge_rxdesc *rxd;
905 struct sge_txdesc *txd;
906 int i;
907
908 cd = &sc->sge_cdata;
909 ld = &sc->sge_ldata;
910 /* Rx ring. */
911 if (cd->sge_rx_tag != NULL) {
912 if (ld->sge_rx_paddr != 0)
913 bus_dmamap_unload(cd->sge_rx_tag, cd->sge_rx_dmamap);
914 if (ld->sge_rx_ring != NULL)
915 bus_dmamem_free(cd->sge_rx_tag, ld->sge_rx_ring,
916 cd->sge_rx_dmamap);
917 ld->sge_rx_ring = NULL;
918 ld->sge_rx_paddr = 0;
919 bus_dma_tag_destroy(cd->sge_rx_tag);
920 cd->sge_rx_tag = NULL;
921 }
922 /* Tx ring. */
923 if (cd->sge_tx_tag != NULL) {
924 if (ld->sge_tx_paddr != 0)
925 bus_dmamap_unload(cd->sge_tx_tag, cd->sge_tx_dmamap);
926 if (ld->sge_tx_ring != NULL)
927 bus_dmamem_free(cd->sge_tx_tag, ld->sge_tx_ring,
928 cd->sge_tx_dmamap);
929 ld->sge_tx_ring = NULL;
930 ld->sge_tx_paddr = 0;
931 bus_dma_tag_destroy(cd->sge_tx_tag);
932 cd->sge_tx_tag = NULL;
933 }
934 /* Rx buffers. */
935 if (cd->sge_rxmbuf_tag != NULL) {
936 for (i = 0; i < SGE_RX_RING_CNT; i++) {
937 rxd = &cd->sge_rxdesc[i];
938 if (rxd->rx_dmamap != NULL) {
939 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
940 rxd->rx_dmamap);
941 rxd->rx_dmamap = NULL;
942 }
943 }
944 if (cd->sge_rx_spare_map != NULL) {
945 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
946 cd->sge_rx_spare_map);
947 cd->sge_rx_spare_map = NULL;
948 }
949 bus_dma_tag_destroy(cd->sge_rxmbuf_tag);
950 cd->sge_rxmbuf_tag = NULL;
951 }
952 /* Tx buffers. */
953 if (cd->sge_txmbuf_tag != NULL) {
954 for (i = 0; i < SGE_TX_RING_CNT; i++) {
955 txd = &cd->sge_txdesc[i];
956 if (txd->tx_dmamap != NULL) {
957 bus_dmamap_destroy(cd->sge_txmbuf_tag,
958 txd->tx_dmamap);
959 txd->tx_dmamap = NULL;
960 }
961 }
962 bus_dma_tag_destroy(cd->sge_txmbuf_tag);
963 cd->sge_txmbuf_tag = NULL;
964 }
965 if (cd->sge_tag != NULL)
966 bus_dma_tag_destroy(cd->sge_tag);
967 cd->sge_tag = NULL;
968 }
969
970 /*
971 * Initialize the TX descriptors.
972 */
973 static int
sge_list_tx_init(struct sge_softc * sc)974 sge_list_tx_init(struct sge_softc *sc)
975 {
976 struct sge_list_data *ld;
977 struct sge_chain_data *cd;
978
979 SGE_LOCK_ASSERT(sc);
980 ld = &sc->sge_ldata;
981 cd = &sc->sge_cdata;
982 bzero(ld->sge_tx_ring, SGE_TX_RING_SZ);
983 ld->sge_tx_ring[SGE_TX_RING_CNT - 1].sge_flags = htole32(RING_END);
984 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
986 cd->sge_tx_prod = 0;
987 cd->sge_tx_cons = 0;
988 cd->sge_tx_cnt = 0;
989 return (0);
990 }
991
992 static int
sge_list_tx_free(struct sge_softc * sc)993 sge_list_tx_free(struct sge_softc *sc)
994 {
995 struct sge_chain_data *cd;
996 struct sge_txdesc *txd;
997 int i;
998
999 SGE_LOCK_ASSERT(sc);
1000 cd = &sc->sge_cdata;
1001 for (i = 0; i < SGE_TX_RING_CNT; i++) {
1002 txd = &cd->sge_txdesc[i];
1003 if (txd->tx_m != NULL) {
1004 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1005 BUS_DMASYNC_POSTWRITE);
1006 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1007 m_freem(txd->tx_m);
1008 txd->tx_m = NULL;
1009 txd->tx_ndesc = 0;
1010 }
1011 }
1012
1013 return (0);
1014 }
1015
1016 /*
1017 * Initialize the RX descriptors and allocate mbufs for them. Note that
1018 * we arrange the descriptors in a closed ring, so that the last descriptor
1019 * has RING_END flag set.
1020 */
1021 static int
sge_list_rx_init(struct sge_softc * sc)1022 sge_list_rx_init(struct sge_softc *sc)
1023 {
1024 struct sge_chain_data *cd;
1025 int i;
1026
1027 SGE_LOCK_ASSERT(sc);
1028 cd = &sc->sge_cdata;
1029 cd->sge_rx_cons = 0;
1030 bzero(sc->sge_ldata.sge_rx_ring, SGE_RX_RING_SZ);
1031 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1032 if (sge_newbuf(sc, i) != 0)
1033 return (ENOBUFS);
1034 }
1035 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1036 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1037 return (0);
1038 }
1039
1040 static int
sge_list_rx_free(struct sge_softc * sc)1041 sge_list_rx_free(struct sge_softc *sc)
1042 {
1043 struct sge_chain_data *cd;
1044 struct sge_rxdesc *rxd;
1045 int i;
1046
1047 SGE_LOCK_ASSERT(sc);
1048 cd = &sc->sge_cdata;
1049 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1050 rxd = &cd->sge_rxdesc[i];
1051 if (rxd->rx_m != NULL) {
1052 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1053 BUS_DMASYNC_POSTREAD);
1054 bus_dmamap_unload(cd->sge_rxmbuf_tag,
1055 rxd->rx_dmamap);
1056 m_freem(rxd->rx_m);
1057 rxd->rx_m = NULL;
1058 }
1059 }
1060 return (0);
1061 }
1062
1063 /*
1064 * Initialize an RX descriptor and attach an MBUF cluster.
1065 */
1066 static int
sge_newbuf(struct sge_softc * sc,int prod)1067 sge_newbuf(struct sge_softc *sc, int prod)
1068 {
1069 struct mbuf *m;
1070 struct sge_desc *desc;
1071 struct sge_chain_data *cd;
1072 struct sge_rxdesc *rxd;
1073 bus_dma_segment_t segs[1];
1074 bus_dmamap_t map;
1075 int error, nsegs;
1076
1077 SGE_LOCK_ASSERT(sc);
1078
1079 cd = &sc->sge_cdata;
1080 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1081 if (m == NULL)
1082 return (ENOBUFS);
1083 m->m_len = m->m_pkthdr.len = MCLBYTES;
1084 m_adj(m, SGE_RX_BUF_ALIGN);
1085 error = bus_dmamap_load_mbuf_sg(cd->sge_rxmbuf_tag,
1086 cd->sge_rx_spare_map, m, segs, &nsegs, 0);
1087 if (error != 0) {
1088 m_freem(m);
1089 return (error);
1090 }
1091 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1092 rxd = &cd->sge_rxdesc[prod];
1093 if (rxd->rx_m != NULL) {
1094 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1095 BUS_DMASYNC_POSTREAD);
1096 bus_dmamap_unload(cd->sge_rxmbuf_tag, rxd->rx_dmamap);
1097 }
1098 map = rxd->rx_dmamap;
1099 rxd->rx_dmamap = cd->sge_rx_spare_map;
1100 cd->sge_rx_spare_map = map;
1101 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1102 BUS_DMASYNC_PREREAD);
1103 rxd->rx_m = m;
1104
1105 desc = &sc->sge_ldata.sge_rx_ring[prod];
1106 desc->sge_sts_size = 0;
1107 desc->sge_ptr = htole32(SGE_ADDR_LO(segs[0].ds_addr));
1108 desc->sge_flags = htole32(segs[0].ds_len);
1109 if (prod == SGE_RX_RING_CNT - 1)
1110 desc->sge_flags |= htole32(RING_END);
1111 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR);
1112 return (0);
1113 }
1114
1115 static __inline void
sge_discard_rxbuf(struct sge_softc * sc,int index)1116 sge_discard_rxbuf(struct sge_softc *sc, int index)
1117 {
1118 struct sge_desc *desc;
1119
1120 desc = &sc->sge_ldata.sge_rx_ring[index];
1121 desc->sge_sts_size = 0;
1122 desc->sge_flags = htole32(MCLBYTES - SGE_RX_BUF_ALIGN);
1123 if (index == SGE_RX_RING_CNT - 1)
1124 desc->sge_flags |= htole32(RING_END);
1125 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR);
1126 }
1127
1128 /*
1129 * A frame has been uploaded: pass the resulting mbuf chain up to
1130 * the higher level protocols.
1131 */
1132 static void
sge_rxeof(struct sge_softc * sc)1133 sge_rxeof(struct sge_softc *sc)
1134 {
1135 if_t ifp;
1136 struct mbuf *m;
1137 struct sge_chain_data *cd;
1138 struct sge_desc *cur_rx;
1139 uint32_t rxinfo, rxstat;
1140 int cons, prog;
1141
1142 SGE_LOCK_ASSERT(sc);
1143
1144 ifp = sc->sge_ifp;
1145 cd = &sc->sge_cdata;
1146
1147 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1148 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1149 cons = cd->sge_rx_cons;
1150 for (prog = 0; prog < SGE_RX_RING_CNT; prog++,
1151 SGE_INC(cons, SGE_RX_RING_CNT)) {
1152 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1153 break;
1154 cur_rx = &sc->sge_ldata.sge_rx_ring[cons];
1155 rxinfo = le32toh(cur_rx->sge_cmdsts);
1156 if ((rxinfo & RDC_OWN) != 0)
1157 break;
1158 rxstat = le32toh(cur_rx->sge_sts_size);
1159 if ((rxstat & RDS_CRCOK) == 0 || SGE_RX_ERROR(rxstat) != 0 ||
1160 SGE_RX_NSEGS(rxstat) != 1) {
1161 /* XXX We don't support multi-segment frames yet. */
1162 #ifdef SGE_SHOW_ERRORS
1163 device_printf(sc->sge_dev, "Rx error : 0x%b\n", rxstat,
1164 RX_ERR_BITS);
1165 #endif
1166 sge_discard_rxbuf(sc, cons);
1167 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1168 continue;
1169 }
1170 m = cd->sge_rxdesc[cons].rx_m;
1171 if (sge_newbuf(sc, cons) != 0) {
1172 sge_discard_rxbuf(sc, cons);
1173 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1174 continue;
1175 }
1176 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1177 if ((rxinfo & RDC_IP_CSUM) != 0 &&
1178 (rxinfo & RDC_IP_CSUM_OK) != 0)
1179 m->m_pkthdr.csum_flags |=
1180 CSUM_IP_CHECKED | CSUM_IP_VALID;
1181 if (((rxinfo & RDC_TCP_CSUM) != 0 &&
1182 (rxinfo & RDC_TCP_CSUM_OK) != 0) ||
1183 ((rxinfo & RDC_UDP_CSUM) != 0 &&
1184 (rxinfo & RDC_UDP_CSUM_OK) != 0)) {
1185 m->m_pkthdr.csum_flags |=
1186 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1187 m->m_pkthdr.csum_data = 0xffff;
1188 }
1189 }
1190 /* Check for VLAN tagged frame. */
1191 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1192 (rxstat & RDS_VLAN) != 0) {
1193 m->m_pkthdr.ether_vtag = rxinfo & RDC_VLAN_MASK;
1194 m->m_flags |= M_VLANTAG;
1195 }
1196 /*
1197 * Account for 10bytes auto padding which is used
1198 * to align IP header on 32bit boundary. Also note,
1199 * CRC bytes is automatically removed by the
1200 * hardware.
1201 */
1202 m->m_data += SGE_RX_PAD_BYTES;
1203 m->m_pkthdr.len = m->m_len = SGE_RX_BYTES(rxstat) -
1204 SGE_RX_PAD_BYTES;
1205 m->m_pkthdr.rcvif = ifp;
1206 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1207 SGE_UNLOCK(sc);
1208 if_input(ifp, m);
1209 SGE_LOCK(sc);
1210 }
1211
1212 if (prog > 0) {
1213 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1214 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1215 cd->sge_rx_cons = cons;
1216 }
1217 }
1218
1219 /*
1220 * A frame was downloaded to the chip. It's safe for us to clean up
1221 * the list buffers.
1222 */
1223 static void
sge_txeof(struct sge_softc * sc)1224 sge_txeof(struct sge_softc *sc)
1225 {
1226 if_t ifp;
1227 struct sge_list_data *ld;
1228 struct sge_chain_data *cd;
1229 struct sge_txdesc *txd;
1230 uint32_t txstat;
1231 int cons, nsegs, prod;
1232
1233 SGE_LOCK_ASSERT(sc);
1234
1235 ifp = sc->sge_ifp;
1236 ld = &sc->sge_ldata;
1237 cd = &sc->sge_cdata;
1238
1239 if (cd->sge_tx_cnt == 0)
1240 return;
1241 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
1242 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1243 cons = cd->sge_tx_cons;
1244 prod = cd->sge_tx_prod;
1245 for (; cons != prod;) {
1246 txstat = le32toh(ld->sge_tx_ring[cons].sge_cmdsts);
1247 if ((txstat & TDC_OWN) != 0)
1248 break;
1249 /*
1250 * Only the first descriptor of multi-descriptor transmission
1251 * is updated by controller. Driver should skip entire
1252 * chained buffers for the transmitted frame. In other words
1253 * TDC_OWN bit is valid only at the first descriptor of a
1254 * multi-descriptor transmission.
1255 */
1256 if (SGE_TX_ERROR(txstat) != 0) {
1257 #ifdef SGE_SHOW_ERRORS
1258 device_printf(sc->sge_dev, "Tx error : 0x%b\n",
1259 txstat, TX_ERR_BITS);
1260 #endif
1261 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1262 } else {
1263 #ifdef notyet
1264 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & 0xFFFF) - 1);
1265 #endif
1266 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1267 }
1268 txd = &cd->sge_txdesc[cons];
1269 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1270 ld->sge_tx_ring[cons].sge_cmdsts = 0;
1271 SGE_INC(cons, SGE_TX_RING_CNT);
1272 }
1273 /* Reclaim transmitted mbuf. */
1274 KASSERT(txd->tx_m != NULL,
1275 ("%s: freeing NULL mbuf\n", __func__));
1276 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1277 BUS_DMASYNC_POSTWRITE);
1278 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1279 m_freem(txd->tx_m);
1280 txd->tx_m = NULL;
1281 cd->sge_tx_cnt -= txd->tx_ndesc;
1282 KASSERT(cd->sge_tx_cnt >= 0,
1283 ("%s: Active Tx desc counter was garbled\n", __func__));
1284 txd->tx_ndesc = 0;
1285 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1286 }
1287 cd->sge_tx_cons = cons;
1288 if (cd->sge_tx_cnt == 0)
1289 sc->sge_timer = 0;
1290 }
1291
1292 static void
sge_tick(void * arg)1293 sge_tick(void *arg)
1294 {
1295 struct sge_softc *sc;
1296 struct mii_data *mii;
1297 if_t ifp;
1298
1299 sc = arg;
1300 SGE_LOCK_ASSERT(sc);
1301
1302 ifp = sc->sge_ifp;
1303 mii = device_get_softc(sc->sge_miibus);
1304 mii_tick(mii);
1305 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1306 sge_miibus_statchg(sc->sge_dev);
1307 if ((sc->sge_flags & SGE_FLAG_LINK) != 0 &&
1308 !if_sendq_empty(ifp))
1309 sge_start_locked(ifp);
1310 }
1311 /*
1312 * Reclaim transmitted frames here as we do not request
1313 * Tx completion interrupt for every queued frames to
1314 * reduce excessive interrupts.
1315 */
1316 sge_txeof(sc);
1317 sge_watchdog(sc);
1318 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1319 }
1320
1321 static void
sge_intr(void * arg)1322 sge_intr(void *arg)
1323 {
1324 struct sge_softc *sc;
1325 if_t ifp;
1326 uint32_t status;
1327
1328 sc = arg;
1329 SGE_LOCK(sc);
1330 ifp = sc->sge_ifp;
1331
1332 status = CSR_READ_4(sc, IntrStatus);
1333 if (status == 0xFFFFFFFF || (status & SGE_INTRS) == 0) {
1334 /* Not ours. */
1335 SGE_UNLOCK(sc);
1336 return;
1337 }
1338 /* Acknowledge interrupts. */
1339 CSR_WRITE_4(sc, IntrStatus, status);
1340 /* Disable further interrupts. */
1341 CSR_WRITE_4(sc, IntrMask, 0);
1342 /*
1343 * It seems the controller supports some kind of interrupt
1344 * moderation mechanism but we still don't know how to
1345 * enable that. To reduce number of generated interrupts
1346 * under load we check pending interrupts in a loop. This
1347 * will increase number of register access and is not correct
1348 * way to handle interrupt moderation but there seems to be
1349 * no other way at this time.
1350 */
1351 for (;;) {
1352 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1353 break;
1354 if ((status & (INTR_RX_DONE | INTR_RX_IDLE)) != 0) {
1355 sge_rxeof(sc);
1356 /* Wakeup Rx MAC. */
1357 if ((status & INTR_RX_IDLE) != 0)
1358 CSR_WRITE_4(sc, RX_CTL,
1359 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1360 }
1361 if ((status & (INTR_TX_DONE | INTR_TX_IDLE)) != 0)
1362 sge_txeof(sc);
1363 status = CSR_READ_4(sc, IntrStatus);
1364 if ((status & SGE_INTRS) == 0)
1365 break;
1366 /* Acknowledge interrupts. */
1367 CSR_WRITE_4(sc, IntrStatus, status);
1368 }
1369 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1370 /* Re-enable interrupts */
1371 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1372 if (!if_sendq_empty(ifp))
1373 sge_start_locked(ifp);
1374 }
1375 SGE_UNLOCK(sc);
1376 }
1377
1378 /*
1379 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1380 * pointers to the fragment pointers.
1381 */
1382 static int
sge_encap(struct sge_softc * sc,struct mbuf ** m_head)1383 sge_encap(struct sge_softc *sc, struct mbuf **m_head)
1384 {
1385 struct mbuf *m;
1386 struct sge_desc *desc;
1387 struct sge_txdesc *txd;
1388 bus_dma_segment_t txsegs[SGE_MAXTXSEGS];
1389 uint32_t cflags, mss;
1390 int error, i, nsegs, prod, si;
1391
1392 SGE_LOCK_ASSERT(sc);
1393
1394 si = prod = sc->sge_cdata.sge_tx_prod;
1395 txd = &sc->sge_cdata.sge_txdesc[prod];
1396 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1397 struct ether_header *eh;
1398 struct ip *ip;
1399 struct tcphdr *tcp;
1400 uint32_t ip_off, poff;
1401
1402 if (M_WRITABLE(*m_head) == 0) {
1403 /* Get a writable copy. */
1404 m = m_dup(*m_head, M_NOWAIT);
1405 m_freem(*m_head);
1406 if (m == NULL) {
1407 *m_head = NULL;
1408 return (ENOBUFS);
1409 }
1410 *m_head = m;
1411 }
1412 ip_off = sizeof(struct ether_header);
1413 m = m_pullup(*m_head, ip_off);
1414 if (m == NULL) {
1415 *m_head = NULL;
1416 return (ENOBUFS);
1417 }
1418 eh = mtod(m, struct ether_header *);
1419 /* Check the existence of VLAN tag. */
1420 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1421 ip_off = sizeof(struct ether_vlan_header);
1422 m = m_pullup(m, ip_off);
1423 if (m == NULL) {
1424 *m_head = NULL;
1425 return (ENOBUFS);
1426 }
1427 }
1428 m = m_pullup(m, ip_off + sizeof(struct ip));
1429 if (m == NULL) {
1430 *m_head = NULL;
1431 return (ENOBUFS);
1432 }
1433 ip = (struct ip *)(mtod(m, char *) + ip_off);
1434 poff = ip_off + (ip->ip_hl << 2);
1435 m = m_pullup(m, poff + sizeof(struct tcphdr));
1436 if (m == NULL) {
1437 *m_head = NULL;
1438 return (ENOBUFS);
1439 }
1440 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1441 m = m_pullup(m, poff + (tcp->th_off << 2));
1442 if (m == NULL) {
1443 *m_head = NULL;
1444 return (ENOBUFS);
1445 }
1446 /*
1447 * Reset IP checksum and recompute TCP pseudo
1448 * checksum that NDIS specification requires.
1449 */
1450 ip = (struct ip *)(mtod(m, char *) + ip_off);
1451 ip->ip_sum = 0;
1452 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1453 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1454 htons(IPPROTO_TCP));
1455 *m_head = m;
1456 }
1457
1458 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1459 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1460 if (error == EFBIG) {
1461 m = m_collapse(*m_head, M_NOWAIT, SGE_MAXTXSEGS);
1462 if (m == NULL) {
1463 m_freem(*m_head);
1464 *m_head = NULL;
1465 return (ENOBUFS);
1466 }
1467 *m_head = m;
1468 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1469 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1470 if (error != 0) {
1471 m_freem(*m_head);
1472 *m_head = NULL;
1473 return (error);
1474 }
1475 } else if (error != 0)
1476 return (error);
1477
1478 KASSERT(nsegs != 0, ("zero segment returned"));
1479 /* Check descriptor overrun. */
1480 if (sc->sge_cdata.sge_tx_cnt + nsegs >= SGE_TX_RING_CNT) {
1481 bus_dmamap_unload(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap);
1482 return (ENOBUFS);
1483 }
1484 bus_dmamap_sync(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap,
1485 BUS_DMASYNC_PREWRITE);
1486
1487 m = *m_head;
1488 cflags = 0;
1489 mss = 0;
1490 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1491 cflags |= TDC_LS;
1492 mss = (uint32_t)m->m_pkthdr.tso_segsz;
1493 mss <<= 16;
1494 } else {
1495 if (m->m_pkthdr.csum_flags & CSUM_IP)
1496 cflags |= TDC_IP_CSUM;
1497 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1498 cflags |= TDC_TCP_CSUM;
1499 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1500 cflags |= TDC_UDP_CSUM;
1501 }
1502 for (i = 0; i < nsegs; i++) {
1503 desc = &sc->sge_ldata.sge_tx_ring[prod];
1504 if (i == 0) {
1505 desc->sge_sts_size = htole32(m->m_pkthdr.len | mss);
1506 desc->sge_cmdsts = 0;
1507 } else {
1508 desc->sge_sts_size = 0;
1509 desc->sge_cmdsts = htole32(TDC_OWN);
1510 }
1511 desc->sge_ptr = htole32(SGE_ADDR_LO(txsegs[i].ds_addr));
1512 desc->sge_flags = htole32(txsegs[i].ds_len);
1513 if (prod == SGE_TX_RING_CNT - 1)
1514 desc->sge_flags |= htole32(RING_END);
1515 sc->sge_cdata.sge_tx_cnt++;
1516 SGE_INC(prod, SGE_TX_RING_CNT);
1517 }
1518 /* Update producer index. */
1519 sc->sge_cdata.sge_tx_prod = prod;
1520
1521 desc = &sc->sge_ldata.sge_tx_ring[si];
1522 /* Configure VLAN. */
1523 if((m->m_flags & M_VLANTAG) != 0) {
1524 cflags |= m->m_pkthdr.ether_vtag;
1525 desc->sge_sts_size |= htole32(TDS_INS_VLAN);
1526 }
1527 desc->sge_cmdsts |= htole32(TDC_DEF | TDC_CRC | TDC_PAD | cflags);
1528 #if 1
1529 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1530 desc->sge_cmdsts |= htole32(TDC_BST);
1531 #else
1532 if ((sc->sge_flags & SGE_FLAG_FDX) == 0) {
1533 desc->sge_cmdsts |= htole32(TDC_COL | TDC_CRS | TDC_BKF);
1534 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1535 desc->sge_cmdsts |= htole32(TDC_EXT | TDC_BST);
1536 }
1537 #endif
1538 /* Request interrupt and give ownership to controller. */
1539 desc->sge_cmdsts |= htole32(TDC_OWN | TDC_INTR);
1540 txd->tx_m = m;
1541 txd->tx_ndesc = nsegs;
1542 return (0);
1543 }
1544
1545 static void
sge_start(if_t ifp)1546 sge_start(if_t ifp)
1547 {
1548 struct sge_softc *sc;
1549
1550 sc = if_getsoftc(ifp);
1551 SGE_LOCK(sc);
1552 sge_start_locked(ifp);
1553 SGE_UNLOCK(sc);
1554 }
1555
1556 static void
sge_start_locked(if_t ifp)1557 sge_start_locked(if_t ifp)
1558 {
1559 struct sge_softc *sc;
1560 struct mbuf *m_head;
1561 int queued = 0;
1562
1563 sc = if_getsoftc(ifp);
1564 SGE_LOCK_ASSERT(sc);
1565
1566 if ((sc->sge_flags & SGE_FLAG_LINK) == 0 ||
1567 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1568 IFF_DRV_RUNNING)
1569 return;
1570
1571 for (queued = 0; !if_sendq_empty(ifp); ) {
1572 if (sc->sge_cdata.sge_tx_cnt > (SGE_TX_RING_CNT -
1573 SGE_MAXTXSEGS)) {
1574 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1575 break;
1576 }
1577 m_head = if_dequeue(ifp);
1578 if (m_head == NULL)
1579 break;
1580 if (sge_encap(sc, &m_head)) {
1581 if (m_head == NULL)
1582 break;
1583 if_sendq_prepend(ifp, m_head);
1584 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1585 break;
1586 }
1587 queued++;
1588 /*
1589 * If there's a BPF listener, bounce a copy of this frame
1590 * to him.
1591 */
1592 BPF_MTAP(ifp, m_head);
1593 }
1594
1595 if (queued > 0) {
1596 bus_dmamap_sync(sc->sge_cdata.sge_tx_tag,
1597 sc->sge_cdata.sge_tx_dmamap,
1598 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1599 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL);
1600 sc->sge_timer = 5;
1601 }
1602 }
1603
1604 static void
sge_init(void * arg)1605 sge_init(void *arg)
1606 {
1607 struct sge_softc *sc;
1608
1609 sc = arg;
1610 SGE_LOCK(sc);
1611 sge_init_locked(sc);
1612 SGE_UNLOCK(sc);
1613 }
1614
1615 static void
sge_init_locked(struct sge_softc * sc)1616 sge_init_locked(struct sge_softc *sc)
1617 {
1618 if_t ifp;
1619 struct mii_data *mii;
1620 uint16_t rxfilt;
1621 int i;
1622
1623 SGE_LOCK_ASSERT(sc);
1624 ifp = sc->sge_ifp;
1625 mii = device_get_softc(sc->sge_miibus);
1626 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1627 return;
1628 /*
1629 * Cancel pending I/O and free all RX/TX buffers.
1630 */
1631 sge_stop(sc);
1632 sge_reset(sc);
1633
1634 /* Init circular RX list. */
1635 if (sge_list_rx_init(sc) == ENOBUFS) {
1636 device_printf(sc->sge_dev, "no memory for Rx buffers\n");
1637 sge_stop(sc);
1638 return;
1639 }
1640 /* Init TX descriptors. */
1641 sge_list_tx_init(sc);
1642 /*
1643 * Load the address of the RX and TX lists.
1644 */
1645 CSR_WRITE_4(sc, TX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_tx_paddr));
1646 CSR_WRITE_4(sc, RX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_rx_paddr));
1647
1648 CSR_WRITE_4(sc, TxMacControl, 0x60);
1649 CSR_WRITE_4(sc, RxWakeOnLan, 0);
1650 CSR_WRITE_4(sc, RxWakeOnLanData, 0);
1651 /* Allow receiving VLAN frames. */
1652 CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +
1653 SGE_RX_PAD_BYTES);
1654
1655 for (i = 0; i < ETHER_ADDR_LEN; i++)
1656 CSR_WRITE_1(sc, RxMacAddr + i, if_getlladdr(ifp)[i]);
1657 /* Configure RX MAC. */
1658 rxfilt = RXMAC_STRIP_FCS | RXMAC_PAD_ENB | RXMAC_CSUM_ENB;
1659 CSR_WRITE_2(sc, RxMacControl, rxfilt);
1660 sge_rxfilter(sc);
1661 sge_setvlan(sc);
1662
1663 /* Initialize default speed/duplex information. */
1664 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0)
1665 sc->sge_flags |= SGE_FLAG_SPEED_1000;
1666 sc->sge_flags |= SGE_FLAG_FDX;
1667 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0)
1668 CSR_WRITE_4(sc, StationControl, 0x04008001);
1669 else
1670 CSR_WRITE_4(sc, StationControl, 0x04000001);
1671 /*
1672 * XXX Try to mitigate interrupts.
1673 */
1674 CSR_WRITE_4(sc, IntrControl, 0x08880000);
1675 #ifdef notyet
1676 if (sc->sge_intrcontrol != 0)
1677 CSR_WRITE_4(sc, IntrControl, sc->sge_intrcontrol);
1678 if (sc->sge_intrtimer != 0)
1679 CSR_WRITE_4(sc, IntrTimer, sc->sge_intrtimer);
1680 #endif
1681
1682 /*
1683 * Clear and enable interrupts.
1684 */
1685 CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF);
1686 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1687
1688 /* Enable receiver and transmitter. */
1689 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB);
1690 CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1691
1692 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1693 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1694
1695 sc->sge_flags &= ~SGE_FLAG_LINK;
1696 mii_mediachg(mii);
1697 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1698 }
1699
1700 /*
1701 * Set media options.
1702 */
1703 static int
sge_ifmedia_upd(if_t ifp)1704 sge_ifmedia_upd(if_t ifp)
1705 {
1706 struct sge_softc *sc;
1707 struct mii_data *mii;
1708 struct mii_softc *miisc;
1709 int error;
1710
1711 sc = if_getsoftc(ifp);
1712 SGE_LOCK(sc);
1713 mii = device_get_softc(sc->sge_miibus);
1714 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1715 PHY_RESET(miisc);
1716 error = mii_mediachg(mii);
1717 SGE_UNLOCK(sc);
1718
1719 return (error);
1720 }
1721
1722 /*
1723 * Report current media status.
1724 */
1725 static void
sge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1726 sge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1727 {
1728 struct sge_softc *sc;
1729 struct mii_data *mii;
1730
1731 sc = if_getsoftc(ifp);
1732 SGE_LOCK(sc);
1733 mii = device_get_softc(sc->sge_miibus);
1734 if ((if_getflags(ifp) & IFF_UP) == 0) {
1735 SGE_UNLOCK(sc);
1736 return;
1737 }
1738 mii_pollstat(mii);
1739 ifmr->ifm_active = mii->mii_media_active;
1740 ifmr->ifm_status = mii->mii_media_status;
1741 SGE_UNLOCK(sc);
1742 }
1743
1744 static int
sge_ioctl(if_t ifp,u_long command,caddr_t data)1745 sge_ioctl(if_t ifp, u_long command, caddr_t data)
1746 {
1747 struct sge_softc *sc;
1748 struct ifreq *ifr;
1749 struct mii_data *mii;
1750 int error = 0, mask, reinit;
1751
1752 sc = if_getsoftc(ifp);
1753 ifr = (struct ifreq *)data;
1754
1755 switch(command) {
1756 case SIOCSIFFLAGS:
1757 SGE_LOCK(sc);
1758 if ((if_getflags(ifp) & IFF_UP) != 0) {
1759 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
1760 ((if_getflags(ifp) ^ sc->sge_if_flags) &
1761 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1762 sge_rxfilter(sc);
1763 else
1764 sge_init_locked(sc);
1765 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1766 sge_stop(sc);
1767 sc->sge_if_flags = if_getflags(ifp);
1768 SGE_UNLOCK(sc);
1769 break;
1770 case SIOCSIFCAP:
1771 SGE_LOCK(sc);
1772 reinit = 0;
1773 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1774 if ((mask & IFCAP_TXCSUM) != 0 &&
1775 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1776 if_togglecapenable(ifp, IFCAP_TXCSUM);
1777 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1778 if_sethwassistbits(ifp, SGE_CSUM_FEATURES, 0);
1779 else
1780 if_sethwassistbits(ifp, 0, SGE_CSUM_FEATURES);
1781 }
1782 if ((mask & IFCAP_RXCSUM) != 0 &&
1783 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
1784 if_togglecapenable(ifp, IFCAP_RXCSUM);
1785 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1786 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
1787 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1788 if ((mask & IFCAP_TSO4) != 0 &&
1789 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
1790 if_togglecapenable(ifp, IFCAP_TSO4);
1791 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
1792 if_sethwassistbits(ifp, CSUM_TSO, 0);
1793 else
1794 if_sethwassistbits(ifp, 0, CSUM_TSO);
1795 }
1796 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1797 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
1798 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1799 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1800 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1801 /*
1802 * Due to unknown reason, toggling VLAN hardware
1803 * tagging require interface reinitialization.
1804 */
1805 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1806 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
1807 if_setcapenablebit(ifp, 0,
1808 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1809 reinit = 1;
1810 }
1811 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1812 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1813 sge_init_locked(sc);
1814 }
1815 SGE_UNLOCK(sc);
1816 VLAN_CAPABILITIES(ifp);
1817 break;
1818 case SIOCADDMULTI:
1819 case SIOCDELMULTI:
1820 SGE_LOCK(sc);
1821 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1822 sge_rxfilter(sc);
1823 SGE_UNLOCK(sc);
1824 break;
1825 case SIOCGIFMEDIA:
1826 case SIOCSIFMEDIA:
1827 mii = device_get_softc(sc->sge_miibus);
1828 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1829 break;
1830 default:
1831 error = ether_ioctl(ifp, command, data);
1832 break;
1833 }
1834
1835 return (error);
1836 }
1837
1838 static void
sge_watchdog(struct sge_softc * sc)1839 sge_watchdog(struct sge_softc *sc)
1840 {
1841 if_t ifp;
1842
1843 SGE_LOCK_ASSERT(sc);
1844 if (sc->sge_timer == 0 || --sc->sge_timer > 0)
1845 return;
1846
1847 ifp = sc->sge_ifp;
1848 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1849 if (1 || bootverbose)
1850 device_printf(sc->sge_dev,
1851 "watchdog timeout (lost link)\n");
1852 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1853 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1854 sge_init_locked(sc);
1855 return;
1856 }
1857 device_printf(sc->sge_dev, "watchdog timeout\n");
1858 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1859
1860 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1861 sge_init_locked(sc);
1862 if (!if_sendq_empty(sc->sge_ifp))
1863 sge_start_locked(ifp);
1864 }
1865
1866 /*
1867 * Stop the adapter and free any mbufs allocated to the
1868 * RX and TX lists.
1869 */
1870 static void
sge_stop(struct sge_softc * sc)1871 sge_stop(struct sge_softc *sc)
1872 {
1873 if_t ifp;
1874
1875 ifp = sc->sge_ifp;
1876
1877 SGE_LOCK_ASSERT(sc);
1878
1879 sc->sge_timer = 0;
1880 callout_stop(&sc->sge_stat_ch);
1881 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1882
1883 CSR_WRITE_4(sc, IntrMask, 0);
1884 CSR_READ_4(sc, IntrMask);
1885 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1886 /* Stop TX/RX MAC. */
1887 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
1888 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
1889 /* XXX Can we assume active DMA cycles gone? */
1890 DELAY(2000);
1891 CSR_WRITE_4(sc, IntrMask, 0);
1892 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1893
1894 sc->sge_flags &= ~SGE_FLAG_LINK;
1895 sge_list_rx_free(sc);
1896 sge_list_tx_free(sc);
1897 }
1898