1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <linux/dmi.h>
27 #include <linux/slab.h>
28
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_crtc.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_mipi_dsi.h>
33
34 #include "i915_drv.h"
35 #include "i915_reg.h"
36 #include "intel_atomic.h"
37 #include "intel_backlight.h"
38 #include "intel_connector.h"
39 #include "intel_crtc.h"
40 #include "intel_de.h"
41 #include "intel_display_types.h"
42 #include "intel_dsi.h"
43 #include "intel_dsi_vbt.h"
44 #include "intel_fifo_underrun.h"
45 #include "intel_panel.h"
46 #include "skl_scaler.h"
47 #include "vlv_dsi.h"
48 #include "vlv_dsi_pll.h"
49 #include "vlv_dsi_regs.h"
50 #include "vlv_sideband.h"
51
52 /* return pixels in terms of txbyteclkhs */
txbyteclkhs(u16 pixels,int bpp,int lane_count,u16 burst_mode_ratio)53 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
54 u16 burst_mode_ratio)
55 {
56 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
57 8 * 100), lane_count);
58 }
59
60 /* return pixels equvalent to txbyteclkhs */
pixels_from_txbyteclkhs(u16 clk_hs,int bpp,int lane_count,u16 burst_mode_ratio)61 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
62 u16 burst_mode_ratio)
63 {
64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
65 (bpp * burst_mode_ratio));
66 }
67
pixel_format_from_register_bits(u32 fmt)68 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
69 {
70 /* It just so happens the VBT matches register contents. */
71 switch (fmt) {
72 case VID_MODE_FORMAT_RGB888:
73 return MIPI_DSI_FMT_RGB888;
74 case VID_MODE_FORMAT_RGB666:
75 return MIPI_DSI_FMT_RGB666;
76 case VID_MODE_FORMAT_RGB666_PACKED:
77 return MIPI_DSI_FMT_RGB666_PACKED;
78 case VID_MODE_FORMAT_RGB565:
79 return MIPI_DSI_FMT_RGB565;
80 default:
81 MISSING_CASE(fmt);
82 return MIPI_DSI_FMT_RGB666;
83 }
84 }
85
vlv_dsi_wait_for_fifo_empty(struct intel_dsi * intel_dsi,enum port port)86 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
87 {
88 struct intel_display *display = to_intel_display(&intel_dsi->base);
89 u32 mask;
90
91 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
92 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
93
94 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
95 mask, 100))
96 drm_err(display->drm, "DPI FIFOs are not empty\n");
97 }
98
write_data(struct intel_display * display,i915_reg_t reg,const u8 * data,u32 len)99 static void write_data(struct intel_display *display,
100 i915_reg_t reg,
101 const u8 *data, u32 len)
102 {
103 u32 i, j;
104
105 for (i = 0; i < len; i += 4) {
106 u32 val = 0;
107
108 for (j = 0; j < min_t(u32, len - i, 4); j++)
109 val |= *data++ << 8 * j;
110
111 intel_de_write(display, reg, val);
112 }
113 }
114
read_data(struct intel_display * display,i915_reg_t reg,u8 * data,u32 len)115 static void read_data(struct intel_display *display,
116 i915_reg_t reg,
117 u8 *data, u32 len)
118 {
119 u32 i, j;
120
121 for (i = 0; i < len; i += 4) {
122 u32 val = intel_de_read(display, reg);
123
124 for (j = 0; j < min_t(u32, len - i, 4); j++)
125 *data++ = val >> 8 * j;
126 }
127 }
128
intel_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)129 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
130 const struct mipi_dsi_msg *msg)
131 {
132 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
133 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi;
134 struct intel_display *display = to_intel_display(&intel_dsi->base);
135 enum port port = intel_dsi_host->port;
136 struct mipi_dsi_packet packet;
137 ssize_t ret;
138 const u8 *header;
139 i915_reg_t data_reg, ctrl_reg;
140 u32 data_mask, ctrl_mask;
141
142 ret = mipi_dsi_create_packet(&packet, msg);
143 if (ret < 0)
144 return ret;
145
146 header = packet.header;
147
148 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
149 data_reg = MIPI_LP_GEN_DATA(display, port);
150 data_mask = LP_DATA_FIFO_FULL;
151 ctrl_reg = MIPI_LP_GEN_CTRL(display, port);
152 ctrl_mask = LP_CTRL_FIFO_FULL;
153 } else {
154 data_reg = MIPI_HS_GEN_DATA(display, port);
155 data_mask = HS_DATA_FIFO_FULL;
156 ctrl_reg = MIPI_HS_GEN_CTRL(display, port);
157 ctrl_mask = HS_CTRL_FIFO_FULL;
158 }
159
160 /* note: this is never true for reads */
161 if (packet.payload_length) {
162 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
163 data_mask, 50))
164 drm_err(display->drm,
165 "Timeout waiting for HS/LP DATA FIFO !full\n");
166
167 write_data(display, data_reg, packet.payload,
168 packet.payload_length);
169 }
170
171 if (msg->rx_len) {
172 intel_de_write(display, MIPI_INTR_STAT(display, port),
173 GEN_READ_DATA_AVAIL);
174 }
175
176 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
177 ctrl_mask, 50)) {
178 drm_err(display->drm,
179 "Timeout waiting for HS/LP CTRL FIFO !full\n");
180 }
181
182 intel_de_write(display, ctrl_reg,
183 header[2] << 16 | header[1] << 8 | header[0]);
184
185 /* ->rx_len is set only for reads */
186 if (msg->rx_len) {
187 data_mask = GEN_READ_DATA_AVAIL;
188 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),
189 data_mask, 50))
190 drm_err(display->drm,
191 "Timeout waiting for read data.\n");
192
193 read_data(display, data_reg, msg->rx_buf, msg->rx_len);
194 }
195
196 /* XXX: fix for reads and writes */
197 return 4 + packet.payload_length;
198 }
199
intel_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)200 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
201 struct mipi_dsi_device *dsi)
202 {
203 return 0;
204 }
205
intel_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)206 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
207 struct mipi_dsi_device *dsi)
208 {
209 return 0;
210 }
211
212 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
213 .attach = intel_dsi_host_attach,
214 .detach = intel_dsi_host_detach,
215 .transfer = intel_dsi_host_transfer,
216 };
217
218 /*
219 * send a video mode command
220 *
221 * XXX: commands with data in MIPI_DPI_DATA?
222 */
dpi_send_cmd(struct intel_dsi * intel_dsi,u32 cmd,bool hs,enum port port)223 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
224 enum port port)
225 {
226 struct intel_display *display = to_intel_display(&intel_dsi->base);
227 u32 mask;
228
229 /* XXX: pipe, hs */
230 if (hs)
231 cmd &= ~DPI_LP_MODE;
232 else
233 cmd |= DPI_LP_MODE;
234
235 /* clear bit */
236 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);
237
238 /* XXX: old code skips write if control unchanged */
239 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))
240 drm_dbg_kms(display->drm,
241 "Same special packet %02x twice in a row.\n", cmd);
242
243 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
244
245 mask = SPL_PKT_SENT_INTERRUPT;
246 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))
247 drm_err(display->drm,
248 "Video mode command 0x%08x send failed.\n", cmd);
249
250 return 0;
251 }
252
band_gap_reset(struct drm_i915_private * dev_priv)253 static void band_gap_reset(struct drm_i915_private *dev_priv)
254 {
255 vlv_flisdsi_get(dev_priv);
256
257 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
258 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
259 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
260 udelay(150);
261 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
262 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
263
264 vlv_flisdsi_put(dev_priv);
265 }
266
intel_dsi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)267 static int intel_dsi_compute_config(struct intel_encoder *encoder,
268 struct intel_crtc_state *pipe_config,
269 struct drm_connector_state *conn_state)
270 {
271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
272 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
273 struct intel_connector *intel_connector = intel_dsi->attached_connector;
274 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
275 int ret;
276
277 drm_dbg_kms(&dev_priv->drm, "\n");
278 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
279 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
280
281 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
282 if (ret)
283 return ret;
284
285 ret = intel_panel_fitting(pipe_config, conn_state);
286 if (ret)
287 return ret;
288
289 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
290 return -EINVAL;
291
292 /* DSI uses short packets for sync events, so clear mode flags for DSI */
293 adjusted_mode->flags = 0;
294
295 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
296 pipe_config->pipe_bpp = 24;
297 else
298 pipe_config->pipe_bpp = 18;
299
300 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
301 /* Enable Frame time stamp based scanline reporting */
302 pipe_config->mode_flags |=
303 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
304
305 /* Dual link goes to DSI transcoder A. */
306 if (intel_dsi->ports == BIT(PORT_C))
307 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
308 else
309 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
310
311 ret = bxt_dsi_pll_compute(encoder, pipe_config);
312 if (ret)
313 return -EINVAL;
314 } else {
315 ret = vlv_dsi_pll_compute(encoder, pipe_config);
316 if (ret)
317 return -EINVAL;
318 }
319
320 pipe_config->clock_set = true;
321
322 return 0;
323 }
324
glk_dsi_enable_io(struct intel_encoder * encoder)325 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
326 {
327 struct intel_display *display = to_intel_display(encoder);
328 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
329 enum port port;
330 bool cold_boot = false;
331
332 /* Set the MIPI mode
333 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
334 * Power ON MIPI IO first and then write into IO reset and LP wake bits
335 */
336 for_each_dsi_port(port, intel_dsi->ports)
337 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);
338
339 /* Put the IO into reset */
340 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
341
342 /* Program LP Wake */
343 for_each_dsi_port(port, intel_dsi->ports) {
344 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));
345
346 intel_de_rmw(display, MIPI_CTRL(display, port),
347 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
348 }
349
350 /* Wait for Pwr ACK */
351 for_each_dsi_port(port, intel_dsi->ports) {
352 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
353 GLK_MIPIIO_PORT_POWERED, 20))
354 drm_err(display->drm, "MIPIO port is powergated\n");
355 }
356
357 /* Check for cold boot scenario */
358 for_each_dsi_port(port, intel_dsi->ports) {
359 cold_boot |=
360 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);
361 }
362
363 return cold_boot;
364 }
365
glk_dsi_device_ready(struct intel_encoder * encoder)366 static void glk_dsi_device_ready(struct intel_encoder *encoder)
367 {
368 struct intel_display *display = to_intel_display(encoder);
369 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
370 enum port port;
371
372 /* Wait for MIPI PHY status bit to set */
373 for_each_dsi_port(port, intel_dsi->ports) {
374 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
375 GLK_PHY_STATUS_PORT_READY, 20))
376 drm_err(display->drm, "PHY is not ON\n");
377 }
378
379 /* Get IO out of reset */
380 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
381
382 /* Get IO out of Low power state*/
383 for_each_dsi_port(port, intel_dsi->ports) {
384 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {
385 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
386 ULPS_STATE_MASK, DEVICE_READY);
387 usleep_range(10, 15);
388 } else {
389 /* Enter ULPS */
390 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
391 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
392
393 /* Wait for ULPS active */
394 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
395 GLK_ULPS_NOT_ACTIVE, 20))
396 drm_err(display->drm, "ULPS not active\n");
397
398 /* Exit ULPS */
399 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
400 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
401
402 /* Enter Normal Mode */
403 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
404 ULPS_STATE_MASK,
405 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
406
407 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);
408 }
409 }
410
411 /* Wait for Stop state */
412 for_each_dsi_port(port, intel_dsi->ports) {
413 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
414 GLK_DATA_LANE_STOP_STATE, 20))
415 drm_err(display->drm,
416 "Date lane not in STOP state\n");
417 }
418
419 /* Wait for AFE LATCH */
420 for_each_dsi_port(port, intel_dsi->ports) {
421 if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),
422 AFE_LATCHOUT, 20))
423 drm_err(display->drm,
424 "D-PHY not entering LP-11 state\n");
425 }
426 }
427
bxt_dsi_device_ready(struct intel_encoder * encoder)428 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
429 {
430 struct intel_display *display = to_intel_display(encoder);
431 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
432 enum port port;
433 u32 val;
434
435 drm_dbg_kms(display->drm, "\n");
436
437 /* Enable MIPI PHY transparent latch */
438 for_each_dsi_port(port, intel_dsi->ports) {
439 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
440 usleep_range(2000, 2500);
441 }
442
443 /* Clear ULPS and set device ready */
444 for_each_dsi_port(port, intel_dsi->ports) {
445 val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
446 val &= ~ULPS_STATE_MASK;
447 intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
448 usleep_range(2000, 2500);
449 val |= DEVICE_READY;
450 intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
451 }
452 }
453
vlv_dsi_device_ready(struct intel_encoder * encoder)454 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
455 {
456 struct intel_display *display = to_intel_display(encoder);
457 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
458 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
459 enum port port;
460
461 drm_dbg_kms(display->drm, "\n");
462
463 vlv_flisdsi_get(dev_priv);
464 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
465 * needed everytime after power gate */
466 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
467 vlv_flisdsi_put(dev_priv);
468
469 /* bandgap reset is needed after everytime we do power gate */
470 band_gap_reset(dev_priv);
471
472 for_each_dsi_port(port, intel_dsi->ports) {
473
474 intel_de_write(display, MIPI_DEVICE_READY(display, port),
475 ULPS_STATE_ENTER);
476 usleep_range(2500, 3000);
477
478 /* Enable MIPI PHY transparent latch
479 * Common bit for both MIPI Port A & MIPI Port C
480 * No similar bit in MIPI Port C reg
481 */
482 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
483 usleep_range(1000, 1500);
484
485 intel_de_write(display, MIPI_DEVICE_READY(display, port),
486 ULPS_STATE_EXIT);
487 usleep_range(2500, 3000);
488
489 intel_de_write(display, MIPI_DEVICE_READY(display, port),
490 DEVICE_READY);
491 usleep_range(2500, 3000);
492 }
493 }
494
intel_dsi_device_ready(struct intel_encoder * encoder)495 static void intel_dsi_device_ready(struct intel_encoder *encoder)
496 {
497 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
498
499 if (IS_GEMINILAKE(dev_priv))
500 glk_dsi_device_ready(encoder);
501 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
502 bxt_dsi_device_ready(encoder);
503 else
504 vlv_dsi_device_ready(encoder);
505 }
506
glk_dsi_enter_low_power_mode(struct intel_encoder * encoder)507 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
508 {
509 struct intel_display *display = to_intel_display(encoder);
510 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
511 enum port port;
512
513 /* Enter ULPS */
514 for_each_dsi_port(port, intel_dsi->ports)
515 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
516 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
517
518 /* Wait for MIPI PHY status bit to unset */
519 for_each_dsi_port(port, intel_dsi->ports) {
520 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
521 GLK_PHY_STATUS_PORT_READY, 20))
522 drm_err(display->drm, "PHY is not turning OFF\n");
523 }
524
525 /* Wait for Pwr ACK bit to unset */
526 for_each_dsi_port(port, intel_dsi->ports) {
527 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
528 GLK_MIPIIO_PORT_POWERED, 20))
529 drm_err(display->drm,
530 "MIPI IO Port is not powergated\n");
531 }
532 }
533
glk_dsi_disable_mipi_io(struct intel_encoder * encoder)534 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
535 {
536 struct intel_display *display = to_intel_display(encoder);
537 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
538 enum port port;
539
540 /* Put the IO into reset */
541 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
542
543 /* Wait for MIPI PHY status bit to unset */
544 for_each_dsi_port(port, intel_dsi->ports) {
545 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
546 GLK_PHY_STATUS_PORT_READY, 20))
547 drm_err(display->drm, "PHY is not turning OFF\n");
548 }
549
550 /* Clear MIPI mode */
551 for_each_dsi_port(port, intel_dsi->ports)
552 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);
553 }
554
glk_dsi_clear_device_ready(struct intel_encoder * encoder)555 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
556 {
557 glk_dsi_enter_low_power_mode(encoder);
558 glk_dsi_disable_mipi_io(encoder);
559 }
560
port_ctrl_reg(struct drm_i915_private * i915,enum port port)561 static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port)
562 {
563 return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ?
564 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
565 }
566
vlv_dsi_clear_device_ready(struct intel_encoder * encoder)567 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
568 {
569 struct intel_display *display = to_intel_display(encoder);
570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
571 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
572 enum port port;
573
574 drm_dbg_kms(display->drm, "\n");
575 for_each_dsi_port(port, intel_dsi->ports) {
576 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
577 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
578 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
579
580 intel_de_write(display, MIPI_DEVICE_READY(display, port),
581 DEVICE_READY | ULPS_STATE_ENTER);
582 usleep_range(2000, 2500);
583
584 intel_de_write(display, MIPI_DEVICE_READY(display, port),
585 DEVICE_READY | ULPS_STATE_EXIT);
586 usleep_range(2000, 2500);
587
588 intel_de_write(display, MIPI_DEVICE_READY(display, port),
589 DEVICE_READY | ULPS_STATE_ENTER);
590 usleep_range(2000, 2500);
591
592 /*
593 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
594 * Port A only. MIPI Port C has no similar bit for checking.
595 */
596 if ((IS_BROXTON(dev_priv) || port == PORT_A) &&
597 intel_de_wait_for_clear(display, port_ctrl,
598 AFE_LATCHOUT, 30))
599 drm_err(display->drm, "DSI LP not going Low\n");
600
601 /* Disable MIPI PHY transparent latch */
602 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);
603 usleep_range(1000, 1500);
604
605 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);
606 usleep_range(2000, 2500);
607 }
608 }
609
intel_dsi_port_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)610 static void intel_dsi_port_enable(struct intel_encoder *encoder,
611 const struct intel_crtc_state *crtc_state)
612 {
613 struct intel_display *display = to_intel_display(encoder);
614 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
615 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
616 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
617 enum port port;
618
619 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
620 u32 temp = intel_dsi->pixel_overlap;
621
622 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
623 for_each_dsi_port(port, intel_dsi->ports)
624 intel_de_rmw(display, MIPI_CTRL(display, port),
625 BXT_PIXEL_OVERLAP_CNT_MASK,
626 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
627 } else {
628 intel_de_rmw(display, VLV_CHICKEN_3,
629 PIXEL_OVERLAP_CNT_MASK,
630 temp << PIXEL_OVERLAP_CNT_SHIFT);
631 }
632 }
633
634 for_each_dsi_port(port, intel_dsi->ports) {
635 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
636 u32 temp;
637
638 temp = intel_de_read(display, port_ctrl);
639
640 temp &= ~LANE_CONFIGURATION_MASK;
641 temp &= ~DUAL_LINK_MODE_MASK;
642
643 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
644 temp |= (intel_dsi->dual_link - 1)
645 << DUAL_LINK_MODE_SHIFT;
646 if (IS_BROXTON(dev_priv))
647 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
648 else
649 temp |= crtc->pipe ?
650 LANE_CONFIGURATION_DUAL_LINK_B :
651 LANE_CONFIGURATION_DUAL_LINK_A;
652 }
653
654 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
655 temp |= DITHERING_ENABLE;
656
657 /* assert ip_tg_enable signal */
658 intel_de_write(display, port_ctrl, temp | DPI_ENABLE);
659 intel_de_posting_read(display, port_ctrl);
660 }
661 }
662
intel_dsi_port_disable(struct intel_encoder * encoder)663 static void intel_dsi_port_disable(struct intel_encoder *encoder)
664 {
665 struct intel_display *display = to_intel_display(encoder);
666 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
667 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
668 enum port port;
669
670 for_each_dsi_port(port, intel_dsi->ports) {
671 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
672
673 /* de-assert ip_tg_enable signal */
674 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);
675 intel_de_posting_read(display, port_ctrl);
676 }
677 }
678
679 static void intel_dsi_prepare(struct intel_encoder *encoder,
680 const struct intel_crtc_state *pipe_config);
681 static void intel_dsi_unprepare(struct intel_encoder *encoder);
682
683 /*
684 * Panel enable/disable sequences from the VBT spec.
685 *
686 * Note the spec has AssertReset / DeassertReset swapped from their
687 * usual naming. We use the normal names to avoid confusion (so below
688 * they are swapped compared to the spec).
689 *
690 * Steps starting with MIPI refer to VBT sequences, note that for v2
691 * VBTs several steps which have a VBT in v2 are expected to be handled
692 * directly by the driver, by directly driving gpios for example.
693 *
694 * v2 video mode seq v3 video mode seq command mode seq
695 * - power on - MIPIPanelPowerOn - power on
696 * - wait t1+t2 - wait t1+t2
697 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
698 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
699 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
700 * - MIPITearOn
701 * - MIPIDisplayOn
702 * - turn on DPI - turn on DPI - set pipe to dsr mode
703 * - MIPIDisplayOn - MIPIDisplayOn
704 * - wait t5 - wait t5
705 * - backlight on - MIPIBacklightOn - backlight on
706 * ... ... ... issue mem cmds ...
707 * - backlight off - MIPIBacklightOff - backlight off
708 * - wait t6 - wait t6
709 * - MIPIDisplayOff
710 * - turn off DPI - turn off DPI - disable pipe dsr mode
711 * - MIPITearOff
712 * - MIPIDisplayOff - MIPIDisplayOff
713 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
714 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
715 * - wait t3 - wait t3
716 * - power off - MIPIPanelPowerOff - power off
717 * - wait t4 - wait t4
718 */
719
720 /*
721 * DSI port enable has to be done before pipe and plane enable, so we do it in
722 * the pre_enable hook instead of the enable hook.
723 */
intel_dsi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)724 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
725 struct intel_encoder *encoder,
726 const struct intel_crtc_state *pipe_config,
727 const struct drm_connector_state *conn_state)
728 {
729 struct intel_display *display = to_intel_display(encoder);
730 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
731 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
733 enum pipe pipe = crtc->pipe;
734 enum port port;
735 bool glk_cold_boot = false;
736
737 drm_dbg_kms(display->drm, "\n");
738
739 intel_dsi_wait_panel_power_cycle(intel_dsi);
740
741 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
742
743 /*
744 * The BIOS may leave the PLL in a wonky state where it doesn't
745 * lock. It needs to be fully powered down to fix it.
746 */
747 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
748 bxt_dsi_pll_disable(encoder);
749 bxt_dsi_pll_enable(encoder, pipe_config);
750 } else {
751 vlv_dsi_pll_disable(encoder);
752 vlv_dsi_pll_enable(encoder, pipe_config);
753 }
754
755 if (IS_BROXTON(dev_priv)) {
756 /* Add MIPI IO reset programming for modeset */
757 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
758
759 /* Power up DSI regulator */
760 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
761 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
762 }
763
764 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
765 /* Disable DPOunit clock gating, can stall pipe */
766 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),
767 0, DPOUNIT_CLOCK_GATE_DISABLE);
768 }
769
770 if (!IS_GEMINILAKE(dev_priv))
771 intel_dsi_prepare(encoder, pipe_config);
772
773 /* Give the panel time to power-on and then deassert its reset */
774 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
775 msleep(intel_dsi->panel_on_delay);
776 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
777
778 if (IS_GEMINILAKE(dev_priv)) {
779 glk_cold_boot = glk_dsi_enable_io(encoder);
780
781 /* Prepare port in cold boot(s3/s4) scenario */
782 if (glk_cold_boot)
783 intel_dsi_prepare(encoder, pipe_config);
784 }
785
786 /* Put device in ready state (LP-11) */
787 intel_dsi_device_ready(encoder);
788
789 /* Prepare port in normal boot scenario */
790 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
791 intel_dsi_prepare(encoder, pipe_config);
792
793 /* Send initialization commands in LP mode */
794 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
795
796 /*
797 * Enable port in pre-enable phase itself because as per hw team
798 * recommendation, port should be enabled before plane & pipe
799 */
800 if (is_cmd_mode(intel_dsi)) {
801 for_each_dsi_port(port, intel_dsi->ports)
802 intel_de_write(display,
803 MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);
804 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
805 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
806 } else {
807 msleep(20); /* XXX */
808 for_each_dsi_port(port, intel_dsi->ports)
809 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
810 msleep(100);
811
812 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
813
814 intel_dsi_port_enable(encoder, pipe_config);
815 }
816
817 intel_backlight_enable(pipe_config, conn_state);
818 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
819 }
820
bxt_dsi_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)821 static void bxt_dsi_enable(struct intel_atomic_state *state,
822 struct intel_encoder *encoder,
823 const struct intel_crtc_state *crtc_state,
824 const struct drm_connector_state *conn_state)
825 {
826 intel_crtc_vblank_on(crtc_state);
827 }
828
829 /*
830 * DSI port disable has to be done after pipe and plane disable, so we do it in
831 * the post_disable hook.
832 */
intel_dsi_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)833 static void intel_dsi_disable(struct intel_atomic_state *state,
834 struct intel_encoder *encoder,
835 const struct intel_crtc_state *old_crtc_state,
836 const struct drm_connector_state *old_conn_state)
837 {
838 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
839 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
840 enum port port;
841
842 drm_dbg_kms(&i915->drm, "\n");
843
844 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
845 intel_backlight_disable(old_conn_state);
846
847 /*
848 * According to the spec we should send SHUTDOWN before
849 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
850 * has shown that the v3 sequence works for v2 VBTs too
851 */
852 if (is_vid_mode(intel_dsi)) {
853 /* Send Shutdown command to the panel in LP mode */
854 for_each_dsi_port(port, intel_dsi->ports)
855 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
856 msleep(10);
857 }
858 }
859
intel_dsi_clear_device_ready(struct intel_encoder * encoder)860 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
861 {
862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
863
864 if (IS_GEMINILAKE(dev_priv))
865 glk_dsi_clear_device_ready(encoder);
866 else
867 vlv_dsi_clear_device_ready(encoder);
868 }
869
intel_dsi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)870 static void intel_dsi_post_disable(struct intel_atomic_state *state,
871 struct intel_encoder *encoder,
872 const struct intel_crtc_state *old_crtc_state,
873 const struct drm_connector_state *old_conn_state)
874 {
875 struct intel_display *display = to_intel_display(encoder);
876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
877 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
878 enum port port;
879
880 drm_dbg_kms(display->drm, "\n");
881
882 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
883 intel_crtc_vblank_off(old_crtc_state);
884
885 skl_scaler_disable(old_crtc_state);
886 }
887
888 if (is_vid_mode(intel_dsi)) {
889 for_each_dsi_port(port, intel_dsi->ports)
890 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
891
892 intel_dsi_port_disable(encoder);
893 usleep_range(2000, 5000);
894 }
895
896 intel_dsi_unprepare(encoder);
897
898 /*
899 * if disable packets are sent before sending shutdown packet then in
900 * some next enable sequence send turn on packet error is observed
901 */
902 if (is_cmd_mode(intel_dsi))
903 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
904 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
905
906 /* Transition to LP-00 */
907 intel_dsi_clear_device_ready(encoder);
908
909 if (IS_BROXTON(dev_priv)) {
910 /* Power down DSI regulator to save power */
911 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
912 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,
913 HS_IO_CTRL_SELECT);
914
915 /* Add MIPI IO reset programming for modeset */
916 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
917 }
918
919 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
920 bxt_dsi_pll_disable(encoder);
921 } else {
922 vlv_dsi_pll_disable(encoder);
923
924 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),
925 DPOUNIT_CLOCK_GATE_DISABLE, 0);
926 }
927
928 /* Assert reset */
929 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
930
931 msleep(intel_dsi->panel_off_delay);
932 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
933
934 intel_dsi->panel_power_off_time = ktime_get_boottime();
935 }
936
intel_dsi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)937 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
938 enum pipe *pipe)
939 {
940 struct intel_display *display = to_intel_display(encoder);
941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
942 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
943 intel_wakeref_t wakeref;
944 enum port port;
945 bool active = false;
946
947 drm_dbg_kms(display->drm, "\n");
948
949 wakeref = intel_display_power_get_if_enabled(dev_priv,
950 encoder->power_domain);
951 if (!wakeref)
952 return false;
953
954 /*
955 * On Broxton the PLL needs to be enabled with a valid divider
956 * configuration, otherwise accessing DSI registers will hang the
957 * machine. See BSpec North Display Engine registers/MIPI[BXT].
958 */
959 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
960 !bxt_dsi_pll_is_enabled(dev_priv))
961 goto out_put_power;
962
963 /* XXX: this only works for one DSI output */
964 for_each_dsi_port(port, intel_dsi->ports) {
965 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
966 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
967
968 /*
969 * Due to some hardware limitations on VLV/CHV, the DPI enable
970 * bit in port C control register does not get set. As a
971 * workaround, check pipe B conf instead.
972 */
973 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
974 port == PORT_C)
975 enabled = intel_de_read(display,
976 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
977
978 /* Try command mode if video mode not enabled */
979 if (!enabled) {
980 u32 tmp = intel_de_read(display,
981 MIPI_DSI_FUNC_PRG(display, port));
982 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
983 }
984
985 if (!enabled)
986 continue;
987
988 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))
989 continue;
990
991 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
992 u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
993 tmp &= BXT_PIPE_SELECT_MASK;
994 tmp >>= BXT_PIPE_SELECT_SHIFT;
995
996 if (drm_WARN_ON(display->drm, tmp > PIPE_C))
997 continue;
998
999 *pipe = tmp;
1000 } else {
1001 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1002 }
1003
1004 active = true;
1005 break;
1006 }
1007
1008 out_put_power:
1009 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1010
1011 return active;
1012 }
1013
bxt_dsi_get_pipe_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1014 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1015 struct intel_crtc_state *pipe_config)
1016 {
1017 struct intel_display *display = to_intel_display(encoder);
1018 struct drm_display_mode *adjusted_mode =
1019 &pipe_config->hw.adjusted_mode;
1020 struct drm_display_mode *adjusted_mode_sw;
1021 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1022 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1023 unsigned int lane_count = intel_dsi->lane_count;
1024 unsigned int bpp, fmt;
1025 enum port port;
1026 u16 hactive, hfp, hsync, hbp, vfp, vsync;
1027 u16 hfp_sw, hsync_sw, hbp_sw;
1028 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1029 crtc_hblank_start_sw, crtc_hblank_end_sw;
1030
1031 /* FIXME: hw readout should not depend on SW state */
1032 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1033
1034 /*
1035 * Atleast one port is active as encoder->get_config called only if
1036 * encoder->get_hw_state() returns true.
1037 */
1038 for_each_dsi_port(port, intel_dsi->ports) {
1039 if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1040 break;
1041 }
1042
1043 fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;
1044 bpp = mipi_dsi_pixel_format_to_bpp(
1045 pixel_format_from_register_bits(fmt));
1046
1047 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1048
1049 /* Enable Frame time stamo based scanline reporting */
1050 pipe_config->mode_flags |=
1051 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1052
1053 /* In terms of pixels */
1054 adjusted_mode->crtc_hdisplay =
1055 intel_de_read(display,
1056 BXT_MIPI_TRANS_HACTIVE(port));
1057 adjusted_mode->crtc_vdisplay =
1058 intel_de_read(display,
1059 BXT_MIPI_TRANS_VACTIVE(port));
1060 adjusted_mode->crtc_vtotal =
1061 intel_de_read(display,
1062 BXT_MIPI_TRANS_VTOTAL(port));
1063
1064 hactive = adjusted_mode->crtc_hdisplay;
1065 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));
1066
1067 /*
1068 * Meaningful for video mode non-burst sync pulse mode only,
1069 * can be zero for non-burst sync events and burst modes
1070 */
1071 hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));
1072 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));
1073
1074 /* harizontal values are in terms of high speed byte clock */
1075 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1076 intel_dsi->burst_mode_ratio);
1077 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1078 intel_dsi->burst_mode_ratio);
1079 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1080 intel_dsi->burst_mode_ratio);
1081
1082 if (intel_dsi->dual_link) {
1083 hfp *= 2;
1084 hsync *= 2;
1085 hbp *= 2;
1086 }
1087
1088 /* vertical values are in terms of lines */
1089 vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));
1090 vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));
1091
1092 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1093 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1094 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1095 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1096 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1097
1098 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1099 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1100 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1101 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1102
1103 /*
1104 * In BXT DSI there is no regs programmed with few horizontal timings
1105 * in Pixels but txbyteclkhs.. So retrieval process adds some
1106 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1107 * Actually here for the given adjusted_mode, we are calculating the
1108 * value programmed to the port and then back to the horizontal timing
1109 * param in pixels. This is the expected value, including roundup errors
1110 * And if that is same as retrieved value from port, then
1111 * (HW state) adjusted_mode's horizontal timings are corrected to
1112 * match with SW state to nullify the errors.
1113 */
1114 /* Calculating the value programmed to the Port register */
1115 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1116 adjusted_mode_sw->crtc_hdisplay;
1117 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1118 adjusted_mode_sw->crtc_hsync_start;
1119 hbp_sw = adjusted_mode_sw->crtc_htotal -
1120 adjusted_mode_sw->crtc_hsync_end;
1121
1122 if (intel_dsi->dual_link) {
1123 hfp_sw /= 2;
1124 hsync_sw /= 2;
1125 hbp_sw /= 2;
1126 }
1127
1128 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1129 intel_dsi->burst_mode_ratio);
1130 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1131 intel_dsi->burst_mode_ratio);
1132 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1133 intel_dsi->burst_mode_ratio);
1134
1135 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1136 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1137 intel_dsi->burst_mode_ratio);
1138 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1139 intel_dsi->burst_mode_ratio);
1140 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1141 intel_dsi->burst_mode_ratio);
1142
1143 if (intel_dsi->dual_link) {
1144 hfp_sw *= 2;
1145 hsync_sw *= 2;
1146 hbp_sw *= 2;
1147 }
1148
1149 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1150 hsync_sw + hbp_sw;
1151 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1152 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1153 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1154 crtc_hblank_end_sw = crtc_htotal_sw;
1155
1156 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1157 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1158
1159 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1160 adjusted_mode->crtc_hsync_start =
1161 adjusted_mode_sw->crtc_hsync_start;
1162
1163 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1164 adjusted_mode->crtc_hsync_end =
1165 adjusted_mode_sw->crtc_hsync_end;
1166
1167 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1168 adjusted_mode->crtc_hblank_start =
1169 adjusted_mode_sw->crtc_hblank_start;
1170
1171 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1172 adjusted_mode->crtc_hblank_end =
1173 adjusted_mode_sw->crtc_hblank_end;
1174 }
1175
intel_dsi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1176 static void intel_dsi_get_config(struct intel_encoder *encoder,
1177 struct intel_crtc_state *pipe_config)
1178 {
1179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1180 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1181 u32 pclk;
1182
1183 drm_dbg_kms(&dev_priv->drm, "\n");
1184
1185 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1186
1187 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1188 bxt_dsi_get_pipe_config(encoder, pipe_config);
1189 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1190 } else {
1191 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1192 }
1193
1194 pipe_config->port_clock = pclk;
1195
1196 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1197 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1198 if (intel_dsi->dual_link)
1199 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1200 }
1201
1202 /* return txclkesc cycles in terms of divider and duration in us */
txclkesc(u32 divider,unsigned int us)1203 static u16 txclkesc(u32 divider, unsigned int us)
1204 {
1205 switch (divider) {
1206 case ESCAPE_CLOCK_DIVIDER_1:
1207 default:
1208 return 20 * us;
1209 case ESCAPE_CLOCK_DIVIDER_2:
1210 return 10 * us;
1211 case ESCAPE_CLOCK_DIVIDER_4:
1212 return 5 * us;
1213 }
1214 }
1215
set_dsi_timings(struct intel_encoder * encoder,const struct drm_display_mode * adjusted_mode)1216 static void set_dsi_timings(struct intel_encoder *encoder,
1217 const struct drm_display_mode *adjusted_mode)
1218 {
1219 struct intel_display *display = to_intel_display(encoder);
1220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1221 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1222 enum port port;
1223 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1224 unsigned int lane_count = intel_dsi->lane_count;
1225
1226 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1227
1228 hactive = adjusted_mode->crtc_hdisplay;
1229 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1230 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1231 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1232
1233 if (intel_dsi->dual_link) {
1234 hactive /= 2;
1235 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1236 hactive += intel_dsi->pixel_overlap;
1237 hfp /= 2;
1238 hsync /= 2;
1239 hbp /= 2;
1240 }
1241
1242 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1243 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1244 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1245
1246 /* horizontal values are in terms of high speed byte clock */
1247 hactive = txbyteclkhs(hactive, bpp, lane_count,
1248 intel_dsi->burst_mode_ratio);
1249 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1250 hsync = txbyteclkhs(hsync, bpp, lane_count,
1251 intel_dsi->burst_mode_ratio);
1252 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1253
1254 for_each_dsi_port(port, intel_dsi->ports) {
1255 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1256 /*
1257 * Program hdisplay and vdisplay on MIPI transcoder.
1258 * This is different from calculated hactive and
1259 * vactive, as they are calculated per channel basis,
1260 * whereas these values should be based on resolution.
1261 */
1262 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),
1263 adjusted_mode->crtc_hdisplay);
1264 intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),
1265 adjusted_mode->crtc_vdisplay);
1266 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),
1267 adjusted_mode->crtc_vtotal);
1268 }
1269
1270 intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),
1271 hactive);
1272 intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);
1273
1274 /* meaningful for video mode non-burst sync pulse mode only,
1275 * can be zero for non-burst sync events and burst modes */
1276 intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),
1277 hsync);
1278 intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);
1279
1280 /* vertical values are in terms of lines */
1281 intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);
1282 intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),
1283 vsync);
1284 intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);
1285 }
1286 }
1287
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)1288 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1289 {
1290 switch (fmt) {
1291 case MIPI_DSI_FMT_RGB888:
1292 return VID_MODE_FORMAT_RGB888;
1293 case MIPI_DSI_FMT_RGB666:
1294 return VID_MODE_FORMAT_RGB666;
1295 case MIPI_DSI_FMT_RGB666_PACKED:
1296 return VID_MODE_FORMAT_RGB666_PACKED;
1297 case MIPI_DSI_FMT_RGB565:
1298 return VID_MODE_FORMAT_RGB565;
1299 default:
1300 MISSING_CASE(fmt);
1301 return VID_MODE_FORMAT_RGB666;
1302 }
1303 }
1304
intel_dsi_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)1305 static void intel_dsi_prepare(struct intel_encoder *encoder,
1306 const struct intel_crtc_state *pipe_config)
1307 {
1308 struct intel_display *display = to_intel_display(encoder);
1309 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1310 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1311 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1312 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1313 enum port port;
1314 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1315 u32 val, tmp;
1316 u16 mode_hdisplay;
1317
1318 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));
1319
1320 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1321
1322 if (intel_dsi->dual_link) {
1323 mode_hdisplay /= 2;
1324 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1325 mode_hdisplay += intel_dsi->pixel_overlap;
1326 }
1327
1328 for_each_dsi_port(port, intel_dsi->ports) {
1329 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1330 /*
1331 * escape clock divider, 20MHz, shared for A and C.
1332 * device ready must be off when doing this! txclkesc?
1333 */
1334 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
1335 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1336 intel_de_write(display, MIPI_CTRL(display, PORT_A),
1337 tmp | ESCAPE_CLOCK_DIVIDER_1);
1338
1339 /* read request priority is per pipe */
1340 tmp = intel_de_read(display, MIPI_CTRL(display, port));
1341 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1342 intel_de_write(display, MIPI_CTRL(display, port),
1343 tmp | READ_REQUEST_PRIORITY_HIGH);
1344 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1345 enum pipe pipe = crtc->pipe;
1346
1347 intel_de_rmw(display, MIPI_CTRL(display, port),
1348 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1349 }
1350
1351 /* XXX: why here, why like this? handling in irq handler?! */
1352 intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);
1353 intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);
1354
1355 intel_de_write(display, MIPI_DPHY_PARAM(display, port),
1356 intel_dsi->dphy_reg);
1357
1358 intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),
1359 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1360 }
1361
1362 set_dsi_timings(encoder, adjusted_mode);
1363
1364 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1365 if (is_cmd_mode(intel_dsi)) {
1366 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1367 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1368 } else {
1369 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1370 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1371 }
1372
1373 tmp = 0;
1374 if (intel_dsi->eotp_pkt == 0)
1375 tmp |= EOT_DISABLE;
1376 if (intel_dsi->clock_stop)
1377 tmp |= CLOCKSTOP;
1378
1379 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1380 tmp |= BXT_DPHY_DEFEATURE_EN;
1381 if (!is_cmd_mode(intel_dsi))
1382 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1383 }
1384
1385 for_each_dsi_port(port, intel_dsi->ports) {
1386 intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);
1387
1388 /* timeouts for recovery. one frame IIUC. if counter expires,
1389 * EOT and stop state. */
1390
1391 /*
1392 * In burst mode, value greater than one DPI line Time in byte
1393 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1394 * said value is recommended.
1395 *
1396 * In non-burst mode, Value greater than one DPI frame time in
1397 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1398 * said value is recommended.
1399 *
1400 * In DBI only mode, value greater than one DBI frame time in
1401 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1402 * said value is recommended.
1403 */
1404
1405 if (is_vid_mode(intel_dsi) &&
1406 intel_dsi->video_mode == BURST_MODE) {
1407 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
1408 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1409 } else {
1410 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
1411 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1412 }
1413 intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),
1414 intel_dsi->lp_rx_timeout);
1415 intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),
1416 intel_dsi->turn_arnd_val);
1417 intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),
1418 intel_dsi->rst_timer_val);
1419
1420 /* dphy stuff */
1421
1422 /* in terms of low power clock */
1423 intel_de_write(display, MIPI_INIT_COUNT(display, port),
1424 txclkesc(intel_dsi->escape_clk_div, 100));
1425
1426 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1427 !intel_dsi->dual_link) {
1428 /*
1429 * BXT spec says write MIPI_INIT_COUNT for
1430 * both the ports, even if only one is
1431 * getting used. So write the other port
1432 * if not in dual link mode.
1433 */
1434 intel_de_write(display,
1435 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),
1436 intel_dsi->init_count);
1437 }
1438
1439 /* recovery disables */
1440 intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);
1441
1442 /* in terms of low power clock */
1443 intel_de_write(display, MIPI_INIT_COUNT(display, port),
1444 intel_dsi->init_count);
1445
1446 /* in terms of txbyteclkhs. actual high to low switch +
1447 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1448 *
1449 * XXX: write MIPI_STOP_STATE_STALL?
1450 */
1451 intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),
1452 intel_dsi->hs_to_lp_count);
1453
1454 /* XXX: low power clock equivalence in terms of byte clock.
1455 * the number of byte clocks occupied in one low power clock.
1456 * based on txbyteclkhs and txclkesc.
1457 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1458 * ) / 105.???
1459 */
1460 intel_de_write(display, MIPI_LP_BYTECLK(display, port),
1461 intel_dsi->lp_byte_clk);
1462
1463 if (IS_GEMINILAKE(dev_priv)) {
1464 intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),
1465 intel_dsi->lp_byte_clk);
1466 /* Shadow of DPHY reg */
1467 intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),
1468 intel_dsi->dphy_reg);
1469 }
1470
1471 /* the bw essential for transmitting 16 long packets containing
1472 * 252 bytes meant for dcs write memory command is programmed in
1473 * this register in terms of byte clocks. based on dsi transfer
1474 * rate and the number of lanes configured the time taken to
1475 * transmit 16 long packets in a dsi stream varies. */
1476 intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),
1477 intel_dsi->bw_timer);
1478
1479 intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),
1480 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1481
1482 if (is_vid_mode(intel_dsi)) {
1483 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1484
1485 /*
1486 * Some panels might have resolution which is not a
1487 * multiple of 64 like 1366 x 768. Enable RANDOM
1488 * resolution support for such panels by default.
1489 */
1490 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1491
1492 switch (intel_dsi->video_mode) {
1493 default:
1494 MISSING_CASE(intel_dsi->video_mode);
1495 fallthrough;
1496 case NON_BURST_SYNC_EVENTS:
1497 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1498 break;
1499 case NON_BURST_SYNC_PULSE:
1500 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1501 break;
1502 case BURST_MODE:
1503 fmt |= VIDEO_MODE_BURST;
1504 break;
1505 }
1506
1507 intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);
1508 }
1509 }
1510 }
1511
intel_dsi_unprepare(struct intel_encoder * encoder)1512 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1513 {
1514 struct intel_display *display = to_intel_display(encoder);
1515 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1516 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1517 enum port port;
1518
1519 if (IS_GEMINILAKE(dev_priv))
1520 return;
1521
1522 for_each_dsi_port(port, intel_dsi->ports) {
1523 /* Panel commands can be sent when clock is in LP11 */
1524 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);
1525
1526 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1527 bxt_dsi_reset_clocks(encoder, port);
1528 else
1529 vlv_dsi_reset_clocks(encoder, port);
1530 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
1531
1532 intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);
1533
1534 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);
1535 }
1536 }
1537
1538 static const struct drm_encoder_funcs intel_dsi_funcs = {
1539 .destroy = intel_encoder_destroy,
1540 };
1541
vlv_dsi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1542 static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
1543 struct drm_display_mode *mode)
1544 {
1545 struct drm_i915_private *i915 = to_i915(connector->dev);
1546
1547 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1548 enum drm_mode_status status;
1549
1550 status = intel_cpu_transcoder_mode_valid(i915, mode);
1551 if (status != MODE_OK)
1552 return status;
1553 }
1554
1555 return intel_dsi_mode_valid(connector, mode);
1556 }
1557
1558 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1559 .get_modes = intel_dsi_get_modes,
1560 .mode_valid = vlv_dsi_mode_valid,
1561 .atomic_check = intel_digital_connector_atomic_check,
1562 };
1563
1564 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1565 .detect = intel_panel_detect,
1566 .late_register = intel_connector_register,
1567 .early_unregister = intel_connector_unregister,
1568 .destroy = intel_connector_destroy,
1569 .fill_modes = drm_helper_probe_single_connector_modes,
1570 .atomic_get_property = intel_digital_connector_atomic_get_property,
1571 .atomic_set_property = intel_digital_connector_atomic_set_property,
1572 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1573 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1574 };
1575
vlv_dsi_add_properties(struct intel_connector * connector)1576 static void vlv_dsi_add_properties(struct intel_connector *connector)
1577 {
1578 const struct drm_display_mode *fixed_mode =
1579 intel_panel_preferred_fixed_mode(connector);
1580
1581 intel_attach_scaling_mode_property(&connector->base);
1582
1583 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1584 intel_dsi_get_panel_orientation(connector),
1585 fixed_mode->hdisplay,
1586 fixed_mode->vdisplay);
1587 }
1588
1589 #define NS_KHZ_RATIO 1000000
1590
1591 #define PREPARE_CNT_MAX 0x3F
1592 #define EXIT_ZERO_CNT_MAX 0x3F
1593 #define CLK_ZERO_CNT_MAX 0xFF
1594 #define TRAIL_CNT_MAX 0x1F
1595
vlv_dphy_param_init(struct intel_dsi * intel_dsi)1596 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1597 {
1598 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
1599 struct intel_connector *connector = intel_dsi->attached_connector;
1600 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1601 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1602 u32 ui_num, ui_den;
1603 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1604 u32 ths_prepare_ns, tclk_trail_ns;
1605 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1606 u32 lp_to_hs_switch, hs_to_lp_switch;
1607 u32 mul;
1608
1609 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1610
1611 switch (intel_dsi->lane_count) {
1612 case 1:
1613 case 2:
1614 extra_byte_count = 2;
1615 break;
1616 case 3:
1617 extra_byte_count = 4;
1618 break;
1619 case 4:
1620 default:
1621 extra_byte_count = 3;
1622 break;
1623 }
1624
1625 /* in Kbps */
1626 ui_num = NS_KHZ_RATIO;
1627 ui_den = intel_dsi_bitrate(intel_dsi);
1628
1629 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1630 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1631
1632 /*
1633 * B060
1634 * LP byte clock = TLPX/ (8UI)
1635 */
1636 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1637
1638 /* DDR clock period = 2 * UI
1639 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1640 * UI(nsec) = 10^6 / bitrate
1641 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1642 * DDR clock count = ns_value / DDR clock period
1643 *
1644 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1645 * HS byte clock count for other platform in HS ddr clock count
1646 */
1647 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1648 ths_prepare_ns = max(mipi_config->ths_prepare,
1649 mipi_config->tclk_prepare);
1650
1651 /* prepare count */
1652 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1653
1654 if (prepare_cnt > PREPARE_CNT_MAX) {
1655 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1656 prepare_cnt);
1657 prepare_cnt = PREPARE_CNT_MAX;
1658 }
1659
1660 /* exit zero count */
1661 exit_zero_cnt = DIV_ROUND_UP(
1662 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1663 ui_num * mul
1664 );
1665
1666 /*
1667 * Exit zero is unified val ths_zero and ths_exit
1668 * minimum value for ths_exit = 110ns
1669 * min (exit_zero_cnt * 2) = 110/UI
1670 * exit_zero_cnt = 55/UI
1671 */
1672 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1673 exit_zero_cnt += 1;
1674
1675 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1676 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1677 exit_zero_cnt);
1678 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1679 }
1680
1681 /* clk zero count */
1682 clk_zero_cnt = DIV_ROUND_UP(
1683 (tclk_prepare_clkzero - ths_prepare_ns)
1684 * ui_den, ui_num * mul);
1685
1686 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1687 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1688 clk_zero_cnt);
1689 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1690 }
1691
1692 /* trail count */
1693 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1694 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1695
1696 if (trail_cnt > TRAIL_CNT_MAX) {
1697 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1698 trail_cnt);
1699 trail_cnt = TRAIL_CNT_MAX;
1700 }
1701
1702 /* B080 */
1703 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1704 clk_zero_cnt << 8 | prepare_cnt;
1705
1706 /*
1707 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1708 * mul + 10UI + Extra Byte Count
1709 *
1710 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1711 * Extra Byte Count is calculated according to number of lanes.
1712 * High Low Switch Count is the Max of LP to HS and
1713 * HS to LP switch count
1714 *
1715 */
1716 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1717
1718 /* B044 */
1719 /* FIXME:
1720 * The comment above does not match with the code */
1721 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1722 exit_zero_cnt * mul + 10, 8);
1723
1724 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1725
1726 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1727 intel_dsi->hs_to_lp_count += extra_byte_count;
1728
1729 /* B088 */
1730 /* LP -> HS for clock lanes
1731 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1732 * extra byte count
1733 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1734 * 2(in UI) + extra byte count
1735 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1736 * 8 + extra byte count
1737 */
1738 intel_dsi->clk_lp_to_hs_count =
1739 DIV_ROUND_UP(
1740 4 * tlpx_ui + prepare_cnt * 2 +
1741 clk_zero_cnt * 2,
1742 8);
1743
1744 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1745
1746 /* HS->LP for Clock Lanes
1747 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1748 * Extra byte count
1749 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1750 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1751 * Extra byte count
1752 */
1753 intel_dsi->clk_hs_to_lp_count =
1754 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1755 8);
1756 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1757
1758 intel_dsi_log_params(intel_dsi);
1759 }
1760
1761 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
1762
1763 /*
1764 * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1765 * being shown as the first line. The factory installed Android has a hardcoded
1766 * modeline, causing it to not suffer from this BIOS bug.
1767 *
1768 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa
1769 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa
1770 *
1771 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1772 */
vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi * intel_dsi)1773 static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi)
1774 {
1775 /* Cast away the const as we want to fixup the mode */
1776 struct drm_display_mode *fixed_mode = (struct drm_display_mode *)
1777 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1778
1779 if (fixed_mode->vtotal == 820)
1780 fixed_mode->vtotal -= 4;
1781 }
1782
1783 /*
1784 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems:
1785 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1786 * which under Linux become bus 0 - 6. And the MIPI sequence reference
1787 * to bus 3 is indented for I2C3 which is bus 2 under Linux.
1788 *
1789 * Note mipi_exec_i2c() cannot just subtract 1 from the bus
1790 * given in the I2C MIPI sequence element. Since on other
1791 * devices the I2C bus-numbers used in the MIPI sequences do
1792 * actually start at 0.
1793 *
1794 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is
1795 * especially a problem on the 8" 830 version which uses a 10:16
1796 * portrait screen where as the bogus size is 16:10.
1797 *
1798 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1799 */
vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi * intel_dsi)1800 static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi)
1801 {
1802 const struct drm_display_mode *fixed_mode =
1803 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1804 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info;
1805
1806 intel_dsi->i2c_bus_num = 2;
1807
1808 /*
1809 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830
1810 * uses a 1200x1920 portrait screen.
1811 */
1812 if (fixed_mode->hdisplay == 1920) {
1813 info->width_mm = 216;
1814 info->height_mm = 135;
1815 } else {
1816 info->width_mm = 107;
1817 info->height_mm = 171;
1818 }
1819 }
1820
1821 /*
1822 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1823 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c()
1824 * to not work. Fix this by setting i2c_bus_num.
1825 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on.
1826 * Add a backlight off sequence mirroring the existing backlight on sequence.
1827 *
1828 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1829 */
vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi * intel_dsi)1830 static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi)
1831 {
1832 static const u8 backlight_off_sequence[16] = {
1833 /* Header Seq-id 7, length after header 11 bytes */
1834 0x07, 0x0b, 0x00, 0x00, 0x00,
1835 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */
1836 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00,
1837 /* MIPI_SEQ_ELEM_END */
1838 0x00
1839 };
1840 struct intel_connector *connector = intel_dsi->attached_connector;
1841
1842 intel_dsi->i2c_bus_num = 0;
1843 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence;
1844 }
1845
1846 static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
1847 {
1848 /* Asus Transformer Pad TF103C */
1849 .matches = {
1850 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1851 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"),
1852 },
1853 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup,
1854 },
1855 {
1856 /*
1857 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10"
1858 * Lenovo Yoga Tablet 2 use the same mainboard)
1859 */
1860 .matches = {
1861 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
1862 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
1863 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1864 /* Partial match on beginning of BIOS version */
1865 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
1866 },
1867 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup,
1868 },
1869 {
1870 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1871 .matches = {
1872 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
1873 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1874 },
1875 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,
1876 },
1877 { }
1878 };
1879
vlv_dsi_init(struct drm_i915_private * dev_priv)1880 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1881 {
1882 struct intel_display *display = &dev_priv->display;
1883 struct intel_dsi *intel_dsi;
1884 struct intel_encoder *encoder;
1885 struct intel_connector *connector;
1886 struct drm_display_mode *current_mode;
1887 const struct dmi_system_id *dmi_id;
1888 enum port port;
1889 enum pipe pipe;
1890
1891 drm_dbg_kms(&dev_priv->drm, "\n");
1892
1893 /* There is no detection method for MIPI so rely on VBT */
1894 if (!intel_bios_is_dsi_present(display, &port))
1895 return;
1896
1897 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1898 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1899 else
1900 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1901
1902 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1903 if (!intel_dsi)
1904 return;
1905
1906 connector = intel_connector_alloc();
1907 if (!connector) {
1908 kfree(intel_dsi);
1909 return;
1910 }
1911
1912 encoder = &intel_dsi->base;
1913 intel_dsi->attached_connector = connector;
1914
1915 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs,
1916 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1917
1918 encoder->compute_config = intel_dsi_compute_config;
1919 encoder->pre_enable = intel_dsi_pre_enable;
1920 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1921 encoder->enable = bxt_dsi_enable;
1922 encoder->disable = intel_dsi_disable;
1923 encoder->post_disable = intel_dsi_post_disable;
1924 encoder->get_hw_state = intel_dsi_get_hw_state;
1925 encoder->get_config = intel_dsi_get_config;
1926 encoder->update_pipe = intel_backlight_update;
1927 encoder->shutdown = intel_dsi_shutdown;
1928
1929 connector->get_hw_state = intel_connector_get_hw_state;
1930
1931 encoder->port = port;
1932 encoder->type = INTEL_OUTPUT_DSI;
1933 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1934 encoder->cloneable = 0;
1935
1936 /*
1937 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1938 * port C. BXT isn't limited like this.
1939 */
1940 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1941 encoder->pipe_mask = ~0;
1942 else if (port == PORT_A)
1943 encoder->pipe_mask = BIT(PIPE_A);
1944 else
1945 encoder->pipe_mask = BIT(PIPE_B);
1946
1947 intel_dsi->panel_power_off_time = ktime_get_boottime();
1948
1949 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);
1950
1951 if (connector->panel.vbt.dsi.config->dual_link)
1952 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1953 else
1954 intel_dsi->ports = BIT(port);
1955
1956 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1957 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1958
1959 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1960 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1961
1962 /* Create a DSI host (and a device) for each port. */
1963 for_each_dsi_port(port, intel_dsi->ports) {
1964 struct intel_dsi_host *host;
1965
1966 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1967 port);
1968 if (!host)
1969 goto err;
1970
1971 intel_dsi->dsi_hosts[port] = host;
1972 }
1973
1974 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1975 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1976 goto err;
1977 }
1978
1979 /* Use clock read-back from current hw-state for fastboot */
1980 current_mode = intel_encoder_current_mode(encoder);
1981 if (current_mode) {
1982 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1983 intel_dsi->pclk, current_mode->clock);
1984 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1985 current_mode->clock)) {
1986 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1987 intel_dsi->pclk = current_mode->clock;
1988 }
1989
1990 kfree(current_mode);
1991 }
1992
1993 vlv_dphy_param_init(intel_dsi);
1994
1995 intel_dsi_vbt_gpio_init(intel_dsi,
1996 intel_dsi_get_hw_state(encoder, &pipe));
1997
1998 drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs,
1999 DRM_MODE_CONNECTOR_DSI);
2000
2001 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs);
2002
2003 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
2004
2005 intel_connector_attach_encoder(connector, encoder);
2006
2007 mutex_lock(&dev_priv->drm.mode_config.mutex);
2008 intel_panel_add_vbt_lfp_fixed_mode(connector);
2009 mutex_unlock(&dev_priv->drm.mode_config.mutex);
2010
2011 if (!intel_panel_preferred_fixed_mode(connector)) {
2012 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
2013 goto err_cleanup_connector;
2014 }
2015
2016 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table);
2017 if (dmi_id) {
2018 vlv_dsi_dmi_quirk_func quirk_func =
2019 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data;
2020
2021 quirk_func(intel_dsi);
2022 }
2023
2024 intel_panel_init(connector, NULL);
2025
2026 intel_backlight_setup(connector, INVALID_PIPE);
2027
2028 vlv_dsi_add_properties(connector);
2029
2030 return;
2031
2032 err_cleanup_connector:
2033 drm_connector_cleanup(&connector->base);
2034 err:
2035 drm_encoder_cleanup(&encoder->base);
2036 kfree(intel_dsi);
2037 kfree(connector);
2038 }
2039