1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file exposes functions that may be used with BuildMI from the
10 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
11 //
12 // The BuildMem function may be used with the BuildMI function to add entire
13 // memory references in a single, typed, function call. X86 memory references
14 // can be very complex expressions (described in the README), so wrapping them
15 // up behind an easier to use interface makes sense. Descriptions of the
16 // functions are included below.
17 //
18 // For reference, the order of operands for memory references is:
19 // (Operand), Base, Scale, Index, Displacement.
20 //
21 //===----------------------------------------------------------------------===//
22
23 #ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
24 #define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
25
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include <cassert>
35
36 namespace llvm {
37
38 /// X86AddressMode - This struct holds a generalized full x86 address mode.
39 /// The base register can be a frame index, which will eventually be replaced
40 /// with BP or SP and Disp being offsetted accordingly. The displacement may
41 /// also include the offset of a global value.
42 struct X86AddressMode {
43 enum { RegBase, FrameIndexBase } BaseType = RegBase;
44
45 union BaseUnion {
46 Register Reg;
47 int FrameIndex;
48
BaseUnion()49 BaseUnion() : Reg() {}
50 } Base;
51
52 unsigned Scale = 1;
53 Register IndexReg;
54 int Disp = 0;
55 const GlobalValue *GV = nullptr;
56 unsigned GVOpFlags = 0;
57 bool CP = false;
58
getFullAddressX86AddressMode59 void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
60 assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
61
62 if (BaseType == X86AddressMode::RegBase)
63 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
64 false, false, false, 0, false));
65 else {
66 assert(BaseType == X86AddressMode::FrameIndexBase);
67 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
68 }
69
70 MO.push_back(MachineOperand::CreateImm(Scale));
71 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
72 false, false, 0, false));
73
74 if (GV)
75 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
76 else
77 MO.push_back(MachineOperand::CreateImm(Disp));
78
79 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
80 false, 0, false));
81 }
82 };
83
84 /// Compute the addressing mode from an machine instruction starting with the
85 /// given operand.
getAddressFromInstr(const MachineInstr * MI,unsigned Operand)86 static inline X86AddressMode getAddressFromInstr(const MachineInstr *MI,
87 unsigned Operand) {
88 X86AddressMode AM;
89 const MachineOperand &Op0 = MI->getOperand(Operand);
90 if (Op0.isReg()) {
91 AM.BaseType = X86AddressMode::RegBase;
92 AM.Base.Reg = Op0.getReg();
93 } else {
94 AM.BaseType = X86AddressMode::FrameIndexBase;
95 AM.Base.FrameIndex = Op0.getIndex();
96 }
97
98 const MachineOperand &Op1 = MI->getOperand(Operand + 1);
99 AM.Scale = Op1.getImm();
100
101 const MachineOperand &Op2 = MI->getOperand(Operand + 2);
102 AM.IndexReg = Op2.getReg();
103
104 const MachineOperand &Op3 = MI->getOperand(Operand + 3);
105 if (Op3.isGlobal())
106 AM.GV = Op3.getGlobal();
107 else
108 AM.Disp = Op3.getImm();
109
110 return AM;
111 }
112
113 /// addDirectMem - This function is used to add a direct memory reference to the
114 /// current instruction -- that is, a dereference of an address in a register,
115 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
116 ///
117 static inline const MachineInstrBuilder &
addDirectMem(const MachineInstrBuilder & MIB,Register Reg)118 addDirectMem(const MachineInstrBuilder &MIB, Register Reg) {
119 // Because memory references are always represented with five
120 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
121 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
122 }
123
124 /// Replace the address used in the instruction with the direct memory
125 /// reference.
setDirectAddressInInstr(MachineInstr * MI,unsigned Operand,Register Reg)126 static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand,
127 Register Reg) {
128 // Direct memory address is in a form of: Reg/FI, 1 (Scale), NoReg, 0, NoReg.
129 MI->getOperand(Operand).ChangeToRegister(Reg, /*isDef=*/false);
130 MI->getOperand(Operand + 1).setImm(1);
131 MI->getOperand(Operand + 2).setReg(0);
132 MI->getOperand(Operand + 3).ChangeToImmediate(0);
133 MI->getOperand(Operand + 4).setReg(0);
134 }
135
136 static inline const MachineInstrBuilder &
addOffset(const MachineInstrBuilder & MIB,int Offset)137 addOffset(const MachineInstrBuilder &MIB, int Offset) {
138 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
139 }
140
141 static inline const MachineInstrBuilder &
addOffset(const MachineInstrBuilder & MIB,const MachineOperand & Offset)142 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
143 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
144 }
145
146 /// addRegOffset - This function is used to add a memory reference of the form
147 /// [Reg + Offset], i.e., one with no scale or index, but with a
148 /// displacement. An example is: DWORD PTR [EAX + 4].
149 ///
150 static inline const MachineInstrBuilder &
addRegOffset(const MachineInstrBuilder & MIB,Register Reg,bool isKill,int Offset)151 addRegOffset(const MachineInstrBuilder &MIB, Register Reg, bool isKill,
152 int Offset) {
153 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
154 }
155
156 /// addRegReg - This function is used to add a memory reference of the form:
157 /// [Reg + Reg].
158 static inline const MachineInstrBuilder &
addRegReg(const MachineInstrBuilder & MIB,Register Reg1,bool isKill1,unsigned SubReg1,Register Reg2,bool isKill2,unsigned SubReg2)159 addRegReg(const MachineInstrBuilder &MIB, Register Reg1, bool isKill1,
160 unsigned SubReg1, Register Reg2, bool isKill2, unsigned SubReg2) {
161 return MIB.addReg(Reg1, getKillRegState(isKill1), SubReg1)
162 .addImm(1)
163 .addReg(Reg2, getKillRegState(isKill2), SubReg2)
164 .addImm(0)
165 .addReg(0);
166 }
167
168 static inline const MachineInstrBuilder &
addFullAddress(const MachineInstrBuilder & MIB,const X86AddressMode & AM)169 addFullAddress(const MachineInstrBuilder &MIB,
170 const X86AddressMode &AM) {
171 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
172
173 if (AM.BaseType == X86AddressMode::RegBase)
174 MIB.addReg(AM.Base.Reg);
175 else {
176 assert(AM.BaseType == X86AddressMode::FrameIndexBase);
177 MIB.addFrameIndex(AM.Base.FrameIndex);
178 }
179
180 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
181 if (AM.GV)
182 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
183 else
184 MIB.addImm(AM.Disp);
185
186 return MIB.addReg(0);
187 }
188
189 /// addFrameReference - This function is used to add a reference to the base of
190 /// an abstract object on the stack frame of the current function. This
191 /// reference has base register as the FrameIndex offset until it is resolved.
192 /// This allows a constant offset to be specified as well...
193 ///
194 static inline const MachineInstrBuilder &
195 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
196 MachineInstr *MI = MIB;
197 MachineFunction &MF = *MI->getParent()->getParent();
198 MachineFrameInfo &MFI = MF.getFrameInfo();
199 const MCInstrDesc &MCID = MI->getDesc();
200 auto Flags = MachineMemOperand::MONone;
201 if (MCID.mayLoad())
202 Flags |= MachineMemOperand::MOLoad;
203 if (MCID.mayStore())
204 Flags |= MachineMemOperand::MOStore;
205 MachineMemOperand *MMO = MF.getMachineMemOperand(
206 MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
207 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
208 return addOffset(MIB.addFrameIndex(FI), Offset)
209 .addMemOperand(MMO);
210 }
211
212 /// addConstantPoolReference - This function is used to add a reference to the
213 /// base of a constant value spilled to the per-function constant pool. The
214 /// reference uses the abstract ConstantPoolIndex which is retained until
215 /// either machine code emission or assembly output. In PIC mode on x86-32,
216 /// the GlobalBaseReg parameter can be used to make this a
217 /// GlobalBaseReg-relative reference.
218 ///
219 static inline const MachineInstrBuilder &
addConstantPoolReference(const MachineInstrBuilder & MIB,unsigned CPI,Register GlobalBaseReg,unsigned char OpFlags)220 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
221 Register GlobalBaseReg, unsigned char OpFlags) {
222 //FIXME: factor this
223 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
224 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
225 }
226
227 } // end namespace llvm
228
229 #endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
230