1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010-2013, by Broadcom, Inc. 24 * All Rights Reserved. 25 */ 26 27 /* 28 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. 29 * All rights reserved. 30 */ 31 32 #ifndef _BGE_IMPL_H 33 #define _BGE_IMPL_H 34 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include <sys/types.h> 41 #include <sys/stream.h> 42 #include <sys/strsun.h> 43 #include <sys/strsubr.h> 44 #include <sys/stat.h> 45 #include <sys/pci.h> 46 #include <sys/note.h> 47 #include <sys/modctl.h> 48 #include <sys/crc32.h> 49 #ifdef __sparcv9 50 #include <v9/sys/membar.h> 51 #endif /* __sparcv9 */ 52 #include <sys/kstat.h> 53 #include <sys/ethernet.h> 54 #include <sys/errno.h> 55 #include <sys/dlpi.h> 56 #include <sys/devops.h> 57 #include <sys/debug.h> 58 #include <sys/conf.h> 59 60 #include <netinet/ip6.h> 61 62 #include <inet/common.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/pattr.h> 67 68 #include <sys/disp.h> 69 #include <sys/cmn_err.h> 70 #include <sys/ddi.h> 71 #include <sys/sunddi.h> 72 73 #include <sys/ddifm.h> 74 #include <sys/fm/protocol.h> 75 #include <sys/fm/util.h> 76 #include <sys/fm/io/ddi.h> 77 78 #include <sys/mac_provider.h> 79 #include <sys/mac_ether.h> 80 81 #ifdef __amd64 82 #include <sys/x86_archext.h> 83 #endif 84 85 #ifndef VLAN_TAGSZ 86 #define VLAN_TAGSZ 4 87 #endif 88 89 #define BGE_STR_SIZE 32 90 91 #ifndef OFFSETOF 92 #define OFFSETOF(_s, _f) \ 93 ((uint32_t)((uint8_t *)(&((_s *)0)->_f) - \ 94 (uint8_t *)((uint8_t *) 0))) 95 #endif 96 97 /* 98 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t; 99 * but of course C doesn't provide a way to check this directly. So here 100 * we rely on the fact that the symbol ETHERTYPE_AT was added to the 101 * header file (as a #define, which we *can* test for) at the same time 102 * as the typedef for ether_addr_t ;-! 103 */ 104 #ifndef ETHERTYPE_AT 105 typedef uchar_t ether_addr_t[ETHERADDRL]; 106 #endif /* ETHERTYPE_AT */ 107 108 /* 109 * Reconfiguring the network devices requires the net_config privilege 110 * in Solaris 10+. 111 */ 112 extern int secpolicy_net_config(const cred_t *, boolean_t); 113 114 #include <sys/miiregs.h> /* by fjlite out of intel */ 115 116 #include "bge.h" 117 #include "bge_hw.h" 118 119 /* 120 * Compile-time feature switches ... 121 */ 122 #define BGE_DO_PPIO 0 /* peek/poke ioctls */ 123 #define BGE_RX_SOFTINT 0 /* softint per receive ring */ 124 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */ 125 126 /* 127 * NOTES: 128 * 129 * #defines: 130 * 131 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the 132 * register-set numbers to use for the config space registers 133 * and the operating registers respectively. On an OBP-based 134 * machine, regset 0 refers to CONFIG space, and regset 1 will 135 * be the operating registers in MEMORY space. If an expansion 136 * ROM is fitted, it may appear as a further register set. 137 * 138 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 139 * for the data buffers. The descriptors are always set up 140 * in CONSISTENT mode. 141 * 142 * BGE_HEADROOM defines how much space we'll leave in allocated 143 * mblks before the first valid data byte. This should be chosen 144 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 145 * has been stripped off, the packet data will be 4-byte aligned. 146 * The remaining space can be used by upstream modules to prepend 147 * any headers required. 148 */ 149 150 #define BGE_PCI_CONFIG_RNUMBER 0 151 #define BGE_PCI_OPREGS_RNUMBER 1 152 #define BGE_PCI_APEREGS_RNUMBER 2 153 #define BGE_DMA_MODE DDI_DMA_STREAMING 154 #define BGE_HEADROOM 34 155 156 /* 157 * BGE_HALFTICK is half the period of the cyclic callback (in 158 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s. 159 * Other time values are derived as odd multiples of this value 160 * so that there's little chance of ambiguity w.r.t. which tick 161 * a timeout expires on. 162 * 163 * BGE_PHY_STABLE_TIME is the period for which the contents of the 164 * PHY's status register must remain unchanging before we accept 165 * that the link has come up. [Sometimes the link comes up, only 166 * to go down again within a short time as the autonegotiation 167 * process cycles through various options before finding the best 168 * compatible mode. We don't want to report repeated link up/down 169 * cycles, so we wait until we think it's stable.] 170 * 171 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes 172 * interface. It's much shorter, 'cos the SerDes doesn't show 173 * these effects as much as the copper PHY. 174 * 175 * BGE_LINK_SETTLE_TIME is the period during which we regard link 176 * up/down cycles as an normal event after resetting/reprogramming 177 * the PHY. During this time, link up/down messages are sent to 178 * the log only, not the console. At any other time, link change 179 * events are regarded as unexpected and sent to both console & log. 180 * 181 * These latter two values have no theoretical justification, but 182 * are derived from observations and heuristics - the values below 183 * just seem to work quite well. 184 */ 185 186 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */ 187 #define BGE_CYCLIC_PERIOD (4*BGE_HALFTICK) /* ~1.0s */ 188 #define BGE_CYCLIC_TIMEOUT (drv_usectohz(1000000)) /* ~1.0s */ 189 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */ 190 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */ 191 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */ 192 193 /* 194 * Indices used to identify the different buffer rings internally 195 */ 196 #define BGE_STD_BUFF_RING 0 197 #define BGE_JUMBO_BUFF_RING 1 198 #define BGE_MINI_BUFF_RING 2 199 200 /* 201 * Current implementation limits 202 */ 203 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */ 204 /* for now */ 205 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */ 206 /* for now */ 207 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */ 208 /* for now */ 209 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */ 210 211 /* 212 * Ring/buffer size parameters 213 * 214 * All of the (up to) 16 TX rings & and the corresponding buffers are the 215 * same size. 216 * 217 * Each of the (up to) 3 receive producer (aka buffer) rings is a different 218 * size and has different sized buffers associated with it too. 219 * 220 * The (up to) 16 receive return rings have no buffers associated with them. 221 * The number of slots per receive return ring must be 2048 if the mini 222 * ring is enabled, otherwise it may be 1024. See Broadcom document 223 * 570X-PG102-R page 56. 224 * 225 * Note: only the 5700 supported external memory (and therefore the mini 226 * ring); the 5702/3/4 don't. This driver doesn't support the original 227 * 5700, so we won't ever use the mini ring capability. 228 */ 229 230 #define BGE_SEND_RINGS_DEFAULT 1 231 #define BGE_RECV_RINGS_DEFAULT 1 232 233 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536 234 #define BGE_SEND_BUFF_SIZE_JUMBO 9022 235 #define BGE_SEND_SLOTS_USED 512 236 237 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */ 238 #define BGE_STD_SLOTS_USED 512 239 240 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */ 241 #define BGE_JUMBO_SLOTS_USED 256 242 243 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */ 244 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */ 245 246 #define BGE_RECV_BUFF_SIZE 0 247 #if BGE_MINI_SLOTS_USED > 0 248 #define BGE_RECV_SLOTS_USED 2048 /* required */ 249 #else 250 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */ 251 #endif 252 253 #define BGE_SEND_BUF_NUM 512 254 #define BGE_SEND_BUF_ARRAY 16 255 #define BGE_SEND_BUF_ARRAY_JUMBO 3 256 #define BGE_SEND_BUF_MAX (BGE_SEND_BUF_NUM*BGE_SEND_BUF_ARRAY) 257 258 /* 259 * PCI type. PCI-Express or PCI/PCIX 260 */ 261 #define BGE_PCI 0 262 #define BGE_PCI_E 1 263 #define BGE_PCI_X 2 264 265 /* 266 * Statistic type. There are two type of statistic: 267 * statistic block and statistic registers 268 */ 269 #define BGE_STAT_BLK 1 270 #define BGE_STAT_REG 2 271 272 /* 273 * MTU.for all chipsets ,the default is 1500 ,and some chipsets 274 * support 9k jumbo frames size 275 */ 276 #define BGE_DEFAULT_MTU 1500 277 #define BGE_MAXIMUM_MTU 9000 278 279 /* 280 * Pad the h/w defined status block (which can be up to 80 bytes long) 281 * to a power-of-two boundary 282 */ 283 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t)) 284 285 /* 286 * On platforms which support DVMA, we can simply allocate one big piece 287 * of memory for all the Tx buffers and another for the Rx buffers, and 288 * then carve them up as required. It doesn't matter if they aren't just 289 * one physically contiguous piece each, because both the CPU *and* the 290 * I/O device can see them *as though they were*. 291 * 292 * However, if only physically-addressed DMA is possible, this doesn't 293 * work; we can't expect to get enough contiguously-addressed memory for 294 * all the buffers of each type, so in this case we request a number of 295 * smaller pieces, each still large enough for several buffers but small 296 * enough to fit within "an I/O page" (e.g. 64K). 297 * 298 * The #define below specifies how many pieces of memory are to be used; 299 * 16 has been shown to work on an i86pc architecture but this could be 300 * different on other non-DVMA platforms ... 301 */ 302 #ifdef _DMA_USES_VIRTADDR 303 #define BGE_SPLIT 1 /* no split required */ 304 #else 305 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \ 306 (BGE_RECV_RINGS_USED > 1)) 307 #define BGE_SPLIT 128 /* split 128 ways */ 308 #else 309 #define BGE_SPLIT 16 /* split 16 ways */ 310 #endif 311 #endif /* _DMA_USES_VIRTADDR */ 312 313 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1) 314 315 /* 316 * STREAMS parameters 317 */ 318 #define BGE_IDNUM 0 /* zero seems to work */ 319 #define BGE_LOWAT (256) 320 #define BGE_HIWAT (256*1024) 321 322 /* 323 * Basic data types, for clarity in distinguishing 'numbers' 324 * used for different purposes ... 325 * 326 * A <bge_regno_t> is a register 'address' (offset) in any one of 327 * various address spaces (PCI config space, PCI memory-mapped I/O 328 * register space, MII registers, etc). None of these exceeds 64K, 329 * so we could use a 16-bit representation but pointer-sized objects 330 * are more "natural" in most architectures; they seem to be handled 331 * more efficiently on SPARC and no worse on x86. 332 * 333 * BGE_REGNO_NONE represents the non-existent value in this space. 334 */ 335 typedef uintptr_t bge_regno_t; /* register # (offset) */ 336 #define BGE_REGNO_NONE (~(uintptr_t)0u) 337 338 /* 339 * Describes one chunk of allocated DMA-able memory 340 * 341 * In some cases, this is a single chunk as allocated from the system; 342 * but we also use this structure to represent slices carved off such 343 * a chunk. Even when we don't really need all the information, we 344 * use this structure as a convenient way of correlating the various 345 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 346 * handle+offset, etc). 347 */ 348 typedef struct { 349 ddi_acc_handle_t acc_hdl; /* handle for memory */ 350 void *mem_va; /* CPU VA of memory */ 351 uint32_t nslots; /* number of slots */ 352 uint32_t size; /* size per slot */ 353 size_t alength; /* allocated size */ 354 /* >= product of above */ 355 356 ddi_dma_handle_t dma_hdl; /* DMA handle */ 357 offset_t offset; /* relative to handle */ 358 ddi_dma_cookie_t cookie; /* associated cookie */ 359 uint32_t ncookies; /* must be 1 */ 360 uint32_t token; /* arbitrary identifier */ 361 } dma_area_t; /* 0x50 (80) bytes */ 362 363 typedef struct bge_queue_item { 364 struct bge_queue_item *next; 365 void *item; 366 } bge_queue_item_t; 367 368 typedef struct bge_queue { 369 bge_queue_item_t *head; 370 uint32_t count; 371 kmutex_t *lock; 372 } bge_queue_t; 373 /* 374 * Software version of the Receive Buffer Descriptor 375 * There's one of these for each receive buffer (up to 256/512/1024 per ring). 376 */ 377 typedef struct sw_rbd { 378 dma_area_t pbuf; /* (const) related */ 379 /* buffer area */ 380 } sw_rbd_t; /* 0x50 (80) bytes */ 381 382 /* 383 * Software Receive Buffer (Producer) Ring Control Block 384 * There's one of these for each receiver producer ring (up to 3), 385 * but each holds buffers of a different size. 386 */ 387 typedef struct buff_ring { 388 dma_area_t desc; /* (const) related h/w */ 389 /* descriptor area */ 390 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 391 /* buffer area(s) */ 392 bge_rcb_t hw_rcb; /* (const) image of h/w */ 393 /* RCB, and used to */ 394 struct bge *bgep; /* (const) containing */ 395 /* driver soft state */ 396 /* initialise same */ 397 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 398 /* "consumer index" */ 399 /* (in status block) */ 400 401 /* 402 * The rf_lock must be held when updating the h/w producer index 403 * mailbox register (*chip_mbox_reg), or the s/w producer index 404 * (rf_next). 405 */ 406 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 407 /* index mailbox offset */ 408 kmutex_t rf_lock[1]; /* serialize refill */ 409 uint64_t rf_next; /* next slot to refill */ 410 /* ("producer index") */ 411 412 sw_rbd_t *sw_rbds; /* software descriptors */ 413 void *spare[4]; /* padding */ 414 } buff_ring_t; /* 0x100 (256) bytes */ 415 416 typedef struct bge_multi_mac { 417 int naddr; /* total supported addresses */ 418 int naddrfree; /* free addresses slots */ 419 ether_addr_t mac_addr[MAC_ADDRESS_REGS_MAX]; 420 boolean_t mac_addr_set[MAC_ADDRESS_REGS_MAX]; 421 } bge_multi_mac_t; 422 423 /* 424 * Software Receive (Return) Ring Control Block 425 * There's one of these for each receiver return ring (up to 16). 426 */ 427 typedef struct recv_ring { 428 /* 429 * The elements flagged (const) in the comments below are 430 * set up once during initialiation and thereafter unchanged. 431 */ 432 dma_area_t desc; /* (const) related h/w */ 433 /* descriptor area */ 434 bge_rcb_t hw_rcb; /* (const) image of h/w */ 435 /* RCB, and used to */ 436 /* initialise same */ 437 struct bge *bgep; /* (const) containing */ 438 /* driver soft state */ 439 ddi_softintr_t rx_softint; /* (const) per-ring */ 440 /* receive callback */ 441 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */ 442 /* "producer index" */ 443 /* (in status block) */ 444 /* 445 * The rx_lock must be held when updating the h/w consumer index 446 * mailbox register (*chip_mbox_reg), or the s/w consumer index 447 * (rx_next). 448 */ 449 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */ 450 /* index mailbox offset */ 451 kmutex_t rx_lock[1]; /* serialize receive */ 452 uint64_t rx_next; /* next slot to examine */ 453 454 mac_ring_handle_t ring_handle; 455 mac_group_handle_t ring_group_handle; 456 uint64_t ring_gen_num; 457 bge_rule_info_t *mac_addr_rule; 458 uint8_t mac_addr_val[ETHERADDRL]; 459 int poll_flag; /* Polling flag */ 460 461 /* Per-ring statistics */ 462 uint64_t rx_pkts; /* Received Packets Count */ 463 uint64_t rx_bytes; /* Received Bytes Count */ 464 } recv_ring_t; 465 466 467 /* 468 * Send packet structure 469 */ 470 typedef struct send_pkt { 471 uint16_t vlan_tci; 472 uint32_t pflags; 473 boolean_t tx_ready; 474 bge_queue_item_t *txbuf_item; 475 } send_pkt_t; 476 477 /* 478 * Software version of tx buffer structure 479 */ 480 typedef struct sw_txbuf { 481 dma_area_t buf; 482 uint32_t copy_len; 483 } sw_txbuf_t; 484 485 /* 486 * Software version of the Send Buffer Descriptor 487 * There's one of these for each send buffer (up to 512 per ring) 488 */ 489 typedef struct sw_sbd { 490 dma_area_t desc; /* (const) related h/w */ 491 /* descriptor area */ 492 bge_queue_item_t *pbuf; /* (const) related */ 493 /* buffer area */ 494 } sw_sbd_t; 495 496 /* 497 * Software Send Ring Control Block 498 * There's one of these for each of (up to) 16 send rings 499 */ 500 typedef struct send_ring { 501 /* 502 * The elements flagged (const) in the comments below are 503 * set up once during initialiation and thereafter unchanged. 504 */ 505 dma_area_t desc; /* (const) related h/w */ 506 /* descriptor area */ 507 dma_area_t buf[BGE_SEND_BUF_ARRAY][BGE_SPLIT]; 508 /* buffer area(s) */ 509 bge_rcb_t hw_rcb; /* (const) image of h/w */ 510 /* RCB, and used to */ 511 /* initialise same */ 512 struct bge *bgep; /* (const) containing */ 513 /* driver soft state */ 514 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 515 /* "consumer index" */ 516 /* (in status block) */ 517 518 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 519 /* index mailbox offset */ 520 /* 521 * Tx buffer queue 522 */ 523 bge_queue_t txbuf_queue; 524 bge_queue_t freetxbuf_queue; 525 bge_queue_t *txbuf_push_queue; 526 bge_queue_t *txbuf_pop_queue; 527 kmutex_t txbuf_lock[1]; 528 kmutex_t freetxbuf_lock[1]; 529 bge_queue_item_t *txbuf_head; 530 send_pkt_t *pktp; 531 uint64_t txpkt_next; 532 uint64_t txfill_next; 533 sw_txbuf_t *txbuf; 534 uint32_t tx_buffers; 535 uint32_t tx_buffers_low; 536 uint32_t tx_array_max; 537 uint32_t tx_array; 538 kmutex_t tx_lock[1]; /* serialize h/w update */ 539 /* ("producer index") */ 540 uint64_t tx_next; /* next slot to use */ 541 uint64_t tx_flow; /* # concurrent sends */ 542 uint64_t tx_block; 543 uint64_t tx_nobd; 544 uint64_t tx_nobuf; 545 uint64_t tx_alloc_fail; 546 547 /* 548 * These counters/indexes are manipulated in the transmit 549 * path using atomics rather than mutexes for speed 550 */ 551 uint64_t tx_free; /* # of slots available */ 552 553 /* 554 * The tc_lock must be held while manipulating the s/w consumer 555 * index (tc_next). 556 */ 557 kmutex_t tc_lock[1]; /* serialize recycle */ 558 uint64_t tc_next; /* next slot to recycle */ 559 /* ("consumer index") */ 560 561 sw_sbd_t *sw_sbds; /* software descriptors */ 562 uint64_t mac_resid; /* special per resource id */ 563 uint64_t pushed_bytes; 564 } send_ring_t; /* 0x100 (256) bytes */ 565 566 typedef struct { 567 ether_addr_t addr; /* in canonical form */ 568 uint8_t spare; 569 boolean_t set; /* B_TRUE => valid */ 570 } bge_mac_addr_t; 571 572 /* 573 * The original 5700/01 supported only SEEPROMs. Later chips (5702+) 574 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for 575 * the hardware and a backwards-compatible software access method), and 576 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus 577 * and using a new software access method. 578 * 579 * The access methods for SEEPROM and Flash are generally similar, with 580 * the chip handling the serialisation/deserialisation and handshaking, 581 * but the registers used are different, as are a few details of the 582 * protocol, and the timing, so we have to determine which (if any) is 583 * fitted. 584 * 585 * The value UNKNOWN means just that; we haven't yet tried to determine 586 * the device type. 587 * 588 * The value NONE can indicate either that a real and definite absence of 589 * any NVmem has been detected, or that there may be NVmem but we can't 590 * determine its type, perhaps because the NVconfig pins on the chip have 591 * been wired up incorrectly. In either case, access to the NVmem (if any) 592 * is not supported. 593 */ 594 enum bge_nvmem_type { 595 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */ 596 BGE_NVTYPE_UNKNOWN, /* not yet checked */ 597 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */ 598 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */ 599 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */ 600 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */ 601 }; 602 603 /* 604 * Describes the characteristics of a specific chip 605 * 606 * Note: elements from <businfo> to <latency> are filled in by during 607 * the first phase of chip initialisation (see bge_chip_cfg_init()). 608 * The remaining ones are determined just after the first RESET, in 609 * bge_poll_firmware(). Thereafter, the entire structure is readonly. 610 */ 611 typedef struct { 612 uint32_t asic_rev; /* masked from MHCR */ 613 uint32_t asic_rev_prod_id; /* new revision ID format */ 614 uint32_t businfo; /* from private reg */ 615 uint16_t command; /* saved during attach */ 616 617 uint16_t vendor; /* vendor-id */ 618 uint16_t device; /* device-id */ 619 uint16_t subven; /* subsystem-vendor-id */ 620 uint16_t subdev; /* subsystem-id */ 621 uint8_t revision; /* revision-id */ 622 uint8_t clsize; /* cache-line-size */ 623 uint8_t latency; /* latency-timer */ 624 625 uint8_t flags; 626 uint16_t chip_label; /* numeric part only */ 627 /* (e.g. 5703/5794/etc) */ 628 uint32_t mbuf_base; /* Mbuf pool parameters */ 629 uint32_t mbuf_length; /* depend on chiptype */ 630 uint32_t pci_type; 631 uint32_t statistic_type; 632 uint32_t bge_dma_rwctrl; 633 uint32_t bge_mlcr_default; 634 uint32_t recv_slots; /* receive ring size */ 635 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */ 636 637 uint16_t jumbo_slots; 638 uint16_t ethmax_size; 639 uint16_t snd_buff_size; 640 uint16_t recv_jumbo_size; 641 uint16_t std_buf_size; 642 uint32_t mbuf_hi_water; 643 uint32_t mbuf_lo_water_rmac; 644 uint32_t mbuf_lo_water_rdma; 645 646 uint32_t rx_rings; /* from bge.conf */ 647 uint32_t tx_rings; /* from bge.conf */ 648 uint32_t eee; /* from bge.conf */ 649 uint32_t default_mtu; /* from bge.conf */ 650 651 uint64_t hw_mac_addr; /* from chip register */ 652 bge_mac_addr_t vendor_addr; /* transform of same */ 653 boolean_t msi_enabled; /* default to true */ 654 655 uint32_t rx_ticks_norm; 656 uint32_t rx_count_norm; 657 uint32_t tx_ticks_norm; 658 uint32_t tx_count_norm; 659 uint32_t mask_pci_int; 660 } chip_id_t; 661 662 #define CHIP_FLAG_SUPPORTED 0x80 663 #define CHIP_FLAG_SERDES 0x40 664 #define CHIP_FLAG_PARTIAL_CSUM 0x20 665 #define CHIP_FLAG_NO_JUMBO 0x1 666 667 /* 668 * Collection of physical-layer functions to: 669 * (re)initialise the physical layer 670 * update it to match software settings 671 * check for link status change 672 */ 673 typedef struct { 674 int (*phys_restart)(struct bge *, boolean_t); 675 int (*phys_update)(struct bge *); 676 boolean_t (*phys_check)(struct bge *, boolean_t); 677 } phys_ops_t; 678 679 680 /* 681 * Actual state of the BCM570x chip 682 */ 683 enum bge_chip_state { 684 BGE_CHIP_FAULT = -2, /* fault, need reset */ 685 BGE_CHIP_ERROR, /* error, want reset */ 686 BGE_CHIP_INITIAL, /* Initial state only */ 687 BGE_CHIP_RESET, /* reset, need init */ 688 BGE_CHIP_STOPPED, /* Tx/Rx stopped */ 689 BGE_CHIP_RUNNING /* with interrupts */ 690 }; 691 692 enum bge_mac_state { 693 BGE_MAC_STOPPED = 0, 694 BGE_MAC_STARTED 695 }; 696 697 /* 698 * (Internal) return values from ioctl subroutines 699 */ 700 enum ioc_reply { 701 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 702 IOC_DONE, /* OK, reply sent */ 703 IOC_ACK, /* OK, just send ACK */ 704 IOC_REPLY, /* OK, just send reply */ 705 IOC_RESTART_ACK, /* OK, restart & ACK */ 706 IOC_RESTART_REPLY /* OK, restart & reply */ 707 }; 708 709 /* 710 * (Internal) return values from send_msg subroutines 711 */ 712 enum send_status { 713 SEND_FAIL = -1, /* Not OK */ 714 SEND_KEEP, /* OK, msg queued */ 715 SEND_FREE /* OK, free msg */ 716 }; 717 718 /* 719 * (Internal) enumeration of this driver's kstats 720 */ 721 enum { 722 BGE_KSTAT_RAW = 0, 723 BGE_KSTAT_STATS, 724 BGE_KSTAT_CHIPID, 725 BGE_KSTAT_DRIVER, 726 BGE_KSTAT_PHYS, 727 728 BGE_KSTAT_COUNT 729 }; 730 731 #define BGE_MAX_RESOURCES 255 732 733 /* 734 * Per-instance soft-state structure 735 */ 736 typedef struct bge { 737 /* 738 * These fields are set by attach() and unchanged thereafter ... 739 */ 740 char version[BGE_STR_SIZE]; 741 #define BGE_FW_VER_SIZE 32 742 char fw_version[BGE_FW_VER_SIZE]; 743 dev_info_t *devinfo; /* device instance */ 744 uint32_t pci_bus; /* from "regs" prop */ 745 uint32_t pci_dev; /* from "regs" prop */ 746 uint32_t pci_func; /* from "regs" prop */ 747 mac_handle_t mh; /* mac module handle */ 748 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 749 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 750 void *io_regs; /* mapped registers */ 751 ddi_acc_handle_t ape_handle; /* DDI I/O handle */ 752 void *ape_regs; /* mapped registers */ 753 boolean_t ape_enabled; 754 boolean_t ape_has_ncsi; 755 756 ddi_periodic_t periodic_id; /* periodical callback */ 757 ddi_softintr_t factotum_id; /* factotum callback */ 758 ddi_softintr_t drain_id; /* reschedule callback */ 759 760 ddi_intr_handle_t *htable; /* For array of interrupts */ 761 int intr_type; /* What type of interrupt */ 762 int intr_cnt; /* # of intrs count returned */ 763 uint_t intr_pri; /* Interrupt priority */ 764 int intr_cap; /* Interrupt capabilities */ 765 uint32_t progress; /* attach tracking */ 766 uint32_t debug; /* per-instance debug */ 767 chip_id_t chipid; 768 const phys_ops_t *physops; 769 char ifname[8]; /* "bge0" ... "bge999" */ 770 771 int fm_capabilities; /* FMA capabilities */ 772 773 /* 774 * These structures describe the blocks of memory allocated during 775 * attach(). They remain unchanged thereafter, although the memory 776 * they describe is carved up into various separate regions and may 777 * therefore be described by other structures as well. 778 */ 779 dma_area_t tx_desc; /* transmit descriptors */ 780 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT]; 781 /* receive descriptors */ 782 dma_area_t tx_buff[BGE_SPLIT]; 783 dma_area_t rx_buff[BGE_SPLIT]; 784 785 /* 786 * The memory described by the <dma_area> structures above 787 * is carved up into various pieces, which are described by 788 * the structures below. 789 */ 790 dma_area_t statistics; /* describes hardware */ 791 /* statistics area */ 792 dma_area_t status_block; /* describes hardware */ 793 /* status block */ 794 /* 795 * For the BCM5705/5788/5721/5751/5752/5714 and 5715, 796 * the statistic block is not available,the statistic counter must 797 * be gotten from statistic registers.And bge_statistics_reg_t record 798 * the statistic registers value 799 */ 800 bge_statistics_reg_t *pstats; 801 802 /* 803 * Runtime read-write data starts here ... 804 * 805 * 3 Buffer Rings (std/jumbo/mini) 806 * 16 Receive (Return) Rings 807 * 16 Send Rings 808 * 809 * Note: they're not necessarily all used. 810 */ 811 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */ 812 813 /* may be obsoleted */ 814 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */ 815 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */ 816 817 mac_resource_handle_t macRxResourceHandles[BGE_RECV_RINGS_MAX]; 818 819 /* 820 * Locks: 821 * 822 * Each buffer ring contains its own <rf_lock> which regulates 823 * ring refilling. 824 * 825 * Each receive (return) ring contains its own <rx_lock> which 826 * protects the critical cyclic counters etc. 827 * 828 * Each send ring contains two locks: <tx_lock> for the send-path 829 * protocol data and <tc_lock> for send-buffer recycling. 830 * 831 * Finally <genlock> is a general lock, protecting most other 832 * operational data in the state structure and chip register 833 * accesses. It is acquired by the interrupt handler and 834 * most "mode-control" routines. 835 * 836 * Any of the locks can be acquired singly, but where multiple 837 * locks are acquired, they *must* be in the order: 838 * 839 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock. 840 * 841 * and within any one class of lock the rings must be locked in 842 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc. 843 * 844 * Note: actually I don't believe there's any need to acquire 845 * locks on multiple rings, or even locks of all these classes 846 * concurrently; but I've set out the above order so there is a 847 * clear definition of lock hierarchy in case it's ever needed. 848 * 849 * Note: the combinations of locks that are actually held 850 * concurrently are: 851 * 852 * genlock >>> (bge_chip_interrupt()) 853 * rx_lock[i] >>> (bge_receive()) 854 * rf_lock[n] (bge_refill()) 855 * tc_lock[i] (bge_recycle()) 856 */ 857 kmutex_t genlock[1]; 858 krwlock_t errlock[1]; 859 kmutex_t softintrlock[1]; 860 861 /* 862 * Current Ethernet addresses and multicast hash (bitmap) and 863 * refcount tables, protected by <genlock> 864 */ 865 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX]; 866 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32]; 867 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE]; 868 uint32_t unicst_addr_total; /* total unicst addresses */ 869 uint32_t unicst_addr_avail; 870 /* unused unicst addr slots */ 871 872 /* 873 * Link state data (protected by genlock) 874 */ 875 link_state_t link_state; 876 877 /* 878 * Physical layer: copper only 879 */ 880 bge_regno_t phy_mii_addr; /* should be (const) 1! */ 881 uint16_t phy_gen_status; 882 uint16_t phy_aux_status; 883 884 /* 885 * Physical layer: serdes only 886 */ 887 uint32_t serdes_status; 888 uint32_t serdes_advert; 889 uint32_t serdes_lpadv; 890 891 /* 892 * Driver kstats, protected by <genlock> where necessary 893 */ 894 kstat_t *bge_kstats[BGE_KSTAT_COUNT]; 895 896 /* 897 * Miscellaneous operating variables (protected by genlock) 898 */ 899 uint64_t chip_resets; /* # of chip RESETs */ 900 uint64_t missed_dmas; /* # of missed DMAs */ 901 uint64_t missed_updates; /* # of missed updates */ 902 enum bge_mac_state bge_mac_state; /* definitions above */ 903 enum bge_chip_state bge_chip_state; /* definitions above */ 904 boolean_t send_hw_tcp_csum; 905 boolean_t recv_hw_tcp_csum; 906 boolean_t promisc; 907 boolean_t manual_reset; 908 909 /* 910 * Miscellaneous operating variables (not synchronised) 911 */ 912 uint32_t watchdog; /* watches for Tx stall */ 913 boolean_t bge_intr_running; 914 boolean_t bge_dma_error; 915 boolean_t tx_resched_needed; 916 uint64_t tx_resched; 917 uint32_t factotum_flag; /* softint pending */ 918 uintptr_t pagemask; 919 boolean_t rdma_length_bug_on_5719; 920 921 /* 922 * NDD parameters (protected by genlock) 923 */ 924 caddr_t nd_data_p; 925 926 /* 927 * A flag to prevent excessive config space accesses 928 * on platforms having BCM5714C/15C 929 */ 930 boolean_t lastWriteZeroData; 931 932 /* 933 * Spare space, plus guard element used to check data integrity 934 */ 935 uint64_t spare[5]; 936 uint64_t bge_guard; 937 938 /* 939 * Receive rules configure 940 */ 941 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX]; 942 943 #ifdef BGE_IPMI_ASF 944 boolean_t asf_enabled; 945 boolean_t asf_wordswapped; 946 boolean_t asf_newhandshake; 947 boolean_t asf_pseudostop; 948 949 uint32_t asf_status; 950 timeout_id_t asf_timeout_id; 951 #endif 952 uint32_t param_en_pause:1, 953 param_en_asym_pause:1, 954 param_en_1000hdx:1, 955 param_en_1000fdx:1, 956 param_en_100fdx:1, 957 param_en_100hdx:1, 958 param_en_10fdx:1, 959 param_en_10hdx:1, 960 param_adv_autoneg:1, 961 param_adv_1000fdx:1, 962 param_adv_1000hdx:1, 963 param_adv_100fdx:1, 964 param_adv_100hdx:1, 965 param_adv_10fdx:1, 966 param_adv_10hdx:1, 967 param_lp_autoneg:1, 968 param_lp_pause:1, 969 param_lp_asym_pause:1, 970 param_lp_1000fdx:1, 971 param_lp_1000hdx:1, 972 param_lp_100fdx:1, 973 param_lp_100hdx:1, 974 param_lp_10fdx:1, 975 param_lp_10hdx:1, 976 param_link_up:1, 977 param_link_autoneg:1, 978 param_adv_pause:1, 979 param_adv_asym_pause:1, 980 param_link_rx_pause:1, 981 param_link_tx_pause:1, 982 param_pad_to_32:2; 983 984 uint32_t param_loop_mode; 985 uint32_t param_msi_cnt; 986 uint32_t param_drain_max; 987 uint64_t param_link_speed; 988 link_duplex_t param_link_duplex; 989 uint32_t eee_lpi_wait; 990 991 uint64_t timestamp; 992 } bge_t; 993 994 #define CATC_TRIGGER(bgep, data) bge_reg_put32(bgep, 0x0a00, (data)) 995 996 /* 997 * 'Progress' bit flags ... 998 */ 999 #define PROGRESS_CFG 0x0001 /* config space mapped */ 1000 #define PROGRESS_REGS 0x0002 /* registers mapped */ 1001 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */ 1002 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 1003 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 1004 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */ 1005 /* and mutexen initialised */ 1006 #define PROGRESS_INTR 0x0080 /* Intrs enabled */ 1007 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 1008 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 1009 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 1010 #define PROGRESS_READY 0x8000 /* ready for work */ 1011 1012 1013 /* 1014 * Sync a DMA area described by a dma_area_t 1015 */ 1016 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 1017 (area).offset, (area).alength, (flag))) 1018 1019 /* 1020 * Find the (kernel virtual) address of block of memory 1021 * described by a dma_area_t 1022 */ 1023 #define DMA_VPTR(area) ((area).mem_va) 1024 1025 /* 1026 * Zero a block of memory described by a dma_area_t 1027 */ 1028 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 1029 1030 /* 1031 * Next value of a cyclic index 1032 */ 1033 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0) 1034 1035 /* 1036 * Property lookups 1037 */ 1038 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 1039 DDI_PROP_DONTPASS, (n)) 1040 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 1041 DDI_PROP_DONTPASS, (n), -1) 1042 1043 /* 1044 * Copy an ethernet address 1045 */ 1046 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 1047 1048 /* 1049 * Endian swap 1050 */ 1051 /* BEGIN CSTYLED */ 1052 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 1053 (((x) & 0x00ff0000) >> 8) | \ 1054 (((x) & 0x0000ff00) << 8) | \ 1055 (((x) & 0x000000ff) << 24)) 1056 /* END CSTYLED */ 1057 1058 /* 1059 * Marker value placed at the end of the driver's state 1060 */ 1061 #define BGE_GUARD 0x1919306009031802 1062 1063 /* 1064 * Bit flags in the 'debug' word ... 1065 */ 1066 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */ 1067 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */ 1068 #define BGE_DBG_APE 0x00000004 /* low-level APE access */ 1069 #define BGE_DBG_HPSD 0x00000008 /* low-level HPSD access*/ 1070 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */ 1071 #define BGE_DBG_MII 0x00000020 /* low-level MII access */ 1072 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 1073 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 1074 #define BGE_DBG_RECV 0x00000100 /* receive-side code */ 1075 #define BGE_DBG_SEND 0x00000200 /* packet-send code */ 1076 #define BGE_DBG_INT 0x00001000 /* interrupt handler */ 1077 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */ 1078 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */ 1079 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */ 1080 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */ 1081 #define BGE_DBG_LINK 0x00080000 /* Link status check */ 1082 #define BGE_DBG_INIT 0x00100000 /* initialisation */ 1083 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */ 1084 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */ 1085 #define BGE_DBG_STATS 0x00800000 /* statistics */ 1086 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 1087 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 1088 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 1089 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 1090 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 1091 #define BGE_DBG_NDD 0x20000000 /* NDD operations */ 1092 #define BGE_DBG_MEM 0x40000000 /* memory allocations and chunking */ 1093 1094 /* 1095 * Debugging ... 1096 */ 1097 #ifdef DEBUG 1098 #define BGE_DEBUGGING 1 1099 #else 1100 #define BGE_DEBUGGING 0 1101 #endif /* DEBUG */ 1102 1103 1104 /* 1105 * 'Do-if-debugging' macro. The parameter <command> should be one or more 1106 * C statements (but without the *final* semicolon), which will either be 1107 * compiled inline or completely ignored, depending on the BGE_DEBUGGING 1108 * compile-time flag. 1109 * 1110 * You should get a compile-time error (at least on a DEBUG build) if 1111 * your statement isn't actually a statement, rather than unexpected 1112 * run-time behaviour caused by unintended matching of if-then-elses etc. 1113 * 1114 * Note that the BGE_DDB() macro itself can only be used as a statement, 1115 * not an expression, and should always be followed by a semicolon. 1116 */ 1117 #if BGE_DEBUGGING 1118 #define BGE_DDB(command) do { \ 1119 { command; } \ 1120 _NOTE(CONSTANTCONDITION) \ 1121 } while (0) 1122 #else /* BGE_DEBUGGING */ 1123 #define BGE_DDB(command) do { \ 1124 { _NOTE(EMPTY); } \ 1125 _NOTE(CONSTANTCONDITION) \ 1126 } while (0) 1127 #endif /* BGE_DEBUGGING */ 1128 1129 /* 1130 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 1131 * These provide the primitive conditional-call capability required. 1132 * Note: the parameter <args> is a parenthesised list of the actual 1133 * printf-style arguments to be passed to the debug function ... 1134 */ 1135 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args) 1136 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args) 1137 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args) 1138 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args) 1139 1140 #define DEVNAME(_sc) ((_sc)->ifname) 1141 #define DPRINTF(f, ...) do { cmn_err(CE_NOTE, (f), __VA_ARGS__); } while (0) 1142 1143 /* 1144 * Conditional-print macros. 1145 * 1146 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values 1147 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G' 1148 * versions look at the Global debug flag word (bge_debug); the non-G 1149 * versions look in the per-instance data (bgep->debug) and so require a 1150 * variable called 'bgep' to be in scope (and initialised!) before use. 1151 * 1152 * You could redefine BGE_TRC too if you really need two different 1153 * flavours of debugging output in the same area of code, but I don't 1154 * really recommend it. 1155 * 1156 * Note: the parameter <args> is a parenthesised list of the actual 1157 * arguments to be passed to the debug function, usually a printf-style 1158 * format string and corresponding values to be formatted. 1159 */ 1160 1161 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */ 1162 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args) 1163 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args) 1164 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args) 1165 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args) 1166 1167 /* 1168 * Debug-only action macros 1169 */ 1170 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s)) 1171 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep)) 1172 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep)) 1173 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args) 1174 #define BGE_REPORT(args) BGE_DDB(bge_log args) 1175 1176 /* 1177 * Inter-source-file linkage ... 1178 */ 1179 1180 /* bge_chip.c */ 1181 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1182 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value); 1183 uint16_t bge_phydsp_read(bge_t *bgep, bge_regno_t regno); 1184 void bge_phydsp_write(bge_t *bgep, bge_regno_t regno, uint16_t value); 1185 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 1186 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value); 1187 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1188 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1189 uint32_t bge_ape_get32(bge_t *bgep, bge_regno_t regno); 1190 void bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t value); 1191 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value); 1192 void bge_ape_lock_init(bge_t *bgep); 1193 int bge_ape_scratchpad_read(bge_t *bgep, uint32_t *data, uint32_t base_off, uint32_t lenToRead); 1194 int bge_ape_scratchpad_write(bge_t *bgep, uint32_t dstoff, uint32_t *data, uint32_t lenToWrite); 1195 int bge_nvmem_read32(bge_t *bgep, bge_regno_t addr, uint32_t *dp); 1196 int bge_nvmem_write32(bge_t *bgep, bge_regno_t addr, uint32_t *dp); 1197 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 1198 int bge_chip_id_init(bge_t *bgep); 1199 void bge_chip_coalesce_update(bge_t *bgep); 1200 int bge_chip_start(bge_t *bgep, boolean_t reset_phy); 1201 void bge_chip_stop(bge_t *bgep, boolean_t fault); 1202 #ifndef __sparc 1203 void bge_chip_stop_nonblocking(bge_t *bgep); 1204 #endif 1205 #ifdef BGE_IPMI_ASF 1206 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 1207 #pragma inline(bge_nic_put32) 1208 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr); 1209 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 1210 #pragma inline(bge_ind_put32) 1211 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 1212 #pragma inline(bge_ind_get32) 1213 void bge_asf_update_status(bge_t *bgep); 1214 void bge_asf_heartbeat(void *bgep); 1215 void bge_asf_stop_timer(bge_t *bgep); 1216 void bge_asf_get_config(bge_t *bgep); 1217 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode); 1218 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode); 1219 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode); 1220 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 1221 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 1222 #else 1223 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 1224 int bge_chip_sync(bge_t *bgep); 1225 #endif 1226 void bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag); 1227 extern mblk_t *bge_poll_ring(void *, int); 1228 uint_t bge_chip_factotum(caddr_t arg); 1229 void bge_chip_cyclic(void *arg); 1230 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1231 struct iocblk *iocp); 1232 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 1233 void bge_sync_mac_modes(bge_t *); 1234 extern uint32_t bge_rx_ticks_norm; 1235 extern uint32_t bge_tx_ticks_norm; 1236 extern uint32_t bge_rx_count_norm; 1237 extern uint32_t bge_tx_count_norm; 1238 extern boolean_t bge_relaxed_ordering; 1239 1240 void bge_chip_msi_trig(bge_t *bgep); 1241 1242 /* bge_kstats.c */ 1243 void bge_init_kstats(bge_t *bgep, int instance); 1244 void bge_fini_kstats(bge_t *bgep); 1245 int bge_m_stat(void *arg, uint_t stat, uint64_t *val); 1246 int bge_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1247 1248 /* bge_log.c */ 1249 #if BGE_DEBUGGING 1250 void (*bge_db(bge_t *bgep))(const char *fmt, ...); 1251 void (*bge_gdb(void))(const char *fmt, ...); 1252 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg); 1253 void bge_dbg_enter(bge_t *bgep, const char *msg); 1254 #endif /* BGE_DEBUGGING */ 1255 void bge_problem(bge_t *bgep, const char *fmt, ...); 1256 void bge_log(bge_t *bgep, const char *fmt, ...); 1257 void bge_error(bge_t *bgep, const char *fmt, ...); 1258 void bge_fm_ereport(bge_t *bgep, char *detail); 1259 extern kmutex_t bge_log_mutex[1]; 1260 extern uint32_t bge_debug; 1261 1262 /* bge_main.c */ 1263 int bge_restart(bge_t *bgep, boolean_t reset_phy); 1264 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle); 1265 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle); 1266 void bge_init_rings(bge_t *bgep); 1267 void bge_fini_rings(bge_t *bgep); 1268 bge_queue_item_t *bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp); 1269 void bge_free_txbuf_arrays(send_ring_t *srp); 1270 int bge_alloc_bufs(bge_t *bgep); 1271 void bge_free_bufs(bge_t *bgep); 1272 void bge_intr_enable(bge_t *bgep); 1273 void bge_intr_disable(bge_t *bgep); 1274 int bge_reprogram(bge_t *); 1275 1276 /* bge_mii.c */ 1277 void bge_eee_init(bge_t *bgep); 1278 void bge_eee_enable(bge_t * bgep); 1279 int bge_phys_init(bge_t *bgep); 1280 void bge_phys_reset(bge_t *bgep); 1281 int bge_phys_idle(bge_t *bgep); 1282 int bge_phys_update(bge_t *bgep); 1283 boolean_t bge_phys_check(bge_t *bgep); 1284 1285 /* bge_ndd.c */ 1286 int bge_nd_init(bge_t *bgep); 1287 1288 /* bge_recv.c */ 1289 void bge_receive(bge_t *bgep, bge_status_t *bsp); 1290 1291 /* bge_send.c */ 1292 mblk_t *bge_m_tx(void *arg, mblk_t *mp); 1293 mblk_t *bge_ring_tx(void *arg, mblk_t *mp); 1294 boolean_t bge_recycle(bge_t *bgep, bge_status_t *bsp); 1295 uint_t bge_send_drain(caddr_t arg); 1296 1297 /* bge_atomic.c */ 1298 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n); 1299 void bge_atomic_renounce(uint64_t *count_p, uint64_t n); 1300 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit); 1301 uint64_t bge_atomic_next(uint64_t *sp, uint64_t limit); 1302 void bge_atomic_sub64(uint64_t *count_p, uint64_t n); 1303 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits); 1304 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count); 1305 1306 /* bge_mii_5906.c */ 1307 void bge_adj_volt_5906(bge_t *bgep); 1308 1309 /* 1310 * Reset type 1311 */ 1312 #define BGE_SHUTDOWN_RESET 0 1313 #define BGE_INIT_RESET 1 1314 #define BGE_SUSPEND_RESET 2 1315 1316 /* For asf_status */ 1317 #define ASF_STAT_NONE 0 1318 #define ASF_STAT_STOP 1 1319 #define ASF_STAT_RUN 2 1320 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */ 1321 1322 /* ASF modes for bge_reset() and bge_chip_reset() */ 1323 #define ASF_MODE_NONE 0 /* don't launch asf */ 1324 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */ 1325 #define ASF_MODE_INIT 2 /* asf init mode */ 1326 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */ 1327 #define ASF_MODE_POST_INIT 4 /* only do post-init */ 1328 1329 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000 1330 1331 #ifdef __cplusplus 1332 } 1333 #endif 1334 1335 #endif /* _BGE_IMPL_H */ 1336