1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn30/dcn30_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "basics/conversion.h"
35 #include "dcn20/dcn20_resource.h"
36
37 #include "dcn30_resource.h"
38
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn30/dcn30_hubbub.h"
41 #include "dcn30/dcn30_mpc.h"
42 #include "dcn30/dcn30_hubp.h"
43 #include "irq/dcn30/irq_service_dcn30.h"
44 #include "dcn30/dcn30_dpp.h"
45 #include "dcn30/dcn30_optc.h"
46 #include "dcn20/dcn20_hwseq.h"
47 #include "dcn30/dcn30_hwseq.h"
48 #include "dce110/dce110_hwseq.h"
49 #include "dcn30/dcn30_opp.h"
50 #include "dcn20/dcn20_dsc.h"
51 #include "dcn30/dcn30_vpg.h"
52 #include "dcn30/dcn30_afmt.h"
53 #include "dcn30/dcn30_dio_stream_encoder.h"
54 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
55 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
56 #include "dcn30/dcn30_dio_link_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "clk_mgr.h"
61 #include "dio/virtual/virtual_stream_encoder.h"
62 #include "dce110/dce110_resource.h"
63 #include "dml/display_mode_vba.h"
64 #include "dcn30/dcn30_dccg.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dio/dcn10/dcn10_dio.h"
67 #include "link_service.h"
68 #include "dce/dce_panel_cntl.h"
69
70 #include "dcn30/dcn30_dwb.h"
71 #include "dcn30/dcn30_mmhubbub.h"
72
73 #include "sienna_cichlid_ip_offset.h"
74 #include "dcn/dcn_3_0_0_offset.h"
75 #include "dcn/dcn_3_0_0_sh_mask.h"
76
77 #include "nbio/nbio_7_4_offset.h"
78
79 #include "dpcs/dpcs_3_0_0_offset.h"
80 #include "dpcs/dpcs_3_0_0_sh_mask.h"
81
82 #include "mmhub/mmhub_2_0_0_offset.h"
83 #include "mmhub/mmhub_2_0_0_sh_mask.h"
84
85 #include "reg_helper.h"
86 #include "dce/dmub_abm.h"
87 #include "dce/dmub_psr.h"
88 #include "dce/dce_aux.h"
89 #include "dce/dce_i2c.h"
90
91 #include "dml/dcn30/dcn30_fpu.h"
92 #include "dml/dcn30/display_mode_vba_30.h"
93 #include "vm_helper.h"
94 #include "dcn20/dcn20_vmid.h"
95 #include "amdgpu_socbb.h"
96 #include "dc_dmub_srv.h"
97
98 #define DC_LOGGER \
99 dc->ctx->logger
100 #define DC_LOGGER_INIT(logger)
101
102 enum dcn30_clk_src_array_id {
103 DCN30_CLK_SRC_PLL0,
104 DCN30_CLK_SRC_PLL1,
105 DCN30_CLK_SRC_PLL2,
106 DCN30_CLK_SRC_PLL3,
107 DCN30_CLK_SRC_PLL4,
108 DCN30_CLK_SRC_PLL5,
109 DCN30_CLK_SRC_TOTAL
110 };
111
112 /* begin *********************
113 * macros to expend register list macro defined in HW object header file
114 */
115
116 /* DCN */
117 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
118
119 #define BASE(seg) BASE_INNER(seg)
120
121 #define SR(reg_name)\
122 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
123 mm ## reg_name
124
125 #define SRI(reg_name, block, id)\
126 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 mm ## block ## id ## _ ## reg_name
128
129 #define SRI2(reg_name, block, id)\
130 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
131 mm ## reg_name
132
133 #define SRIR(var_name, reg_name, block, id)\
134 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
136
137 #define SRII(reg_name, block, id)\
138 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 mm ## block ## id ## _ ## reg_name
140
141 #define SRII_MPC_RMU(reg_name, block, id)\
142 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## reg_name
144
145 #define SRII_DWB(reg_name, temp_name, block, id)\
146 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## temp_name
148
149 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
150 .field_name = reg_name ## __ ## field_name ## post_fix
151
152 #define DCCG_SRII(reg_name, block, id)\
153 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 mm ## block ## id ## _ ## reg_name
155
156 #define VUPDATE_SRII(reg_name, block, id)\
157 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
158 mm ## reg_name ## _ ## block ## id
159
160 /* NBIO */
161 #define NBIO_BASE_INNER(seg) \
162 NBIO_BASE__INST0_SEG ## seg
163
164 #define NBIO_BASE(seg) \
165 NBIO_BASE_INNER(seg)
166
167 #define NBIO_SR(reg_name)\
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
169 mm ## reg_name
170
171 /* MMHUB */
172 #define MMHUB_BASE_INNER(seg) \
173 MMHUB_BASE__INST0_SEG ## seg
174
175 #define MMHUB_BASE(seg) \
176 MMHUB_BASE_INNER(seg)
177
178 #define MMHUB_SR(reg_name)\
179 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
180 mmMM ## reg_name
181
182 /* CLOCK */
183 #define CLK_BASE_INNER(seg) \
184 CLK_BASE__INST0_SEG ## seg
185
186 #define CLK_BASE(seg) \
187 CLK_BASE_INNER(seg)
188
189 #define CLK_SRI(reg_name, block, inst)\
190 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
191 mm ## block ## _ ## inst ## _ ## reg_name
192
193
194 static const struct bios_registers bios_regs = {
195 NBIO_SR(BIOS_SCRATCH_3),
196 NBIO_SR(BIOS_SCRATCH_6)
197 };
198
199 #define clk_src_regs(index, pllid)\
200 [index] = {\
201 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
202 }
203
204 static const struct dce110_clk_src_regs clk_src_regs[] = {
205 clk_src_regs(0, A),
206 clk_src_regs(1, B),
207 clk_src_regs(2, C),
208 clk_src_regs(3, D),
209 clk_src_regs(4, E),
210 clk_src_regs(5, F)
211 };
212
213 static const struct dce110_clk_src_shift cs_shift = {
214 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
215 };
216
217 static const struct dce110_clk_src_mask cs_mask = {
218 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
219 };
220
221 #define abm_regs(id)\
222 [id] = {\
223 ABM_DCN30_REG_LIST(id)\
224 }
225
226 static const struct dce_abm_registers abm_regs[] = {
227 abm_regs(0),
228 abm_regs(1),
229 abm_regs(2),
230 abm_regs(3),
231 abm_regs(4),
232 abm_regs(5),
233 };
234
235 static const struct dce_abm_shift abm_shift = {
236 ABM_MASK_SH_LIST_DCN30(__SHIFT)
237 };
238
239 static const struct dce_abm_mask abm_mask = {
240 ABM_MASK_SH_LIST_DCN30(_MASK)
241 };
242
243
244
245 #define audio_regs(id)\
246 [id] = {\
247 AUD_COMMON_REG_LIST(id)\
248 }
249
250 static const struct dce_audio_registers audio_regs[] = {
251 audio_regs(0),
252 audio_regs(1),
253 audio_regs(2),
254 audio_regs(3),
255 audio_regs(4),
256 audio_regs(5),
257 audio_regs(6)
258 };
259
260 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
262 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
263 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
264
265 static const struct dce_audio_shift audio_shift = {
266 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
267 };
268
269 static const struct dce_audio_mask audio_mask = {
270 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
271 };
272
273 #define vpg_regs(id)\
274 [id] = {\
275 VPG_DCN3_REG_LIST(id)\
276 }
277
278 static const struct dcn30_vpg_registers vpg_regs[] = {
279 vpg_regs(0),
280 vpg_regs(1),
281 vpg_regs(2),
282 vpg_regs(3),
283 vpg_regs(4),
284 vpg_regs(5),
285 vpg_regs(6),
286 };
287
288 static const struct dcn30_vpg_shift vpg_shift = {
289 DCN3_VPG_MASK_SH_LIST(__SHIFT)
290 };
291
292 static const struct dcn30_vpg_mask vpg_mask = {
293 DCN3_VPG_MASK_SH_LIST(_MASK)
294 };
295
296 #define afmt_regs(id)\
297 [id] = {\
298 AFMT_DCN3_REG_LIST(id)\
299 }
300
301 static const struct dcn30_afmt_registers afmt_regs[] = {
302 afmt_regs(0),
303 afmt_regs(1),
304 afmt_regs(2),
305 afmt_regs(3),
306 afmt_regs(4),
307 afmt_regs(5),
308 afmt_regs(6),
309 };
310
311 static const struct dcn30_afmt_shift afmt_shift = {
312 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
313 };
314
315 static const struct dcn30_afmt_mask afmt_mask = {
316 DCN3_AFMT_MASK_SH_LIST(_MASK)
317 };
318
319 #define stream_enc_regs(id)\
320 [id] = {\
321 SE_DCN3_REG_LIST(id)\
322 }
323
324 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
325 stream_enc_regs(0),
326 stream_enc_regs(1),
327 stream_enc_regs(2),
328 stream_enc_regs(3),
329 stream_enc_regs(4),
330 stream_enc_regs(5)
331 };
332
333 static const struct dcn10_stream_encoder_shift se_shift = {
334 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
335 };
336
337 static const struct dcn10_stream_encoder_mask se_mask = {
338 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
339 };
340
341
342 #define aux_regs(id)\
343 [id] = {\
344 DCN2_AUX_REG_LIST(id)\
345 }
346
347 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
348 aux_regs(0),
349 aux_regs(1),
350 aux_regs(2),
351 aux_regs(3),
352 aux_regs(4),
353 aux_regs(5)
354 };
355
356 #define hpd_regs(id)\
357 [id] = {\
358 HPD_REG_LIST(id)\
359 }
360
361 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
362 hpd_regs(0),
363 hpd_regs(1),
364 hpd_regs(2),
365 hpd_regs(3),
366 hpd_regs(4),
367 hpd_regs(5)
368 };
369
370 #define link_regs(id, phyid)\
371 [id] = {\
372 LE_DCN3_REG_LIST(id), \
373 UNIPHY_DCN2_REG_LIST(phyid), \
374 DPCS_DCN2_REG_LIST(id), \
375 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
376 }
377
378 static const struct dce110_aux_registers_shift aux_shift = {
379 DCN_AUX_MASK_SH_LIST(__SHIFT)
380 };
381
382 static const struct dce110_aux_registers_mask aux_mask = {
383 DCN_AUX_MASK_SH_LIST(_MASK)
384 };
385
386 static const struct dcn10_link_enc_registers link_enc_regs[] = {
387 link_regs(0, A),
388 link_regs(1, B),
389 link_regs(2, C),
390 link_regs(3, D),
391 link_regs(4, E),
392 link_regs(5, F)
393 };
394
395 static const struct dcn10_link_enc_shift le_shift = {
396 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
397 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
398 };
399
400 static const struct dcn10_link_enc_mask le_mask = {
401 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
402 DPCS_DCN2_MASK_SH_LIST(_MASK)
403 };
404
405
406 #define hpo_frl_stream_encoder_reg_list(id)\
407 [id] = {\
408 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST(id)\
409 }
410
411 #define hpo_frl_stream_encoder_dme_reg_list(id)\
412 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST(id, 6)
413
414
415 static const struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[] = {
416 hpo_frl_stream_encoder_reg_list(0),
417 hpo_frl_stream_encoder_dme_reg_list(6),
418 };
419
420 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
421 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
422 };
423
424 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
425 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
426 };
427
428 #define hpo_frl_link_encoder_reg_list(id)\
429 [id] = {\
430 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST(id)\
431 }
432
433 static const struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[] = {
434 hpo_frl_link_encoder_reg_list(0),
435 };
436
437 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
438 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
439 };
440
441 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
442 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
443 };
444
445 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
446 { DCN_PANEL_CNTL_REG_LIST() }
447 };
448
449 static const struct dce_panel_cntl_shift panel_cntl_shift = {
450 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
451 };
452
453 static const struct dce_panel_cntl_mask panel_cntl_mask = {
454 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
455 };
456
457 #define dpp_regs(id)\
458 [id] = {\
459 DPP_REG_LIST_DCN30(id),\
460 }
461
462 static const struct dcn3_dpp_registers dpp_regs[] = {
463 dpp_regs(0),
464 dpp_regs(1),
465 dpp_regs(2),
466 dpp_regs(3),
467 dpp_regs(4),
468 dpp_regs(5),
469 };
470
471 static const struct dcn3_dpp_shift tf_shift = {
472 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
473 };
474
475 static const struct dcn3_dpp_mask tf_mask = {
476 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
477 };
478
479 #define opp_regs(id)\
480 [id] = {\
481 OPP_REG_LIST_DCN30(id),\
482 }
483
484 static const struct dcn20_opp_registers opp_regs[] = {
485 opp_regs(0),
486 opp_regs(1),
487 opp_regs(2),
488 opp_regs(3),
489 opp_regs(4),
490 opp_regs(5)
491 };
492
493 static const struct dcn20_opp_shift opp_shift = {
494 OPP_MASK_SH_LIST_DCN20(__SHIFT)
495 };
496
497 static const struct dcn20_opp_mask opp_mask = {
498 OPP_MASK_SH_LIST_DCN20(_MASK)
499 };
500
501 #define aux_engine_regs(id)\
502 [id] = {\
503 AUX_COMMON_REG_LIST0(id), \
504 .AUXN_IMPCAL = 0, \
505 .AUXP_IMPCAL = 0, \
506 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
507 }
508
509 static const struct dce110_aux_registers aux_engine_regs[] = {
510 aux_engine_regs(0),
511 aux_engine_regs(1),
512 aux_engine_regs(2),
513 aux_engine_regs(3),
514 aux_engine_regs(4),
515 aux_engine_regs(5)
516 };
517
518 #define dwbc_regs_dcn3(id)\
519 [id] = {\
520 DWBC_COMMON_REG_LIST_DCN30(id),\
521 }
522
523 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
524 dwbc_regs_dcn3(0),
525 };
526
527 static const struct dcn30_dwbc_shift dwbc30_shift = {
528 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
529 };
530
531 static const struct dcn30_dwbc_mask dwbc30_mask = {
532 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
533 };
534
535 #define mcif_wb_regs_dcn3(id)\
536 [id] = {\
537 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
538 }
539
540 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
541 mcif_wb_regs_dcn3(0)
542 };
543
544 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
545 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
546 };
547
548 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
549 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
550 };
551
552 #define dsc_regsDCN20(id)\
553 [id] = {\
554 DSC_REG_LIST_DCN20(id)\
555 }
556
557 static const struct dcn20_dsc_registers dsc_regs[] = {
558 dsc_regsDCN20(0),
559 dsc_regsDCN20(1),
560 dsc_regsDCN20(2),
561 dsc_regsDCN20(3),
562 dsc_regsDCN20(4),
563 dsc_regsDCN20(5)
564 };
565
566 static const struct dcn20_dsc_shift dsc_shift = {
567 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
568 };
569
570 static const struct dcn20_dsc_mask dsc_mask = {
571 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
572 };
573
574 static const struct dcn30_mpc_registers mpc_regs = {
575 MPC_REG_LIST_DCN3_0(0),
576 MPC_REG_LIST_DCN3_0(1),
577 MPC_REG_LIST_DCN3_0(2),
578 MPC_REG_LIST_DCN3_0(3),
579 MPC_REG_LIST_DCN3_0(4),
580 MPC_REG_LIST_DCN3_0(5),
581 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
582 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
583 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
584 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
585 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
586 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
587 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
588 MPC_RMU_REG_LIST_DCN3AG(0),
589 MPC_RMU_REG_LIST_DCN3AG(1),
590 MPC_RMU_REG_LIST_DCN3AG(2),
591 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
592 };
593
594 static const struct dcn30_mpc_shift mpc_shift = {
595 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
596 };
597
598 static const struct dcn30_mpc_mask mpc_mask = {
599 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
600 };
601
602 #define optc_regs(id)\
603 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
604
605
606 static const struct dcn_optc_registers optc_regs[] = {
607 optc_regs(0),
608 optc_regs(1),
609 optc_regs(2),
610 optc_regs(3),
611 optc_regs(4),
612 optc_regs(5)
613 };
614
615 static const struct dcn_optc_shift optc_shift = {
616 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
617 };
618
619 static const struct dcn_optc_mask optc_mask = {
620 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
621 };
622
623 #define hubp_regs(id)\
624 [id] = {\
625 HUBP_REG_LIST_DCN30(id)\
626 }
627
628 static const struct dcn_hubp2_registers hubp_regs[] = {
629 hubp_regs(0),
630 hubp_regs(1),
631 hubp_regs(2),
632 hubp_regs(3),
633 hubp_regs(4),
634 hubp_regs(5)
635 };
636
637 static const struct dcn_hubp2_shift hubp_shift = {
638 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
639 };
640
641 static const struct dcn_hubp2_mask hubp_mask = {
642 HUBP_MASK_SH_LIST_DCN30(_MASK)
643 };
644
645 static const struct dcn_hubbub_registers hubbub_reg = {
646 HUBBUB_REG_LIST_DCN30(0)
647 };
648
649 static const struct dcn_hubbub_shift hubbub_shift = {
650 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
651 };
652
653 static const struct dcn_hubbub_mask hubbub_mask = {
654 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
655 };
656
657 static const struct dccg_registers dccg_regs = {
658 DCCG_REG_LIST_DCN30()
659 };
660
661 static const struct dccg_shift dccg_shift = {
662 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
663 };
664
665 static const struct dccg_mask dccg_mask = {
666 DCCG_MASK_SH_LIST_DCN3(_MASK)
667 };
668
669 static const struct dce_hwseq_registers hwseq_reg = {
670 HWSEQ_DCN30_REG_LIST()
671 };
672
673 static const struct dce_hwseq_shift hwseq_shift = {
674 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
675 };
676
677 static const struct dce_hwseq_mask hwseq_mask = {
678 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
679 };
680 #define vmid_regs(id)\
681 [id] = {\
682 DCN20_VMID_REG_LIST(id)\
683 }
684
685 static const struct dcn_vmid_registers vmid_regs[] = {
686 vmid_regs(0),
687 vmid_regs(1),
688 vmid_regs(2),
689 vmid_regs(3),
690 vmid_regs(4),
691 vmid_regs(5),
692 vmid_regs(6),
693 vmid_regs(7),
694 vmid_regs(8),
695 vmid_regs(9),
696 vmid_regs(10),
697 vmid_regs(11),
698 vmid_regs(12),
699 vmid_regs(13),
700 vmid_regs(14),
701 vmid_regs(15)
702 };
703
704 static const struct dcn20_vmid_shift vmid_shifts = {
705 DCN20_VMID_MASK_SH_LIST(__SHIFT)
706 };
707
708 static const struct dcn20_vmid_mask vmid_masks = {
709 DCN20_VMID_MASK_SH_LIST(_MASK)
710 };
711
712 static const struct resource_caps res_cap_dcn3 = {
713 .num_timing_generator = 6,
714 .num_opp = 6,
715 .num_video_plane = 6,
716 .num_audio = 6,
717 .num_stream_encoder = 6,
718 .num_hpo_frl = 1,
719 .num_pll = 6,
720 .num_dwb = 1,
721 .num_ddc = 6,
722 .num_vmid = 16,
723 .num_mpc_3dlut = 3,
724 .num_dsc = 6,
725 };
726
727 static const struct dc_plane_cap plane_cap = {
728 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
729 .per_pixel_alpha = true,
730
731 .pixel_format_support = {
732 .argb8888 = true,
733 .nv12 = true,
734 .fp16 = true,
735 .p010 = true,
736 .ayuv = false,
737 },
738
739 .max_upscale_factor = {
740 .argb8888 = 16000,
741 .nv12 = 16000,
742 .fp16 = 16000
743 },
744
745 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
746 .max_downscale_factor = {
747 .argb8888 = 167,
748 .nv12 = 167,
749 .fp16 = 167
750 },
751 16,
752 16
753 };
754
755 static const struct dc_debug_options debug_defaults_drv = {
756 .limit_ffe = 3,
757 .disable_dmcu = true, //No DMCU on DCN30
758 .force_abm_enable = false,
759 .clock_trace = true,
760 .disable_pplib_clock_request = true,
761 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
762 .force_single_disp_pipe_split = false,
763 .disable_dcc = DCC_ENABLE,
764 .vsr_support = true,
765 .performance_trace = false,
766 .max_downscale_src_width = 7680,/*upto 8K*/
767 .disable_pplib_wm_range = false,
768 .scl_reset_length10 = true,
769 .sanity_checks = false,
770 .underflow_assert_delay_us = 0xFFFFFFFF,
771 .dwb_fi_phase = -1, // -1 = disable,
772 .dmub_command_table = true,
773 .use_max_lb = true,
774 .exit_idle_opt_for_cursor_updates = true,
775 .using_dml2 = false,
776 };
777
778 static const struct dc_check_config config_defaults = {
779 .enable_legacy_fast_update = false,
780 };
781
782 static const struct dc_panel_config panel_config_defaults = {
783 .psr = {
784 .disable_psr = false,
785 .disallow_psrsu = false,
786 .disallow_replay = false,
787 },
788 };
789
dcn30_dpp_destroy(struct dpp ** dpp)790 static void dcn30_dpp_destroy(struct dpp **dpp)
791 {
792 kfree(TO_DCN20_DPP(*dpp));
793 *dpp = NULL;
794 }
795
dcn30_dpp_create(struct dc_context * ctx,uint32_t inst)796 static struct dpp *dcn30_dpp_create(
797 struct dc_context *ctx,
798 uint32_t inst)
799 {
800 struct dcn3_dpp *dpp =
801 kzalloc_obj(struct dcn3_dpp);
802
803 if (!dpp)
804 return NULL;
805
806 if (dpp3_construct(dpp, ctx, inst,
807 &dpp_regs[inst], &tf_shift, &tf_mask))
808 return &dpp->base;
809
810 BREAK_TO_DEBUGGER();
811 kfree(dpp);
812 return NULL;
813 }
814
dcn30_opp_create(struct dc_context * ctx,uint32_t inst)815 static struct output_pixel_processor *dcn30_opp_create(
816 struct dc_context *ctx, uint32_t inst)
817 {
818 struct dcn20_opp *opp =
819 kzalloc_obj(struct dcn20_opp);
820
821 if (!opp) {
822 BREAK_TO_DEBUGGER();
823 return NULL;
824 }
825
826 dcn20_opp_construct(opp, ctx, inst,
827 &opp_regs[inst], &opp_shift, &opp_mask);
828 return &opp->base;
829 }
830
dcn30_aux_engine_create(struct dc_context * ctx,uint32_t inst)831 static struct dce_aux *dcn30_aux_engine_create(
832 struct dc_context *ctx,
833 uint32_t inst)
834 {
835 struct aux_engine_dce110 *aux_engine =
836 kzalloc_obj(struct aux_engine_dce110);
837
838 if (!aux_engine)
839 return NULL;
840
841 dce110_aux_engine_construct(aux_engine, ctx, inst,
842 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
843 &aux_engine_regs[inst],
844 &aux_mask,
845 &aux_shift,
846 ctx->dc->caps.extended_aux_timeout_support);
847
848 return &aux_engine->base;
849 }
850
851 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
852
853 static const struct dce_i2c_registers i2c_hw_regs[] = {
854 i2c_inst_regs(1),
855 i2c_inst_regs(2),
856 i2c_inst_regs(3),
857 i2c_inst_regs(4),
858 i2c_inst_regs(5),
859 i2c_inst_regs(6),
860 };
861
862 static const struct dce_i2c_shift i2c_shifts = {
863 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
864 };
865
866 static const struct dce_i2c_mask i2c_masks = {
867 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
868 };
869
dcn30_i2c_hw_create(struct dc_context * ctx,uint32_t inst)870 static struct dce_i2c_hw *dcn30_i2c_hw_create(
871 struct dc_context *ctx,
872 uint32_t inst)
873 {
874 struct dce_i2c_hw *dce_i2c_hw =
875 kzalloc_obj(struct dce_i2c_hw);
876
877 if (!dce_i2c_hw)
878 return NULL;
879
880 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
881 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
882
883 return dce_i2c_hw;
884 }
885
dcn30_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)886 static struct mpc *dcn30_mpc_create(
887 struct dc_context *ctx,
888 int num_mpcc,
889 int num_rmu)
890 {
891 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
892
893 if (!mpc30)
894 return NULL;
895
896 dcn30_mpc_construct(mpc30, ctx,
897 &mpc_regs,
898 &mpc_shift,
899 &mpc_mask,
900 num_mpcc,
901 num_rmu);
902
903 return &mpc30->base;
904 }
905
dcn30_hubbub_create(struct dc_context * ctx)906 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
907 {
908 int i;
909
910 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
911
912 if (!hubbub3)
913 return NULL;
914
915 hubbub3_construct(hubbub3, ctx,
916 &hubbub_reg,
917 &hubbub_shift,
918 &hubbub_mask);
919
920
921 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
922 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
923
924 vmid->ctx = ctx;
925
926 vmid->regs = &vmid_regs[i];
927 vmid->shifts = &vmid_shifts;
928 vmid->masks = &vmid_masks;
929 }
930
931 return &hubbub3->base;
932 }
933
934 static const struct dcn_dio_registers dio_regs = {
935 DIO_REG_LIST_DCN10()
936 };
937
938 #define DIO_MASK_SH_LIST(mask_sh)\
939 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
940
941 static const struct dcn_dio_shift dio_shift = {
942 DIO_MASK_SH_LIST(__SHIFT)
943 };
944
945 static const struct dcn_dio_mask dio_mask = {
946 DIO_MASK_SH_LIST(_MASK)
947 };
948
dcn30_dio_create(struct dc_context * ctx)949 static struct dio *dcn30_dio_create(struct dc_context *ctx)
950 {
951 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
952
953 if (!dio10)
954 return NULL;
955
956 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
957
958 return &dio10->base;
959 }
960
dcn30_timing_generator_create(struct dc_context * ctx,uint32_t instance)961 static struct timing_generator *dcn30_timing_generator_create(
962 struct dc_context *ctx,
963 uint32_t instance)
964 {
965 struct optc *tgn10 =
966 kzalloc_obj(struct optc);
967
968 if (!tgn10)
969 return NULL;
970
971 tgn10->base.inst = instance;
972 tgn10->base.ctx = ctx;
973
974 tgn10->tg_regs = &optc_regs[instance];
975 tgn10->tg_shift = &optc_shift;
976 tgn10->tg_mask = &optc_mask;
977
978 dcn30_timing_generator_init(tgn10);
979
980 return &tgn10->base;
981 }
982
983 static const struct encoder_feature_support link_enc_feature = {
984 .max_hdmi_deep_color = COLOR_DEPTH_121212,
985 .max_hdmi_pixel_clock = 600000,
986 .hdmi_ycbcr420_supported = true,
987 .dp_ycbcr420_supported = true,
988 .fec_supported = true,
989 .flags.bits.IS_HBR2_CAPABLE = true,
990 .flags.bits.IS_HBR3_CAPABLE = true,
991 .flags.bits.IS_TPS3_CAPABLE = true,
992 .flags.bits.IS_TPS4_CAPABLE = true
993 };
994
dcn30_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)995 static struct link_encoder *dcn30_link_encoder_create(
996 struct dc_context *ctx,
997 const struct encoder_init_data *enc_init_data)
998 {
999 (void)ctx;
1000 struct dcn20_link_encoder *enc20 =
1001 kzalloc_obj(struct dcn20_link_encoder);
1002
1003 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1004 return NULL;
1005
1006 dcn30_link_encoder_construct(enc20,
1007 enc_init_data,
1008 &link_enc_feature,
1009 &link_enc_regs[enc_init_data->transmitter],
1010 &link_enc_aux_regs[enc_init_data->channel - 1],
1011 &link_enc_hpd_regs[enc_init_data->hpd_source],
1012 &le_shift,
1013 &le_mask);
1014
1015 return &enc20->enc10.base;
1016 }
1017
dcn30_panel_cntl_create(const struct panel_cntl_init_data * init_data)1018 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1019 {
1020 struct dce_panel_cntl *panel_cntl =
1021 kzalloc_obj(struct dce_panel_cntl);
1022
1023 if (!panel_cntl)
1024 return NULL;
1025
1026 dce_panel_cntl_construct(panel_cntl,
1027 init_data,
1028 &panel_cntl_regs[init_data->inst],
1029 &panel_cntl_shift,
1030 &panel_cntl_mask);
1031
1032 return &panel_cntl->base;
1033 }
1034
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1035 static void read_dce_straps(
1036 struct dc_context *ctx,
1037 struct resource_straps *straps)
1038 {
1039 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1040 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1041
1042 }
1043
dcn30_create_audio(struct dc_context * ctx,unsigned int inst)1044 static struct audio *dcn30_create_audio(
1045 struct dc_context *ctx, unsigned int inst)
1046 {
1047 return dce_audio_create(ctx, inst,
1048 &audio_regs[inst], &audio_shift, &audio_mask);
1049 }
1050
dcn30_vpg_create(struct dc_context * ctx,uint32_t inst)1051 static struct vpg *dcn30_vpg_create(
1052 struct dc_context *ctx,
1053 uint32_t inst)
1054 {
1055 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
1056
1057 if (!vpg3)
1058 return NULL;
1059
1060 vpg3_construct(vpg3, ctx, inst,
1061 &vpg_regs[inst],
1062 &vpg_shift,
1063 &vpg_mask);
1064
1065 return &vpg3->base;
1066 }
1067
dcn30_afmt_create(struct dc_context * ctx,uint32_t inst)1068 static struct afmt *dcn30_afmt_create(
1069 struct dc_context *ctx,
1070 uint32_t inst)
1071 {
1072 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
1073
1074 if (!afmt3)
1075 return NULL;
1076
1077 afmt3_construct(afmt3, ctx, inst,
1078 &afmt_regs[inst],
1079 &afmt_shift,
1080 &afmt_mask);
1081
1082 return &afmt3->base;
1083 }
1084
dcn30_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1085 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1086 struct dc_context *ctx)
1087 {
1088 struct dcn10_stream_encoder *enc1;
1089 struct vpg *vpg;
1090 struct afmt *afmt;
1091 int vpg_inst;
1092 int afmt_inst;
1093
1094 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1095 if (eng_id <= ENGINE_ID_DIGF) {
1096 vpg_inst = eng_id;
1097 afmt_inst = eng_id;
1098 } else
1099 return NULL;
1100
1101 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1102 vpg = dcn30_vpg_create(ctx, vpg_inst);
1103 afmt = dcn30_afmt_create(ctx, afmt_inst);
1104
1105 if (!enc1 || !vpg || !afmt) {
1106 kfree(enc1);
1107 kfree(vpg);
1108 kfree(afmt);
1109 return NULL;
1110 }
1111
1112 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1113 eng_id, vpg, afmt,
1114 &stream_enc_regs[eng_id],
1115 &se_shift, &se_mask);
1116
1117 return &enc1->base;
1118 }
1119
dcn30_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1120 static struct hpo_frl_stream_encoder *dcn30_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1121 struct dc_context *ctx)
1122 {
1123 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1124 struct afmt *afmt;
1125 struct vpg *vpg;
1126 int afmt_inst;
1127 int vpg_inst;
1128
1129 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1130 if (eng_id == ENGINE_ID_HPO_0) {
1131 vpg_inst = 6;
1132 afmt_inst = 6;
1133 } else {
1134 return NULL;
1135 }
1136
1137 /* allocate HPO stream encoder and create VPG sub-block */
1138 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1139 vpg = dcn30_vpg_create(ctx, vpg_inst);
1140 afmt = dcn30_afmt_create(ctx, afmt_inst);
1141
1142 if (!hpo_enc3 || !vpg || !afmt) {
1143 kfree(hpo_enc3);
1144 kfree(vpg);
1145 kfree(afmt);
1146 return NULL;
1147 }
1148
1149 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1150 ctx,
1151 ctx->dc_bios,
1152 eng_id,
1153 vpg,
1154 afmt,
1155 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1156 &hpo_se_shift, &hpo_se_mask);
1157
1158 return &hpo_enc3->base;
1159 }
1160
dcn30_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1161 static struct hpo_frl_link_encoder *dcn30_hpo_frl_link_encoder_create(enum engine_id eng_id,
1162 struct dc_context *ctx)
1163 {
1164 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1165
1166 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1167
1168 /* allocate HPO link encoder */
1169 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1170 if (!hpo_enc3)
1171 return NULL; /* out of memory */
1172
1173 hpo_frl_link_encoder3_construct(hpo_enc3,
1174 ctx,
1175 eng_id-ENGINE_ID_HPO_0,
1176 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1177 &hpo_le_shift,
1178 &hpo_le_mask);
1179
1180 return &hpo_enc3->base;
1181 }
1182
dcn30_hwseq_create(struct dc_context * ctx)1183 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1184 {
1185 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1186
1187 if (hws) {
1188 hws->ctx = ctx;
1189 hws->regs = &hwseq_reg;
1190 hws->shifts = &hwseq_shift;
1191 hws->masks = &hwseq_mask;
1192 }
1193 return hws;
1194 }
1195 static const struct resource_create_funcs res_create_funcs = {
1196 .read_dce_straps = read_dce_straps,
1197 .create_audio = dcn30_create_audio,
1198 .create_stream_encoder = dcn30_stream_encoder_create,
1199 .create_hpo_frl_stream_encoder = dcn30_hpo_frl_stream_encoder_create,
1200 .create_hwseq = dcn30_hwseq_create,
1201 };
1202
dcn30_resource_destruct(struct dcn30_resource_pool * pool)1203 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1204 {
1205 unsigned int i;
1206
1207 for (i = 0; i < pool->base.stream_enc_count; i++) {
1208 if (pool->base.stream_enc[i] != NULL) {
1209 if (pool->base.stream_enc[i]->vpg != NULL) {
1210 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1211 pool->base.stream_enc[i]->vpg = NULL;
1212 }
1213 if (pool->base.stream_enc[i]->afmt != NULL) {
1214 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1215 pool->base.stream_enc[i]->afmt = NULL;
1216 }
1217 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1218 pool->base.stream_enc[i] = NULL;
1219 }
1220 }
1221
1222 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1223 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1224 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1225 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1226 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1227 }
1228
1229 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1230 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1231 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1232 }
1233
1234 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1235 pool->base.hpo_frl_stream_enc[i] = NULL;
1236 }
1237 }
1238
1239 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1240 if (pool->base.dscs[i] != NULL)
1241 dcn20_dsc_destroy(&pool->base.dscs[i]);
1242 }
1243
1244 if (pool->base.mpc != NULL) {
1245 kfree(TO_DCN20_MPC(pool->base.mpc));
1246 pool->base.mpc = NULL;
1247 }
1248 if (pool->base.hubbub != NULL) {
1249 kfree(pool->base.hubbub);
1250 pool->base.hubbub = NULL;
1251 }
1252
1253 if (pool->base.dio != NULL) {
1254 kfree(TO_DCN10_DIO(pool->base.dio));
1255 pool->base.dio = NULL;
1256 }
1257
1258 for (i = 0; i < pool->base.pipe_count; i++) {
1259 if (pool->base.dpps[i] != NULL)
1260 dcn30_dpp_destroy(&pool->base.dpps[i]);
1261
1262 if (pool->base.ipps[i] != NULL)
1263 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1264
1265 if (pool->base.hubps[i] != NULL) {
1266 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1267 pool->base.hubps[i] = NULL;
1268 }
1269
1270 if (pool->base.irqs != NULL) {
1271 dal_irq_service_destroy(&pool->base.irqs);
1272 }
1273 }
1274
1275 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1276 if (pool->base.engines[i] != NULL)
1277 dce110_engine_destroy(&pool->base.engines[i]);
1278 if (pool->base.hw_i2cs[i] != NULL) {
1279 kfree(pool->base.hw_i2cs[i]);
1280 pool->base.hw_i2cs[i] = NULL;
1281 }
1282 if (pool->base.sw_i2cs[i] != NULL) {
1283 kfree(pool->base.sw_i2cs[i]);
1284 pool->base.sw_i2cs[i] = NULL;
1285 }
1286 }
1287
1288 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1289 if (pool->base.opps[i] != NULL)
1290 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1291 }
1292
1293 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1294 if (pool->base.timing_generators[i] != NULL) {
1295 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1296 pool->base.timing_generators[i] = NULL;
1297 }
1298 }
1299
1300 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1301 if (pool->base.dwbc[i] != NULL) {
1302 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1303 pool->base.dwbc[i] = NULL;
1304 }
1305 if (pool->base.mcif_wb[i] != NULL) {
1306 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1307 pool->base.mcif_wb[i] = NULL;
1308 }
1309 }
1310
1311 for (i = 0; i < pool->base.audio_count; i++) {
1312 if (pool->base.audios[i])
1313 dce_aud_destroy(&pool->base.audios[i]);
1314 }
1315
1316 for (i = 0; i < pool->base.clk_src_count; i++) {
1317 if (pool->base.clock_sources[i] != NULL) {
1318 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1319 pool->base.clock_sources[i] = NULL;
1320 }
1321 }
1322
1323 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1324 if (pool->base.mpc_lut[i] != NULL) {
1325 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1326 pool->base.mpc_lut[i] = NULL;
1327 }
1328 if (pool->base.mpc_shaper[i] != NULL) {
1329 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1330 pool->base.mpc_shaper[i] = NULL;
1331 }
1332 }
1333
1334 if (pool->base.dp_clock_source != NULL) {
1335 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1336 pool->base.dp_clock_source = NULL;
1337 }
1338
1339 for (i = 0; i < pool->base.pipe_count; i++) {
1340 if (pool->base.multiple_abms[i] != NULL)
1341 dce_abm_destroy(&pool->base.multiple_abms[i]);
1342 }
1343
1344 if (pool->base.psr != NULL)
1345 dmub_psr_destroy(&pool->base.psr);
1346
1347 if (pool->base.dccg != NULL)
1348 dcn_dccg_destroy(&pool->base.dccg);
1349
1350 if (pool->base.oem_device != NULL) {
1351 struct dc *dc = pool->base.oem_device->ctx->dc;
1352
1353 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1354 }
1355 }
1356
dcn30_hubp_create(struct dc_context * ctx,uint32_t inst)1357 static struct hubp *dcn30_hubp_create(
1358 struct dc_context *ctx,
1359 uint32_t inst)
1360 {
1361 struct dcn20_hubp *hubp2 =
1362 kzalloc_obj(struct dcn20_hubp);
1363
1364 if (!hubp2)
1365 return NULL;
1366
1367 if (hubp3_construct(hubp2, ctx, inst,
1368 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1369 return &hubp2->base;
1370
1371 BREAK_TO_DEBUGGER();
1372 kfree(hubp2);
1373 return NULL;
1374 }
1375
dcn30_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1376 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1377 {
1378 unsigned int i;
1379 uint32_t pipe_count = pool->res_cap->num_dwb;
1380
1381 for (i = 0; i < pipe_count; i++) {
1382 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1383
1384 if (!dwbc30) {
1385 dm_error("DC: failed to create dwbc30!\n");
1386 return false;
1387 }
1388
1389 dcn30_dwbc_construct(dwbc30, ctx,
1390 &dwbc30_regs[i],
1391 &dwbc30_shift,
1392 &dwbc30_mask,
1393 i);
1394
1395 pool->dwbc[i] = &dwbc30->base;
1396 }
1397 return true;
1398 }
1399
dcn30_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1400 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1401 {
1402 unsigned int i;
1403 uint32_t pipe_count = pool->res_cap->num_dwb;
1404
1405 for (i = 0; i < pipe_count; i++) {
1406 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1407
1408 if (!mcif_wb30) {
1409 dm_error("DC: failed to create mcif_wb30!\n");
1410 return false;
1411 }
1412
1413 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1414 &mcif_wb30_regs[i],
1415 &mcif_wb30_shift,
1416 &mcif_wb30_mask,
1417 i);
1418
1419 pool->mcif_wb[i] = &mcif_wb30->base;
1420 }
1421 return true;
1422 }
1423
dcn30_dsc_create(struct dc_context * ctx,uint32_t inst)1424 static struct display_stream_compressor *dcn30_dsc_create(
1425 struct dc_context *ctx, uint32_t inst)
1426 {
1427 struct dcn20_dsc *dsc =
1428 kzalloc_obj(struct dcn20_dsc);
1429
1430 if (!dsc) {
1431 BREAK_TO_DEBUGGER();
1432 return NULL;
1433 }
1434
1435 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1436 return &dsc->base;
1437 }
1438
dcn30_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1439 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1440 {
1441
1442 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1443 }
1444
dcn30_destroy_resource_pool(struct resource_pool ** pool)1445 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1446 {
1447 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1448
1449 dcn30_resource_destruct(dcn30_pool);
1450 kfree(dcn30_pool);
1451 *pool = NULL;
1452 }
1453
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1454 static struct clock_source *dcn30_clock_source_create(
1455 struct dc_context *ctx,
1456 struct dc_bios *bios,
1457 enum clock_source_id id,
1458 const struct dce110_clk_src_regs *regs,
1459 bool dp_clk_src)
1460 {
1461 struct dce110_clk_src *clk_src =
1462 kzalloc_obj(struct dce110_clk_src);
1463
1464 if (!clk_src)
1465 return NULL;
1466
1467 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1468 regs, &cs_shift, &cs_mask)) {
1469 clk_src->base.dp_clk_src = dp_clk_src;
1470 return &clk_src->base;
1471 }
1472
1473 kfree(clk_src);
1474 BREAK_TO_DEBUGGER();
1475 return NULL;
1476 }
1477
dcn30_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1478 int dcn30_populate_dml_pipes_from_context(
1479 struct dc *dc, struct dc_state *context,
1480 display_e2e_pipe_params_st *pipes,
1481 enum dc_validate_mode validate_mode)
1482 {
1483 int pipe_cnt;
1484 unsigned int i;
1485 struct resource_context *res_ctx = &context->res_ctx;
1486
1487 DC_FP_START();
1488 dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1489 DC_FP_END();
1490
1491 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1492 if (!res_ctx->pipe_ctx[i].stream)
1493 continue;
1494
1495 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1496 dm_lb_16;
1497 }
1498
1499 return pipe_cnt;
1500 }
1501
dcn30_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1502 void dcn30_populate_dml_writeback_from_context(
1503 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1504 {
1505 DC_FP_START();
1506 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1507 DC_FP_END();
1508 }
1509
dcn30_calc_max_scaled_time(unsigned int time_per_pixel,enum mmhubbub_wbif_mode mode,unsigned int urgent_watermark)1510 unsigned int dcn30_calc_max_scaled_time(
1511 unsigned int time_per_pixel,
1512 enum mmhubbub_wbif_mode mode,
1513 unsigned int urgent_watermark)
1514 {
1515 unsigned int time_per_byte = 0;
1516 unsigned int total_free_entry = 0xb40;
1517 unsigned int buf_lh_capability;
1518 unsigned int max_scaled_time;
1519
1520 if (mode == PACKED_444) /* packed mode 32 bpp */
1521 time_per_byte = time_per_pixel/4;
1522 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1523 time_per_byte = time_per_pixel/8;
1524
1525 if (time_per_byte == 0)
1526 time_per_byte = 1;
1527
1528 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1529 max_scaled_time = buf_lh_capability - urgent_watermark;
1530 return max_scaled_time;
1531 }
1532
dcn30_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1533 void dcn30_set_mcif_arb_params(
1534 struct dc *dc,
1535 struct dc_state *context,
1536 display_e2e_pipe_params_st *pipes,
1537 int pipe_cnt)
1538 {
1539 enum mmhubbub_wbif_mode wbif_mode;
1540 struct display_mode_lib *dml = &context->bw_ctx.dml;
1541 struct mcif_arb_params *wb_arb_params;
1542 int j, dwb_pipe;
1543 unsigned int i;
1544
1545 /* Writeback MCIF_WB arbitration parameters */
1546 dwb_pipe = 0;
1547 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1548
1549 if (!context->res_ctx.pipe_ctx[i].stream)
1550 continue;
1551
1552 for (j = 0; j < MAX_DWB_PIPES; j++) {
1553 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1554
1555 if (writeback_info->wb_enabled == false)
1556 continue;
1557
1558 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1559 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1560
1561 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1562 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1563 wbif_mode = PACKED_444_FP16;
1564 else
1565 wbif_mode = PACKED_444;
1566
1567 DC_FP_START();
1568 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1569 DC_FP_END();
1570 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1571 wb_arb_params->slice_lines = 32;
1572 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1573 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1574 wbif_mode,
1575 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1576
1577 dwb_pipe++;
1578
1579 if (dwb_pipe >= MAX_DWB_PIPES)
1580 return;
1581 }
1582 }
1583 }
1584
1585 static struct dc_cap_funcs cap_funcs = {
1586 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1587 };
1588
dcn30_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1589 bool dcn30_acquire_post_bldn_3dlut(
1590 struct resource_context *res_ctx,
1591 const struct resource_pool *pool,
1592 int mpcc_id,
1593 struct dc_3dlut **lut,
1594 struct dc_transfer_func **shaper)
1595 {
1596 int i;
1597 bool ret = false;
1598 union dc_3dlut_state *state;
1599
1600 ASSERT(*lut == NULL && *shaper == NULL);
1601 *lut = NULL;
1602 *shaper = NULL;
1603
1604 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1605 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1606 *lut = pool->mpc_lut[i];
1607 *shaper = pool->mpc_shaper[i];
1608 state = &pool->mpc_lut[i]->state;
1609 res_ctx->is_mpc_3dlut_acquired[i] = true;
1610 state->bits.rmu_idx_valid = 1;
1611 state->bits.rmu_mux_num = i;
1612 if (state->bits.rmu_mux_num == 0)
1613 state->bits.mpc_rmu0_mux = mpcc_id;
1614 else if (state->bits.rmu_mux_num == 1)
1615 state->bits.mpc_rmu1_mux = mpcc_id;
1616 else if (state->bits.rmu_mux_num == 2)
1617 state->bits.mpc_rmu2_mux = mpcc_id;
1618 ret = true;
1619 break;
1620 }
1621 }
1622 return ret;
1623 }
1624
dcn30_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1625 bool dcn30_release_post_bldn_3dlut(
1626 struct resource_context *res_ctx,
1627 const struct resource_pool *pool,
1628 struct dc_3dlut **lut,
1629 struct dc_transfer_func **shaper)
1630 {
1631 int i;
1632 bool ret = false;
1633
1634 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1635 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1636 res_ctx->is_mpc_3dlut_acquired[i] = false;
1637 pool->mpc_lut[i]->state.raw = 0;
1638 *lut = NULL;
1639 *shaper = NULL;
1640 ret = true;
1641 break;
1642 }
1643 }
1644 return ret;
1645 }
1646
is_soc_bounding_box_valid(struct dc * dc)1647 static bool is_soc_bounding_box_valid(struct dc *dc)
1648 {
1649 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1650
1651 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1652 return true;
1653
1654 return false;
1655 }
1656
init_soc_bounding_box(struct dc * dc,struct dcn30_resource_pool * pool)1657 static bool init_soc_bounding_box(struct dc *dc,
1658 struct dcn30_resource_pool *pool)
1659 {
1660 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1661 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1662
1663 DC_LOGGER_INIT(dc->ctx->logger);
1664
1665 if (!is_soc_bounding_box_valid(dc)) {
1666 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1667 return false;
1668 }
1669
1670 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1671 loaded_ip->max_num_dpp = pool->base.pipe_count;
1672 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1673 dcn20_patch_bounding_box(dc, loaded_bb);
1674 DC_FP_START();
1675 patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1676 DC_FP_END();
1677
1678 return true;
1679 }
1680
dcn30_split_stream_for_mpc_or_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm)1681 static bool dcn30_split_stream_for_mpc_or_odm(
1682 const struct dc *dc,
1683 struct resource_context *res_ctx,
1684 struct pipe_ctx *pri_pipe,
1685 struct pipe_ctx *sec_pipe,
1686 bool odm)
1687 {
1688 int pipe_idx = sec_pipe->pipe_idx;
1689 const struct resource_pool *pool = dc->res_pool;
1690
1691 *sec_pipe = *pri_pipe;
1692
1693 sec_pipe->pipe_idx = (uint8_t)pipe_idx;
1694 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1695 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1696 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1697 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1698 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1699 sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
1700 sec_pipe->stream_res.dsc = NULL;
1701 if (odm) {
1702 if (pri_pipe->next_odm_pipe) {
1703 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1704 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1705 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1706 }
1707 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1708 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1709 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1710 }
1711 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1712 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1713 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1714 }
1715 pri_pipe->next_odm_pipe = sec_pipe;
1716 sec_pipe->prev_odm_pipe = pri_pipe;
1717
1718 if (!sec_pipe->top_pipe)
1719 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1720 else
1721 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1722 if (sec_pipe->stream->timing.flags.DSC == 1) {
1723 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1724 ASSERT(sec_pipe->stream_res.dsc);
1725 if (sec_pipe->stream_res.dsc == NULL)
1726 return false;
1727 }
1728 } else {
1729 if (pri_pipe->bottom_pipe) {
1730 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1731 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1732 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1733 }
1734 pri_pipe->bottom_pipe = sec_pipe;
1735 sec_pipe->top_pipe = pri_pipe;
1736
1737 ASSERT(pri_pipe->plane_state);
1738 }
1739
1740 return true;
1741 }
1742
dcn30_find_split_pipe(struct dc * dc,struct dc_state * context,int old_index)1743 static struct pipe_ctx *dcn30_find_split_pipe(
1744 struct dc *dc,
1745 struct dc_state *context,
1746 int old_index)
1747 {
1748 struct pipe_ctx *pipe = NULL;
1749 int i;
1750
1751 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1752 pipe = &context->res_ctx.pipe_ctx[old_index];
1753 pipe->pipe_idx = (uint8_t)old_index;
1754 }
1755
1756 if (!pipe)
1757 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1758 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1759 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1760 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1761 pipe = &context->res_ctx.pipe_ctx[i];
1762 pipe->pipe_idx = (uint8_t)i;
1763 break;
1764 }
1765 }
1766 }
1767
1768 /*
1769 * May need to fix pipes getting tossed from 1 opp to another on flip
1770 * Add for debugging transient underflow during topology updates:
1771 * ASSERT(pipe);
1772 */
1773 if (!pipe)
1774 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1775 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1776 pipe = &context->res_ctx.pipe_ctx[i];
1777 pipe->pipe_idx = (uint8_t)i;
1778 break;
1779 }
1780 }
1781
1782 return pipe;
1783 }
1784
dcn30_internal_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * vlevel_out,enum dc_validate_mode validate_mode,bool allow_self_refresh_only)1785 noinline bool dcn30_internal_validate_bw(
1786 struct dc *dc,
1787 struct dc_state *context,
1788 display_e2e_pipe_params_st *pipes,
1789 int *pipe_cnt_out,
1790 int *vlevel_out,
1791 enum dc_validate_mode validate_mode,
1792 bool allow_self_refresh_only)
1793 {
1794 bool out = false;
1795 bool repopulate_pipes = false;
1796 int split[MAX_PIPES] = { 0 };
1797 bool merge[MAX_PIPES] = { false };
1798 bool newly_split[MAX_PIPES] = { false };
1799 unsigned int i;
1800 int pipe_cnt, pipe_idx, vlevel = 0;
1801 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1802
1803 ASSERT(pipes);
1804 if (!pipes)
1805 return false;
1806
1807 dcn20_merge_pipes_for_validate(dc, context);
1808
1809 context->bw_ctx.dml.vba.maxMpcComb = 0;
1810 context->bw_ctx.dml.vba.VoltageLevel = 0;
1811 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1812 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1813 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
1814
1815 if (!pipe_cnt) {
1816 out = true;
1817 goto validate_out;
1818 }
1819
1820 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1821
1822 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING || !allow_self_refresh_only) {
1823 /*
1824 * DML favors voltage over p-state, but we're more interested in
1825 * supporting p-state over voltage. We can't support p-state in
1826 * prefetch mode > 0 so try capping the prefetch mode to start.
1827 */
1828 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1829 dm_allow_self_refresh_and_mclk_switch;
1830 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1831 /* This may adjust vlevel and maxMpcComb */
1832 if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states)
1833 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1834 }
1835 if (allow_self_refresh_only &&
1836 (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states ||
1837 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
1838 /*
1839 * If mode is unsupported or there's still no p-state support
1840 * then fall back to favoring voltage.
1841 *
1842 * We don't actually support prefetch mode 2, so require that we
1843 * at least support prefetch mode 1.
1844 */
1845 context->bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);
1846 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1847 dm_allow_self_refresh;
1848
1849 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1850 if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) {
1851 memset(split, 0, sizeof(split));
1852 memset(merge, 0, sizeof(merge));
1853 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1854 }
1855 context->bw_ctx.dml.validate_max_state = false;
1856 }
1857
1858 dml_log_mode_support_params(&context->bw_ctx.dml);
1859
1860 if (vlevel == context->bw_ctx.dml.soc.num_states)
1861 goto validate_fail;
1862
1863 if (!dc->config.enable_windowed_mpo_odm) {
1864 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1865 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1866 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1867
1868 if (!pipe->stream)
1869 continue;
1870
1871 /* We only support full screen mpo with ODM */
1872 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1873 && pipe->plane_state && mpo_pipe
1874 && memcmp(&mpo_pipe->plane_state->clip_rect,
1875 &pipe->stream->src,
1876 sizeof(struct rect)) != 0) {
1877 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1878 goto validate_fail;
1879 }
1880 pipe_idx++;
1881 }
1882 }
1883
1884 /* merge pipes if necessary */
1885 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1886 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1887
1888 /*skip pipes that don't need merging*/
1889 if (!merge[i])
1890 continue;
1891
1892 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1893 if (pipe->prev_odm_pipe) {
1894 /*split off odm pipe*/
1895 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1896 if (pipe->next_odm_pipe)
1897 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1898
1899 pipe->bottom_pipe = NULL;
1900 pipe->next_odm_pipe = NULL;
1901 pipe->plane_state = NULL;
1902 pipe->stream = NULL;
1903 pipe->top_pipe = NULL;
1904 pipe->prev_odm_pipe = NULL;
1905 if (pipe->stream_res.dsc)
1906 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1907 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1908 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1909 repopulate_pipes = true;
1910 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1911 struct pipe_ctx *top_pipe = pipe->top_pipe;
1912 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1913
1914 top_pipe->bottom_pipe = bottom_pipe;
1915 if (bottom_pipe)
1916 bottom_pipe->top_pipe = top_pipe;
1917
1918 pipe->top_pipe = NULL;
1919 pipe->bottom_pipe = NULL;
1920 pipe->plane_state = NULL;
1921 pipe->stream = NULL;
1922 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1923 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1924 repopulate_pipes = true;
1925 } else
1926 ASSERT(0); /* Should never try to merge master pipe */
1927
1928 }
1929
1930 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1931 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1932 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1933 struct pipe_ctx *hsplit_pipe = NULL;
1934 bool odm;
1935 int old_index = -1;
1936
1937 if (!pipe->stream || newly_split[i])
1938 continue;
1939
1940 pipe_idx++;
1941 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1942
1943 if (!pipe->plane_state && !odm)
1944 continue;
1945
1946 if (split[i]) {
1947 if (odm) {
1948 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1949 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1950 else if (old_pipe->next_odm_pipe)
1951 old_index = old_pipe->next_odm_pipe->pipe_idx;
1952 } else {
1953 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1954 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1955 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1956 else if (old_pipe->bottom_pipe &&
1957 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1958 old_index = old_pipe->bottom_pipe->pipe_idx;
1959 }
1960 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1961 ASSERT(hsplit_pipe);
1962 if (!hsplit_pipe)
1963 goto validate_fail;
1964
1965 if (!dcn30_split_stream_for_mpc_or_odm(
1966 dc, &context->res_ctx,
1967 pipe, hsplit_pipe, odm))
1968 goto validate_fail;
1969
1970 newly_split[hsplit_pipe->pipe_idx] = true;
1971 repopulate_pipes = true;
1972 }
1973 if (split[i] == 4) {
1974 struct pipe_ctx *pipe_4to1;
1975
1976 if (odm && old_pipe->next_odm_pipe)
1977 old_index = old_pipe->next_odm_pipe->pipe_idx;
1978 else if (!odm && old_pipe->bottom_pipe &&
1979 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1980 old_index = old_pipe->bottom_pipe->pipe_idx;
1981 else
1982 old_index = -1;
1983 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1984 ASSERT(pipe_4to1);
1985 if (!pipe_4to1)
1986 goto validate_fail;
1987 if (!dcn30_split_stream_for_mpc_or_odm(
1988 dc, &context->res_ctx,
1989 pipe, pipe_4to1, odm))
1990 goto validate_fail;
1991 newly_split[pipe_4to1->pipe_idx] = true;
1992
1993 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1994 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1995 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1996 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1997 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1998 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1999 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2000 else
2001 old_index = -1;
2002 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2003 ASSERT(pipe_4to1);
2004 if (!pipe_4to1)
2005 goto validate_fail;
2006 if (!dcn30_split_stream_for_mpc_or_odm(
2007 dc, &context->res_ctx,
2008 hsplit_pipe, pipe_4to1, odm))
2009 goto validate_fail;
2010 newly_split[pipe_4to1->pipe_idx] = true;
2011 }
2012 if (odm)
2013 dcn20_build_mapped_resource(dc, context, pipe->stream);
2014 }
2015
2016 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2017 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2018
2019 if (pipe->plane_state) {
2020 if (!resource_build_scaling_params(pipe))
2021 goto validate_fail;
2022 }
2023 }
2024
2025 /* Actual dsc count per stream dsc validation*/
2026 if (!dcn20_validate_dsc(dc, context)) {
2027 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2028 goto validate_fail;
2029 }
2030
2031 if (repopulate_pipes)
2032 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
2033 context->bw_ctx.dml.vba.VoltageLevel = vlevel;
2034 *vlevel_out = vlevel;
2035 *pipe_cnt_out = pipe_cnt;
2036
2037 out = true;
2038 goto validate_out;
2039
2040 validate_fail:
2041 out = false;
2042
2043 validate_out:
2044 return out;
2045 }
2046
get_refresh_rate(struct dc_state * context)2047 static int get_refresh_rate(struct dc_state *context)
2048 {
2049 int refresh_rate = 0;
2050 int h_v_total = 0;
2051 struct dc_crtc_timing *timing = NULL;
2052
2053 if (context == NULL || context->streams[0] == NULL)
2054 return 0;
2055
2056 /* check if refresh rate at least 120hz */
2057 timing = &context->streams[0]->timing;
2058
2059 h_v_total = timing->h_total * timing->v_total;
2060 if (h_v_total == 0)
2061 return 0;
2062
2063 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
2064 return refresh_rate;
2065 }
2066
2067 #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
2068 /*
2069 * Scaling factor for v_blank stretch calculations considering timing in
2070 * micro-seconds and pixel clock in 100hz.
2071 * Note: the parenthesis are necessary to ensure the correct order of
2072 * operation where V_SCALE is used.
2073 */
2074 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
2075
get_frame_rate_at_max_stretch_100hz(struct dc_state * context)2076 static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
2077 {
2078 struct dc_crtc_timing *timing = NULL;
2079 uint32_t sec_per_100_lines;
2080 uint32_t max_v_blank;
2081 uint32_t curr_v_blank;
2082 uint32_t v_stretch_max;
2083 uint32_t stretched_frame_pix_cnt;
2084 uint32_t scaled_stretched_frame_pix_cnt;
2085 uint32_t scaled_refresh_rate;
2086
2087 if (context == NULL || context->streams[0] == NULL)
2088 return 0;
2089
2090 /* check if refresh rate at least 120hz */
2091 timing = &context->streams[0]->timing;
2092 if (timing == NULL)
2093 return 0;
2094
2095 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
2096 max_v_blank = sec_per_100_lines / V_SCALE + 1;
2097 curr_v_blank = timing->v_total - timing->v_addressable;
2098 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
2099 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
2100 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
2101 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
2102
2103 return scaled_refresh_rate;
2104 }
2105
is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state * context)2106 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
2107 {
2108 int refresh_rate_max_stretch_100hz;
2109 int min_refresh_100hz;
2110
2111 if (context == NULL || context->streams[0] == NULL)
2112 return false;
2113
2114 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
2115 min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
2116
2117 if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
2118 return false;
2119
2120 return true;
2121 }
2122
dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc * dc,struct dc_state * context)2123 bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2124 {
2125 int refresh_rate = 0;
2126 const int minimum_refreshrate_supported = 120;
2127 struct dc_stream_status *stream_status = NULL;
2128
2129 if (context == NULL || context->streams[0] == NULL)
2130 return false;
2131
2132 if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
2133 return false;
2134
2135 if (dc->debug.disable_fams)
2136 return false;
2137
2138 if (!dc->caps.dmub_caps.mclk_sw)
2139 return false;
2140
2141 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
2142 return false;
2143
2144 /* more then 1 monitor connected */
2145 if (context->stream_count != 1)
2146 return false;
2147
2148 refresh_rate = get_refresh_rate(context);
2149 if (refresh_rate < minimum_refreshrate_supported)
2150 return false;
2151
2152 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
2153 return false;
2154
2155 if (!context->streams[0]->allow_freesync)
2156 return false;
2157
2158 if (context->streams[0]->vrr_active_variable && (dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE))
2159 return false;
2160
2161 stream_status = dc_state_get_stream_status(context, context->streams[0]);
2162
2163 if (!stream_status)
2164 return false;
2165
2166 stream_status->fpo_in_use = true;
2167
2168 return true;
2169 }
2170
2171 /*
2172 * set up FPO watermarks, pstate, dram latency
2173 */
dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc * dc,struct dc_state * context)2174 void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2175 {
2176 ASSERT(dc != NULL && context != NULL);
2177 if (dc == NULL || context == NULL)
2178 return;
2179
2180 /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2181 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2182 }
2183
dcn30_update_soc_for_wm_a(struct dc * dc,struct dc_state * context)2184 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2185 {
2186 DC_FP_START();
2187 dcn30_fpu_update_soc_for_wm_a(dc, context);
2188 DC_FP_END();
2189 }
2190
dcn30_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)2191 void dcn30_calculate_wm_and_dlg(
2192 struct dc *dc, struct dc_state *context,
2193 display_e2e_pipe_params_st *pipes,
2194 int pipe_cnt,
2195 int vlevel)
2196 {
2197 DC_FP_START();
2198 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2199 DC_FP_END();
2200 }
2201
dcn30_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)2202 enum dc_status dcn30_validate_bandwidth(struct dc *dc,
2203 struct dc_state *context,
2204 enum dc_validate_mode validate_mode)
2205 {
2206 bool out = false;
2207
2208 BW_VAL_TRACE_SETUP();
2209
2210 int vlevel = 0;
2211 int pipe_cnt = 0;
2212 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
2213 dc->res_pool->pipe_count);
2214 DC_LOGGER_INIT(dc->ctx->logger);
2215
2216 BW_VAL_TRACE_COUNT();
2217
2218 if (!pipes)
2219 goto validate_fail;
2220
2221 DC_FP_START();
2222 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);
2223 DC_FP_END();
2224
2225 if (pipe_cnt == 0)
2226 goto validate_out;
2227
2228 if (!out)
2229 goto validate_fail;
2230
2231 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2232
2233 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
2234 BW_VAL_TRACE_SKIP(fast);
2235 goto validate_out;
2236 }
2237
2238 DC_FP_START();
2239 if (dc->res_pool->funcs->calculate_wm_and_dlg)
2240 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2241 DC_FP_END();
2242
2243 BW_VAL_TRACE_END_WATERMARKS();
2244
2245 goto validate_out;
2246
2247 validate_fail:
2248 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2249 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2250
2251 BW_VAL_TRACE_SKIP(fail);
2252 out = false;
2253
2254 validate_out:
2255 kfree(pipes);
2256
2257 BW_VAL_TRACE_FINISH();
2258
2259 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
2260 }
2261
dcn30_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2262 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2263 {
2264 unsigned int i, j;
2265 unsigned int num_states = 0;
2266
2267 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2268 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2269 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2270 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2271
2272 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2273 unsigned int num_dcfclk_sta_targets = 4;
2274 unsigned int num_uclk_states;
2275
2276 struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2277
2278 memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2279
2280 if (dc->ctx->dc_bios->vram_info.num_chans)
2281 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2282
2283 DC_FP_START();
2284 dcn30_fpu_update_dram_channel_width_bytes(dc);
2285 DC_FP_END();
2286
2287 if (bw_params->clk_table.entries[0].memclk_mhz) {
2288
2289 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2290 if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz)
2291 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2292 if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz)
2293 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2294 if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz)
2295 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2296 if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz)
2297 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2298 }
2299
2300 DC_FP_START();
2301 dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2302 DC_FP_END();
2303
2304 if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2305 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2306 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2307 num_dcfclk_sta_targets++;
2308 } else if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2309 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2310 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2311 if (dcfclk_sta_targets[i] > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
2312 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2313 break;
2314 }
2315 }
2316 // Update size of array since we "removed" duplicates
2317 num_dcfclk_sta_targets = i + 1;
2318 }
2319
2320 num_uclk_states = bw_params->clk_table.num_entries;
2321
2322 // Calculate optimal dcfclk for each uclk
2323 for (i = 0; i < num_uclk_states; i++) {
2324 DC_FP_START();
2325 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2326 &optimal_dcfclk_for_uclk[i], NULL);
2327 DC_FP_END();
2328 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2329 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2330 }
2331 }
2332
2333 // Calculate optimal uclk for each dcfclk sta target
2334 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2335 for (j = 0; j < num_uclk_states; j++) {
2336 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2337 optimal_uclk_for_dcfclk_sta_targets[i] =
2338 bw_params->clk_table.entries[j].memclk_mhz * 16;
2339 break;
2340 } else {
2341 /* condition where (dcfclk_sta_targets[i] >= optimal_dcfclk_for_uclk[j]):
2342 * If it just so happens that the memory bandwidth is low enough such that
2343 * all the optimal DCFCLK for each UCLK is lower than the smallest DCFCLK STA
2344 * target, we need to populate the optimal UCLK for each DCFCLK STA target to
2345 * be the max UCLK.
2346 */
2347 if (j == num_uclk_states - 1) {
2348 optimal_uclk_for_dcfclk_sta_targets[i] =
2349 bw_params->clk_table.entries[j].memclk_mhz * 16;
2350 }
2351 }
2352 }
2353 }
2354
2355 i = 0;
2356 j = 0;
2357 // create the final dcfclk and uclk table
2358 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2359 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2360 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2361 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2362 } else {
2363 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
2364 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2365 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2366 } else {
2367 j = num_uclk_states;
2368 }
2369 }
2370 }
2371
2372 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2373 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2374 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2375 }
2376
2377 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2378 optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
2379 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2380 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2381 }
2382
2383 dcn3_0_soc.num_states = num_states;
2384 DC_FP_START();
2385 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2386 DC_FP_END();
2387 }
2388 }
2389
dcn30_get_panel_config_defaults(struct dc_panel_config * panel_config)2390 static void dcn30_get_panel_config_defaults(struct dc_panel_config *panel_config)
2391 {
2392 *panel_config = panel_config_defaults;
2393 }
2394
2395 static const struct resource_funcs dcn30_res_pool_funcs = {
2396 .destroy = dcn30_destroy_resource_pool,
2397 .link_enc_create = dcn30_link_encoder_create,
2398 .panel_cntl_create = dcn30_panel_cntl_create,
2399 .hpo_frl_link_enc_create = dcn30_hpo_frl_link_encoder_create,
2400 .validate_bandwidth = dcn30_validate_bandwidth,
2401 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2402 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2403 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2404 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2405 .release_pipe = dcn20_release_pipe,
2406 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2407 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2408 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2409 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2410 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2411 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2412 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2413 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2414 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2415 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2416 .get_panel_config_defaults = dcn30_get_panel_config_defaults,
2417 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
2418 .get_default_tiling_info = dcn10_get_default_tiling_info
2419 };
2420
2421 #define CTX ctx
2422
2423 #define REG(reg_name) \
2424 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2425
read_pipe_fuses(struct dc_context * ctx)2426 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2427 {
2428 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2429 /* Support for max 6 pipes */
2430 value = value & 0x3f;
2431 return value;
2432 }
2433
dcn30_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn30_resource_pool * pool)2434 static bool dcn30_resource_construct(
2435 uint8_t num_virtual_links,
2436 struct dc *dc,
2437 struct dcn30_resource_pool *pool)
2438 {
2439 unsigned int i;
2440 struct dc_context *ctx = dc->ctx;
2441 struct irq_service_init_data init_data;
2442 struct ddc_service_init_data ddc_init_data = {0};
2443 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2444 uint32_t num_pipes = 0;
2445
2446 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2447 BREAK_TO_DEBUGGER();
2448 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2449 /* fault to single pipe */
2450 pipe_fuses = 0x3e;
2451 }
2452
2453 DC_FP_START();
2454
2455 ctx->dc_bios->regs = &bios_regs;
2456
2457 pool->base.res_cap = &res_cap_dcn3;
2458
2459 pool->base.funcs = &dcn30_res_pool_funcs;
2460
2461 /*************************************************
2462 * Resource + asic cap harcoding *
2463 *************************************************/
2464 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2465 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2466 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2467 dc->caps.max_downscale_ratio = 600;
2468 dc->caps.i2c_speed_in_khz = 100;
2469 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2470 dc->caps.max_cursor_size = 256;
2471 dc->caps.min_horizontal_blanking_period = 80;
2472 dc->caps.dmdata_alloc_size = 2048;
2473 dc->caps.mall_size_per_mem_channel = 8;
2474 /* total size = mall per channel * num channels * 1024 * 1024 */
2475 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2476 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2477
2478 dc->caps.max_slave_planes = 2;
2479 dc->caps.max_slave_yuv_planes = 2;
2480 dc->caps.max_slave_rgb_planes = 2;
2481 dc->caps.post_blend_color_processing = true;
2482 dc->caps.force_dp_tps4_for_cp2520 = true;
2483 dc->caps.hdmi_hpo = true;
2484 dc->caps.extended_aux_timeout_support = true;
2485 dc->caps.dmcub_support = true;
2486
2487 /* Color pipeline capabilities */
2488 dc->caps.color.dpp.dcn_arch = 1;
2489 dc->caps.color.dpp.input_lut_shared = 0;
2490 dc->caps.color.dpp.icsc = 1;
2491 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2492 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2493 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2494 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2495 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2496 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2497 dc->caps.color.dpp.post_csc = 1;
2498 dc->caps.color.dpp.gamma_corr = 1;
2499 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2500 dc->caps.color.dpp.upsp_pre_scaler = 0;
2501
2502 dc->caps.color.dpp.hw_3d_lut = 1;
2503 dc->caps.color.dpp.ogam_ram = 1;
2504 // no OGAM ROM on DCN3
2505 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2506 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2507 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2508 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2509 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2510 dc->caps.color.dpp.ocsc = 0;
2511
2512 dc->caps.color.mpc.gamut_remap = 1;
2513 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
2514 dc->caps.color.mpc.ogam_ram = 1;
2515 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2516 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2517 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2518 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2519 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2520 dc->caps.color.mpc.ocsc = 1;
2521 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2522
2523 dc->caps.dp_hdmi21_pcon_support = true;
2524 dc->caps.max_v_total = (1 << 15) - 1;
2525 dc->caps.vtotal_limited_by_fp2 = true;
2526
2527 /* read VBIOS LTTPR caps */
2528 {
2529 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2530 enum bp_result bp_query_result;
2531 uint8_t is_vbios_lttpr_enable = 0;
2532
2533 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2534 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2535 }
2536
2537 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2538 enum bp_result bp_query_result;
2539 uint8_t is_vbios_interop_enabled = 0;
2540
2541 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2542 &is_vbios_interop_enabled);
2543 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2544 }
2545 }
2546 dc->check_config = config_defaults;
2547
2548 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2549 dc->debug = debug_defaults_drv;
2550
2551 // Init the vm_helper
2552 if (dc->vm_helper)
2553 vm_helper_init(dc->vm_helper, 16);
2554
2555 /*************************************************
2556 * Create resources *
2557 *************************************************/
2558
2559 /* Clock Sources for Pixel Clock*/
2560 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2561 dcn30_clock_source_create(ctx, ctx->dc_bios,
2562 CLOCK_SOURCE_COMBO_PHY_PLL0,
2563 &clk_src_regs[0], false);
2564 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2565 dcn30_clock_source_create(ctx, ctx->dc_bios,
2566 CLOCK_SOURCE_COMBO_PHY_PLL1,
2567 &clk_src_regs[1], false);
2568 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2569 dcn30_clock_source_create(ctx, ctx->dc_bios,
2570 CLOCK_SOURCE_COMBO_PHY_PLL2,
2571 &clk_src_regs[2], false);
2572 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2573 dcn30_clock_source_create(ctx, ctx->dc_bios,
2574 CLOCK_SOURCE_COMBO_PHY_PLL3,
2575 &clk_src_regs[3], false);
2576 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2577 dcn30_clock_source_create(ctx, ctx->dc_bios,
2578 CLOCK_SOURCE_COMBO_PHY_PLL4,
2579 &clk_src_regs[4], false);
2580 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2581 dcn30_clock_source_create(ctx, ctx->dc_bios,
2582 CLOCK_SOURCE_COMBO_PHY_PLL5,
2583 &clk_src_regs[5], false);
2584
2585 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2586
2587 /* todo: not reuse phy_pll registers */
2588 pool->base.dp_clock_source =
2589 dcn30_clock_source_create(ctx, ctx->dc_bios,
2590 CLOCK_SOURCE_ID_DP_DTO,
2591 &clk_src_regs[0], true);
2592
2593 for (i = 0; i < pool->base.clk_src_count; i++) {
2594 if (pool->base.clock_sources[i] == NULL) {
2595 dm_error("DC: failed to create clock sources!\n");
2596 BREAK_TO_DEBUGGER();
2597 goto create_fail;
2598 }
2599 }
2600
2601 /* DCCG */
2602 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2603 if (pool->base.dccg == NULL) {
2604 dm_error("DC: failed to create dccg!\n");
2605 BREAK_TO_DEBUGGER();
2606 goto create_fail;
2607 }
2608
2609 /* PP Lib and SMU interfaces */
2610 init_soc_bounding_box(dc, pool);
2611
2612 num_pipes = dcn3_0_ip.max_num_dpp;
2613
2614 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2615 if (pipe_fuses & 1 << i)
2616 num_pipes--;
2617
2618 dcn3_0_ip.max_num_dpp = num_pipes;
2619 dcn3_0_ip.max_num_otg = num_pipes;
2620
2621 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2622
2623 /* IRQ */
2624 init_data.ctx = dc->ctx;
2625 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2626 if (!pool->base.irqs)
2627 goto create_fail;
2628
2629 /* HUBBUB */
2630 pool->base.hubbub = dcn30_hubbub_create(ctx);
2631 if (pool->base.hubbub == NULL) {
2632 BREAK_TO_DEBUGGER();
2633 dm_error("DC: failed to create hubbub!\n");
2634 goto create_fail;
2635 }
2636
2637 /* DIO */
2638 pool->base.dio = dcn30_dio_create(ctx);
2639 if (pool->base.dio == NULL) {
2640 BREAK_TO_DEBUGGER();
2641 dm_error("DC: failed to create dio!\n");
2642 goto create_fail;
2643 }
2644
2645 /* HUBPs, DPPs, OPPs and TGs */
2646 for (i = 0; i < pool->base.pipe_count; i++) {
2647 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2648 if (pool->base.hubps[i] == NULL) {
2649 BREAK_TO_DEBUGGER();
2650 dm_error(
2651 "DC: failed to create hubps!\n");
2652 goto create_fail;
2653 }
2654
2655 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2656 if (pool->base.dpps[i] == NULL) {
2657 BREAK_TO_DEBUGGER();
2658 dm_error(
2659 "DC: failed to create dpps!\n");
2660 goto create_fail;
2661 }
2662 }
2663
2664 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
2665 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2666 if (pool->base.opps[i] == NULL) {
2667 BREAK_TO_DEBUGGER();
2668 dm_error(
2669 "DC: failed to create output pixel processor!\n");
2670 goto create_fail;
2671 }
2672 }
2673
2674 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
2675 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2676 ctx, i);
2677 if (pool->base.timing_generators[i] == NULL) {
2678 BREAK_TO_DEBUGGER();
2679 dm_error("DC: failed to create tg!\n");
2680 goto create_fail;
2681 }
2682 }
2683 pool->base.timing_generator_count = i;
2684 /* PSR */
2685 pool->base.psr = dmub_psr_create(ctx);
2686
2687 if (pool->base.psr == NULL) {
2688 dm_error("DC: failed to create PSR obj!\n");
2689 BREAK_TO_DEBUGGER();
2690 goto create_fail;
2691 }
2692
2693 /* ABM */
2694 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
2695 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2696 &abm_regs[i],
2697 &abm_shift,
2698 &abm_mask);
2699 if (pool->base.multiple_abms[i] == NULL) {
2700 dm_error("DC: failed to create abm for pipe %u!\n", i);
2701 BREAK_TO_DEBUGGER();
2702 goto create_fail;
2703 }
2704 }
2705 /* MPC and DSC */
2706 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2707 if (pool->base.mpc == NULL) {
2708 BREAK_TO_DEBUGGER();
2709 dm_error("DC: failed to create mpc!\n");
2710 goto create_fail;
2711 }
2712
2713 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
2714 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2715 if (pool->base.dscs[i] == NULL) {
2716 BREAK_TO_DEBUGGER();
2717 dm_error("DC: failed to create display stream compressor %u!\n", i);
2718 goto create_fail;
2719 }
2720 }
2721
2722 /* DWB and MMHUBBUB */
2723 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2724 BREAK_TO_DEBUGGER();
2725 dm_error("DC: failed to create dwbc!\n");
2726 goto create_fail;
2727 }
2728
2729 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2730 BREAK_TO_DEBUGGER();
2731 dm_error("DC: failed to create mcif_wb!\n");
2732 goto create_fail;
2733 }
2734
2735 /* AUX and I2C */
2736 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
2737 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2738 if (pool->base.engines[i] == NULL) {
2739 BREAK_TO_DEBUGGER();
2740 dm_error(
2741 "DC:failed to create aux engine!!\n");
2742 goto create_fail;
2743 }
2744 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2745 if (pool->base.hw_i2cs[i] == NULL) {
2746 BREAK_TO_DEBUGGER();
2747 dm_error(
2748 "DC:failed to create hw i2c!!\n");
2749 goto create_fail;
2750 }
2751 pool->base.sw_i2cs[i] = NULL;
2752 }
2753
2754 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2755 if (!resource_construct(num_virtual_links, dc, &pool->base,
2756 &res_create_funcs))
2757 goto create_fail;
2758
2759 /* HW Sequencer and Plane caps */
2760 dcn30_hw_sequencer_construct(dc);
2761
2762 dc->caps.max_planes = pool->base.pipe_count;
2763
2764 for (i = 0; i < dc->caps.max_planes; ++i)
2765 dc->caps.planes[i] = plane_cap;
2766
2767 dc->caps.max_odm_combine_factor = 4;
2768
2769 dc->cap_funcs = cap_funcs;
2770
2771 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2772 ddc_init_data.ctx = dc->ctx;
2773 ddc_init_data.link = NULL;
2774 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2775 ddc_init_data.id.enum_id = 0;
2776 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2777 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2778 } else {
2779 pool->base.oem_device = NULL;
2780 }
2781
2782 DC_FP_END();
2783
2784 return true;
2785
2786 create_fail:
2787
2788 DC_FP_END();
2789 dcn30_resource_destruct(pool);
2790
2791 return false;
2792 }
2793
dcn30_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2794 struct resource_pool *dcn30_create_resource_pool(
2795 const struct dc_init_data *init_data,
2796 struct dc *dc)
2797 {
2798 struct dcn30_resource_pool *pool =
2799 kzalloc_obj(struct dcn30_resource_pool);
2800
2801 if (!pool)
2802 return NULL;
2803
2804 if (dcn30_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2805 return &pool->base;
2806
2807 BREAK_TO_DEBUGGER();
2808 kfree(pool);
2809 return NULL;
2810 }
2811