1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51
52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
56
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA3_REG_OFFSET 0x400
59 #define SDMA0_HYP_DEC_REG_START 0x5880
60 #define SDMA0_HYP_DEC_REG_END 0x5893
61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
62
63 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = {
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
109 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
110 };
111
112 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
113 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
114 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
115 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
116
sdma_v5_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)117 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
118 {
119 u32 base;
120
121 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
122 internal_offset <= SDMA0_HYP_DEC_REG_END) {
123 base = adev->reg_offset[GC_HWIP][0][1];
124 if (instance != 0)
125 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
126 } else {
127 if (instance < 2) {
128 base = adev->reg_offset[GC_HWIP][0][0];
129 if (instance == 1)
130 internal_offset += SDMA1_REG_OFFSET;
131 } else {
132 base = adev->reg_offset[GC_HWIP][0][2];
133 if (instance == 3)
134 internal_offset += SDMA3_REG_OFFSET;
135 }
136 }
137
138 return base + internal_offset;
139 }
140
sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)141 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring,
142 uint64_t addr)
143 {
144 unsigned ret;
145
146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
147 amdgpu_ring_write(ring, lower_32_bits(addr));
148 amdgpu_ring_write(ring, upper_32_bits(addr));
149 amdgpu_ring_write(ring, 1);
150 /* this is the offset we need patch later */
151 ret = ring->wptr & ring->buf_mask;
152 /* insert dummy here and patch it later */
153 amdgpu_ring_write(ring, 0);
154
155 return ret;
156 }
157
158 /**
159 * sdma_v5_2_ring_get_rptr - get the current read pointer
160 *
161 * @ring: amdgpu ring pointer
162 *
163 * Get the current rptr from the hardware (NAVI10+).
164 */
sdma_v5_2_ring_get_rptr(struct amdgpu_ring * ring)165 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
166 {
167 u64 *rptr;
168
169 /* XXX check if swapping is necessary on BE */
170 rptr = (u64 *)ring->rptr_cpu_addr;
171
172 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
173 return ((*rptr) >> 2);
174 }
175
176 /**
177 * sdma_v5_2_ring_get_wptr - get the current write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Get the current wptr from the hardware (NAVI10+).
182 */
sdma_v5_2_ring_get_wptr(struct amdgpu_ring * ring)183 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
184 {
185 struct amdgpu_device *adev = ring->adev;
186 u64 wptr;
187
188 if (ring->use_doorbell) {
189 /* XXX check if swapping is necessary on BE */
190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
192 } else {
193 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
194 wptr = wptr << 32;
195 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
196 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
197 }
198
199 return wptr >> 2;
200 }
201
202 /**
203 * sdma_v5_2_ring_set_wptr - commit the write pointer
204 *
205 * @ring: amdgpu ring pointer
206 *
207 * Write the wptr back to the hardware (NAVI10+).
208 */
sdma_v5_2_ring_set_wptr(struct amdgpu_ring * ring)209 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
210 {
211 struct amdgpu_device *adev = ring->adev;
212
213 DRM_DEBUG("Setting write pointer\n");
214 if (ring->use_doorbell) {
215 DRM_DEBUG("Using doorbell -- "
216 "wptr_offs == 0x%08x "
217 "lower_32_bits(ring->wptr << 2) == 0x%08x "
218 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
219 ring->wptr_offs,
220 lower_32_bits(ring->wptr << 2),
221 upper_32_bits(ring->wptr << 2));
222 /* XXX check if swapping is necessary on BE */
223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
224 ring->wptr << 2);
225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
226 ring->doorbell_index, ring->wptr << 2);
227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
228 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) {
229 /* SDMA seems to miss doorbells sometimes when powergating kicks in.
230 * Updating the wptr directly will wake it. This is only safe because
231 * we disallow gfxoff in begin_use() and then allow it again in end_use().
232 */
233 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
234 lower_32_bits(ring->wptr << 2));
235 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
236 upper_32_bits(ring->wptr << 2));
237 }
238 } else {
239 DRM_DEBUG("Not using doorbell -- "
240 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
241 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
242 ring->me,
243 lower_32_bits(ring->wptr << 2),
244 ring->me,
245 upper_32_bits(ring->wptr << 2));
246 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
247 lower_32_bits(ring->wptr << 2));
248 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
249 upper_32_bits(ring->wptr << 2));
250 }
251 }
252
sdma_v5_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)253 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
254 {
255 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
256 int i;
257
258 for (i = 0; i < count; i++)
259 if (sdma && sdma->burst_nop && (i == 0))
260 amdgpu_ring_write(ring, ring->funcs->nop |
261 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
262 else
263 amdgpu_ring_write(ring, ring->funcs->nop);
264 }
265
266 /**
267 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
268 *
269 * @ring: amdgpu ring pointer
270 * @job: job to retrieve vmid from
271 * @ib: IB object to schedule
272 * @flags: unused
273 *
274 * Schedule an IB in the DMA ring.
275 */
sdma_v5_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)276 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
277 struct amdgpu_job *job,
278 struct amdgpu_ib *ib,
279 uint32_t flags)
280 {
281 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
282 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
283
284 /* An IB packet must end on a 8 DW boundary--the next dword
285 * must be on a 8-dword boundary. Our IB packet below is 6
286 * dwords long, thus add x number of NOPs, such that, in
287 * modular arithmetic,
288 * wptr + 6 + x = 8k, k >= 0, which in C is,
289 * (wptr + 6 + x) % 8 = 0.
290 * The expression below, is a solution of x.
291 */
292 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
293
294 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
295 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
296 /* base must be 32 byte aligned */
297 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
298 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
299 amdgpu_ring_write(ring, ib->length_dw);
300 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
301 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
302 }
303
304 /**
305 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
306 *
307 * @ring: amdgpu ring pointer
308 *
309 * flush the IB by graphics cache rinse.
310 */
sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring * ring)311 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
312 {
313 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
314 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
315 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
316 SDMA_GCR_GLI_INV(1);
317
318 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
320 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
321 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
322 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
323 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
324 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
325 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
326 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
327 }
328
329 /**
330 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
331 *
332 * @ring: amdgpu ring pointer
333 *
334 * Emit an hdp flush packet on the requested DMA ring.
335 */
sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)336 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
337 {
338 struct amdgpu_device *adev = ring->adev;
339 u32 ref_and_mask = 0;
340 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
341
342 if (ring->me > 1) {
343 amdgpu_asic_flush_hdp(adev, ring);
344 } else {
345 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
346
347 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
348 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
349 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
350 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
351 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
352 amdgpu_ring_write(ring, ref_and_mask); /* reference */
353 amdgpu_ring_write(ring, ref_and_mask); /* mask */
354 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
355 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
356 }
357 }
358
359 /**
360 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
361 *
362 * @ring: amdgpu ring pointer
363 * @addr: address
364 * @seq: sequence number
365 * @flags: fence related flags
366 *
367 * Add a DMA fence packet to the ring to write
368 * the fence seq number and DMA trap packet to generate
369 * an interrupt if needed.
370 */
sdma_v5_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)371 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
372 unsigned flags)
373 {
374 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
375 /* write the fence */
376 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
377 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
378 /* zero in first two bits */
379 BUG_ON(addr & 0x3);
380 amdgpu_ring_write(ring, lower_32_bits(addr));
381 amdgpu_ring_write(ring, upper_32_bits(addr));
382 amdgpu_ring_write(ring, lower_32_bits(seq));
383
384 /* optionally write high bits as well */
385 if (write64bit) {
386 addr += 4;
387 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
388 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
389 /* zero in first two bits */
390 BUG_ON(addr & 0x3);
391 amdgpu_ring_write(ring, lower_32_bits(addr));
392 amdgpu_ring_write(ring, upper_32_bits(addr));
393 amdgpu_ring_write(ring, upper_32_bits(seq));
394 }
395
396 if ((flags & AMDGPU_FENCE_FLAG_INT)) {
397 uint32_t ctx = ring->is_mes_queue ?
398 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
399 /* generate an interrupt */
400 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
401 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
402 }
403 }
404
405
406 /**
407 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
408 *
409 * @adev: amdgpu_device pointer
410 *
411 * Stop the gfx async dma ring buffers.
412 */
sdma_v5_2_gfx_stop(struct amdgpu_device * adev)413 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
414 {
415 u32 rb_cntl, ib_cntl;
416 int i;
417
418 for (i = 0; i < adev->sdma.num_instances; i++) {
419 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
420 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
421 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
422 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
423 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
424 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
425 }
426 }
427
428 /**
429 * sdma_v5_2_rlc_stop - stop the compute async dma engines
430 *
431 * @adev: amdgpu_device pointer
432 *
433 * Stop the compute async dma queues.
434 */
sdma_v5_2_rlc_stop(struct amdgpu_device * adev)435 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
436 {
437 /* XXX todo */
438 }
439
440 /**
441 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
442 *
443 * @adev: amdgpu_device pointer
444 * @enable: enable/disable the DMA MEs context switch.
445 *
446 * Halt or unhalt the async dma engines context switch.
447 */
sdma_v5_2_ctx_switch_enable(struct amdgpu_device * adev,bool enable)448 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
449 {
450 u32 f32_cntl, phase_quantum = 0;
451 int i;
452
453 if (amdgpu_sdma_phase_quantum) {
454 unsigned value = amdgpu_sdma_phase_quantum;
455 unsigned unit = 0;
456
457 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
458 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
459 value = (value + 1) >> 1;
460 unit++;
461 }
462 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
463 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
464 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
465 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
466 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
467 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
468 WARN_ONCE(1,
469 "clamping sdma_phase_quantum to %uK clock cycles\n",
470 value << unit);
471 }
472 phase_quantum =
473 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
474 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
475 }
476
477 for (i = 0; i < adev->sdma.num_instances; i++) {
478 if (enable && amdgpu_sdma_phase_quantum) {
479 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
480 phase_quantum);
481 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
482 phase_quantum);
483 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
484 phase_quantum);
485 }
486
487 if (!amdgpu_sriov_vf(adev)) {
488 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
490 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
491 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
492 }
493 }
494
495 }
496
497 /**
498 * sdma_v5_2_enable - stop the async dma engines
499 *
500 * @adev: amdgpu_device pointer
501 * @enable: enable/disable the DMA MEs.
502 *
503 * Halt or unhalt the async dma engines.
504 */
sdma_v5_2_enable(struct amdgpu_device * adev,bool enable)505 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
506 {
507 u32 f32_cntl;
508 int i;
509
510 if (!enable) {
511 sdma_v5_2_gfx_stop(adev);
512 sdma_v5_2_rlc_stop(adev);
513 }
514
515 if (!amdgpu_sriov_vf(adev)) {
516 for (i = 0; i < adev->sdma.num_instances; i++) {
517 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
518 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
519 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
520 }
521 }
522 }
523
524 /**
525 * sdma_v5_2_gfx_resume - setup and start the async dma engines
526 *
527 * @adev: amdgpu_device pointer
528 *
529 * Set up the gfx DMA ring buffers and enable them.
530 * Returns 0 for success, error for failure.
531 */
sdma_v5_2_gfx_resume(struct amdgpu_device * adev)532 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
533 {
534 struct amdgpu_ring *ring;
535 u32 rb_cntl, ib_cntl;
536 u32 rb_bufsz;
537 u32 doorbell;
538 u32 doorbell_offset;
539 u32 temp;
540 u32 wptr_poll_cntl;
541 u64 wptr_gpu_addr;
542 int i, r;
543
544 for (i = 0; i < adev->sdma.num_instances; i++) {
545 ring = &adev->sdma.instance[i].ring;
546
547 if (!amdgpu_sriov_vf(adev))
548 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
549
550 /* Set ring buffer size in dwords */
551 rb_bufsz = order_base_2(ring->ring_size / 4);
552 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
554 #ifdef __BIG_ENDIAN
555 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
556 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
557 RPTR_WRITEBACK_SWAP_ENABLE, 1);
558 #endif
559 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
560
561 /* Initialize the ring buffer's read and write pointers */
562 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
563 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
564 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
565 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
566
567 /* setup the wptr shadow polling */
568 wptr_gpu_addr = ring->wptr_gpu_addr;
569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
570 lower_32_bits(wptr_gpu_addr));
571 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
572 upper_32_bits(wptr_gpu_addr));
573 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
574 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
575 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
576 SDMA0_GFX_RB_WPTR_POLL_CNTL,
577 F32_POLL_ENABLE, 1);
578 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
579 wptr_poll_cntl);
580
581 /* set the wb address whether it's enabled or not */
582 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
583 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
584 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
585 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
586
587 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
588
589 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
590 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
591
592 ring->wptr = 0;
593
594 /* before programing wptr to a less value, need set minor_ptr_update first */
595 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
596
597 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
598 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
599 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
600 }
601
602 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
603 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
604
605 if (ring->use_doorbell) {
606 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
607 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
608 OFFSET, ring->doorbell_index);
609 } else {
610 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
611 }
612 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
613 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
614
615 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
616 ring->doorbell_index,
617 adev->doorbell_index.sdma_doorbell_range);
618
619 if (amdgpu_sriov_vf(adev))
620 sdma_v5_2_ring_set_wptr(ring);
621
622 /* set minor_ptr_update to 0 after wptr programed */
623
624 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
625
626 /* SRIOV VF has no control of any of registers below */
627 if (!amdgpu_sriov_vf(adev)) {
628 /* set utc l1 enable flag always to 1 */
629 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
630 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
631
632 /* enable MCBP */
633 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
634 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
635
636 /* Set up RESP_MODE to non-copy addresses */
637 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
638 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
639 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
640 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
641
642 /* program default cache read and write policy */
643 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
644 /* clean read policy and write policy bits */
645 temp &= 0xFF0FFF;
646 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
647 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
648 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
650
651 /* unhalt engine */
652 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
653 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
654 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
655 }
656
657 /* enable DMA RB */
658 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
659 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
660
661 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
662 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
663 #ifdef __BIG_ENDIAN
664 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
665 #endif
666 /* enable DMA IBs */
667 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
668
669 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
670 sdma_v5_2_ctx_switch_enable(adev, true);
671 sdma_v5_2_enable(adev, true);
672 }
673
674 r = amdgpu_ring_test_helper(ring);
675 if (r)
676 return r;
677 }
678
679 return 0;
680 }
681
682 /**
683 * sdma_v5_2_rlc_resume - setup and start the async dma engines
684 *
685 * @adev: amdgpu_device pointer
686 *
687 * Set up the compute DMA queues and enable them.
688 * Returns 0 for success, error for failure.
689 */
sdma_v5_2_rlc_resume(struct amdgpu_device * adev)690 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
691 {
692 return 0;
693 }
694
695 /**
696 * sdma_v5_2_load_microcode - load the sDMA ME ucode
697 *
698 * @adev: amdgpu_device pointer
699 *
700 * Loads the sDMA0/1/2/3 ucode.
701 * Returns 0 for success, -EINVAL if the ucode is not available.
702 */
sdma_v5_2_load_microcode(struct amdgpu_device * adev)703 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
704 {
705 const struct sdma_firmware_header_v1_0 *hdr;
706 const __le32 *fw_data;
707 u32 fw_size;
708 int i, j;
709
710 /* halt the MEs */
711 sdma_v5_2_enable(adev, false);
712
713 for (i = 0; i < adev->sdma.num_instances; i++) {
714 if (!adev->sdma.instance[i].fw)
715 return -EINVAL;
716
717 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
718 amdgpu_ucode_print_sdma_hdr(&hdr->header);
719 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
720
721 fw_data = (const __le32 *)
722 (adev->sdma.instance[i].fw->data +
723 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
724
725 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
726
727 for (j = 0; j < fw_size; j++) {
728 if (amdgpu_emu_mode == 1 && j % 500 == 0)
729 msleep(1);
730 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
731 }
732
733 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
734 }
735
736 return 0;
737 }
738
sdma_v5_2_soft_reset(void * handle)739 static int sdma_v5_2_soft_reset(void *handle)
740 {
741 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
742 u32 grbm_soft_reset;
743 u32 tmp;
744 int i;
745
746 for (i = 0; i < adev->sdma.num_instances; i++) {
747 grbm_soft_reset = REG_SET_FIELD(0,
748 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
749 1);
750 grbm_soft_reset <<= i;
751
752 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
753 tmp |= grbm_soft_reset;
754 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
755 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
756 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
757
758 udelay(50);
759
760 tmp &= ~grbm_soft_reset;
761 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
762 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
763
764 udelay(50);
765 }
766
767 return 0;
768 }
769
770 /**
771 * sdma_v5_2_start - setup and start the async dma engines
772 *
773 * @adev: amdgpu_device pointer
774 *
775 * Set up the DMA engines and enable them.
776 * Returns 0 for success, error for failure.
777 */
sdma_v5_2_start(struct amdgpu_device * adev)778 static int sdma_v5_2_start(struct amdgpu_device *adev)
779 {
780 int r = 0;
781
782 if (amdgpu_sriov_vf(adev)) {
783 sdma_v5_2_ctx_switch_enable(adev, false);
784 sdma_v5_2_enable(adev, false);
785
786 /* set RB registers */
787 r = sdma_v5_2_gfx_resume(adev);
788 return r;
789 }
790
791 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
792 r = sdma_v5_2_load_microcode(adev);
793 if (r)
794 return r;
795
796 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
797 if (amdgpu_emu_mode == 1)
798 msleep(1000);
799 }
800
801 sdma_v5_2_soft_reset(adev);
802 /* unhalt the MEs */
803 sdma_v5_2_enable(adev, true);
804 /* enable sdma ring preemption */
805 sdma_v5_2_ctx_switch_enable(adev, true);
806
807 /* start the gfx rings and rlc compute queues */
808 r = sdma_v5_2_gfx_resume(adev);
809 if (r)
810 return r;
811 r = sdma_v5_2_rlc_resume(adev);
812
813 return r;
814 }
815
sdma_v5_2_mqd_init(struct amdgpu_device * adev,void * mqd,struct amdgpu_mqd_prop * prop)816 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
817 struct amdgpu_mqd_prop *prop)
818 {
819 struct v10_sdma_mqd *m = mqd;
820 uint64_t wb_gpu_addr;
821
822 m->sdmax_rlcx_rb_cntl =
823 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
824 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
825 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
826 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
827
828 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
829 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
830
831 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
832 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
833
834 wb_gpu_addr = prop->wptr_gpu_addr;
835 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
836 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
837
838 wb_gpu_addr = prop->rptr_gpu_addr;
839 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
840 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
841
842 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
843 mmSDMA0_GFX_IB_CNTL));
844
845 m->sdmax_rlcx_doorbell_offset =
846 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
847
848 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
849
850 return 0;
851 }
852
sdma_v5_2_set_mqd_funcs(struct amdgpu_device * adev)853 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
854 {
855 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
856 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
857 }
858
859 /**
860 * sdma_v5_2_ring_test_ring - simple async dma engine test
861 *
862 * @ring: amdgpu_ring structure holding ring information
863 *
864 * Test the DMA engine by writing using it to write an
865 * value to memory.
866 * Returns 0 for success, error for failure.
867 */
sdma_v5_2_ring_test_ring(struct amdgpu_ring * ring)868 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
869 {
870 struct amdgpu_device *adev = ring->adev;
871 unsigned i;
872 unsigned index;
873 int r;
874 u32 tmp;
875 u64 gpu_addr;
876 volatile uint32_t *cpu_ptr = NULL;
877
878 tmp = 0xCAFEDEAD;
879
880 if (ring->is_mes_queue) {
881 uint32_t offset = 0;
882 offset = amdgpu_mes_ctx_get_offs(ring,
883 AMDGPU_MES_CTX_PADDING_OFFS);
884 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
885 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
886 *cpu_ptr = tmp;
887 } else {
888 r = amdgpu_device_wb_get(adev, &index);
889 if (r) {
890 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
891 return r;
892 }
893
894 gpu_addr = adev->wb.gpu_addr + (index * 4);
895 adev->wb.wb[index] = cpu_to_le32(tmp);
896 }
897
898 r = amdgpu_ring_alloc(ring, 20);
899 if (r) {
900 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
901 if (!ring->is_mes_queue)
902 amdgpu_device_wb_free(adev, index);
903 return r;
904 }
905
906 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
907 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
908 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
909 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
910 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
911 amdgpu_ring_write(ring, 0xDEADBEEF);
912 amdgpu_ring_commit(ring);
913
914 for (i = 0; i < adev->usec_timeout; i++) {
915 if (ring->is_mes_queue)
916 tmp = le32_to_cpu(*cpu_ptr);
917 else
918 tmp = le32_to_cpu(adev->wb.wb[index]);
919 if (tmp == 0xDEADBEEF)
920 break;
921 if (amdgpu_emu_mode == 1)
922 msleep(1);
923 else
924 udelay(1);
925 }
926
927 if (i >= adev->usec_timeout)
928 r = -ETIMEDOUT;
929
930 if (!ring->is_mes_queue)
931 amdgpu_device_wb_free(adev, index);
932
933 return r;
934 }
935
936 /**
937 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
938 *
939 * @ring: amdgpu_ring structure holding ring information
940 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
941 *
942 * Test a simple IB in the DMA ring.
943 * Returns 0 on success, error on failure.
944 */
sdma_v5_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)945 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
946 {
947 struct amdgpu_device *adev = ring->adev;
948 struct amdgpu_ib ib;
949 struct dma_fence *f = NULL;
950 unsigned index;
951 long r;
952 u32 tmp = 0;
953 u64 gpu_addr;
954 volatile uint32_t *cpu_ptr = NULL;
955
956 tmp = 0xCAFEDEAD;
957 memset(&ib, 0, sizeof(ib));
958
959 if (ring->is_mes_queue) {
960 uint32_t offset = 0;
961 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
962 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
963 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
964
965 offset = amdgpu_mes_ctx_get_offs(ring,
966 AMDGPU_MES_CTX_PADDING_OFFS);
967 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
968 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
969 *cpu_ptr = tmp;
970 } else {
971 r = amdgpu_device_wb_get(adev, &index);
972 if (r) {
973 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
974 return r;
975 }
976
977 gpu_addr = adev->wb.gpu_addr + (index * 4);
978 adev->wb.wb[index] = cpu_to_le32(tmp);
979
980 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
981 if (r) {
982 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
983 goto err0;
984 }
985 }
986
987 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
988 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
989 ib.ptr[1] = lower_32_bits(gpu_addr);
990 ib.ptr[2] = upper_32_bits(gpu_addr);
991 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
992 ib.ptr[4] = 0xDEADBEEF;
993 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
994 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
995 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
996 ib.length_dw = 8;
997
998 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
999 if (r)
1000 goto err1;
1001
1002 r = dma_fence_wait_timeout(f, false, timeout);
1003 if (r == 0) {
1004 DRM_ERROR("amdgpu: IB test timed out\n");
1005 r = -ETIMEDOUT;
1006 goto err1;
1007 } else if (r < 0) {
1008 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1009 goto err1;
1010 }
1011
1012 if (ring->is_mes_queue)
1013 tmp = le32_to_cpu(*cpu_ptr);
1014 else
1015 tmp = le32_to_cpu(adev->wb.wb[index]);
1016
1017 if (tmp == 0xDEADBEEF)
1018 r = 0;
1019 else
1020 r = -EINVAL;
1021
1022 err1:
1023 amdgpu_ib_free(adev, &ib, NULL);
1024 dma_fence_put(f);
1025 err0:
1026 if (!ring->is_mes_queue)
1027 amdgpu_device_wb_free(adev, index);
1028 return r;
1029 }
1030
1031
1032 /**
1033 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1034 *
1035 * @ib: indirect buffer to fill with commands
1036 * @pe: addr of the page entry
1037 * @src: src addr to copy from
1038 * @count: number of page entries to update
1039 *
1040 * Update PTEs by copying them from the GART using sDMA.
1041 */
sdma_v5_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1042 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1043 uint64_t pe, uint64_t src,
1044 unsigned count)
1045 {
1046 unsigned bytes = count * 8;
1047
1048 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1049 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1050 ib->ptr[ib->length_dw++] = bytes - 1;
1051 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1052 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1053 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1054 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1055 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1056
1057 }
1058
1059 /**
1060 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1061 *
1062 * @ib: indirect buffer to fill with commands
1063 * @pe: addr of the page entry
1064 * @value: dst addr to write into pe
1065 * @count: number of page entries to update
1066 * @incr: increase next addr by incr bytes
1067 *
1068 * Update PTEs by writing them manually using sDMA.
1069 */
sdma_v5_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1070 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1071 uint64_t value, unsigned count,
1072 uint32_t incr)
1073 {
1074 unsigned ndw = count * 2;
1075
1076 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1077 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1078 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1079 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1080 ib->ptr[ib->length_dw++] = ndw - 1;
1081 for (; ndw > 0; ndw -= 2) {
1082 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1083 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1084 value += incr;
1085 }
1086 }
1087
1088 /**
1089 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1090 *
1091 * @ib: indirect buffer to fill with commands
1092 * @pe: addr of the page entry
1093 * @addr: dst addr to write into pe
1094 * @count: number of page entries to update
1095 * @incr: increase next addr by incr bytes
1096 * @flags: access flags
1097 *
1098 * Update the page tables using sDMA.
1099 */
sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1100 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1101 uint64_t pe,
1102 uint64_t addr, unsigned count,
1103 uint32_t incr, uint64_t flags)
1104 {
1105 /* for physically contiguous pages (vram) */
1106 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1107 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1108 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1109 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1110 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1111 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1112 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1113 ib->ptr[ib->length_dw++] = incr; /* increment size */
1114 ib->ptr[ib->length_dw++] = 0;
1115 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1116 }
1117
1118 /**
1119 * sdma_v5_2_ring_pad_ib - pad the IB
1120 *
1121 * @ib: indirect buffer to fill with padding
1122 * @ring: amdgpu_ring structure holding ring information
1123 *
1124 * Pad the IB with NOPs to a boundary multiple of 8.
1125 */
sdma_v5_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1126 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1127 {
1128 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1129 u32 pad_count;
1130 int i;
1131
1132 pad_count = (-ib->length_dw) & 0x7;
1133 for (i = 0; i < pad_count; i++)
1134 if (sdma && sdma->burst_nop && (i == 0))
1135 ib->ptr[ib->length_dw++] =
1136 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1137 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1138 else
1139 ib->ptr[ib->length_dw++] =
1140 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1141 }
1142
1143
1144 /**
1145 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1146 *
1147 * @ring: amdgpu_ring pointer
1148 *
1149 * Make sure all previous operations are completed (CIK).
1150 */
sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1151 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1152 {
1153 uint32_t seq = ring->fence_drv.sync_seq;
1154 uint64_t addr = ring->fence_drv.gpu_addr;
1155
1156 /* wait for idle */
1157 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1158 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1159 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1160 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1161 amdgpu_ring_write(ring, addr & 0xfffffffc);
1162 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1163 amdgpu_ring_write(ring, seq); /* reference */
1164 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1165 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1166 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1167 }
1168
1169
1170 /**
1171 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1172 *
1173 * @ring: amdgpu_ring pointer
1174 * @vmid: vmid number to use
1175 * @pd_addr: address
1176 *
1177 * Update the page table base and flush the VM TLB
1178 * using sDMA.
1179 */
sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1180 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1181 unsigned vmid, uint64_t pd_addr)
1182 {
1183 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1184 }
1185
sdma_v5_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1186 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1187 uint32_t reg, uint32_t val)
1188 {
1189 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1190 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1191 amdgpu_ring_write(ring, reg);
1192 amdgpu_ring_write(ring, val);
1193 }
1194
sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1195 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1196 uint32_t val, uint32_t mask)
1197 {
1198 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1199 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1200 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1201 amdgpu_ring_write(ring, reg << 2);
1202 amdgpu_ring_write(ring, 0);
1203 amdgpu_ring_write(ring, val); /* reference */
1204 amdgpu_ring_write(ring, mask); /* mask */
1205 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1206 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1207 }
1208
sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1209 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1210 uint32_t reg0, uint32_t reg1,
1211 uint32_t ref, uint32_t mask)
1212 {
1213 amdgpu_ring_emit_wreg(ring, reg0, ref);
1214 /* wait for a cycle to reset vm_inv_eng*_ack */
1215 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1216 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1217 }
1218
sdma_v5_2_early_init(void * handle)1219 static int sdma_v5_2_early_init(void *handle)
1220 {
1221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222 int r;
1223
1224 r = amdgpu_sdma_init_microcode(adev, 0, true);
1225 if (r)
1226 return r;
1227
1228 sdma_v5_2_set_ring_funcs(adev);
1229 sdma_v5_2_set_buffer_funcs(adev);
1230 sdma_v5_2_set_vm_pte_funcs(adev);
1231 sdma_v5_2_set_irq_funcs(adev);
1232 sdma_v5_2_set_mqd_funcs(adev);
1233
1234 return 0;
1235 }
1236
sdma_v5_2_seq_to_irq_id(int seq_num)1237 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1238 {
1239 switch (seq_num) {
1240 case 0:
1241 return SOC15_IH_CLIENTID_SDMA0;
1242 case 1:
1243 return SOC15_IH_CLIENTID_SDMA1;
1244 case 2:
1245 return SOC15_IH_CLIENTID_SDMA2;
1246 case 3:
1247 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1248 default:
1249 break;
1250 }
1251 return -EINVAL;
1252 }
1253
sdma_v5_2_seq_to_trap_id(int seq_num)1254 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1255 {
1256 switch (seq_num) {
1257 case 0:
1258 return SDMA0_5_0__SRCID__SDMA_TRAP;
1259 case 1:
1260 return SDMA1_5_0__SRCID__SDMA_TRAP;
1261 case 2:
1262 return SDMA2_5_0__SRCID__SDMA_TRAP;
1263 case 3:
1264 return SDMA3_5_0__SRCID__SDMA_TRAP;
1265 default:
1266 break;
1267 }
1268 return -EINVAL;
1269 }
1270
sdma_v5_2_sw_init(void * handle)1271 static int sdma_v5_2_sw_init(void *handle)
1272 {
1273 struct amdgpu_ring *ring;
1274 int r, i;
1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1276 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
1277 uint32_t *ptr;
1278
1279 /* SDMA trap event */
1280 for (i = 0; i < adev->sdma.num_instances; i++) {
1281 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1282 sdma_v5_2_seq_to_trap_id(i),
1283 &adev->sdma.trap_irq);
1284 if (r)
1285 return r;
1286 }
1287
1288 for (i = 0; i < adev->sdma.num_instances; i++) {
1289 ring = &adev->sdma.instance[i].ring;
1290 ring->ring_obj = NULL;
1291 ring->use_doorbell = true;
1292 ring->me = i;
1293
1294 DRM_INFO("use_doorbell being set to: [%s]\n",
1295 ring->use_doorbell?"true":"false");
1296
1297 ring->doorbell_index =
1298 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1299
1300 ring->vm_hub = AMDGPU_GFXHUB(0);
1301 sprintf(ring->name, "sdma%d", i);
1302 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1303 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1304 AMDGPU_RING_PRIO_DEFAULT, NULL);
1305 if (r)
1306 return r;
1307 }
1308
1309 /* Allocate memory for SDMA IP Dump buffer */
1310 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1311 if (ptr)
1312 adev->sdma.ip_dump = ptr;
1313 else
1314 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1315
1316 return r;
1317 }
1318
sdma_v5_2_sw_fini(void * handle)1319 static int sdma_v5_2_sw_fini(void *handle)
1320 {
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322 int i;
1323
1324 for (i = 0; i < adev->sdma.num_instances; i++)
1325 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1326
1327 amdgpu_sdma_destroy_inst_ctx(adev, true);
1328
1329 kfree(adev->sdma.ip_dump);
1330
1331 return 0;
1332 }
1333
sdma_v5_2_hw_init(void * handle)1334 static int sdma_v5_2_hw_init(void *handle)
1335 {
1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337
1338 return sdma_v5_2_start(adev);
1339 }
1340
sdma_v5_2_hw_fini(void * handle)1341 static int sdma_v5_2_hw_fini(void *handle)
1342 {
1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345 if (amdgpu_sriov_vf(adev))
1346 return 0;
1347
1348 sdma_v5_2_ctx_switch_enable(adev, false);
1349 sdma_v5_2_enable(adev, false);
1350
1351 return 0;
1352 }
1353
sdma_v5_2_suspend(void * handle)1354 static int sdma_v5_2_suspend(void *handle)
1355 {
1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357
1358 return sdma_v5_2_hw_fini(adev);
1359 }
1360
sdma_v5_2_resume(void * handle)1361 static int sdma_v5_2_resume(void *handle)
1362 {
1363 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364
1365 return sdma_v5_2_hw_init(adev);
1366 }
1367
sdma_v5_2_is_idle(void * handle)1368 static bool sdma_v5_2_is_idle(void *handle)
1369 {
1370 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371 u32 i;
1372
1373 for (i = 0; i < adev->sdma.num_instances; i++) {
1374 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1375
1376 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1377 return false;
1378 }
1379
1380 return true;
1381 }
1382
sdma_v5_2_wait_for_idle(void * handle)1383 static int sdma_v5_2_wait_for_idle(void *handle)
1384 {
1385 unsigned i;
1386 u32 sdma0, sdma1, sdma2, sdma3;
1387 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1388
1389 for (i = 0; i < adev->usec_timeout; i++) {
1390 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1391 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1392 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1393 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1394
1395 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1396 return 0;
1397 udelay(1);
1398 }
1399 return -ETIMEDOUT;
1400 }
1401
sdma_v5_2_ring_preempt_ib(struct amdgpu_ring * ring)1402 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1403 {
1404 int i, r = 0;
1405 struct amdgpu_device *adev = ring->adev;
1406 u32 index = 0;
1407 u64 sdma_gfx_preempt;
1408
1409 amdgpu_sdma_get_index_from_ring(ring, &index);
1410 sdma_gfx_preempt =
1411 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1412
1413 /* assert preemption condition */
1414 amdgpu_ring_set_preempt_cond_exec(ring, false);
1415
1416 /* emit the trailing fence */
1417 ring->trail_seq += 1;
1418 amdgpu_ring_alloc(ring, 10);
1419 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1420 ring->trail_seq, 0);
1421 amdgpu_ring_commit(ring);
1422
1423 /* assert IB preemption */
1424 WREG32(sdma_gfx_preempt, 1);
1425
1426 /* poll the trailing fence */
1427 for (i = 0; i < adev->usec_timeout; i++) {
1428 if (ring->trail_seq ==
1429 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1430 break;
1431 udelay(1);
1432 }
1433
1434 if (i >= adev->usec_timeout) {
1435 r = -EINVAL;
1436 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1437 }
1438
1439 /* deassert IB preemption */
1440 WREG32(sdma_gfx_preempt, 0);
1441
1442 /* deassert the preemption condition */
1443 amdgpu_ring_set_preempt_cond_exec(ring, true);
1444 return r;
1445 }
1446
sdma_v5_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1447 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1448 struct amdgpu_irq_src *source,
1449 unsigned type,
1450 enum amdgpu_interrupt_state state)
1451 {
1452 u32 sdma_cntl;
1453 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1454
1455 if (!amdgpu_sriov_vf(adev)) {
1456 sdma_cntl = RREG32(reg_offset);
1457 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1458 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1459 WREG32(reg_offset, sdma_cntl);
1460 }
1461
1462 return 0;
1463 }
1464
sdma_v5_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1465 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1466 struct amdgpu_irq_src *source,
1467 struct amdgpu_iv_entry *entry)
1468 {
1469 uint32_t mes_queue_id = entry->src_data[0];
1470
1471 DRM_DEBUG("IH: SDMA trap\n");
1472
1473 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1474 struct amdgpu_mes_queue *queue;
1475
1476 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1477
1478 spin_lock(&adev->mes.queue_id_lock);
1479 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1480 if (queue) {
1481 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1482 amdgpu_fence_process(queue->ring);
1483 }
1484 spin_unlock(&adev->mes.queue_id_lock);
1485 return 0;
1486 }
1487
1488 switch (entry->client_id) {
1489 case SOC15_IH_CLIENTID_SDMA0:
1490 switch (entry->ring_id) {
1491 case 0:
1492 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1493 break;
1494 case 1:
1495 /* XXX compute */
1496 break;
1497 case 2:
1498 /* XXX compute */
1499 break;
1500 case 3:
1501 /* XXX page queue*/
1502 break;
1503 }
1504 break;
1505 case SOC15_IH_CLIENTID_SDMA1:
1506 switch (entry->ring_id) {
1507 case 0:
1508 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1509 break;
1510 case 1:
1511 /* XXX compute */
1512 break;
1513 case 2:
1514 /* XXX compute */
1515 break;
1516 case 3:
1517 /* XXX page queue*/
1518 break;
1519 }
1520 break;
1521 case SOC15_IH_CLIENTID_SDMA2:
1522 switch (entry->ring_id) {
1523 case 0:
1524 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1525 break;
1526 case 1:
1527 /* XXX compute */
1528 break;
1529 case 2:
1530 /* XXX compute */
1531 break;
1532 case 3:
1533 /* XXX page queue*/
1534 break;
1535 }
1536 break;
1537 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1538 switch (entry->ring_id) {
1539 case 0:
1540 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1541 break;
1542 case 1:
1543 /* XXX compute */
1544 break;
1545 case 2:
1546 /* XXX compute */
1547 break;
1548 case 3:
1549 /* XXX page queue*/
1550 break;
1551 }
1552 break;
1553 }
1554 return 0;
1555 }
1556
sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1557 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1558 struct amdgpu_irq_src *source,
1559 struct amdgpu_iv_entry *entry)
1560 {
1561 return 0;
1562 }
1563
sdma_v5_2_firmware_mgcg_support(struct amdgpu_device * adev,int i)1564 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev,
1565 int i)
1566 {
1567 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1568 case IP_VERSION(5, 2, 1):
1569 if (adev->sdma.instance[i].fw_version < 70)
1570 return false;
1571 break;
1572 case IP_VERSION(5, 2, 3):
1573 if (adev->sdma.instance[i].fw_version < 47)
1574 return false;
1575 break;
1576 case IP_VERSION(5, 2, 7):
1577 if (adev->sdma.instance[i].fw_version < 9)
1578 return false;
1579 break;
1580 default:
1581 return true;
1582 }
1583
1584 return true;
1585
1586 }
1587
sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1588 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1589 bool enable)
1590 {
1591 uint32_t data, def;
1592 int i;
1593
1594 for (i = 0; i < adev->sdma.num_instances; i++) {
1595
1596 if (!sdma_v5_2_firmware_mgcg_support(adev, i))
1597 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1598
1599 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1600 /* Enable sdma clock gating */
1601 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1602 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1603 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1604 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1605 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1606 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1607 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1608 if (def != data)
1609 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1610 } else {
1611 /* Disable sdma clock gating */
1612 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1613 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1614 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1615 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1616 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1617 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1618 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1619 if (def != data)
1620 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1621 }
1622 }
1623 }
1624
sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1625 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1626 bool enable)
1627 {
1628 uint32_t data, def;
1629 int i;
1630
1631 for (i = 0; i < adev->sdma.num_instances; i++) {
1632 if (adev->sdma.instance[i].fw_version < 70 &&
1633 amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
1634 IP_VERSION(5, 2, 1))
1635 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1636
1637 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1638 /* Enable sdma mem light sleep */
1639 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1640 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1641 if (def != data)
1642 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1643
1644 } else {
1645 /* Disable sdma mem light sleep */
1646 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1647 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1648 if (def != data)
1649 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1650
1651 }
1652 }
1653 }
1654
sdma_v5_2_set_clockgating_state(void * handle,enum amd_clockgating_state state)1655 static int sdma_v5_2_set_clockgating_state(void *handle,
1656 enum amd_clockgating_state state)
1657 {
1658 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1659
1660 if (amdgpu_sriov_vf(adev))
1661 return 0;
1662
1663 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1664 case IP_VERSION(5, 2, 0):
1665 case IP_VERSION(5, 2, 2):
1666 case IP_VERSION(5, 2, 1):
1667 case IP_VERSION(5, 2, 4):
1668 case IP_VERSION(5, 2, 5):
1669 case IP_VERSION(5, 2, 6):
1670 case IP_VERSION(5, 2, 3):
1671 case IP_VERSION(5, 2, 7):
1672 sdma_v5_2_update_medium_grain_clock_gating(adev,
1673 state == AMD_CG_STATE_GATE);
1674 sdma_v5_2_update_medium_grain_light_sleep(adev,
1675 state == AMD_CG_STATE_GATE);
1676 break;
1677 default:
1678 break;
1679 }
1680
1681 return 0;
1682 }
1683
sdma_v5_2_set_powergating_state(void * handle,enum amd_powergating_state state)1684 static int sdma_v5_2_set_powergating_state(void *handle,
1685 enum amd_powergating_state state)
1686 {
1687 return 0;
1688 }
1689
sdma_v5_2_get_clockgating_state(void * handle,u64 * flags)1690 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1691 {
1692 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1693 int data;
1694
1695 if (amdgpu_sriov_vf(adev))
1696 *flags = 0;
1697
1698 /* AMD_CG_SUPPORT_SDMA_MGCG */
1699 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1700 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1701 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1702
1703 /* AMD_CG_SUPPORT_SDMA_LS */
1704 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1705 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1706 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1707 }
1708
sdma_v5_2_ring_begin_use(struct amdgpu_ring * ring)1709 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)
1710 {
1711 struct amdgpu_device *adev = ring->adev;
1712
1713 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1714 * disallow GFXOFF in some cases leading to
1715 * hangs in SDMA. Disallow GFXOFF while SDMA is active.
1716 * We can probably just limit this to 5.2.3,
1717 * but it shouldn't hurt for other parts since
1718 * this GFXOFF will be disallowed anyway when SDMA is
1719 * active, this just makes it explicit.
1720 * sdma_v5_2_ring_set_wptr() takes advantage of this
1721 * to update the wptr because sometimes SDMA seems to miss
1722 * doorbells when entering PG. If you remove this, update
1723 * sdma_v5_2_ring_set_wptr() as well!
1724 */
1725 amdgpu_gfx_off_ctrl(adev, false);
1726 }
1727
sdma_v5_2_ring_end_use(struct amdgpu_ring * ring)1728 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)
1729 {
1730 struct amdgpu_device *adev = ring->adev;
1731
1732 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1733 * disallow GFXOFF in some cases leading to
1734 * hangs in SDMA. Allow GFXOFF when SDMA is complete.
1735 */
1736 amdgpu_gfx_off_ctrl(adev, true);
1737 }
1738
sdma_v5_2_print_ip_state(void * handle,struct drm_printer * p)1739 static void sdma_v5_2_print_ip_state(void *handle, struct drm_printer *p)
1740 {
1741 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1742 int i, j;
1743 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
1744 uint32_t instance_offset;
1745
1746 if (!adev->sdma.ip_dump)
1747 return;
1748
1749 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1750 for (i = 0; i < adev->sdma.num_instances; i++) {
1751 instance_offset = i * reg_count;
1752 drm_printf(p, "\nInstance:%d\n", i);
1753
1754 for (j = 0; j < reg_count; j++)
1755 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name,
1756 adev->sdma.ip_dump[instance_offset + j]);
1757 }
1758 }
1759
sdma_v5_2_dump_ip_state(void * handle)1760 static void sdma_v5_2_dump_ip_state(void *handle)
1761 {
1762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1763 int i, j;
1764 uint32_t instance_offset;
1765 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
1766
1767 if (!adev->sdma.ip_dump)
1768 return;
1769
1770 amdgpu_gfx_off_ctrl(adev, false);
1771 for (i = 0; i < adev->sdma.num_instances; i++) {
1772 instance_offset = i * reg_count;
1773 for (j = 0; j < reg_count; j++)
1774 adev->sdma.ip_dump[instance_offset + j] =
1775 RREG32(sdma_v5_2_get_reg_offset(adev, i,
1776 sdma_reg_list_5_2[j].reg_offset));
1777 }
1778 amdgpu_gfx_off_ctrl(adev, true);
1779 }
1780
1781 static const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1782 .name = "sdma_v5_2",
1783 .early_init = sdma_v5_2_early_init,
1784 .late_init = NULL,
1785 .sw_init = sdma_v5_2_sw_init,
1786 .sw_fini = sdma_v5_2_sw_fini,
1787 .hw_init = sdma_v5_2_hw_init,
1788 .hw_fini = sdma_v5_2_hw_fini,
1789 .suspend = sdma_v5_2_suspend,
1790 .resume = sdma_v5_2_resume,
1791 .is_idle = sdma_v5_2_is_idle,
1792 .wait_for_idle = sdma_v5_2_wait_for_idle,
1793 .soft_reset = sdma_v5_2_soft_reset,
1794 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1795 .set_powergating_state = sdma_v5_2_set_powergating_state,
1796 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1797 .dump_ip_state = sdma_v5_2_dump_ip_state,
1798 .print_ip_state = sdma_v5_2_print_ip_state,
1799 };
1800
1801 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1802 .type = AMDGPU_RING_TYPE_SDMA,
1803 .align_mask = 0xf,
1804 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1805 .support_64bit_ptrs = true,
1806 .secure_submission_supported = true,
1807 .get_rptr = sdma_v5_2_ring_get_rptr,
1808 .get_wptr = sdma_v5_2_ring_get_wptr,
1809 .set_wptr = sdma_v5_2_ring_set_wptr,
1810 .emit_frame_size =
1811 5 + /* sdma_v5_2_ring_init_cond_exec */
1812 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1813 3 + /* hdp_invalidate */
1814 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1815 /* sdma_v5_2_ring_emit_vm_flush */
1816 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1817 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1818 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1819 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1820 .emit_ib = sdma_v5_2_ring_emit_ib,
1821 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1822 .emit_fence = sdma_v5_2_ring_emit_fence,
1823 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1824 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1825 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1826 .test_ring = sdma_v5_2_ring_test_ring,
1827 .test_ib = sdma_v5_2_ring_test_ib,
1828 .insert_nop = sdma_v5_2_ring_insert_nop,
1829 .pad_ib = sdma_v5_2_ring_pad_ib,
1830 .begin_use = sdma_v5_2_ring_begin_use,
1831 .end_use = sdma_v5_2_ring_end_use,
1832 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1833 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1834 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1835 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1836 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1837 };
1838
sdma_v5_2_set_ring_funcs(struct amdgpu_device * adev)1839 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1840 {
1841 int i;
1842
1843 for (i = 0; i < adev->sdma.num_instances; i++) {
1844 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1845 adev->sdma.instance[i].ring.me = i;
1846 }
1847 }
1848
1849 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1850 .set = sdma_v5_2_set_trap_irq_state,
1851 .process = sdma_v5_2_process_trap_irq,
1852 };
1853
1854 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1855 .process = sdma_v5_2_process_illegal_inst_irq,
1856 };
1857
sdma_v5_2_set_irq_funcs(struct amdgpu_device * adev)1858 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1859 {
1860 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1861 adev->sdma.num_instances;
1862 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1863 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1864 }
1865
1866 /**
1867 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1868 *
1869 * @ib: indirect buffer to copy to
1870 * @src_offset: src GPU address
1871 * @dst_offset: dst GPU address
1872 * @byte_count: number of bytes to xfer
1873 * @copy_flags: copy flags for the buffers
1874 *
1875 * Copy GPU buffers using the DMA engine.
1876 * Used by the amdgpu ttm implementation to move pages if
1877 * registered as the asic copy callback.
1878 */
sdma_v5_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)1879 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1880 uint64_t src_offset,
1881 uint64_t dst_offset,
1882 uint32_t byte_count,
1883 uint32_t copy_flags)
1884 {
1885 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1886 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1887 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1888 ib->ptr[ib->length_dw++] = byte_count - 1;
1889 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1890 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1891 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1892 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1893 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1894 }
1895
1896 /**
1897 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1898 *
1899 * @ib: indirect buffer to fill
1900 * @src_data: value to write to buffer
1901 * @dst_offset: dst GPU address
1902 * @byte_count: number of bytes to xfer
1903 *
1904 * Fill GPU buffers using the DMA engine.
1905 */
sdma_v5_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1906 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1907 uint32_t src_data,
1908 uint64_t dst_offset,
1909 uint32_t byte_count)
1910 {
1911 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1912 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1913 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1914 ib->ptr[ib->length_dw++] = src_data;
1915 ib->ptr[ib->length_dw++] = byte_count - 1;
1916 }
1917
1918 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1919 .copy_max_bytes = 0x400000,
1920 .copy_num_dw = 7,
1921 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1922
1923 .fill_max_bytes = 0x400000,
1924 .fill_num_dw = 5,
1925 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1926 };
1927
sdma_v5_2_set_buffer_funcs(struct amdgpu_device * adev)1928 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1929 {
1930 if (adev->mman.buffer_funcs == NULL) {
1931 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1932 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1933 }
1934 }
1935
1936 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1937 .copy_pte_num_dw = 7,
1938 .copy_pte = sdma_v5_2_vm_copy_pte,
1939 .write_pte = sdma_v5_2_vm_write_pte,
1940 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1941 };
1942
sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device * adev)1943 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1944 {
1945 unsigned i;
1946
1947 if (adev->vm_manager.vm_pte_funcs == NULL) {
1948 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1949 for (i = 0; i < adev->sdma.num_instances; i++) {
1950 adev->vm_manager.vm_pte_scheds[i] =
1951 &adev->sdma.instance[i].ring.sched;
1952 }
1953 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1954 }
1955 }
1956
1957 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1958 .type = AMD_IP_BLOCK_TYPE_SDMA,
1959 .major = 5,
1960 .minor = 2,
1961 .rev = 0,
1962 .funcs = &sdma_v5_2_ip_funcs,
1963 };
1964