1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ip.h" 31 #include "amdgpu_xcp.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_trace.h" 34 #include "amdgpu_sdma.h" 35 #include "amdgpu_reset.h" 36 37 #include "sdma/sdma_4_4_2_offset.h" 38 #include "sdma/sdma_4_4_2_sh_mask.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "vega10_sdma_pkt_open.h" 43 44 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 45 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 46 47 #include "amdgpu_ras.h" 48 49 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_4_4_4.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 52 53 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 98 }; 99 100 #define WREG32_SDMA(instance, offset, value) \ 101 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 102 #define RREG32_SDMA(instance, offset) \ 103 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 104 105 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 109 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 110 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring); 111 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring); 112 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 113 u32 instance_id); 114 115 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 116 u32 instance, u32 offset) 117 { 118 u32 dev_inst = GET_INST(SDMA0, instance); 119 120 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 121 } 122 123 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 124 { 125 switch (seq_num) { 126 case 0: 127 return SOC15_IH_CLIENTID_SDMA0; 128 case 1: 129 return SOC15_IH_CLIENTID_SDMA1; 130 case 2: 131 return SOC15_IH_CLIENTID_SDMA2; 132 case 3: 133 return SOC15_IH_CLIENTID_SDMA3; 134 default: 135 return -EINVAL; 136 } 137 } 138 139 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 140 { 141 switch (client_id) { 142 case SOC15_IH_CLIENTID_SDMA0: 143 return 0; 144 case SOC15_IH_CLIENTID_SDMA1: 145 return 1; 146 case SOC15_IH_CLIENTID_SDMA2: 147 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 148 return 0; 149 else 150 return 2; 151 case SOC15_IH_CLIENTID_SDMA3: 152 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 153 return 1; 154 else 155 return 3; 156 default: 157 return -EINVAL; 158 } 159 } 160 161 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 162 uint32_t inst_mask) 163 { 164 u32 val; 165 int i; 166 167 for (i = 0; i < adev->sdma.num_instances; i++) { 168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 170 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 171 PIPE_INTERLEAVE_SIZE, 0); 172 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 173 174 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 175 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 176 4); 177 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 178 PIPE_INTERLEAVE_SIZE, 0); 179 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 180 } 181 } 182 183 /** 184 * sdma_v4_4_2_init_microcode - load ucode images from disk 185 * 186 * @adev: amdgpu_device pointer 187 * 188 * Use the firmware interface to load the ucode images into 189 * the driver (not loaded into hw). 190 * Returns 0 on success, error on failure. 191 */ 192 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 193 { 194 int ret, i; 195 196 for (i = 0; i < adev->sdma.num_instances; i++) { 197 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 198 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 199 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 200 ret = amdgpu_sdma_init_microcode(adev, 0, true); 201 break; 202 } else { 203 ret = amdgpu_sdma_init_microcode(adev, i, false); 204 if (ret) 205 return ret; 206 } 207 } 208 209 return ret; 210 } 211 212 /** 213 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 214 * 215 * @ring: amdgpu ring pointer 216 * 217 * Get the current rptr from the hardware. 218 */ 219 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 220 { 221 u64 rptr; 222 223 /* XXX check if swapping is necessary on BE */ 224 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 225 226 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 227 return rptr >> 2; 228 } 229 230 /** 231 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 232 * 233 * @ring: amdgpu ring pointer 234 * 235 * Get the current wptr from the hardware. 236 */ 237 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 238 { 239 struct amdgpu_device *adev = ring->adev; 240 u64 wptr; 241 242 if (ring->use_doorbell) { 243 /* XXX check if swapping is necessary on BE */ 244 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 245 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 246 } else { 247 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 248 wptr = wptr << 32; 249 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 250 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 251 ring->me, wptr); 252 } 253 254 return wptr >> 2; 255 } 256 257 /** 258 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 259 * 260 * @ring: amdgpu ring pointer 261 * 262 * Write the wptr back to the hardware. 263 */ 264 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 265 { 266 struct amdgpu_device *adev = ring->adev; 267 268 DRM_DEBUG("Setting write pointer\n"); 269 if (ring->use_doorbell) { 270 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 271 272 DRM_DEBUG("Using doorbell -- " 273 "wptr_offs == 0x%08x " 274 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 275 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 276 ring->wptr_offs, 277 lower_32_bits(ring->wptr << 2), 278 upper_32_bits(ring->wptr << 2)); 279 /* XXX check if swapping is necessary on BE */ 280 WRITE_ONCE(*wb, (ring->wptr << 2)); 281 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 282 ring->doorbell_index, ring->wptr << 2); 283 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 284 } else { 285 DRM_DEBUG("Not using doorbell -- " 286 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 287 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 288 ring->me, 289 lower_32_bits(ring->wptr << 2), 290 ring->me, 291 upper_32_bits(ring->wptr << 2)); 292 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 293 lower_32_bits(ring->wptr << 2)); 294 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 295 upper_32_bits(ring->wptr << 2)); 296 } 297 } 298 299 /** 300 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 301 * 302 * @ring: amdgpu ring pointer 303 * 304 * Get the current wptr from the hardware. 305 */ 306 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 u64 wptr; 310 311 if (ring->use_doorbell) { 312 /* XXX check if swapping is necessary on BE */ 313 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 314 } else { 315 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 316 wptr = wptr << 32; 317 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 318 } 319 320 return wptr >> 2; 321 } 322 323 /** 324 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 325 * 326 * @ring: amdgpu ring pointer 327 * 328 * Write the wptr back to the hardware. 329 */ 330 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 331 { 332 struct amdgpu_device *adev = ring->adev; 333 334 if (ring->use_doorbell) { 335 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 336 337 /* XXX check if swapping is necessary on BE */ 338 WRITE_ONCE(*wb, (ring->wptr << 2)); 339 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 340 } else { 341 uint64_t wptr = ring->wptr << 2; 342 343 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 344 lower_32_bits(wptr)); 345 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 346 upper_32_bits(wptr)); 347 } 348 } 349 350 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 351 { 352 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 353 const u32 nop = ring->funcs->nop; 354 355 if (count && sdma->burst_nop) { 356 --count; 357 amdgpu_ring_write(ring, nop | SDMA_PKT_NOP_HEADER_COUNT(count)); 358 } 359 360 amdgpu_ring_fill(ring, nop, count); 361 } 362 363 /** 364 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 365 * 366 * @ring: amdgpu ring pointer 367 * @job: job to retrieve vmid from 368 * @ib: IB object to schedule 369 * @flags: unused 370 * 371 * Schedule an IB in the DMA ring. 372 */ 373 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 374 struct amdgpu_job *job, 375 struct amdgpu_ib *ib, 376 uint32_t flags) 377 { 378 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 379 380 /* IB packet must end on a 8 DW boundary */ 381 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 382 383 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 384 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 385 /* base must be 32 byte aligned */ 386 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 387 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 388 amdgpu_ring_write(ring, ib->length_dw); 389 amdgpu_ring_write(ring, 0); 390 amdgpu_ring_write(ring, 0); 391 392 } 393 394 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 395 int mem_space, int hdp, 396 uint32_t addr0, uint32_t addr1, 397 uint32_t ref, uint32_t mask, 398 uint32_t inv) 399 { 400 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 401 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 402 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 403 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 404 if (mem_space) { 405 /* memory */ 406 amdgpu_ring_write(ring, addr0); 407 amdgpu_ring_write(ring, addr1); 408 } else { 409 /* registers */ 410 amdgpu_ring_write(ring, addr0 << 2); 411 amdgpu_ring_write(ring, addr1 << 2); 412 } 413 amdgpu_ring_write(ring, ref); /* reference */ 414 amdgpu_ring_write(ring, mask); /* mask */ 415 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 416 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 417 } 418 419 /** 420 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 421 * 422 * @ring: amdgpu ring pointer 423 * 424 * Emit an hdp flush packet on the requested DMA ring. 425 */ 426 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 427 { 428 struct amdgpu_device *adev = ring->adev; 429 u32 ref_and_mask = 0; 430 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 431 432 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 433 << (ring->me % adev->sdma.num_inst_per_aid); 434 435 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 436 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 437 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 438 ref_and_mask, ref_and_mask, 10); 439 } 440 441 /** 442 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 443 * 444 * @ring: amdgpu ring pointer 445 * @addr: address 446 * @seq: sequence number 447 * @flags: fence related flags 448 * 449 * Add a DMA fence packet to the ring to write 450 * the fence seq number and DMA trap packet to generate 451 * an interrupt if needed. 452 */ 453 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 454 unsigned flags) 455 { 456 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 457 /* write the fence */ 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 459 /* zero in first two bits */ 460 WARN_ON(addr & 0x3); 461 amdgpu_ring_write(ring, lower_32_bits(addr)); 462 amdgpu_ring_write(ring, upper_32_bits(addr)); 463 amdgpu_ring_write(ring, lower_32_bits(seq)); 464 465 /* optionally write high bits as well */ 466 if (write64bit) { 467 addr += 4; 468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 469 /* zero in first two bits */ 470 WARN_ON(addr & 0x3); 471 amdgpu_ring_write(ring, lower_32_bits(addr)); 472 amdgpu_ring_write(ring, upper_32_bits(addr)); 473 amdgpu_ring_write(ring, upper_32_bits(seq)); 474 } 475 476 /* generate an interrupt */ 477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 478 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 479 } 480 481 482 /** 483 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 484 * 485 * @adev: amdgpu_device pointer 486 * @inst_mask: mask of dma engine instances to be disabled 487 * 488 * Stop the gfx async dma ring buffers. 489 */ 490 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 491 uint32_t inst_mask) 492 { 493 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 494 u32 doorbell_offset, doorbell; 495 u32 rb_cntl, ib_cntl, sdma_cntl; 496 int i; 497 498 for_each_inst(i, inst_mask) { 499 sdma[i] = &adev->sdma.instance[i].ring; 500 501 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 503 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 504 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 505 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 506 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 507 sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL); 508 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0); 509 WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl); 510 511 if (sdma[i]->use_doorbell) { 512 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 513 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 514 515 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 516 doorbell_offset = REG_SET_FIELD(doorbell_offset, 517 SDMA_GFX_DOORBELL_OFFSET, 518 OFFSET, 0); 519 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 520 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 521 } 522 } 523 } 524 525 /** 526 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 527 * 528 * @adev: amdgpu_device pointer 529 * @inst_mask: mask of dma engine instances to be disabled 530 * 531 * Stop the page async dma ring buffers. 532 */ 533 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 534 uint32_t inst_mask) 535 { 536 u32 rb_cntl, ib_cntl; 537 int i; 538 539 for_each_inst(i, inst_mask) { 540 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 541 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 542 RB_ENABLE, 0); 543 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 544 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 545 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 546 IB_ENABLE, 0); 547 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 548 } 549 } 550 551 /** 552 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 553 * 554 * @adev: amdgpu_device pointer 555 * @enable: enable/disable the DMA MEs context switch. 556 * @inst_mask: mask of dma engine instances to be enabled 557 * 558 * Halt or unhalt the async dma engines context switch. 559 */ 560 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 561 bool enable, uint32_t inst_mask) 562 { 563 u32 f32_cntl, phase_quantum = 0; 564 int i; 565 566 if (amdgpu_sdma_phase_quantum) { 567 unsigned value = amdgpu_sdma_phase_quantum; 568 unsigned unit = 0; 569 570 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 571 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 572 value = (value + 1) >> 1; 573 unit++; 574 } 575 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 576 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 577 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 578 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 579 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 580 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 581 WARN_ONCE(1, 582 "clamping sdma_phase_quantum to %uK clock cycles\n", 583 value << unit); 584 } 585 phase_quantum = 586 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 587 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 588 } 589 590 for_each_inst(i, inst_mask) { 591 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 593 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 594 if (enable && amdgpu_sdma_phase_quantum) { 595 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 596 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 597 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 598 } 599 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 600 601 /* Extend page fault timeout to avoid interrupt storm */ 602 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 603 } 604 } 605 606 /** 607 * sdma_v4_4_2_inst_enable - stop the async dma engines 608 * 609 * @adev: amdgpu_device pointer 610 * @enable: enable/disable the DMA MEs. 611 * @inst_mask: mask of dma engine instances to be enabled 612 * 613 * Halt or unhalt the async dma engines. 614 */ 615 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 616 uint32_t inst_mask) 617 { 618 u32 f32_cntl; 619 int i; 620 621 if (!enable) { 622 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 623 if (adev->sdma.has_page_queue) 624 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 625 626 /* SDMA FW needs to respond to FREEZE requests during reset. 627 * Keep it running during reset */ 628 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 629 return; 630 } 631 632 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 633 return; 634 635 for_each_inst(i, inst_mask) { 636 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 637 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 638 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 639 } 640 } 641 642 /* 643 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 644 */ 645 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 646 { 647 /* Set ring buffer size in dwords */ 648 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 649 650 barrier(); /* work around https://llvm.org/pr42576 */ 651 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 652 #ifdef __BIG_ENDIAN 653 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 654 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 655 RPTR_WRITEBACK_SWAP_ENABLE, 1); 656 #endif 657 return rb_cntl; 658 } 659 660 /** 661 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 662 * 663 * @adev: amdgpu_device pointer 664 * @i: instance to resume 665 * 666 * Set up the gfx DMA ring buffers and enable them. 667 * Returns 0 for success, error for failure. 668 */ 669 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 670 { 671 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 672 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 673 u32 wb_offset; 674 u32 doorbell; 675 u32 doorbell_offset; 676 u64 wptr_gpu_addr; 677 678 wb_offset = (ring->rptr_offs * 4); 679 680 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 681 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 682 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 683 684 /* set the wb address whether it's enabled or not */ 685 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 686 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 687 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 688 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 689 690 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 691 RPTR_WRITEBACK_ENABLE, 1); 692 693 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 694 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 695 696 ring->wptr = 0; 697 698 /* before programing wptr to a less value, need set minor_ptr_update first */ 699 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 700 701 /* Initialize the ring buffer's read and write pointers */ 702 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 703 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 704 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 705 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 706 707 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 708 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 709 710 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 711 ring->use_doorbell); 712 doorbell_offset = REG_SET_FIELD(doorbell_offset, 713 SDMA_GFX_DOORBELL_OFFSET, 714 OFFSET, ring->doorbell_index); 715 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 716 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 717 718 sdma_v4_4_2_ring_set_wptr(ring); 719 720 /* set minor_ptr_update to 0 after wptr programed */ 721 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 722 723 /* setup the wptr shadow polling */ 724 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 725 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 726 lower_32_bits(wptr_gpu_addr)); 727 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 728 upper_32_bits(wptr_gpu_addr)); 729 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 730 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 731 SDMA_GFX_RB_WPTR_POLL_CNTL, 732 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 733 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 734 735 /* enable DMA RB */ 736 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 737 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 738 739 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 740 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 741 #ifdef __BIG_ENDIAN 742 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 743 #endif 744 /* enable DMA IBs */ 745 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 746 } 747 748 /** 749 * sdma_v4_4_2_page_resume - setup and start the async dma engines 750 * 751 * @adev: amdgpu_device pointer 752 * @i: instance to resume 753 * @restore: boolean to say restore needed or not 754 * 755 * Set up the page DMA ring buffers and enable them. 756 * Returns 0 for success, error for failure. 757 */ 758 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 759 { 760 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 761 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 762 u32 wb_offset; 763 u32 doorbell; 764 u32 doorbell_offset; 765 u64 wptr_gpu_addr; 766 767 wb_offset = (ring->rptr_offs * 4); 768 769 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 770 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 771 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 772 773 /* Initialize the ring buffer's read and write pointers */ 774 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 775 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 776 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 777 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 778 779 /* set the wb address whether it's enabled or not */ 780 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 781 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 782 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 783 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 784 785 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 786 RPTR_WRITEBACK_ENABLE, 1); 787 788 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 789 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 790 791 ring->wptr = 0; 792 793 /* before programing wptr to a less value, need set minor_ptr_update first */ 794 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 795 796 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 797 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 798 799 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 800 ring->use_doorbell); 801 doorbell_offset = REG_SET_FIELD(doorbell_offset, 802 SDMA_PAGE_DOORBELL_OFFSET, 803 OFFSET, ring->doorbell_index); 804 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 805 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 806 807 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 808 sdma_v4_4_2_page_ring_set_wptr(ring); 809 810 /* set minor_ptr_update to 0 after wptr programed */ 811 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 812 813 /* setup the wptr shadow polling */ 814 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 815 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 816 lower_32_bits(wptr_gpu_addr)); 817 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 818 upper_32_bits(wptr_gpu_addr)); 819 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 820 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 821 SDMA_PAGE_RB_WPTR_POLL_CNTL, 822 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 823 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 824 825 /* enable DMA RB */ 826 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 827 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 828 829 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 830 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 831 #ifdef __BIG_ENDIAN 832 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 833 #endif 834 /* enable DMA IBs */ 835 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 836 } 837 838 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 839 { 840 841 } 842 843 /** 844 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 845 * 846 * @adev: amdgpu_device pointer 847 * @inst_mask: mask of dma engine instances to be enabled 848 * 849 * Loads the sDMA0/1 ucode. 850 * Returns 0 for success, -EINVAL if the ucode is not available. 851 */ 852 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 853 uint32_t inst_mask) 854 { 855 const struct sdma_firmware_header_v1_0 *hdr; 856 const __le32 *fw_data; 857 u32 fw_size; 858 int i, j; 859 860 /* halt the MEs */ 861 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 862 863 for_each_inst(i, inst_mask) { 864 if (!adev->sdma.instance[i].fw) 865 return -EINVAL; 866 867 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 868 amdgpu_ucode_print_sdma_hdr(&hdr->header); 869 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 870 871 fw_data = (const __le32 *) 872 (adev->sdma.instance[i].fw->data + 873 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 874 875 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 876 877 for (j = 0; j < fw_size; j++) 878 WREG32_SDMA(i, regSDMA_UCODE_DATA, 879 le32_to_cpup(fw_data++)); 880 881 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 882 adev->sdma.instance[i].fw_version); 883 } 884 885 return 0; 886 } 887 888 /** 889 * sdma_v4_4_2_inst_start - setup and start the async dma engines 890 * 891 * @adev: amdgpu_device pointer 892 * @inst_mask: mask of dma engine instances to be enabled 893 * @restore: boolean to say restore needed or not 894 * 895 * Set up the DMA engines and enable them. 896 * Returns 0 for success, error for failure. 897 */ 898 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 899 uint32_t inst_mask, bool restore) 900 { 901 struct amdgpu_ring *ring; 902 uint32_t tmp_mask; 903 int i, r = 0; 904 905 if (amdgpu_sriov_vf(adev)) { 906 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 907 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 908 } else { 909 /* bypass sdma microcode loading on Gopher */ 910 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 911 adev->sdma.instance[0].fw) { 912 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 913 if (r) 914 return r; 915 } 916 917 /* unhalt the MEs */ 918 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 919 /* enable sdma ring preemption */ 920 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 921 } 922 923 /* start the gfx rings and rlc compute queues */ 924 tmp_mask = inst_mask; 925 for_each_inst(i, tmp_mask) { 926 uint32_t temp; 927 928 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 929 sdma_v4_4_2_gfx_resume(adev, i); 930 if (adev->sdma.has_page_queue) 931 sdma_v4_4_2_page_resume(adev, i); 932 933 /* set utc l1 enable flag always to 1 */ 934 temp = RREG32_SDMA(i, regSDMA_CNTL); 935 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 936 WREG32_SDMA(i, regSDMA_CNTL, temp); 937 938 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 939 /* enable context empty interrupt during initialization */ 940 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 941 WREG32_SDMA(i, regSDMA_CNTL, temp); 942 } 943 if (!amdgpu_sriov_vf(adev)) { 944 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 945 /* unhalt engine */ 946 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 947 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 948 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 949 } 950 } 951 } 952 953 if (amdgpu_sriov_vf(adev)) { 954 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 955 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 956 } else { 957 sdma_v4_4_2_init_pg(adev); 958 } 959 960 tmp_mask = inst_mask; 961 for_each_inst(i, tmp_mask) { 962 ring = &adev->sdma.instance[i].ring; 963 964 r = amdgpu_ring_test_helper(ring); 965 if (r) 966 return r; 967 968 if (adev->sdma.has_page_queue) { 969 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 970 971 r = amdgpu_ring_test_helper(page); 972 if (r) 973 return r; 974 } 975 } 976 977 return r; 978 } 979 980 /** 981 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 982 * 983 * @ring: amdgpu_ring structure holding ring information 984 * 985 * Test the DMA engine by writing using it to write an 986 * value to memory. 987 * Returns 0 for success, error for failure. 988 */ 989 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 990 { 991 struct amdgpu_device *adev = ring->adev; 992 unsigned i; 993 unsigned index; 994 int r; 995 u32 tmp; 996 u64 gpu_addr; 997 998 r = amdgpu_wb_get(adev, &index); 999 if (r) 1000 return r; 1001 1002 gpu_addr = adev->wb.gpu_addr + (index * 4); 1003 tmp = 0xCAFEDEAD; 1004 adev->wb.wb[index] = cpu_to_le32(tmp); 1005 1006 r = amdgpu_ring_alloc(ring, 5); 1007 if (r) 1008 goto error_free_wb; 1009 1010 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1011 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1012 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1013 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1014 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1015 amdgpu_ring_write(ring, 0xDEADBEEF); 1016 amdgpu_ring_commit(ring); 1017 1018 for (i = 0; i < adev->usec_timeout; i++) { 1019 tmp = le32_to_cpu(adev->wb.wb[index]); 1020 if (tmp == 0xDEADBEEF) 1021 break; 1022 udelay(1); 1023 } 1024 1025 if (i >= adev->usec_timeout) 1026 r = -ETIMEDOUT; 1027 1028 error_free_wb: 1029 amdgpu_wb_free(adev, index); 1030 return r; 1031 } 1032 1033 /** 1034 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1035 * 1036 * @ring: amdgpu_ring structure holding ring information 1037 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1038 * 1039 * Test a simple IB in the DMA ring. 1040 * Returns 0 on success, error on failure. 1041 */ 1042 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1043 { 1044 struct amdgpu_device *adev = ring->adev; 1045 struct amdgpu_job *job; 1046 struct amdgpu_ib *ib; 1047 struct dma_fence *f = NULL; 1048 unsigned index; 1049 long r; 1050 u32 tmp = 0; 1051 u64 gpu_addr; 1052 1053 r = amdgpu_wb_get(adev, &index); 1054 if (r) 1055 return r; 1056 1057 gpu_addr = adev->wb.gpu_addr + (index * 4); 1058 tmp = 0xCAFEDEAD; 1059 adev->wb.wb[index] = cpu_to_le32(tmp); 1060 1061 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256, 1062 AMDGPU_IB_POOL_DIRECT, 1063 AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST, 1064 &job); 1065 if (r) 1066 goto err0; 1067 1068 ib = &job->ibs[0]; 1069 ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1070 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1071 ib->ptr[1] = lower_32_bits(gpu_addr); 1072 ib->ptr[2] = upper_32_bits(gpu_addr); 1073 ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1074 ib->ptr[4] = 0xDEADBEEF; 1075 ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1076 ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1077 ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1078 ib->length_dw = 8; 1079 1080 r = amdgpu_job_submit_direct(job, ring, &f); 1081 if (r) { 1082 amdgpu_job_free(job); 1083 goto err1; 1084 } 1085 1086 r = dma_fence_wait_timeout(f, false, timeout); 1087 if (r == 0) { 1088 r = -ETIMEDOUT; 1089 goto err1; 1090 } else if (r < 0) { 1091 goto err1; 1092 } 1093 tmp = le32_to_cpu(adev->wb.wb[index]); 1094 if (tmp == 0xDEADBEEF) 1095 r = 0; 1096 else 1097 r = -EINVAL; 1098 1099 err1: 1100 dma_fence_put(f); 1101 err0: 1102 amdgpu_wb_free(adev, index); 1103 return r; 1104 } 1105 1106 1107 /** 1108 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1109 * 1110 * @ib: indirect buffer to fill with commands 1111 * @pe: addr of the page entry 1112 * @src: src addr to copy from 1113 * @count: number of page entries to update 1114 * 1115 * Update PTEs by copying them from the GART using sDMA. 1116 */ 1117 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1118 uint64_t pe, uint64_t src, 1119 unsigned count) 1120 { 1121 unsigned bytes = count * 8; 1122 1123 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1124 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1125 ib->ptr[ib->length_dw++] = bytes - 1; 1126 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1127 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1128 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1129 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1130 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1131 1132 } 1133 1134 /** 1135 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1136 * 1137 * @ib: indirect buffer to fill with commands 1138 * @pe: addr of the page entry 1139 * @value: dst addr to write into pe 1140 * @count: number of page entries to update 1141 * @incr: increase next addr by incr bytes 1142 * 1143 * Update PTEs by writing them manually using sDMA. 1144 */ 1145 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1146 uint64_t value, unsigned count, 1147 uint32_t incr) 1148 { 1149 unsigned ndw = count * 2; 1150 1151 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1152 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1153 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1154 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1155 ib->ptr[ib->length_dw++] = ndw - 1; 1156 for (; ndw > 0; ndw -= 2) { 1157 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1158 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1159 value += incr; 1160 } 1161 } 1162 1163 /** 1164 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1165 * 1166 * @ib: indirect buffer to fill with commands 1167 * @pe: addr of the page entry 1168 * @addr: dst addr to write into pe 1169 * @count: number of page entries to update 1170 * @incr: increase next addr by incr bytes 1171 * @flags: access flags 1172 * 1173 * Update the page tables using sDMA. 1174 */ 1175 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1176 uint64_t pe, 1177 uint64_t addr, unsigned count, 1178 uint32_t incr, uint64_t flags) 1179 { 1180 /* for physically contiguous pages (vram) */ 1181 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1182 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1183 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1184 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1185 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1186 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1187 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1188 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1189 ib->ptr[ib->length_dw++] = 0; 1190 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1191 } 1192 1193 /** 1194 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1195 * 1196 * @ring: amdgpu_ring structure holding ring information 1197 * @ib: indirect buffer to fill with padding 1198 */ 1199 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1200 { 1201 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1202 const bool burst_nop = sdma->burst_nop; 1203 u32 pad_count; 1204 int i; 1205 1206 pad_count = (-ib->length_dw) & 7; 1207 for (i = 0; i < pad_count; i++) 1208 if (i == 0 && burst_nop) 1209 ib->ptr[ib->length_dw++] = 1210 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1211 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1212 else 1213 ib->ptr[ib->length_dw++] = 1214 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1215 } 1216 1217 1218 /** 1219 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1220 * 1221 * @ring: amdgpu_ring pointer 1222 * 1223 * Make sure all previous operations are completed (CIK). 1224 */ 1225 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1226 { 1227 uint32_t seq = ring->fence_drv.sync_seq; 1228 uint64_t addr = ring->fence_drv.gpu_addr; 1229 1230 /* wait for idle */ 1231 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1232 addr & 0xfffffffc, 1233 upper_32_bits(addr) & 0xffffffff, 1234 seq, 0xffffffff, 4); 1235 } 1236 1237 1238 /** 1239 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1240 * 1241 * @ring: amdgpu_ring pointer 1242 * @vmid: vmid number to use 1243 * @pd_addr: address 1244 * 1245 * Update the page table base and flush the VM TLB 1246 * using sDMA. 1247 */ 1248 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1249 unsigned vmid, uint64_t pd_addr) 1250 { 1251 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1252 } 1253 1254 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1255 uint32_t reg, uint32_t val) 1256 { 1257 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1258 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1259 amdgpu_ring_write(ring, reg); 1260 amdgpu_ring_write(ring, val); 1261 } 1262 1263 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1264 uint32_t val, uint32_t mask) 1265 { 1266 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1267 } 1268 1269 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1270 { 1271 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1272 case IP_VERSION(4, 4, 2): 1273 case IP_VERSION(4, 4, 5): 1274 return false; 1275 default: 1276 return false; 1277 } 1278 } 1279 1280 static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { 1281 .stop_kernel_queue = &sdma_v4_4_2_stop_queue, 1282 .start_kernel_queue = &sdma_v4_4_2_restore_queue, 1283 .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, 1284 }; 1285 1286 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 1287 .copy_pte_num_dw = 7, 1288 .copy_pte = sdma_v4_4_2_vm_copy_pte, 1289 1290 .write_pte = sdma_v4_4_2_vm_write_pte, 1291 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 1292 }; 1293 1294 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1295 { 1296 struct amdgpu_device *adev = ip_block->adev; 1297 int r; 1298 1299 switch (amdgpu_user_queue) { 1300 case -1: 1301 case 0: 1302 default: 1303 adev->sdma.no_user_submission = false; 1304 adev->sdma.disable_uq = true; 1305 break; 1306 case 2: 1307 adev->sdma.no_user_submission = true; 1308 adev->sdma.disable_uq = true; 1309 break; 1310 } 1311 1312 r = sdma_v4_4_2_init_microcode(adev); 1313 if (r) 1314 return r; 1315 1316 /* TODO: Page queue breaks driver reload under SRIOV */ 1317 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1318 adev->sdma.has_page_queue = true; 1319 1320 sdma_v4_4_2_set_ring_funcs(adev); 1321 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); 1322 sdma_v4_4_2_set_irq_funcs(adev); 1323 sdma_v4_4_2_set_ras_funcs(adev); 1324 return 0; 1325 } 1326 1327 #if 0 1328 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1329 void *err_data, 1330 struct amdgpu_iv_entry *entry); 1331 #endif 1332 1333 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1334 { 1335 struct amdgpu_device *adev = ip_block->adev; 1336 #if 0 1337 struct ras_ih_if ih_info = { 1338 .cb = sdma_v4_4_2_process_ras_data_cb, 1339 }; 1340 #endif 1341 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1342 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1343 1344 /* The initialization is done in the late_init stage to ensure that the SMU 1345 * initialization and capability setup are completed before we check the SDMA 1346 * reset capability 1347 */ 1348 sdma_v4_4_2_update_reset_mask(adev); 1349 1350 return 0; 1351 } 1352 1353 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1354 { 1355 struct amdgpu_ring *ring; 1356 int r, i; 1357 struct amdgpu_device *adev = ip_block->adev; 1358 u32 aid_id; 1359 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1360 uint32_t *ptr; 1361 1362 /* SDMA trap event */ 1363 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1364 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1365 SDMA0_4_0__SRCID__SDMA_TRAP, 1366 &adev->sdma.trap_irq); 1367 if (r) 1368 return r; 1369 } 1370 1371 /* SDMA SRAM ECC event */ 1372 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1373 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1374 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1375 &adev->sdma.ecc_irq); 1376 if (r) 1377 return r; 1378 } 1379 1380 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1381 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1382 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1383 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1384 &adev->sdma.vm_hole_irq); 1385 if (r) 1386 return r; 1387 1388 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1389 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1390 &adev->sdma.doorbell_invalid_irq); 1391 if (r) 1392 return r; 1393 1394 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1395 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1396 &adev->sdma.pool_timeout_irq); 1397 if (r) 1398 return r; 1399 1400 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1401 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1402 &adev->sdma.srbm_write_irq); 1403 if (r) 1404 return r; 1405 1406 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1407 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1408 &adev->sdma.ctxt_empty_irq); 1409 if (r) 1410 return r; 1411 } 1412 1413 for (i = 0; i < adev->sdma.num_instances; i++) { 1414 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); 1415 adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs; 1416 1417 ring = &adev->sdma.instance[i].ring; 1418 ring->use_doorbell = true; 1419 aid_id = adev->sdma.instance[i].aid_id; 1420 1421 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1422 ring->use_doorbell?"true":"false"); 1423 1424 /* doorbell size is 2 dwords, get DWORD offset */ 1425 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1426 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1427 ring->no_user_submission = adev->sdma.no_user_submission; 1428 r = amdgpu_sdma_ring_init(adev, ring, i, "sdma%d.%d", aid_id, 1429 i % adev->sdma.num_inst_per_aid); 1430 if (r) 1431 return r; 1432 1433 if (adev->sdma.has_page_queue) { 1434 ring = &adev->sdma.instance[i].page; 1435 ring->use_doorbell = true; 1436 1437 /* doorbell index of page queue is assigned right after 1438 * gfx queue on the same instance 1439 */ 1440 ring->doorbell_index = 1441 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1442 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1443 r = amdgpu_sdma_ring_init(adev, ring, i, "page%d.%d", 1444 aid_id, 1445 i % adev->sdma.num_inst_per_aid); 1446 if (r) 1447 return r; 1448 } 1449 } 1450 1451 adev->sdma.supported_reset = 1452 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1453 1454 if (amdgpu_sdma_ras_sw_init(adev)) { 1455 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1456 return -EINVAL; 1457 } 1458 1459 /* Allocate memory for SDMA IP Dump buffer */ 1460 ptr = kzalloc_objs(*ptr, adev->sdma.num_instances * reg_count); 1461 if (ptr) 1462 adev->sdma.ip_dump = ptr; 1463 else 1464 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1465 1466 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1467 if (r) 1468 return r; 1469 1470 return r; 1471 } 1472 1473 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1474 { 1475 struct amdgpu_device *adev = ip_block->adev; 1476 int i; 1477 1478 for (i = 0; i < adev->sdma.num_instances; i++) { 1479 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1480 if (adev->sdma.has_page_queue) 1481 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1482 } 1483 1484 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1485 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1486 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1487 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1488 amdgpu_sdma_destroy_inst_ctx(adev, true); 1489 else 1490 amdgpu_sdma_destroy_inst_ctx(adev, false); 1491 1492 kfree(adev->sdma.ip_dump); 1493 1494 return 0; 1495 } 1496 1497 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1498 { 1499 int r; 1500 struct amdgpu_device *adev = ip_block->adev; 1501 uint32_t inst_mask; 1502 1503 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1504 if (!amdgpu_sriov_vf(adev)) 1505 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1506 1507 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1508 if (r) 1509 return r; 1510 sdma_v4_4_2_set_buffer_funcs(adev); 1511 1512 return 0; 1513 } 1514 1515 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1516 { 1517 struct amdgpu_device *adev = ip_block->adev; 1518 uint32_t inst_mask; 1519 int i; 1520 1521 if (amdgpu_sriov_vf(adev)) 1522 return 0; 1523 1524 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1525 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1526 for (i = 0; i < adev->sdma.num_instances; i++) { 1527 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1528 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1529 } 1530 } 1531 1532 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1533 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1534 1535 return 0; 1536 } 1537 1538 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1539 enum amd_clockgating_state state); 1540 1541 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1542 { 1543 struct amdgpu_device *adev = ip_block->adev; 1544 1545 if (amdgpu_in_reset(adev)) 1546 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1547 1548 return sdma_v4_4_2_hw_fini(ip_block); 1549 } 1550 1551 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1552 { 1553 return sdma_v4_4_2_hw_init(ip_block); 1554 } 1555 1556 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1557 { 1558 unsigned i, j; 1559 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1560 struct amdgpu_device *adev = ip_block->adev; 1561 1562 for (i = 0; i < adev->usec_timeout; i++) { 1563 for (j = 0; j < adev->sdma.num_instances; j++) { 1564 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1565 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1566 break; 1567 } 1568 if (j == adev->sdma.num_instances) 1569 return 0; 1570 udelay(1); 1571 } 1572 return -ETIMEDOUT; 1573 } 1574 1575 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) 1576 { 1577 struct amdgpu_device *adev = ring->adev; 1578 u32 inst_mask; 1579 1580 if (amdgpu_sriov_vf(adev)) 1581 return -EINVAL; 1582 1583 /* stop queue */ 1584 inst_mask = 1 << ring->me; 1585 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1586 if (adev->sdma.has_page_queue) 1587 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1588 1589 return 0; 1590 } 1591 1592 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring) 1593 { 1594 struct amdgpu_device *adev = ring->adev; 1595 u32 inst_mask; 1596 int i, r; 1597 1598 inst_mask = 1 << ring->me; 1599 udelay(50); 1600 1601 for (i = 0; i < adev->usec_timeout; i++) { 1602 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1603 break; 1604 udelay(1); 1605 } 1606 1607 if (i == adev->usec_timeout) { 1608 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1609 ring->me); 1610 return -ETIMEDOUT; 1611 } 1612 1613 r = sdma_v4_4_2_inst_start(adev, inst_mask, true); 1614 1615 return r; 1616 } 1617 1618 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 1619 u32 instance_id) 1620 { 1621 /* For SDMA 4.x, use the existing DPM interface for backward compatibility 1622 * we need to convert the logical instance ID to physical instance ID before reset. 1623 */ 1624 return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id)); 1625 } 1626 1627 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1628 struct amdgpu_irq_src *source, 1629 unsigned type, 1630 enum amdgpu_interrupt_state state) 1631 { 1632 u32 sdma_cntl; 1633 1634 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1635 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1636 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1637 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1638 1639 return 0; 1640 } 1641 1642 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1643 struct amdgpu_irq_src *source, 1644 struct amdgpu_iv_entry *entry) 1645 { 1646 uint32_t instance, i; 1647 1648 DRM_DEBUG("IH: SDMA trap\n"); 1649 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1650 1651 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1652 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1653 * Match node id with the AID id associated with the SDMA instance. */ 1654 for (i = instance; i < adev->sdma.num_instances; 1655 i += adev->sdma.num_inst_per_aid) { 1656 if (adev->sdma.instance[i].aid_id == 1657 node_id_to_phys_map[entry->node_id]) 1658 break; 1659 } 1660 1661 if (i >= adev->sdma.num_instances) { 1662 dev_WARN_ONCE( 1663 adev->dev, 1, 1664 "Couldn't find the right sdma instance in trap handler"); 1665 return 0; 1666 } 1667 1668 switch (entry->ring_id) { 1669 case 0: 1670 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1671 break; 1672 case 1: 1673 amdgpu_fence_process(&adev->sdma.instance[i].page); 1674 break; 1675 default: 1676 break; 1677 } 1678 return 0; 1679 } 1680 1681 #if 0 1682 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1683 void *err_data, 1684 struct amdgpu_iv_entry *entry) 1685 { 1686 int instance; 1687 1688 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1689 * be disabled and the driver should only look for the aggregated 1690 * interrupt via sync flood 1691 */ 1692 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1693 goto out; 1694 1695 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1696 if (instance < 0) 1697 goto out; 1698 1699 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1700 1701 out: 1702 return AMDGPU_RAS_SUCCESS; 1703 } 1704 #endif 1705 1706 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1707 struct amdgpu_irq_src *source, 1708 struct amdgpu_iv_entry *entry) 1709 { 1710 int instance; 1711 1712 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1713 1714 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1715 if (instance < 0) 1716 return 0; 1717 1718 switch (entry->ring_id) { 1719 case 0: 1720 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1721 break; 1722 } 1723 return 0; 1724 } 1725 1726 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1727 struct amdgpu_irq_src *source, 1728 unsigned type, 1729 enum amdgpu_interrupt_state state) 1730 { 1731 u32 sdma_cntl; 1732 1733 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1734 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1735 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1736 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1737 1738 return 0; 1739 } 1740 1741 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1742 struct amdgpu_iv_entry *entry) 1743 { 1744 int instance; 1745 struct amdgpu_task_info *task_info; 1746 u64 addr; 1747 1748 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1749 if (instance < 0 || instance >= adev->sdma.num_instances) { 1750 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1751 return -EINVAL; 1752 } 1753 1754 addr = (u64)entry->src_data[0] << 12; 1755 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1756 1757 dev_dbg_ratelimited(adev->dev, 1758 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1759 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1760 entry->pasid); 1761 1762 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1763 if (task_info) { 1764 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1765 task_info->process_name, task_info->tgid, 1766 task_info->task.comm, task_info->task.pid); 1767 amdgpu_vm_put_task_info(task_info); 1768 } 1769 1770 return 0; 1771 } 1772 1773 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1774 struct amdgpu_irq_src *source, 1775 struct amdgpu_iv_entry *entry) 1776 { 1777 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1778 sdma_v4_4_2_print_iv_entry(adev, entry); 1779 return 0; 1780 } 1781 1782 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1783 struct amdgpu_irq_src *source, 1784 struct amdgpu_iv_entry *entry) 1785 { 1786 1787 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1788 sdma_v4_4_2_print_iv_entry(adev, entry); 1789 return 0; 1790 } 1791 1792 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1793 struct amdgpu_irq_src *source, 1794 struct amdgpu_iv_entry *entry) 1795 { 1796 dev_dbg_ratelimited(adev->dev, 1797 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1798 sdma_v4_4_2_print_iv_entry(adev, entry); 1799 return 0; 1800 } 1801 1802 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1803 struct amdgpu_irq_src *source, 1804 struct amdgpu_iv_entry *entry) 1805 { 1806 dev_dbg_ratelimited(adev->dev, 1807 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1808 sdma_v4_4_2_print_iv_entry(adev, entry); 1809 return 0; 1810 } 1811 1812 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1813 struct amdgpu_irq_src *source, 1814 struct amdgpu_iv_entry *entry) 1815 { 1816 /* There is nothing useful to be done here, only kept for debug */ 1817 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1818 sdma_v4_4_2_print_iv_entry(adev, entry); 1819 return 0; 1820 } 1821 1822 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1823 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1824 { 1825 uint32_t data, def; 1826 int i; 1827 1828 /* leave as default if it is not driver controlled */ 1829 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1830 return; 1831 1832 if (enable) { 1833 for_each_inst(i, inst_mask) { 1834 /* 1-not override: enable sdma mem light sleep */ 1835 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1836 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1837 if (def != data) 1838 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1839 } 1840 } else { 1841 for_each_inst(i, inst_mask) { 1842 /* 0-override:disable sdma mem light sleep */ 1843 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1844 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1845 if (def != data) 1846 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1847 } 1848 } 1849 } 1850 1851 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1852 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1853 { 1854 uint32_t data, def; 1855 int i; 1856 1857 /* leave as default if it is not driver controlled */ 1858 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1859 return; 1860 1861 if (enable) { 1862 for_each_inst(i, inst_mask) { 1863 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1864 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1865 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1866 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1867 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1868 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1869 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1870 if (def != data) 1871 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1872 } 1873 } else { 1874 for_each_inst(i, inst_mask) { 1875 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1876 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1877 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1878 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1879 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1880 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1881 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1882 if (def != data) 1883 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1884 } 1885 } 1886 } 1887 1888 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1889 enum amd_clockgating_state state) 1890 { 1891 struct amdgpu_device *adev = ip_block->adev; 1892 uint32_t inst_mask; 1893 1894 if (amdgpu_sriov_vf(adev)) 1895 return 0; 1896 1897 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1898 1899 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1900 adev, state == AMD_CG_STATE_GATE, inst_mask); 1901 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1902 adev, state == AMD_CG_STATE_GATE, inst_mask); 1903 return 0; 1904 } 1905 1906 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 1907 enum amd_powergating_state state) 1908 { 1909 return 0; 1910 } 1911 1912 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1913 { 1914 struct amdgpu_device *adev = ip_block->adev; 1915 int data; 1916 1917 if (amdgpu_sriov_vf(adev)) 1918 *flags = 0; 1919 1920 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1921 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1922 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1923 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1924 1925 /* AMD_CG_SUPPORT_SDMA_LS */ 1926 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1927 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1928 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1929 } 1930 1931 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1932 { 1933 struct amdgpu_device *adev = ip_block->adev; 1934 int i, j; 1935 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1936 uint32_t instance_offset; 1937 1938 if (!adev->sdma.ip_dump) 1939 return; 1940 1941 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1942 for (i = 0; i < adev->sdma.num_instances; i++) { 1943 instance_offset = i * reg_count; 1944 drm_printf(p, "\nInstance:%d\n", i); 1945 1946 for (j = 0; j < reg_count; j++) 1947 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 1948 adev->sdma.ip_dump[instance_offset + j]); 1949 } 1950 } 1951 1952 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 1953 { 1954 struct amdgpu_device *adev = ip_block->adev; 1955 int i, j; 1956 uint32_t instance_offset; 1957 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1958 1959 if (!adev->sdma.ip_dump) 1960 return; 1961 1962 for (i = 0; i < adev->sdma.num_instances; i++) { 1963 instance_offset = i * reg_count; 1964 for (j = 0; j < reg_count; j++) 1965 adev->sdma.ip_dump[instance_offset + j] = 1966 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 1967 sdma_reg_list_4_4_2[j].reg_offset)); 1968 } 1969 } 1970 1971 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1972 .name = "sdma_v4_4_2", 1973 .early_init = sdma_v4_4_2_early_init, 1974 .late_init = sdma_v4_4_2_late_init, 1975 .sw_init = sdma_v4_4_2_sw_init, 1976 .sw_fini = sdma_v4_4_2_sw_fini, 1977 .hw_init = sdma_v4_4_2_hw_init, 1978 .hw_fini = sdma_v4_4_2_hw_fini, 1979 .suspend = sdma_v4_4_2_suspend, 1980 .resume = sdma_v4_4_2_resume, 1981 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1982 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1983 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1984 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1985 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 1986 .print_ip_state = sdma_v4_4_2_print_ip_state, 1987 }; 1988 1989 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1990 .type = AMDGPU_RING_TYPE_SDMA, 1991 .align_mask = 0xff, 1992 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1993 .support_64bit_ptrs = true, 1994 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1995 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1996 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1997 .emit_frame_size = 1998 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1999 3 + /* hdp invalidate */ 2000 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2001 /* sdma_v4_4_2_ring_emit_vm_flush */ 2002 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2003 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2004 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2005 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2006 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2007 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2008 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2009 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2010 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2011 .test_ring = sdma_v4_4_2_ring_test_ring, 2012 .test_ib = sdma_v4_4_2_ring_test_ib, 2013 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2014 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2015 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2016 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2017 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2018 .reset = amdgpu_sdma_reset_queue_legacy, 2019 }; 2020 2021 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2022 .type = AMDGPU_RING_TYPE_SDMA, 2023 .align_mask = 0xff, 2024 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2025 .support_64bit_ptrs = true, 2026 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2027 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2028 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2029 .emit_frame_size = 2030 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2031 3 + /* hdp invalidate */ 2032 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2033 /* sdma_v4_4_2_ring_emit_vm_flush */ 2034 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2035 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2036 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2037 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2038 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2039 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2040 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2041 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2042 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2043 .test_ring = sdma_v4_4_2_ring_test_ring, 2044 .test_ib = sdma_v4_4_2_ring_test_ib, 2045 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2046 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2047 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2048 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2049 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2050 .reset = amdgpu_sdma_reset_queue_legacy, 2051 }; 2052 2053 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2054 { 2055 int i, dev_inst; 2056 2057 for (i = 0; i < adev->sdma.num_instances; i++) { 2058 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2059 adev->sdma.instance[i].ring.me = i; 2060 if (adev->sdma.has_page_queue) { 2061 adev->sdma.instance[i].page.funcs = 2062 &sdma_v4_4_2_page_ring_funcs; 2063 adev->sdma.instance[i].page.me = i; 2064 } 2065 2066 dev_inst = GET_INST(SDMA0, i); 2067 /* AID to which SDMA belongs depends on physical instance */ 2068 adev->sdma.instance[i].aid_id = 2069 dev_inst / adev->sdma.num_inst_per_aid; 2070 } 2071 } 2072 2073 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2074 .set = sdma_v4_4_2_set_trap_irq_state, 2075 .process = sdma_v4_4_2_process_trap_irq, 2076 }; 2077 2078 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2079 .process = sdma_v4_4_2_process_illegal_inst_irq, 2080 }; 2081 2082 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2083 .set = sdma_v4_4_2_set_ecc_irq_state, 2084 .process = amdgpu_sdma_process_ecc_irq, 2085 }; 2086 2087 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2088 .process = sdma_v4_4_2_process_vm_hole_irq, 2089 }; 2090 2091 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2092 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2093 }; 2094 2095 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2096 .process = sdma_v4_4_2_process_pool_timeout_irq, 2097 }; 2098 2099 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2100 .process = sdma_v4_4_2_process_srbm_write_irq, 2101 }; 2102 2103 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2104 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2105 }; 2106 2107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2108 { 2109 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2110 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2111 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2112 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2113 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2114 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2115 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2116 2117 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2118 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2119 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2120 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2121 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2122 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2123 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2124 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2125 } 2126 2127 /** 2128 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2129 * 2130 * @ib: indirect buffer to copy to 2131 * @src_offset: src GPU address 2132 * @dst_offset: dst GPU address 2133 * @byte_count: number of bytes to xfer 2134 * @copy_flags: copy flags for the buffers 2135 * 2136 * Copy GPU buffers using the DMA engine. 2137 * Used by the amdgpu ttm implementation to move pages if 2138 * registered as the asic copy callback. 2139 */ 2140 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2141 uint64_t src_offset, 2142 uint64_t dst_offset, 2143 uint32_t byte_count, 2144 uint32_t copy_flags) 2145 { 2146 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2147 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2148 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2149 ib->ptr[ib->length_dw++] = byte_count - 1; 2150 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2151 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2152 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2153 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2154 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2155 } 2156 2157 /** 2158 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2159 * 2160 * @ib: indirect buffer to copy to 2161 * @src_data: value to write to buffer 2162 * @dst_offset: dst GPU address 2163 * @byte_count: number of bytes to xfer 2164 * 2165 * Fill GPU buffers using the DMA engine. 2166 */ 2167 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2168 uint32_t src_data, 2169 uint64_t dst_offset, 2170 uint32_t byte_count) 2171 { 2172 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2173 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2174 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2175 ib->ptr[ib->length_dw++] = src_data; 2176 ib->ptr[ib->length_dw++] = byte_count - 1; 2177 } 2178 2179 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2180 .copy_max_bytes = 1 << 30, 2181 .copy_num_dw = 7, 2182 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2183 2184 .fill_max_bytes = 1 << 30, 2185 .fill_num_dw = 5, 2186 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2187 }; 2188 2189 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2190 { 2191 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs); 2192 } 2193 2194 /** 2195 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2196 * @adev: Pointer to the AMDGPU device structure 2197 * 2198 * This function update reset mask for SDMA and sets the supported 2199 * reset types based on the IP version and firmware versions. 2200 * 2201 */ 2202 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2203 { 2204 /* per queue reset not supported for SRIOV */ 2205 if (amdgpu_sriov_vf(adev)) 2206 return; 2207 2208 /* 2209 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2210 * it needs to check both of them at here to skip old mec and pmfw. 2211 */ 2212 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2213 case IP_VERSION(9, 4, 3): 2214 case IP_VERSION(9, 4, 4): 2215 if ((adev->gfx.mec_fw_version >= 0xb0) && 2216 amdgpu_dpm_reset_sdma_is_supported(adev) && 2217 !adev->debug_disable_gpu_ring_reset) 2218 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2219 break; 2220 case IP_VERSION(9, 5, 0): 2221 if ((adev->gfx.mec_fw_version >= 0xf) && 2222 amdgpu_dpm_reset_sdma_is_supported(adev) && 2223 !adev->debug_disable_gpu_ring_reset) 2224 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2225 break; 2226 default: 2227 break; 2228 } 2229 2230 } 2231 2232 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2233 .type = AMD_IP_BLOCK_TYPE_SDMA, 2234 .major = 4, 2235 .minor = 4, 2236 .rev = 2, 2237 .funcs = &sdma_v4_4_2_ip_funcs, 2238 }; 2239 2240 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2241 { 2242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2243 int r; 2244 2245 if (!amdgpu_sriov_vf(adev)) 2246 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2247 2248 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2249 2250 return r; 2251 } 2252 2253 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2254 { 2255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2256 uint32_t tmp_mask = inst_mask; 2257 int i; 2258 2259 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2260 for_each_inst(i, tmp_mask) { 2261 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2262 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2263 } 2264 } 2265 2266 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2267 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2268 2269 return 0; 2270 } 2271 2272 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2273 .suspend = &sdma_v4_4_2_xcp_suspend, 2274 .resume = &sdma_v4_4_2_xcp_resume 2275 }; 2276 2277 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2278 .ras_block = { 2279 .hw_ops = NULL, 2280 }, 2281 }; 2282 2283 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2284 { 2285 adev->sdma.ras = &sdma_v4_4_2_ras; 2286 } 2287