1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_xcp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_trace.h"
33 #include "amdgpu_reset.h"
34
35 #include "sdma/sdma_4_4_2_offset.h"
36 #include "sdma/sdma_4_4_2_sh_mask.h"
37
38 #include "soc15_common.h"
39 #include "soc15.h"
40 #include "vega10_sdma_pkt_open.h"
41
42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
44
45 #include "amdgpu_ras.h"
46
47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
48 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin");
49
50 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = {
51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),
52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),
53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),
54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),
55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),
56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),
57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),
58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),
59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),
60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),
61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO),
71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI),
72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN),
75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG),
76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR),
78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI),
79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR),
80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI),
81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET),
82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO),
83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI),
84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG),
85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL),
86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR),
87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI),
88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR),
89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI),
90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET),
91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO),
92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI),
93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG),
94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL)
95 };
96
97 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
98
99 #define WREG32_SDMA(instance, offset, value) \
100 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
101 #define RREG32_SDMA(instance, offset) \
102 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
103
104 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
105 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
106 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
109 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev);
110 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring);
111 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring);
112
sdma_v4_4_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 offset)113 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
114 u32 instance, u32 offset)
115 {
116 u32 dev_inst = GET_INST(SDMA0, instance);
117
118 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
119 }
120
sdma_v4_4_2_seq_to_irq_id(int seq_num)121 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
122 {
123 switch (seq_num) {
124 case 0:
125 return SOC15_IH_CLIENTID_SDMA0;
126 case 1:
127 return SOC15_IH_CLIENTID_SDMA1;
128 case 2:
129 return SOC15_IH_CLIENTID_SDMA2;
130 case 3:
131 return SOC15_IH_CLIENTID_SDMA3;
132 default:
133 return -EINVAL;
134 }
135 }
136
sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device * adev,unsigned client_id)137 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id)
138 {
139 switch (client_id) {
140 case SOC15_IH_CLIENTID_SDMA0:
141 return 0;
142 case SOC15_IH_CLIENTID_SDMA1:
143 return 1;
144 case SOC15_IH_CLIENTID_SDMA2:
145 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
146 return 0;
147 else
148 return 2;
149 case SOC15_IH_CLIENTID_SDMA3:
150 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
151 return 1;
152 else
153 return 3;
154 default:
155 return -EINVAL;
156 }
157 }
158
sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device * adev,uint32_t inst_mask)159 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
160 uint32_t inst_mask)
161 {
162 u32 val;
163 int i;
164
165 for (i = 0; i < adev->sdma.num_instances; i++) {
166 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
167 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
168 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
169 PIPE_INTERLEAVE_SIZE, 0);
170 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
171
172 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
173 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
174 4);
175 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
176 PIPE_INTERLEAVE_SIZE, 0);
177 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
178 }
179 }
180
181 /**
182 * sdma_v4_4_2_init_microcode - load ucode images from disk
183 *
184 * @adev: amdgpu_device pointer
185 *
186 * Use the firmware interface to load the ucode images into
187 * the driver (not loaded into hw).
188 * Returns 0 on success, error on failure.
189 */
sdma_v4_4_2_init_microcode(struct amdgpu_device * adev)190 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
191 {
192 int ret, i;
193
194 for (i = 0; i < adev->sdma.num_instances; i++) {
195 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
196 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) ||
197 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
198 ret = amdgpu_sdma_init_microcode(adev, 0, true);
199 break;
200 } else {
201 ret = amdgpu_sdma_init_microcode(adev, i, false);
202 if (ret)
203 return ret;
204 }
205 }
206
207 return ret;
208 }
209
210 /**
211 * sdma_v4_4_2_ring_get_rptr - get the current read pointer
212 *
213 * @ring: amdgpu ring pointer
214 *
215 * Get the current rptr from the hardware.
216 */
sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring * ring)217 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
218 {
219 u64 rptr;
220
221 /* XXX check if swapping is necessary on BE */
222 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
223
224 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
225 return rptr >> 2;
226 }
227
228 /**
229 * sdma_v4_4_2_ring_get_wptr - get the current write pointer
230 *
231 * @ring: amdgpu ring pointer
232 *
233 * Get the current wptr from the hardware.
234 */
sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring * ring)235 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
236 {
237 struct amdgpu_device *adev = ring->adev;
238 u64 wptr;
239
240 if (ring->use_doorbell) {
241 /* XXX check if swapping is necessary on BE */
242 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
243 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
244 } else {
245 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
246 wptr = wptr << 32;
247 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
248 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
249 ring->me, wptr);
250 }
251
252 return wptr >> 2;
253 }
254
255 /**
256 * sdma_v4_4_2_ring_set_wptr - commit the write pointer
257 *
258 * @ring: amdgpu ring pointer
259 *
260 * Write the wptr back to the hardware.
261 */
sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring * ring)262 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
263 {
264 struct amdgpu_device *adev = ring->adev;
265
266 DRM_DEBUG("Setting write pointer\n");
267 if (ring->use_doorbell) {
268 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
269
270 DRM_DEBUG("Using doorbell -- "
271 "wptr_offs == 0x%08x "
272 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
273 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
274 ring->wptr_offs,
275 lower_32_bits(ring->wptr << 2),
276 upper_32_bits(ring->wptr << 2));
277 /* XXX check if swapping is necessary on BE */
278 WRITE_ONCE(*wb, (ring->wptr << 2));
279 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
280 ring->doorbell_index, ring->wptr << 2);
281 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
282 } else {
283 DRM_DEBUG("Not using doorbell -- "
284 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
285 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
286 ring->me,
287 lower_32_bits(ring->wptr << 2),
288 ring->me,
289 upper_32_bits(ring->wptr << 2));
290 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
291 lower_32_bits(ring->wptr << 2));
292 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
293 upper_32_bits(ring->wptr << 2));
294 }
295 }
296
297 /**
298 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
299 *
300 * @ring: amdgpu ring pointer
301 *
302 * Get the current wptr from the hardware.
303 */
sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring * ring)304 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
305 {
306 struct amdgpu_device *adev = ring->adev;
307 u64 wptr;
308
309 if (ring->use_doorbell) {
310 /* XXX check if swapping is necessary on BE */
311 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
312 } else {
313 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
314 wptr = wptr << 32;
315 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
316 }
317
318 return wptr >> 2;
319 }
320
321 /**
322 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
323 *
324 * @ring: amdgpu ring pointer
325 *
326 * Write the wptr back to the hardware.
327 */
sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring * ring)328 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
329 {
330 struct amdgpu_device *adev = ring->adev;
331
332 if (ring->use_doorbell) {
333 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
334
335 /* XXX check if swapping is necessary on BE */
336 WRITE_ONCE(*wb, (ring->wptr << 2));
337 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
338 } else {
339 uint64_t wptr = ring->wptr << 2;
340
341 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
342 lower_32_bits(wptr));
343 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
344 upper_32_bits(wptr));
345 }
346 }
347
sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)348 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
349 {
350 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
351 int i;
352
353 for (i = 0; i < count; i++)
354 if (sdma && sdma->burst_nop && (i == 0))
355 amdgpu_ring_write(ring, ring->funcs->nop |
356 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
357 else
358 amdgpu_ring_write(ring, ring->funcs->nop);
359 }
360
361 /**
362 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
363 *
364 * @ring: amdgpu ring pointer
365 * @job: job to retrieve vmid from
366 * @ib: IB object to schedule
367 * @flags: unused
368 *
369 * Schedule an IB in the DMA ring.
370 */
sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)371 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
372 struct amdgpu_job *job,
373 struct amdgpu_ib *ib,
374 uint32_t flags)
375 {
376 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
377
378 /* IB packet must end on a 8 DW boundary */
379 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
380
381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
382 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
383 /* base must be 32 byte aligned */
384 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
385 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
386 amdgpu_ring_write(ring, ib->length_dw);
387 amdgpu_ring_write(ring, 0);
388 amdgpu_ring_write(ring, 0);
389
390 }
391
sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring * ring,int mem_space,int hdp,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)392 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
393 int mem_space, int hdp,
394 uint32_t addr0, uint32_t addr1,
395 uint32_t ref, uint32_t mask,
396 uint32_t inv)
397 {
398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
399 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
400 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
401 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
402 if (mem_space) {
403 /* memory */
404 amdgpu_ring_write(ring, addr0);
405 amdgpu_ring_write(ring, addr1);
406 } else {
407 /* registers */
408 amdgpu_ring_write(ring, addr0 << 2);
409 amdgpu_ring_write(ring, addr1 << 2);
410 }
411 amdgpu_ring_write(ring, ref); /* reference */
412 amdgpu_ring_write(ring, mask); /* mask */
413 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
414 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
415 }
416
417 /**
418 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
419 *
420 * @ring: amdgpu ring pointer
421 *
422 * Emit an hdp flush packet on the requested DMA ring.
423 */
sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)424 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
425 {
426 struct amdgpu_device *adev = ring->adev;
427 u32 ref_and_mask = 0;
428 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
429
430 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
431 << (ring->me % adev->sdma.num_inst_per_aid);
432
433 sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
434 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
435 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
436 ref_and_mask, ref_and_mask, 10);
437 }
438
439 /**
440 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
441 *
442 * @ring: amdgpu ring pointer
443 * @addr: address
444 * @seq: sequence number
445 * @flags: fence related flags
446 *
447 * Add a DMA fence packet to the ring to write
448 * the fence seq number and DMA trap packet to generate
449 * an interrupt if needed.
450 */
sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)451 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
452 unsigned flags)
453 {
454 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
455 /* write the fence */
456 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
457 /* zero in first two bits */
458 BUG_ON(addr & 0x3);
459 amdgpu_ring_write(ring, lower_32_bits(addr));
460 amdgpu_ring_write(ring, upper_32_bits(addr));
461 amdgpu_ring_write(ring, lower_32_bits(seq));
462
463 /* optionally write high bits as well */
464 if (write64bit) {
465 addr += 4;
466 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
467 /* zero in first two bits */
468 BUG_ON(addr & 0x3);
469 amdgpu_ring_write(ring, lower_32_bits(addr));
470 amdgpu_ring_write(ring, upper_32_bits(addr));
471 amdgpu_ring_write(ring, upper_32_bits(seq));
472 }
473
474 /* generate an interrupt */
475 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
476 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
477 }
478
479
480 /**
481 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
482 *
483 * @adev: amdgpu_device pointer
484 * @inst_mask: mask of dma engine instances to be disabled
485 *
486 * Stop the gfx async dma ring buffers.
487 */
sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device * adev,uint32_t inst_mask)488 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
489 uint32_t inst_mask)
490 {
491 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
492 u32 doorbell_offset, doorbell;
493 u32 rb_cntl, ib_cntl, sdma_cntl;
494 int i;
495
496 for_each_inst(i, inst_mask) {
497 sdma[i] = &adev->sdma.instance[i].ring;
498
499 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
501 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
502 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
503 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
504 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
505 sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL);
506 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0);
507 WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl);
508
509 if (sdma[i]->use_doorbell) {
510 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
511 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
512
513 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
514 doorbell_offset = REG_SET_FIELD(doorbell_offset,
515 SDMA_GFX_DOORBELL_OFFSET,
516 OFFSET, 0);
517 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
518 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
519 }
520 }
521 }
522
523 /**
524 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
525 *
526 * @adev: amdgpu_device pointer
527 * @inst_mask: mask of dma engine instances to be disabled
528 *
529 * Stop the compute async dma queues.
530 */
sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device * adev,uint32_t inst_mask)531 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
532 uint32_t inst_mask)
533 {
534 /* XXX todo */
535 }
536
537 /**
538 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
539 *
540 * @adev: amdgpu_device pointer
541 * @inst_mask: mask of dma engine instances to be disabled
542 *
543 * Stop the page async dma ring buffers.
544 */
sdma_v4_4_2_inst_page_stop(struct amdgpu_device * adev,uint32_t inst_mask)545 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
546 uint32_t inst_mask)
547 {
548 u32 rb_cntl, ib_cntl;
549 int i;
550
551 for_each_inst(i, inst_mask) {
552 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
554 RB_ENABLE, 0);
555 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
556 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
557 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
558 IB_ENABLE, 0);
559 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
560 }
561 }
562
563 /**
564 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
565 *
566 * @adev: amdgpu_device pointer
567 * @enable: enable/disable the DMA MEs context switch.
568 * @inst_mask: mask of dma engine instances to be enabled
569 *
570 * Halt or unhalt the async dma engines context switch.
571 */
sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)572 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
573 bool enable, uint32_t inst_mask)
574 {
575 u32 f32_cntl, phase_quantum = 0;
576 int i;
577
578 if (amdgpu_sdma_phase_quantum) {
579 unsigned value = amdgpu_sdma_phase_quantum;
580 unsigned unit = 0;
581
582 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
583 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
584 value = (value + 1) >> 1;
585 unit++;
586 }
587 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
588 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
589 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
590 SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
591 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
592 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
593 WARN_ONCE(1,
594 "clamping sdma_phase_quantum to %uK clock cycles\n",
595 value << unit);
596 }
597 phase_quantum =
598 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
599 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
600 }
601
602 for_each_inst(i, inst_mask) {
603 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
604 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
605 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
606 if (enable && amdgpu_sdma_phase_quantum) {
607 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
608 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
609 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
610 }
611 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
612
613 /* Extend page fault timeout to avoid interrupt storm */
614 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
615 }
616 }
617
618 /**
619 * sdma_v4_4_2_inst_enable - stop the async dma engines
620 *
621 * @adev: amdgpu_device pointer
622 * @enable: enable/disable the DMA MEs.
623 * @inst_mask: mask of dma engine instances to be enabled
624 *
625 * Halt or unhalt the async dma engines.
626 */
sdma_v4_4_2_inst_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)627 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
628 uint32_t inst_mask)
629 {
630 u32 f32_cntl;
631 int i;
632
633 if (!enable) {
634 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
635 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
636 if (adev->sdma.has_page_queue)
637 sdma_v4_4_2_inst_page_stop(adev, inst_mask);
638
639 /* SDMA FW needs to respond to FREEZE requests during reset.
640 * Keep it running during reset */
641 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
642 return;
643 }
644
645 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
646 return;
647
648 for_each_inst(i, inst_mask) {
649 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
650 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
651 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
652 }
653 }
654
655 /*
656 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
657 */
sdma_v4_4_2_rb_cntl(struct amdgpu_ring * ring,uint32_t rb_cntl)658 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
659 {
660 /* Set ring buffer size in dwords */
661 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
662
663 barrier(); /* work around https://llvm.org/pr42576 */
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
665 #ifdef __BIG_ENDIAN
666 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
668 RPTR_WRITEBACK_SWAP_ENABLE, 1);
669 #endif
670 return rb_cntl;
671 }
672
673 /**
674 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
675 *
676 * @adev: amdgpu_device pointer
677 * @i: instance to resume
678 * @restore: used to restore wptr when restart
679 *
680 * Set up the gfx DMA ring buffers and enable them.
681 * Returns 0 for success, error for failure.
682 */
sdma_v4_4_2_gfx_resume(struct amdgpu_device * adev,unsigned int i,bool restore)683 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
684 {
685 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
686 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
687 u32 wb_offset;
688 u32 doorbell;
689 u32 doorbell_offset;
690 u64 wptr_gpu_addr;
691 u64 rwptr;
692
693 wb_offset = (ring->rptr_offs * 4);
694
695 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
696 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
697 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
698
699 /* set the wb address whether it's enabled or not */
700 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
701 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
702 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
704
705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
706 RPTR_WRITEBACK_ENABLE, 1);
707
708 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
709 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
710
711 if (!restore)
712 ring->wptr = 0;
713
714 /* before programing wptr to a less value, need set minor_ptr_update first */
715 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
716
717 /* For the guilty queue, set RPTR to the current wptr to skip bad commands,
718 * It is not a guilty queue, restore cache_rptr and continue execution.
719 */
720 if (adev->sdma.instance[i].gfx_guilty)
721 rwptr = ring->wptr;
722 else
723 rwptr = ring->cached_rptr;
724
725 /* Initialize the ring buffer's read and write pointers */
726 if (restore) {
727 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2));
728 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2));
729 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2));
730 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2));
731 } else {
732 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
733 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
734 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
735 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
736 }
737
738 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
739 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
740
741 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
742 ring->use_doorbell);
743 doorbell_offset = REG_SET_FIELD(doorbell_offset,
744 SDMA_GFX_DOORBELL_OFFSET,
745 OFFSET, ring->doorbell_index);
746 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
747 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
748
749 sdma_v4_4_2_ring_set_wptr(ring);
750
751 /* set minor_ptr_update to 0 after wptr programed */
752 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
753
754 /* setup the wptr shadow polling */
755 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
756 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
757 lower_32_bits(wptr_gpu_addr));
758 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
759 upper_32_bits(wptr_gpu_addr));
760 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
761 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
762 SDMA_GFX_RB_WPTR_POLL_CNTL,
763 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
764 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
765
766 /* enable DMA RB */
767 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
768 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
769
770 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
771 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
772 #ifdef __BIG_ENDIAN
773 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
774 #endif
775 /* enable DMA IBs */
776 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
777 }
778
779 /**
780 * sdma_v4_4_2_page_resume - setup and start the async dma engines
781 *
782 * @adev: amdgpu_device pointer
783 * @i: instance to resume
784 * @restore: boolean to say restore needed or not
785 *
786 * Set up the page DMA ring buffers and enable them.
787 * Returns 0 for success, error for failure.
788 */
sdma_v4_4_2_page_resume(struct amdgpu_device * adev,unsigned int i,bool restore)789 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
790 {
791 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
792 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
793 u32 wb_offset;
794 u32 doorbell;
795 u32 doorbell_offset;
796 u64 wptr_gpu_addr;
797 u64 rwptr;
798
799 wb_offset = (ring->rptr_offs * 4);
800
801 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
802 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
803 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
804
805 /* For the guilty queue, set RPTR to the current wptr to skip bad commands,
806 * It is not a guilty queue, restore cache_rptr and continue execution.
807 */
808 if (adev->sdma.instance[i].page_guilty)
809 rwptr = ring->wptr;
810 else
811 rwptr = ring->cached_rptr;
812
813 /* Initialize the ring buffer's read and write pointers */
814 if (restore) {
815 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2));
816 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2));
817 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2));
818 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2));
819 } else {
820 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
821 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
822 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
823 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
824 }
825
826 /* set the wb address whether it's enabled or not */
827 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
828 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
829 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
830 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
831
832 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
833 RPTR_WRITEBACK_ENABLE, 1);
834
835 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
836 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
837
838 if (!restore)
839 ring->wptr = 0;
840
841 /* before programing wptr to a less value, need set minor_ptr_update first */
842 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
843
844 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
845 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
846
847 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
848 ring->use_doorbell);
849 doorbell_offset = REG_SET_FIELD(doorbell_offset,
850 SDMA_PAGE_DOORBELL_OFFSET,
851 OFFSET, ring->doorbell_index);
852 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
853 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
854
855 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
856 sdma_v4_4_2_page_ring_set_wptr(ring);
857
858 /* set minor_ptr_update to 0 after wptr programed */
859 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
860
861 /* setup the wptr shadow polling */
862 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
863 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
864 lower_32_bits(wptr_gpu_addr));
865 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
866 upper_32_bits(wptr_gpu_addr));
867 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
868 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
869 SDMA_PAGE_RB_WPTR_POLL_CNTL,
870 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
871 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
872
873 /* enable DMA RB */
874 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
875 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
876
877 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
878 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
879 #ifdef __BIG_ENDIAN
880 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
881 #endif
882 /* enable DMA IBs */
883 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
884 }
885
sdma_v4_4_2_init_pg(struct amdgpu_device * adev)886 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
887 {
888
889 }
890
891 /**
892 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
893 *
894 * @adev: amdgpu_device pointer
895 * @inst_mask: mask of dma engine instances to be enabled
896 *
897 * Set up the compute DMA queues and enable them.
898 * Returns 0 for success, error for failure.
899 */
sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device * adev,uint32_t inst_mask)900 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
901 uint32_t inst_mask)
902 {
903 sdma_v4_4_2_init_pg(adev);
904
905 return 0;
906 }
907
908 /**
909 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
910 *
911 * @adev: amdgpu_device pointer
912 * @inst_mask: mask of dma engine instances to be enabled
913 *
914 * Loads the sDMA0/1 ucode.
915 * Returns 0 for success, -EINVAL if the ucode is not available.
916 */
sdma_v4_4_2_inst_load_microcode(struct amdgpu_device * adev,uint32_t inst_mask)917 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
918 uint32_t inst_mask)
919 {
920 const struct sdma_firmware_header_v1_0 *hdr;
921 const __le32 *fw_data;
922 u32 fw_size;
923 int i, j;
924
925 /* halt the MEs */
926 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
927
928 for_each_inst(i, inst_mask) {
929 if (!adev->sdma.instance[i].fw)
930 return -EINVAL;
931
932 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
933 amdgpu_ucode_print_sdma_hdr(&hdr->header);
934 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
935
936 fw_data = (const __le32 *)
937 (adev->sdma.instance[i].fw->data +
938 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
939
940 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
941
942 for (j = 0; j < fw_size; j++)
943 WREG32_SDMA(i, regSDMA_UCODE_DATA,
944 le32_to_cpup(fw_data++));
945
946 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
947 adev->sdma.instance[i].fw_version);
948 }
949
950 return 0;
951 }
952
953 /**
954 * sdma_v4_4_2_inst_start - setup and start the async dma engines
955 *
956 * @adev: amdgpu_device pointer
957 * @inst_mask: mask of dma engine instances to be enabled
958 * @restore: boolean to say restore needed or not
959 *
960 * Set up the DMA engines and enable them.
961 * Returns 0 for success, error for failure.
962 */
sdma_v4_4_2_inst_start(struct amdgpu_device * adev,uint32_t inst_mask,bool restore)963 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
964 uint32_t inst_mask, bool restore)
965 {
966 struct amdgpu_ring *ring;
967 uint32_t tmp_mask;
968 int i, r = 0;
969
970 if (amdgpu_sriov_vf(adev)) {
971 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
972 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
973 } else {
974 /* bypass sdma microcode loading on Gopher */
975 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
976 adev->sdma.instance[0].fw) {
977 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
978 if (r)
979 return r;
980 }
981
982 /* unhalt the MEs */
983 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
984 /* enable sdma ring preemption */
985 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
986 }
987
988 /* start the gfx rings and rlc compute queues */
989 tmp_mask = inst_mask;
990 for_each_inst(i, tmp_mask) {
991 uint32_t temp;
992
993 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
994 sdma_v4_4_2_gfx_resume(adev, i, restore);
995 if (adev->sdma.has_page_queue)
996 sdma_v4_4_2_page_resume(adev, i, restore);
997
998 /* set utc l1 enable flag always to 1 */
999 temp = RREG32_SDMA(i, regSDMA_CNTL);
1000 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
1001 WREG32_SDMA(i, regSDMA_CNTL, temp);
1002
1003 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) {
1004 /* enable context empty interrupt during initialization */
1005 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
1006 WREG32_SDMA(i, regSDMA_CNTL, temp);
1007 }
1008 if (!amdgpu_sriov_vf(adev)) {
1009 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1010 /* unhalt engine */
1011 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
1012 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
1013 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
1014 }
1015 }
1016 }
1017
1018 if (amdgpu_sriov_vf(adev)) {
1019 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
1020 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
1021 } else {
1022 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
1023 if (r)
1024 return r;
1025 }
1026
1027 tmp_mask = inst_mask;
1028 for_each_inst(i, tmp_mask) {
1029 ring = &adev->sdma.instance[i].ring;
1030
1031 r = amdgpu_ring_test_helper(ring);
1032 if (r)
1033 return r;
1034
1035 if (adev->sdma.has_page_queue) {
1036 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1037
1038 r = amdgpu_ring_test_helper(page);
1039 if (r)
1040 return r;
1041 }
1042 }
1043
1044 return r;
1045 }
1046
1047 /**
1048 * sdma_v4_4_2_ring_test_ring - simple async dma engine test
1049 *
1050 * @ring: amdgpu_ring structure holding ring information
1051 *
1052 * Test the DMA engine by writing using it to write an
1053 * value to memory.
1054 * Returns 0 for success, error for failure.
1055 */
sdma_v4_4_2_ring_test_ring(struct amdgpu_ring * ring)1056 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
1057 {
1058 struct amdgpu_device *adev = ring->adev;
1059 unsigned i;
1060 unsigned index;
1061 int r;
1062 u32 tmp;
1063 u64 gpu_addr;
1064
1065 r = amdgpu_device_wb_get(adev, &index);
1066 if (r)
1067 return r;
1068
1069 gpu_addr = adev->wb.gpu_addr + (index * 4);
1070 tmp = 0xCAFEDEAD;
1071 adev->wb.wb[index] = cpu_to_le32(tmp);
1072
1073 r = amdgpu_ring_alloc(ring, 5);
1074 if (r)
1075 goto error_free_wb;
1076
1077 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1078 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1079 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1080 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1081 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1082 amdgpu_ring_write(ring, 0xDEADBEEF);
1083 amdgpu_ring_commit(ring);
1084
1085 for (i = 0; i < adev->usec_timeout; i++) {
1086 tmp = le32_to_cpu(adev->wb.wb[index]);
1087 if (tmp == 0xDEADBEEF)
1088 break;
1089 udelay(1);
1090 }
1091
1092 if (i >= adev->usec_timeout)
1093 r = -ETIMEDOUT;
1094
1095 error_free_wb:
1096 amdgpu_device_wb_free(adev, index);
1097 return r;
1098 }
1099
1100 /**
1101 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1102 *
1103 * @ring: amdgpu_ring structure holding ring information
1104 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1105 *
1106 * Test a simple IB in the DMA ring.
1107 * Returns 0 on success, error on failure.
1108 */
sdma_v4_4_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)1109 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1110 {
1111 struct amdgpu_device *adev = ring->adev;
1112 struct amdgpu_ib ib;
1113 struct dma_fence *f = NULL;
1114 unsigned index;
1115 long r;
1116 u32 tmp = 0;
1117 u64 gpu_addr;
1118
1119 r = amdgpu_device_wb_get(adev, &index);
1120 if (r)
1121 return r;
1122
1123 gpu_addr = adev->wb.gpu_addr + (index * 4);
1124 tmp = 0xCAFEDEAD;
1125 adev->wb.wb[index] = cpu_to_le32(tmp);
1126 memset(&ib, 0, sizeof(ib));
1127 r = amdgpu_ib_get(adev, NULL, 256,
1128 AMDGPU_IB_POOL_DIRECT, &ib);
1129 if (r)
1130 goto err0;
1131
1132 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1133 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1134 ib.ptr[1] = lower_32_bits(gpu_addr);
1135 ib.ptr[2] = upper_32_bits(gpu_addr);
1136 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1137 ib.ptr[4] = 0xDEADBEEF;
1138 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1139 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1140 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1141 ib.length_dw = 8;
1142
1143 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1144 if (r)
1145 goto err1;
1146
1147 r = dma_fence_wait_timeout(f, false, timeout);
1148 if (r == 0) {
1149 r = -ETIMEDOUT;
1150 goto err1;
1151 } else if (r < 0) {
1152 goto err1;
1153 }
1154 tmp = le32_to_cpu(adev->wb.wb[index]);
1155 if (tmp == 0xDEADBEEF)
1156 r = 0;
1157 else
1158 r = -EINVAL;
1159
1160 err1:
1161 amdgpu_ib_free(&ib, NULL);
1162 dma_fence_put(f);
1163 err0:
1164 amdgpu_device_wb_free(adev, index);
1165 return r;
1166 }
1167
1168
1169 /**
1170 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1171 *
1172 * @ib: indirect buffer to fill with commands
1173 * @pe: addr of the page entry
1174 * @src: src addr to copy from
1175 * @count: number of page entries to update
1176 *
1177 * Update PTEs by copying them from the GART using sDMA.
1178 */
sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1179 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1180 uint64_t pe, uint64_t src,
1181 unsigned count)
1182 {
1183 unsigned bytes = count * 8;
1184
1185 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1186 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1187 ib->ptr[ib->length_dw++] = bytes - 1;
1188 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1189 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1190 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1191 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1192 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1193
1194 }
1195
1196 /**
1197 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1198 *
1199 * @ib: indirect buffer to fill with commands
1200 * @pe: addr of the page entry
1201 * @value: dst addr to write into pe
1202 * @count: number of page entries to update
1203 * @incr: increase next addr by incr bytes
1204 *
1205 * Update PTEs by writing them manually using sDMA.
1206 */
sdma_v4_4_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1207 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1208 uint64_t value, unsigned count,
1209 uint32_t incr)
1210 {
1211 unsigned ndw = count * 2;
1212
1213 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1214 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1215 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1216 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1217 ib->ptr[ib->length_dw++] = ndw - 1;
1218 for (; ndw > 0; ndw -= 2) {
1219 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1220 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1221 value += incr;
1222 }
1223 }
1224
1225 /**
1226 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1227 *
1228 * @ib: indirect buffer to fill with commands
1229 * @pe: addr of the page entry
1230 * @addr: dst addr to write into pe
1231 * @count: number of page entries to update
1232 * @incr: increase next addr by incr bytes
1233 * @flags: access flags
1234 *
1235 * Update the page tables using sDMA.
1236 */
sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1237 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1238 uint64_t pe,
1239 uint64_t addr, unsigned count,
1240 uint32_t incr, uint64_t flags)
1241 {
1242 /* for physically contiguous pages (vram) */
1243 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1244 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1245 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1246 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1247 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1248 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1249 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1250 ib->ptr[ib->length_dw++] = incr; /* increment size */
1251 ib->ptr[ib->length_dw++] = 0;
1252 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1253 }
1254
1255 /**
1256 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1257 *
1258 * @ring: amdgpu_ring structure holding ring information
1259 * @ib: indirect buffer to fill with padding
1260 */
sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1261 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1262 {
1263 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1264 u32 pad_count;
1265 int i;
1266
1267 pad_count = (-ib->length_dw) & 7;
1268 for (i = 0; i < pad_count; i++)
1269 if (sdma && sdma->burst_nop && (i == 0))
1270 ib->ptr[ib->length_dw++] =
1271 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1272 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1273 else
1274 ib->ptr[ib->length_dw++] =
1275 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1276 }
1277
1278
1279 /**
1280 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1281 *
1282 * @ring: amdgpu_ring pointer
1283 *
1284 * Make sure all previous operations are completed (CIK).
1285 */
sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1286 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1287 {
1288 uint32_t seq = ring->fence_drv.sync_seq;
1289 uint64_t addr = ring->fence_drv.gpu_addr;
1290
1291 /* wait for idle */
1292 sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1293 addr & 0xfffffffc,
1294 upper_32_bits(addr) & 0xffffffff,
1295 seq, 0xffffffff, 4);
1296 }
1297
1298
1299 /**
1300 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1301 *
1302 * @ring: amdgpu_ring pointer
1303 * @vmid: vmid number to use
1304 * @pd_addr: address
1305 *
1306 * Update the page table base and flush the VM TLB
1307 * using sDMA.
1308 */
sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1309 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1310 unsigned vmid, uint64_t pd_addr)
1311 {
1312 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1313 }
1314
sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1315 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1316 uint32_t reg, uint32_t val)
1317 {
1318 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1319 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1320 amdgpu_ring_write(ring, reg);
1321 amdgpu_ring_write(ring, val);
1322 }
1323
sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1324 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1325 uint32_t val, uint32_t mask)
1326 {
1327 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1328 }
1329
sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device * adev)1330 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1331 {
1332 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1333 case IP_VERSION(4, 4, 2):
1334 case IP_VERSION(4, 4, 5):
1335 return false;
1336 default:
1337 return false;
1338 }
1339 }
1340
1341 static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = {
1342 .stop_kernel_queue = &sdma_v4_4_2_stop_queue,
1343 .start_kernel_queue = &sdma_v4_4_2_restore_queue,
1344 };
1345
sdma_v4_4_2_early_init(struct amdgpu_ip_block * ip_block)1346 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
1347 {
1348 struct amdgpu_device *adev = ip_block->adev;
1349 int r;
1350
1351 r = sdma_v4_4_2_init_microcode(adev);
1352 if (r)
1353 return r;
1354
1355 /* TODO: Page queue breaks driver reload under SRIOV */
1356 if (sdma_v4_4_2_fw_support_paging_queue(adev))
1357 adev->sdma.has_page_queue = true;
1358
1359 sdma_v4_4_2_set_ring_funcs(adev);
1360 sdma_v4_4_2_set_buffer_funcs(adev);
1361 sdma_v4_4_2_set_vm_pte_funcs(adev);
1362 sdma_v4_4_2_set_irq_funcs(adev);
1363 sdma_v4_4_2_set_ras_funcs(adev);
1364 return 0;
1365 }
1366
1367 #if 0
1368 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1369 void *err_data,
1370 struct amdgpu_iv_entry *entry);
1371 #endif
1372
sdma_v4_4_2_late_init(struct amdgpu_ip_block * ip_block)1373 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block)
1374 {
1375 struct amdgpu_device *adev = ip_block->adev;
1376 #if 0
1377 struct ras_ih_if ih_info = {
1378 .cb = sdma_v4_4_2_process_ras_data_cb,
1379 };
1380 #endif
1381 if (!amdgpu_persistent_edc_harvesting_supported(adev))
1382 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1383
1384 /* The initialization is done in the late_init stage to ensure that the SMU
1385 * initialization and capability setup are completed before we check the SDMA
1386 * reset capability
1387 */
1388 sdma_v4_4_2_update_reset_mask(adev);
1389
1390 return 0;
1391 }
1392
sdma_v4_4_2_sw_init(struct amdgpu_ip_block * ip_block)1393 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block)
1394 {
1395 struct amdgpu_ring *ring;
1396 int r, i;
1397 struct amdgpu_device *adev = ip_block->adev;
1398 u32 aid_id;
1399 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1400 uint32_t *ptr;
1401
1402 /* SDMA trap event */
1403 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1404 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1405 SDMA0_4_0__SRCID__SDMA_TRAP,
1406 &adev->sdma.trap_irq);
1407 if (r)
1408 return r;
1409 }
1410
1411 /* SDMA SRAM ECC event */
1412 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1413 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1414 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1415 &adev->sdma.ecc_irq);
1416 if (r)
1417 return r;
1418 }
1419
1420 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1421 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1422 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1423 SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1424 &adev->sdma.vm_hole_irq);
1425 if (r)
1426 return r;
1427
1428 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1429 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1430 &adev->sdma.doorbell_invalid_irq);
1431 if (r)
1432 return r;
1433
1434 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1435 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1436 &adev->sdma.pool_timeout_irq);
1437 if (r)
1438 return r;
1439
1440 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1441 SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1442 &adev->sdma.srbm_write_irq);
1443 if (r)
1444 return r;
1445
1446 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1447 SDMA0_4_0__SRCID__SDMA_CTXEMPTY,
1448 &adev->sdma.ctxt_empty_irq);
1449 if (r)
1450 return r;
1451 }
1452
1453 for (i = 0; i < adev->sdma.num_instances; i++) {
1454 mutex_init(&adev->sdma.instance[i].engine_reset_mutex);
1455 /* Initialize guilty flags for GFX and PAGE queues */
1456 adev->sdma.instance[i].gfx_guilty = false;
1457 adev->sdma.instance[i].page_guilty = false;
1458 adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs;
1459
1460 ring = &adev->sdma.instance[i].ring;
1461 ring->ring_obj = NULL;
1462 ring->use_doorbell = true;
1463 aid_id = adev->sdma.instance[i].aid_id;
1464
1465 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1466 ring->use_doorbell?"true":"false");
1467
1468 /* doorbell size is 2 dwords, get DWORD offset */
1469 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1470 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1471
1472 sprintf(ring->name, "sdma%d.%d", aid_id,
1473 i % adev->sdma.num_inst_per_aid);
1474 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1475 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1476 AMDGPU_RING_PRIO_DEFAULT, NULL);
1477 if (r)
1478 return r;
1479
1480 if (adev->sdma.has_page_queue) {
1481 ring = &adev->sdma.instance[i].page;
1482 ring->ring_obj = NULL;
1483 ring->use_doorbell = true;
1484
1485 /* doorbell index of page queue is assigned right after
1486 * gfx queue on the same instance
1487 */
1488 ring->doorbell_index =
1489 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1490 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1491
1492 sprintf(ring->name, "page%d.%d", aid_id,
1493 i % adev->sdma.num_inst_per_aid);
1494 r = amdgpu_ring_init(adev, ring, 1024,
1495 &adev->sdma.trap_irq,
1496 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1497 AMDGPU_RING_PRIO_DEFAULT, NULL);
1498 if (r)
1499 return r;
1500 }
1501 }
1502
1503 adev->sdma.supported_reset =
1504 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
1505
1506 if (amdgpu_sdma_ras_sw_init(adev)) {
1507 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1508 return -EINVAL;
1509 }
1510
1511 /* Allocate memory for SDMA IP Dump buffer */
1512 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1513 if (ptr)
1514 adev->sdma.ip_dump = ptr;
1515 else
1516 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1517
1518 r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1519 if (r)
1520 return r;
1521
1522 return r;
1523 }
1524
sdma_v4_4_2_sw_fini(struct amdgpu_ip_block * ip_block)1525 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block)
1526 {
1527 struct amdgpu_device *adev = ip_block->adev;
1528 int i;
1529
1530 for (i = 0; i < adev->sdma.num_instances; i++) {
1531 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1532 if (adev->sdma.has_page_queue)
1533 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1534 }
1535
1536 amdgpu_sdma_sysfs_reset_mask_fini(adev);
1537 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
1538 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) ||
1539 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5))
1540 amdgpu_sdma_destroy_inst_ctx(adev, true);
1541 else
1542 amdgpu_sdma_destroy_inst_ctx(adev, false);
1543
1544 kfree(adev->sdma.ip_dump);
1545
1546 return 0;
1547 }
1548
sdma_v4_4_2_hw_init(struct amdgpu_ip_block * ip_block)1549 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block)
1550 {
1551 int r;
1552 struct amdgpu_device *adev = ip_block->adev;
1553 uint32_t inst_mask;
1554
1555 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1556 if (!amdgpu_sriov_vf(adev))
1557 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1558
1559 r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
1560
1561 return r;
1562 }
1563
sdma_v4_4_2_hw_fini(struct amdgpu_ip_block * ip_block)1564 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
1565 {
1566 struct amdgpu_device *adev = ip_block->adev;
1567 uint32_t inst_mask;
1568 int i;
1569
1570 if (amdgpu_sriov_vf(adev))
1571 return 0;
1572
1573 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1574 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1575 for (i = 0; i < adev->sdma.num_instances; i++) {
1576 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1577 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1578 }
1579 }
1580
1581 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1582 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1583
1584 return 0;
1585 }
1586
1587 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1588 enum amd_clockgating_state state);
1589
sdma_v4_4_2_suspend(struct amdgpu_ip_block * ip_block)1590 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
1591 {
1592 struct amdgpu_device *adev = ip_block->adev;
1593
1594 if (amdgpu_in_reset(adev))
1595 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
1596
1597 return sdma_v4_4_2_hw_fini(ip_block);
1598 }
1599
sdma_v4_4_2_resume(struct amdgpu_ip_block * ip_block)1600 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)
1601 {
1602 return sdma_v4_4_2_hw_init(ip_block);
1603 }
1604
sdma_v4_4_2_is_idle(struct amdgpu_ip_block * ip_block)1605 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
1606 {
1607 struct amdgpu_device *adev = ip_block->adev;
1608 u32 i;
1609
1610 for (i = 0; i < adev->sdma.num_instances; i++) {
1611 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1612
1613 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1614 return false;
1615 }
1616
1617 return true;
1618 }
1619
sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block * ip_block)1620 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
1621 {
1622 unsigned i, j;
1623 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1624 struct amdgpu_device *adev = ip_block->adev;
1625
1626 for (i = 0; i < adev->usec_timeout; i++) {
1627 for (j = 0; j < adev->sdma.num_instances; j++) {
1628 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1629 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1630 break;
1631 }
1632 if (j == adev->sdma.num_instances)
1633 return 0;
1634 udelay(1);
1635 }
1636 return -ETIMEDOUT;
1637 }
1638
sdma_v4_4_2_soft_reset(struct amdgpu_ip_block * ip_block)1639 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block)
1640 {
1641 /* todo */
1642
1643 return 0;
1644 }
1645
sdma_v4_4_2_is_queue_selected(struct amdgpu_device * adev,uint32_t instance_id,bool is_page_queue)1646 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)
1647 {
1648 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;
1649 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));
1650
1651 /* Check if the SELECTED bit is set */
1652 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0;
1653 }
1654
sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring * ring)1655 static bool sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring *ring)
1656 {
1657 struct amdgpu_device *adev = ring->adev;
1658 uint32_t instance_id = ring->me;
1659
1660 return sdma_v4_4_2_is_queue_selected(adev, instance_id, false);
1661 }
1662
sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring * ring)1663 static bool sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring *ring)
1664 {
1665 struct amdgpu_device *adev = ring->adev;
1666 uint32_t instance_id = ring->me;
1667
1668 if (!adev->sdma.has_page_queue)
1669 return false;
1670
1671 return sdma_v4_4_2_is_queue_selected(adev, instance_id, true);
1672 }
1673
sdma_v4_4_2_reset_queue(struct amdgpu_ring * ring,unsigned int vmid)1674 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
1675 {
1676 struct amdgpu_device *adev = ring->adev;
1677 u32 id = ring->me;
1678 int r;
1679
1680 if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
1681 return -EOPNOTSUPP;
1682
1683 amdgpu_amdkfd_suspend(adev, false);
1684 r = amdgpu_sdma_reset_engine(adev, id);
1685 amdgpu_amdkfd_resume(adev, false);
1686
1687 return r;
1688 }
1689
sdma_v4_4_2_stop_queue(struct amdgpu_ring * ring)1690 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
1691 {
1692 struct amdgpu_device *adev = ring->adev;
1693 u32 instance_id = ring->me;
1694 u32 inst_mask;
1695 uint64_t rptr;
1696
1697 if (amdgpu_sriov_vf(adev))
1698 return -EINVAL;
1699
1700 /* Check if this queue is the guilty one */
1701 adev->sdma.instance[instance_id].gfx_guilty =
1702 sdma_v4_4_2_is_queue_selected(adev, instance_id, false);
1703 if (adev->sdma.has_page_queue)
1704 adev->sdma.instance[instance_id].page_guilty =
1705 sdma_v4_4_2_is_queue_selected(adev, instance_id, true);
1706
1707 /* Cache the rptr before reset, after the reset,
1708 * all of the registers will be reset to 0
1709 */
1710 rptr = amdgpu_ring_get_rptr(ring);
1711 ring->cached_rptr = rptr;
1712 /* Cache the rptr for the page queue if it exists */
1713 if (adev->sdma.has_page_queue) {
1714 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page;
1715 rptr = amdgpu_ring_get_rptr(page_ring);
1716 page_ring->cached_rptr = rptr;
1717 }
1718
1719 /* stop queue */
1720 inst_mask = 1 << ring->me;
1721 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
1722 if (adev->sdma.has_page_queue)
1723 sdma_v4_4_2_inst_page_stop(adev, inst_mask);
1724
1725 return 0;
1726 }
1727
sdma_v4_4_2_restore_queue(struct amdgpu_ring * ring)1728 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
1729 {
1730 struct amdgpu_device *adev = ring->adev;
1731 u32 inst_mask;
1732 int i;
1733
1734 inst_mask = 1 << ring->me;
1735 udelay(50);
1736
1737 for (i = 0; i < adev->usec_timeout; i++) {
1738 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT))
1739 break;
1740 udelay(1);
1741 }
1742
1743 if (i == adev->usec_timeout) {
1744 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n",
1745 ring->me);
1746 return -ETIMEDOUT;
1747 }
1748
1749 return sdma_v4_4_2_inst_start(adev, inst_mask, true);
1750 }
1751
sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1752 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1753 struct amdgpu_irq_src *source,
1754 unsigned type,
1755 enum amdgpu_interrupt_state state)
1756 {
1757 u32 sdma_cntl;
1758
1759 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1760 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1761 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1762 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1763
1764 return 0;
1765 }
1766
sdma_v4_4_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1767 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1768 struct amdgpu_irq_src *source,
1769 struct amdgpu_iv_entry *entry)
1770 {
1771 uint32_t instance, i;
1772
1773 DRM_DEBUG("IH: SDMA trap\n");
1774 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1775
1776 /* Client id gives the SDMA instance in AID. To know the exact SDMA
1777 * instance, interrupt entry gives the node id which corresponds to the AID instance.
1778 * Match node id with the AID id associated with the SDMA instance. */
1779 for (i = instance; i < adev->sdma.num_instances;
1780 i += adev->sdma.num_inst_per_aid) {
1781 if (adev->sdma.instance[i].aid_id ==
1782 node_id_to_phys_map[entry->node_id])
1783 break;
1784 }
1785
1786 if (i >= adev->sdma.num_instances) {
1787 dev_WARN_ONCE(
1788 adev->dev, 1,
1789 "Couldn't find the right sdma instance in trap handler");
1790 return 0;
1791 }
1792
1793 switch (entry->ring_id) {
1794 case 0:
1795 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1796 break;
1797 case 1:
1798 amdgpu_fence_process(&adev->sdma.instance[i].page);
1799 break;
1800 default:
1801 break;
1802 }
1803 return 0;
1804 }
1805
1806 #if 0
1807 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1808 void *err_data,
1809 struct amdgpu_iv_entry *entry)
1810 {
1811 int instance;
1812
1813 /* When “Full RAS” is enabled, the per-IP interrupt sources should
1814 * be disabled and the driver should only look for the aggregated
1815 * interrupt via sync flood
1816 */
1817 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1818 goto out;
1819
1820 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1821 if (instance < 0)
1822 goto out;
1823
1824 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1825
1826 out:
1827 return AMDGPU_RAS_SUCCESS;
1828 }
1829 #endif
1830
sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1831 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1832 struct amdgpu_irq_src *source,
1833 struct amdgpu_iv_entry *entry)
1834 {
1835 int instance;
1836
1837 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1838
1839 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1840 if (instance < 0)
1841 return 0;
1842
1843 switch (entry->ring_id) {
1844 case 0:
1845 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1846 break;
1847 }
1848 return 0;
1849 }
1850
sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1851 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1852 struct amdgpu_irq_src *source,
1853 unsigned type,
1854 enum amdgpu_interrupt_state state)
1855 {
1856 u32 sdma_cntl;
1857
1858 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1859 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1860 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1861 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1862
1863 return 0;
1864 }
1865
sdma_v4_4_2_print_iv_entry(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)1866 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1867 struct amdgpu_iv_entry *entry)
1868 {
1869 int instance;
1870 struct amdgpu_task_info *task_info;
1871 u64 addr;
1872
1873 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1874 if (instance < 0 || instance >= adev->sdma.num_instances) {
1875 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1876 return -EINVAL;
1877 }
1878
1879 addr = (u64)entry->src_data[0] << 12;
1880 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1881
1882 dev_dbg_ratelimited(adev->dev,
1883 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1884 instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1885 entry->pasid);
1886
1887 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1888 if (task_info) {
1889 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1890 task_info->process_name, task_info->tgid,
1891 task_info->task_name, task_info->pid);
1892 amdgpu_vm_put_task_info(task_info);
1893 }
1894
1895 return 0;
1896 }
1897
sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1898 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1899 struct amdgpu_irq_src *source,
1900 struct amdgpu_iv_entry *entry)
1901 {
1902 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1903 sdma_v4_4_2_print_iv_entry(adev, entry);
1904 return 0;
1905 }
1906
sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1907 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1908 struct amdgpu_irq_src *source,
1909 struct amdgpu_iv_entry *entry)
1910 {
1911
1912 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1913 sdma_v4_4_2_print_iv_entry(adev, entry);
1914 return 0;
1915 }
1916
sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1917 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1918 struct amdgpu_irq_src *source,
1919 struct amdgpu_iv_entry *entry)
1920 {
1921 dev_dbg_ratelimited(adev->dev,
1922 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1923 sdma_v4_4_2_print_iv_entry(adev, entry);
1924 return 0;
1925 }
1926
sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1927 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1928 struct amdgpu_irq_src *source,
1929 struct amdgpu_iv_entry *entry)
1930 {
1931 dev_dbg_ratelimited(adev->dev,
1932 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1933 sdma_v4_4_2_print_iv_entry(adev, entry);
1934 return 0;
1935 }
1936
sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1937 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev,
1938 struct amdgpu_irq_src *source,
1939 struct amdgpu_iv_entry *entry)
1940 {
1941 /* There is nothing useful to be done here, only kept for debug */
1942 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt");
1943 sdma_v4_4_2_print_iv_entry(adev, entry);
1944 return 0;
1945 }
1946
sdma_v4_4_2_inst_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)1947 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1948 struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1949 {
1950 uint32_t data, def;
1951 int i;
1952
1953 /* leave as default if it is not driver controlled */
1954 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1955 return;
1956
1957 if (enable) {
1958 for_each_inst(i, inst_mask) {
1959 /* 1-not override: enable sdma mem light sleep */
1960 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1961 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1962 if (def != data)
1963 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1964 }
1965 } else {
1966 for_each_inst(i, inst_mask) {
1967 /* 0-override:disable sdma mem light sleep */
1968 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1969 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1970 if (def != data)
1971 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1972 }
1973 }
1974 }
1975
sdma_v4_4_2_inst_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)1976 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1977 struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1978 {
1979 uint32_t data, def;
1980 int i;
1981
1982 /* leave as default if it is not driver controlled */
1983 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1984 return;
1985
1986 if (enable) {
1987 for_each_inst(i, inst_mask) {
1988 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1989 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1990 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1991 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1992 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1993 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1994 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1995 if (def != data)
1996 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1997 }
1998 } else {
1999 for_each_inst(i, inst_mask) {
2000 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
2001 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2002 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2003 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2004 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2005 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2006 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2007 if (def != data)
2008 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
2009 }
2010 }
2011 }
2012
sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2013 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2014 enum amd_clockgating_state state)
2015 {
2016 struct amdgpu_device *adev = ip_block->adev;
2017 uint32_t inst_mask;
2018
2019 if (amdgpu_sriov_vf(adev))
2020 return 0;
2021
2022 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2023
2024 sdma_v4_4_2_inst_update_medium_grain_clock_gating(
2025 adev, state == AMD_CG_STATE_GATE, inst_mask);
2026 sdma_v4_4_2_inst_update_medium_grain_light_sleep(
2027 adev, state == AMD_CG_STATE_GATE, inst_mask);
2028 return 0;
2029 }
2030
sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2031 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
2032 enum amd_powergating_state state)
2033 {
2034 return 0;
2035 }
2036
sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)2037 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
2038 {
2039 struct amdgpu_device *adev = ip_block->adev;
2040 int data;
2041
2042 if (amdgpu_sriov_vf(adev))
2043 *flags = 0;
2044
2045 /* AMD_CG_SUPPORT_SDMA_MGCG */
2046 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
2047 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
2048 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2049
2050 /* AMD_CG_SUPPORT_SDMA_LS */
2051 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
2052 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2053 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2054 }
2055
sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)2056 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2057 {
2058 struct amdgpu_device *adev = ip_block->adev;
2059 int i, j;
2060 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
2061 uint32_t instance_offset;
2062
2063 if (!adev->sdma.ip_dump)
2064 return;
2065
2066 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
2067 for (i = 0; i < adev->sdma.num_instances; i++) {
2068 instance_offset = i * reg_count;
2069 drm_printf(p, "\nInstance:%d\n", i);
2070
2071 for (j = 0; j < reg_count; j++)
2072 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name,
2073 adev->sdma.ip_dump[instance_offset + j]);
2074 }
2075 }
2076
sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block * ip_block)2077 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block)
2078 {
2079 struct amdgpu_device *adev = ip_block->adev;
2080 int i, j;
2081 uint32_t instance_offset;
2082 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
2083
2084 if (!adev->sdma.ip_dump)
2085 return;
2086
2087 for (i = 0; i < adev->sdma.num_instances; i++) {
2088 instance_offset = i * reg_count;
2089 for (j = 0; j < reg_count; j++)
2090 adev->sdma.ip_dump[instance_offset + j] =
2091 RREG32(sdma_v4_4_2_get_reg_offset(adev, i,
2092 sdma_reg_list_4_4_2[j].reg_offset));
2093 }
2094 }
2095
2096 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
2097 .name = "sdma_v4_4_2",
2098 .early_init = sdma_v4_4_2_early_init,
2099 .late_init = sdma_v4_4_2_late_init,
2100 .sw_init = sdma_v4_4_2_sw_init,
2101 .sw_fini = sdma_v4_4_2_sw_fini,
2102 .hw_init = sdma_v4_4_2_hw_init,
2103 .hw_fini = sdma_v4_4_2_hw_fini,
2104 .suspend = sdma_v4_4_2_suspend,
2105 .resume = sdma_v4_4_2_resume,
2106 .is_idle = sdma_v4_4_2_is_idle,
2107 .wait_for_idle = sdma_v4_4_2_wait_for_idle,
2108 .soft_reset = sdma_v4_4_2_soft_reset,
2109 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
2110 .set_powergating_state = sdma_v4_4_2_set_powergating_state,
2111 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
2112 .dump_ip_state = sdma_v4_4_2_dump_ip_state,
2113 .print_ip_state = sdma_v4_4_2_print_ip_state,
2114 };
2115
2116 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
2117 .type = AMDGPU_RING_TYPE_SDMA,
2118 .align_mask = 0xff,
2119 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2120 .support_64bit_ptrs = true,
2121 .get_rptr = sdma_v4_4_2_ring_get_rptr,
2122 .get_wptr = sdma_v4_4_2_ring_get_wptr,
2123 .set_wptr = sdma_v4_4_2_ring_set_wptr,
2124 .emit_frame_size =
2125 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
2126 3 + /* hdp invalidate */
2127 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
2128 /* sdma_v4_4_2_ring_emit_vm_flush */
2129 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2130 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2131 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
2132 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
2133 .emit_ib = sdma_v4_4_2_ring_emit_ib,
2134 .emit_fence = sdma_v4_4_2_ring_emit_fence,
2135 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
2136 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
2137 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
2138 .test_ring = sdma_v4_4_2_ring_test_ring,
2139 .test_ib = sdma_v4_4_2_ring_test_ib,
2140 .insert_nop = sdma_v4_4_2_ring_insert_nop,
2141 .pad_ib = sdma_v4_4_2_ring_pad_ib,
2142 .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
2143 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
2144 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2145 .reset = sdma_v4_4_2_reset_queue,
2146 .is_guilty = sdma_v4_4_2_ring_is_guilty,
2147 };
2148
2149 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
2150 .type = AMDGPU_RING_TYPE_SDMA,
2151 .align_mask = 0xff,
2152 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2153 .support_64bit_ptrs = true,
2154 .get_rptr = sdma_v4_4_2_ring_get_rptr,
2155 .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
2156 .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
2157 .emit_frame_size =
2158 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
2159 3 + /* hdp invalidate */
2160 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
2161 /* sdma_v4_4_2_ring_emit_vm_flush */
2162 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2163 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2164 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
2165 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
2166 .emit_ib = sdma_v4_4_2_ring_emit_ib,
2167 .emit_fence = sdma_v4_4_2_ring_emit_fence,
2168 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
2169 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
2170 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
2171 .test_ring = sdma_v4_4_2_ring_test_ring,
2172 .test_ib = sdma_v4_4_2_ring_test_ib,
2173 .insert_nop = sdma_v4_4_2_ring_insert_nop,
2174 .pad_ib = sdma_v4_4_2_ring_pad_ib,
2175 .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
2176 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
2177 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2178 .reset = sdma_v4_4_2_reset_queue,
2179 .is_guilty = sdma_v4_4_2_page_ring_is_guilty,
2180 };
2181
sdma_v4_4_2_set_ring_funcs(struct amdgpu_device * adev)2182 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
2183 {
2184 int i, dev_inst;
2185
2186 for (i = 0; i < adev->sdma.num_instances; i++) {
2187 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
2188 adev->sdma.instance[i].ring.me = i;
2189 if (adev->sdma.has_page_queue) {
2190 adev->sdma.instance[i].page.funcs =
2191 &sdma_v4_4_2_page_ring_funcs;
2192 adev->sdma.instance[i].page.me = i;
2193 }
2194
2195 dev_inst = GET_INST(SDMA0, i);
2196 /* AID to which SDMA belongs depends on physical instance */
2197 adev->sdma.instance[i].aid_id =
2198 dev_inst / adev->sdma.num_inst_per_aid;
2199 }
2200 }
2201
2202 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
2203 .set = sdma_v4_4_2_set_trap_irq_state,
2204 .process = sdma_v4_4_2_process_trap_irq,
2205 };
2206
2207 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
2208 .process = sdma_v4_4_2_process_illegal_inst_irq,
2209 };
2210
2211 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
2212 .set = sdma_v4_4_2_set_ecc_irq_state,
2213 .process = amdgpu_sdma_process_ecc_irq,
2214 };
2215
2216 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
2217 .process = sdma_v4_4_2_process_vm_hole_irq,
2218 };
2219
2220 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
2221 .process = sdma_v4_4_2_process_doorbell_invalid_irq,
2222 };
2223
2224 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
2225 .process = sdma_v4_4_2_process_pool_timeout_irq,
2226 };
2227
2228 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
2229 .process = sdma_v4_4_2_process_srbm_write_irq,
2230 };
2231
2232 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = {
2233 .process = sdma_v4_4_2_process_ctxt_empty_irq,
2234 };
2235
sdma_v4_4_2_set_irq_funcs(struct amdgpu_device * adev)2236 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
2237 {
2238 adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2239 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2240 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2241 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2242 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2243 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2244 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances;
2245
2246 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
2247 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
2248 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
2249 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
2250 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
2251 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
2252 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
2253 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs;
2254 }
2255
2256 /**
2257 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
2258 *
2259 * @ib: indirect buffer to copy to
2260 * @src_offset: src GPU address
2261 * @dst_offset: dst GPU address
2262 * @byte_count: number of bytes to xfer
2263 * @copy_flags: copy flags for the buffers
2264 *
2265 * Copy GPU buffers using the DMA engine.
2266 * Used by the amdgpu ttm implementation to move pages if
2267 * registered as the asic copy callback.
2268 */
sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)2269 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
2270 uint64_t src_offset,
2271 uint64_t dst_offset,
2272 uint32_t byte_count,
2273 uint32_t copy_flags)
2274 {
2275 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2276 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2277 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
2278 ib->ptr[ib->length_dw++] = byte_count - 1;
2279 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2280 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2281 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2282 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2283 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2284 }
2285
2286 /**
2287 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
2288 *
2289 * @ib: indirect buffer to copy to
2290 * @src_data: value to write to buffer
2291 * @dst_offset: dst GPU address
2292 * @byte_count: number of bytes to xfer
2293 *
2294 * Fill GPU buffers using the DMA engine.
2295 */
sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)2296 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
2297 uint32_t src_data,
2298 uint64_t dst_offset,
2299 uint32_t byte_count)
2300 {
2301 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2302 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2303 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2304 ib->ptr[ib->length_dw++] = src_data;
2305 ib->ptr[ib->length_dw++] = byte_count - 1;
2306 }
2307
2308 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2309 .copy_max_bytes = 0x400000,
2310 .copy_num_dw = 7,
2311 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2312
2313 .fill_max_bytes = 0x400000,
2314 .fill_num_dw = 5,
2315 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2316 };
2317
sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device * adev)2318 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2319 {
2320 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2321 if (adev->sdma.has_page_queue)
2322 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2323 else
2324 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2325 }
2326
2327 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2328 .copy_pte_num_dw = 7,
2329 .copy_pte = sdma_v4_4_2_vm_copy_pte,
2330
2331 .write_pte = sdma_v4_4_2_vm_write_pte,
2332 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2333 };
2334
sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device * adev)2335 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2336 {
2337 struct drm_gpu_scheduler *sched;
2338 unsigned i;
2339
2340 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2341 for (i = 0; i < adev->sdma.num_instances; i++) {
2342 if (adev->sdma.has_page_queue)
2343 sched = &adev->sdma.instance[i].page.sched;
2344 else
2345 sched = &adev->sdma.instance[i].ring.sched;
2346 adev->vm_manager.vm_pte_scheds[i] = sched;
2347 }
2348 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2349 }
2350
2351 /**
2352 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA
2353 * @adev: Pointer to the AMDGPU device structure
2354 *
2355 * This function update reset mask for SDMA and sets the supported
2356 * reset types based on the IP version and firmware versions.
2357 *
2358 */
sdma_v4_4_2_update_reset_mask(struct amdgpu_device * adev)2359 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev)
2360 {
2361 /* per queue reset not supported for SRIOV */
2362 if (amdgpu_sriov_vf(adev))
2363 return;
2364
2365 /*
2366 * the user queue relies on MEC fw and pmfw when the sdma queue do reset.
2367 * it needs to check both of them at here to skip old mec and pmfw.
2368 */
2369 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2370 case IP_VERSION(9, 4, 3):
2371 case IP_VERSION(9, 4, 4):
2372 if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev))
2373 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
2374 break;
2375 case IP_VERSION(9, 5, 0):
2376 if ((adev->gfx.mec_fw_version >= 0xf) && amdgpu_dpm_reset_sdma_is_supported(adev))
2377 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
2378 break;
2379 default:
2380 break;
2381 }
2382
2383 }
2384
2385 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2386 .type = AMD_IP_BLOCK_TYPE_SDMA,
2387 .major = 4,
2388 .minor = 4,
2389 .rev = 2,
2390 .funcs = &sdma_v4_4_2_ip_funcs,
2391 };
2392
sdma_v4_4_2_xcp_resume(void * handle,uint32_t inst_mask)2393 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2394 {
2395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2396 int r;
2397
2398 if (!amdgpu_sriov_vf(adev))
2399 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2400
2401 r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
2402
2403 return r;
2404 }
2405
sdma_v4_4_2_xcp_suspend(void * handle,uint32_t inst_mask)2406 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2407 {
2408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2409 uint32_t tmp_mask = inst_mask;
2410 int i;
2411
2412 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2413 for_each_inst(i, tmp_mask) {
2414 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2415 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2416 }
2417 }
2418
2419 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2420 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2421
2422 return 0;
2423 }
2424
2425 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2426 .suspend = &sdma_v4_4_2_xcp_suspend,
2427 .resume = &sdma_v4_4_2_xcp_resume
2428 };
2429
2430 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2431 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2432 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2433 };
2434
2435 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2436 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2437 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2438 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2439 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2440 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2441 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2442 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2443 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2444 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2445 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2446 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2447 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2448 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2449 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2450 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2451 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2452 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2453 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2454 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2455 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2456 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2457 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2458 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2459 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2460 };
2461
sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device * adev,uint32_t sdma_inst,void * ras_err_status)2462 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2463 uint32_t sdma_inst,
2464 void *ras_err_status)
2465 {
2466 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2467 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2468 unsigned long ue_count = 0;
2469 struct amdgpu_smuio_mcm_config_info mcm_info = {
2470 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2471 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2472 };
2473
2474 /* sdma v4_4_2 doesn't support query ce counts */
2475 amdgpu_ras_inst_query_ras_error_count(adev,
2476 sdma_v4_2_2_ue_reg_list,
2477 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2478 sdma_v4_4_2_ras_memory_list,
2479 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2480 sdma_dev_inst,
2481 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2482 &ue_count);
2483
2484 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
2485 }
2486
sdma_v4_4_2_query_ras_error_count(struct amdgpu_device * adev,void * ras_err_status)2487 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2488 void *ras_err_status)
2489 {
2490 uint32_t inst_mask;
2491 int i = 0;
2492
2493 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2494 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2495 for_each_inst(i, inst_mask)
2496 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2497 } else {
2498 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2499 }
2500 }
2501
sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device * adev,uint32_t sdma_inst)2502 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2503 uint32_t sdma_inst)
2504 {
2505 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2506
2507 amdgpu_ras_inst_reset_ras_error_count(adev,
2508 sdma_v4_2_2_ue_reg_list,
2509 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2510 sdma_dev_inst);
2511 }
2512
sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device * adev)2513 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2514 {
2515 uint32_t inst_mask;
2516 int i = 0;
2517
2518 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2519 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2520 for_each_inst(i, inst_mask)
2521 sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2522 } else {
2523 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2524 }
2525 }
2526
2527 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2528 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2529 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2530 };
2531
sdma_v4_4_2_aca_bank_parser(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)2532 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
2533 enum aca_smu_type type, void *data)
2534 {
2535 struct aca_bank_info info;
2536 u64 misc0;
2537 int ret;
2538
2539 ret = aca_bank_info_decode(bank, &info);
2540 if (ret)
2541 return ret;
2542
2543 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2544 switch (type) {
2545 case ACA_SMU_TYPE_UE:
2546 bank->aca_err_type = ACA_ERROR_TYPE_UE;
2547 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
2548 1ULL);
2549 break;
2550 case ACA_SMU_TYPE_CE:
2551 bank->aca_err_type = ACA_ERROR_TYPE_CE;
2552 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
2553 ACA_REG__MISC0__ERRCNT(misc0));
2554 break;
2555 default:
2556 return -EINVAL;
2557 }
2558
2559 return ret;
2560 }
2561
2562 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2563 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2564
sdma_v4_4_2_aca_bank_is_valid(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)2565 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2566 enum aca_smu_type type, void *data)
2567 {
2568 u32 instlo;
2569
2570 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2571 instlo &= GENMASK(31, 1);
2572
2573 if (instlo != mmSMNAID_AID0_MCA_SMU)
2574 return false;
2575
2576 if (aca_bank_check_error_codes(handle->adev, bank,
2577 sdma_v4_4_2_err_codes,
2578 ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2579 return false;
2580
2581 return true;
2582 }
2583
2584 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2585 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser,
2586 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2587 };
2588
2589 static const struct aca_info sdma_v4_4_2_aca_info = {
2590 .hwip = ACA_HWIP_TYPE_SMU,
2591 .mask = ACA_ERROR_UE_MASK,
2592 .bank_ops = &sdma_v4_4_2_aca_bank_ops,
2593 };
2594
sdma_v4_4_2_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)2595 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2596 {
2597 int r;
2598
2599 r = amdgpu_sdma_ras_late_init(adev, ras_block);
2600 if (r)
2601 return r;
2602
2603 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2604 &sdma_v4_4_2_aca_info, NULL);
2605 }
2606
2607 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2608 .ras_block = {
2609 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2610 .ras_late_init = sdma_v4_4_2_ras_late_init,
2611 },
2612 };
2613
sdma_v4_4_2_set_ras_funcs(struct amdgpu_device * adev)2614 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2615 {
2616 adev->sdma.ras = &sdma_v4_4_2_ras;
2617 }
2618