1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25 #include <linux/delay.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 #include "vi.h"
33 #include "vid.h"
34
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
37
38 #include "gmc/gmc_8_1_d.h"
39 #include "gmc/gmc_8_1_sh_mask.h"
40
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
44
45 #include "bif/bif_5_0_d.h"
46 #include "bif/bif_5_0_sh_mask.h"
47
48 #include "tonga_sdma_pkt_open.h"
49
50 #include "ivsrcid/ivsrcid_vislands30.h"
51
52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
56
57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
72
73
74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
75 {
76 SDMA0_REGISTER_OFFSET,
77 SDMA1_REGISTER_OFFSET
78 };
79
80 static const u32 golden_settings_tonga_a11[] =
81 {
82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
92 };
93
94 static const u32 tonga_mgcg_cgcg_init[] =
95 {
96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
97 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
98 };
99
100 static const u32 golden_settings_fiji_a10[] =
101 {
102 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
107 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
109 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
110 };
111
112 static const u32 fiji_mgcg_cgcg_init[] =
113 {
114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
115 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
116 };
117
118 static const u32 golden_settings_polaris11_a11[] =
119 {
120 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
123 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
125 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
126 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
127 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
129 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
130 };
131
132 static const u32 golden_settings_polaris10_a11[] =
133 {
134 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
137 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
139 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
140 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
143 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
144 };
145
146 static const u32 cz_golden_settings_a11[] =
147 {
148 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
152 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
154 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
155 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
156 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
157 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
159 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
160 };
161
162 static const u32 cz_mgcg_cgcg_init[] =
163 {
164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
165 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
166 };
167
168 static const u32 stoney_golden_settings_a11[] =
169 {
170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
172 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
174 };
175
176 static const u32 stoney_mgcg_cgcg_init[] =
177 {
178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
179 };
180
181 /*
182 * sDMA - System DMA
183 * Starting with CIK, the GPU has new asynchronous
184 * DMA engines. These engines are used for compute
185 * and gfx. There are two DMA engines (SDMA0, SDMA1)
186 * and each one supports 1 ring buffer used for gfx
187 * and 2 queues used for compute.
188 *
189 * The programming model is very similar to the CP
190 * (ring buffer, IBs, etc.), but sDMA has it's own
191 * packet format that is different from the PM4 format
192 * used by the CP. sDMA supports copying data, writing
193 * embedded data, solid fills, and a number of other
194 * things. It also has support for tiling/detiling of
195 * buffers.
196 */
197
sdma_v3_0_init_golden_registers(struct amdgpu_device * adev)198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
199 {
200 switch (adev->asic_type) {
201 case CHIP_FIJI:
202 amdgpu_device_program_register_sequence(adev,
203 fiji_mgcg_cgcg_init,
204 ARRAY_SIZE(fiji_mgcg_cgcg_init));
205 amdgpu_device_program_register_sequence(adev,
206 golden_settings_fiji_a10,
207 ARRAY_SIZE(golden_settings_fiji_a10));
208 break;
209 case CHIP_TONGA:
210 amdgpu_device_program_register_sequence(adev,
211 tonga_mgcg_cgcg_init,
212 ARRAY_SIZE(tonga_mgcg_cgcg_init));
213 amdgpu_device_program_register_sequence(adev,
214 golden_settings_tonga_a11,
215 ARRAY_SIZE(golden_settings_tonga_a11));
216 break;
217 case CHIP_POLARIS11:
218 case CHIP_POLARIS12:
219 case CHIP_VEGAM:
220 amdgpu_device_program_register_sequence(adev,
221 golden_settings_polaris11_a11,
222 ARRAY_SIZE(golden_settings_polaris11_a11));
223 break;
224 case CHIP_POLARIS10:
225 amdgpu_device_program_register_sequence(adev,
226 golden_settings_polaris10_a11,
227 ARRAY_SIZE(golden_settings_polaris10_a11));
228 break;
229 case CHIP_CARRIZO:
230 amdgpu_device_program_register_sequence(adev,
231 cz_mgcg_cgcg_init,
232 ARRAY_SIZE(cz_mgcg_cgcg_init));
233 amdgpu_device_program_register_sequence(adev,
234 cz_golden_settings_a11,
235 ARRAY_SIZE(cz_golden_settings_a11));
236 break;
237 case CHIP_STONEY:
238 amdgpu_device_program_register_sequence(adev,
239 stoney_mgcg_cgcg_init,
240 ARRAY_SIZE(stoney_mgcg_cgcg_init));
241 amdgpu_device_program_register_sequence(adev,
242 stoney_golden_settings_a11,
243 ARRAY_SIZE(stoney_golden_settings_a11));
244 break;
245 default:
246 break;
247 }
248 }
249
sdma_v3_0_free_microcode(struct amdgpu_device * adev)250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
251 {
252 int i;
253
254 for (i = 0; i < adev->sdma.num_instances; i++)
255 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
256 }
257
258 /**
259 * sdma_v3_0_init_microcode - load ucode images from disk
260 *
261 * @adev: amdgpu_device pointer
262 *
263 * Use the firmware interface to load the ucode images into
264 * the driver (not loaded into hw).
265 * Returns 0 on success, error on failure.
266 */
sdma_v3_0_init_microcode(struct amdgpu_device * adev)267 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
268 {
269 const char *chip_name;
270 int err = 0, i;
271 struct amdgpu_firmware_info *info = NULL;
272 const struct common_firmware_header *header = NULL;
273 const struct sdma_firmware_header_v1_0 *hdr;
274
275 DRM_DEBUG("\n");
276
277 switch (adev->asic_type) {
278 case CHIP_TONGA:
279 chip_name = "tonga";
280 break;
281 case CHIP_FIJI:
282 chip_name = "fiji";
283 break;
284 case CHIP_POLARIS10:
285 chip_name = "polaris10";
286 break;
287 case CHIP_POLARIS11:
288 chip_name = "polaris11";
289 break;
290 case CHIP_POLARIS12:
291 chip_name = "polaris12";
292 break;
293 case CHIP_VEGAM:
294 chip_name = "vegam";
295 break;
296 case CHIP_CARRIZO:
297 chip_name = "carrizo";
298 break;
299 case CHIP_STONEY:
300 chip_name = "stoney";
301 break;
302 default: BUG();
303 }
304
305 for (i = 0; i < adev->sdma.num_instances; i++) {
306 if (i == 0)
307 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
308 "amdgpu/%s_sdma.bin", chip_name);
309 else
310 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
311 "amdgpu/%s_sdma1.bin", chip_name);
312 if (err)
313 goto out;
314 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
315 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
316 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
317 if (adev->sdma.instance[i].feature_version >= 20)
318 adev->sdma.instance[i].burst_nop = true;
319
320 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
321 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
322 info->fw = adev->sdma.instance[i].fw;
323 header = (const struct common_firmware_header *)info->fw->data;
324 adev->firmware.fw_size +=
325 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
326
327 }
328 out:
329 if (err) {
330 pr_err("sdma_v3_0: Failed to load firmware \"%s_sdma%s.bin\"\n",
331 chip_name, i == 0 ? "" : "1");
332 for (i = 0; i < adev->sdma.num_instances; i++)
333 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
334 }
335 return err;
336 }
337
338 /**
339 * sdma_v3_0_ring_get_rptr - get the current read pointer
340 *
341 * @ring: amdgpu ring pointer
342 *
343 * Get the current rptr from the hardware (VI+).
344 */
sdma_v3_0_ring_get_rptr(struct amdgpu_ring * ring)345 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
346 {
347 /* XXX check if swapping is necessary on BE */
348 return *ring->rptr_cpu_addr >> 2;
349 }
350
351 /**
352 * sdma_v3_0_ring_get_wptr - get the current write pointer
353 *
354 * @ring: amdgpu ring pointer
355 *
356 * Get the current wptr from the hardware (VI+).
357 */
sdma_v3_0_ring_get_wptr(struct amdgpu_ring * ring)358 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
359 {
360 struct amdgpu_device *adev = ring->adev;
361 u32 wptr;
362
363 if (ring->use_doorbell || ring->use_pollmem) {
364 /* XXX check if swapping is necessary on BE */
365 wptr = *ring->wptr_cpu_addr >> 2;
366 } else {
367 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
368 }
369
370 return wptr;
371 }
372
373 /**
374 * sdma_v3_0_ring_set_wptr - commit the write pointer
375 *
376 * @ring: amdgpu ring pointer
377 *
378 * Write the wptr back to the hardware (VI+).
379 */
sdma_v3_0_ring_set_wptr(struct amdgpu_ring * ring)380 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
381 {
382 struct amdgpu_device *adev = ring->adev;
383
384 if (ring->use_doorbell) {
385 u32 *wb = (u32 *)ring->wptr_cpu_addr;
386 /* XXX check if swapping is necessary on BE */
387 WRITE_ONCE(*wb, ring->wptr << 2);
388 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
389 } else if (ring->use_pollmem) {
390 u32 *wb = (u32 *)ring->wptr_cpu_addr;
391
392 WRITE_ONCE(*wb, ring->wptr << 2);
393 } else {
394 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
395 }
396 }
397
sdma_v3_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)398 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
399 {
400 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
401 int i;
402
403 for (i = 0; i < count; i++)
404 if (sdma && sdma->burst_nop && (i == 0))
405 amdgpu_ring_write(ring, ring->funcs->nop |
406 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
407 else
408 amdgpu_ring_write(ring, ring->funcs->nop);
409 }
410
411 /**
412 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
413 *
414 * @ring: amdgpu ring pointer
415 * @job: job to retrieve vmid from
416 * @ib: IB object to schedule
417 * @flags: unused
418 *
419 * Schedule an IB in the DMA ring (VI).
420 */
sdma_v3_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)421 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
422 struct amdgpu_job *job,
423 struct amdgpu_ib *ib,
424 uint32_t flags)
425 {
426 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
427
428 /* IB packet must end on a 8 DW boundary */
429 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
430
431 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
432 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
433 /* base must be 32 byte aligned */
434 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
435 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
436 amdgpu_ring_write(ring, ib->length_dw);
437 amdgpu_ring_write(ring, 0);
438 amdgpu_ring_write(ring, 0);
439
440 }
441
442 /**
443 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
444 *
445 * @ring: amdgpu ring pointer
446 *
447 * Emit an hdp flush packet on the requested DMA ring.
448 */
sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)449 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
450 {
451 u32 ref_and_mask = 0;
452
453 if (ring->me == 0)
454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
455 else
456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
457
458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
459 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
460 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
461 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
462 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
463 amdgpu_ring_write(ring, ref_and_mask); /* reference */
464 amdgpu_ring_write(ring, ref_and_mask); /* mask */
465 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
466 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
467 }
468
469 /**
470 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
471 *
472 * @ring: amdgpu ring pointer
473 * @addr: address
474 * @seq: sequence number
475 * @flags: fence related flags
476 *
477 * Add a DMA fence packet to the ring to write
478 * the fence seq number and DMA trap packet to generate
479 * an interrupt if needed (VI).
480 */
sdma_v3_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)481 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
482 unsigned flags)
483 {
484 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
485 /* write the fence */
486 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
487 amdgpu_ring_write(ring, lower_32_bits(addr));
488 amdgpu_ring_write(ring, upper_32_bits(addr));
489 amdgpu_ring_write(ring, lower_32_bits(seq));
490
491 /* optionally write high bits as well */
492 if (write64bit) {
493 addr += 4;
494 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
495 amdgpu_ring_write(ring, lower_32_bits(addr));
496 amdgpu_ring_write(ring, upper_32_bits(addr));
497 amdgpu_ring_write(ring, upper_32_bits(seq));
498 }
499
500 /* generate an interrupt */
501 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
502 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
503 }
504
505 /**
506 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
507 *
508 * @adev: amdgpu_device pointer
509 *
510 * Stop the gfx async dma ring buffers (VI).
511 */
sdma_v3_0_gfx_stop(struct amdgpu_device * adev)512 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
513 {
514 u32 rb_cntl, ib_cntl;
515 int i;
516
517 for (i = 0; i < adev->sdma.num_instances; i++) {
518 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
519 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
520 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
521 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
522 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
523 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
524 }
525 }
526
527 /**
528 * sdma_v3_0_rlc_stop - stop the compute async dma engines
529 *
530 * @adev: amdgpu_device pointer
531 *
532 * Stop the compute async dma queues (VI).
533 */
sdma_v3_0_rlc_stop(struct amdgpu_device * adev)534 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
535 {
536 /* XXX todo */
537 }
538
539 /**
540 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
541 *
542 * @adev: amdgpu_device pointer
543 * @enable: enable/disable the DMA MEs context switch.
544 *
545 * Halt or unhalt the async dma engines context switch (VI).
546 */
sdma_v3_0_ctx_switch_enable(struct amdgpu_device * adev,bool enable)547 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
548 {
549 u32 f32_cntl, phase_quantum = 0;
550 int i;
551
552 if (amdgpu_sdma_phase_quantum) {
553 unsigned value = amdgpu_sdma_phase_quantum;
554 unsigned unit = 0;
555
556 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
557 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
558 value = (value + 1) >> 1;
559 unit++;
560 }
561 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
562 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
563 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
564 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
565 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
566 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
567 WARN_ONCE(1,
568 "clamping sdma_phase_quantum to %uK clock cycles\n",
569 value << unit);
570 }
571 phase_quantum =
572 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
573 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
574 }
575
576 for (i = 0; i < adev->sdma.num_instances; i++) {
577 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
578 if (enable) {
579 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
580 AUTO_CTXSW_ENABLE, 1);
581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
582 ATC_L1_ENABLE, 1);
583 if (amdgpu_sdma_phase_quantum) {
584 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
585 phase_quantum);
586 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
587 phase_quantum);
588 }
589 } else {
590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
591 AUTO_CTXSW_ENABLE, 0);
592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
593 ATC_L1_ENABLE, 1);
594 }
595
596 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
597 }
598 }
599
600 /**
601 * sdma_v3_0_enable - stop the async dma engines
602 *
603 * @adev: amdgpu_device pointer
604 * @enable: enable/disable the DMA MEs.
605 *
606 * Halt or unhalt the async dma engines (VI).
607 */
sdma_v3_0_enable(struct amdgpu_device * adev,bool enable)608 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
609 {
610 u32 f32_cntl;
611 int i;
612
613 if (!enable) {
614 sdma_v3_0_gfx_stop(adev);
615 sdma_v3_0_rlc_stop(adev);
616 }
617
618 for (i = 0; i < adev->sdma.num_instances; i++) {
619 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
620 if (enable)
621 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
622 else
623 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
624 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
625 }
626 }
627
628 /**
629 * sdma_v3_0_gfx_resume - setup and start the async dma engines
630 *
631 * @adev: amdgpu_device pointer
632 *
633 * Set up the gfx DMA ring buffers and enable them (VI).
634 * Returns 0 for success, error for failure.
635 */
sdma_v3_0_gfx_resume(struct amdgpu_device * adev)636 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
637 {
638 struct amdgpu_ring *ring;
639 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
640 u32 rb_bufsz;
641 u32 doorbell;
642 u64 wptr_gpu_addr;
643 int i, j, r;
644
645 for (i = 0; i < adev->sdma.num_instances; i++) {
646 ring = &adev->sdma.instance[i].ring;
647 amdgpu_ring_clear_ring(ring);
648
649 mutex_lock(&adev->srbm_mutex);
650 for (j = 0; j < 16; j++) {
651 vi_srbm_select(adev, 0, 0, 0, j);
652 /* SDMA GFX */
653 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
654 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
655 }
656 vi_srbm_select(adev, 0, 0, 0, 0);
657 mutex_unlock(&adev->srbm_mutex);
658
659 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
660 adev->gfx.config.gb_addr_config & 0x70);
661
662 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
663
664 /* Set ring buffer size in dwords */
665 rb_bufsz = order_base_2(ring->ring_size / 4);
666 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
668 #ifdef __BIG_ENDIAN
669 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
670 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
671 RPTR_WRITEBACK_SWAP_ENABLE, 1);
672 #endif
673 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
674
675 /* Initialize the ring buffer's read and write pointers */
676 ring->wptr = 0;
677 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
678 sdma_v3_0_ring_set_wptr(ring);
679 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
680 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
681
682 /* set the wb address whether it's enabled or not */
683 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
684 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
685 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
686 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
687
688 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
689
690 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
691 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
692
693 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
694
695 if (ring->use_doorbell) {
696 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
697 OFFSET, ring->doorbell_index);
698 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
699 } else {
700 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
701 }
702 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
703
704 /* setup the wptr shadow polling */
705 wptr_gpu_addr = ring->wptr_gpu_addr;
706
707 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
708 lower_32_bits(wptr_gpu_addr));
709 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
710 upper_32_bits(wptr_gpu_addr));
711 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
712 if (ring->use_pollmem) {
713 /*wptr polling is not enough fast, directly clean the wptr register */
714 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
715 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
716 SDMA0_GFX_RB_WPTR_POLL_CNTL,
717 ENABLE, 1);
718 } else {
719 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
720 SDMA0_GFX_RB_WPTR_POLL_CNTL,
721 ENABLE, 0);
722 }
723 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
724
725 /* enable DMA RB */
726 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
727 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
728
729 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
730 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
731 #ifdef __BIG_ENDIAN
732 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
733 #endif
734 /* enable DMA IBs */
735 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
736 }
737
738 /* unhalt the MEs */
739 sdma_v3_0_enable(adev, true);
740 /* enable sdma ring preemption */
741 sdma_v3_0_ctx_switch_enable(adev, true);
742
743 for (i = 0; i < adev->sdma.num_instances; i++) {
744 ring = &adev->sdma.instance[i].ring;
745 r = amdgpu_ring_test_helper(ring);
746 if (r)
747 return r;
748 }
749
750 return 0;
751 }
752
753 /**
754 * sdma_v3_0_rlc_resume - setup and start the async dma engines
755 *
756 * @adev: amdgpu_device pointer
757 *
758 * Set up the compute DMA queues and enable them (VI).
759 * Returns 0 for success, error for failure.
760 */
sdma_v3_0_rlc_resume(struct amdgpu_device * adev)761 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
762 {
763 /* XXX todo */
764 return 0;
765 }
766
767 /**
768 * sdma_v3_0_start - setup and start the async dma engines
769 *
770 * @adev: amdgpu_device pointer
771 *
772 * Set up the DMA engines and enable them (VI).
773 * Returns 0 for success, error for failure.
774 */
sdma_v3_0_start(struct amdgpu_device * adev)775 static int sdma_v3_0_start(struct amdgpu_device *adev)
776 {
777 int r;
778
779 /* disable sdma engine before programing it */
780 sdma_v3_0_ctx_switch_enable(adev, false);
781 sdma_v3_0_enable(adev, false);
782
783 /* start the gfx rings and rlc compute queues */
784 r = sdma_v3_0_gfx_resume(adev);
785 if (r)
786 return r;
787 r = sdma_v3_0_rlc_resume(adev);
788 if (r)
789 return r;
790
791 return 0;
792 }
793
794 /**
795 * sdma_v3_0_ring_test_ring - simple async dma engine test
796 *
797 * @ring: amdgpu_ring structure holding ring information
798 *
799 * Test the DMA engine by writing using it to write an
800 * value to memory. (VI).
801 * Returns 0 for success, error for failure.
802 */
sdma_v3_0_ring_test_ring(struct amdgpu_ring * ring)803 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
804 {
805 struct amdgpu_device *adev = ring->adev;
806 unsigned i;
807 unsigned index;
808 int r;
809 u32 tmp;
810 u64 gpu_addr;
811
812 r = amdgpu_device_wb_get(adev, &index);
813 if (r)
814 return r;
815
816 gpu_addr = adev->wb.gpu_addr + (index * 4);
817 tmp = 0xCAFEDEAD;
818 adev->wb.wb[index] = cpu_to_le32(tmp);
819
820 r = amdgpu_ring_alloc(ring, 5);
821 if (r)
822 goto error_free_wb;
823
824 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
825 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
826 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
827 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
828 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
829 amdgpu_ring_write(ring, 0xDEADBEEF);
830 amdgpu_ring_commit(ring);
831
832 for (i = 0; i < adev->usec_timeout; i++) {
833 tmp = le32_to_cpu(adev->wb.wb[index]);
834 if (tmp == 0xDEADBEEF)
835 break;
836 udelay(1);
837 }
838
839 if (i >= adev->usec_timeout)
840 r = -ETIMEDOUT;
841
842 error_free_wb:
843 amdgpu_device_wb_free(adev, index);
844 return r;
845 }
846
847 /**
848 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
849 *
850 * @ring: amdgpu_ring structure holding ring information
851 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
852 *
853 * Test a simple IB in the DMA ring (VI).
854 * Returns 0 on success, error on failure.
855 */
sdma_v3_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)856 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
857 {
858 struct amdgpu_device *adev = ring->adev;
859 struct amdgpu_ib ib;
860 struct dma_fence *f = NULL;
861 unsigned index;
862 u32 tmp = 0;
863 u64 gpu_addr;
864 long r;
865
866 r = amdgpu_device_wb_get(adev, &index);
867 if (r)
868 return r;
869
870 gpu_addr = adev->wb.gpu_addr + (index * 4);
871 tmp = 0xCAFEDEAD;
872 adev->wb.wb[index] = cpu_to_le32(tmp);
873 memset(&ib, 0, sizeof(ib));
874 r = amdgpu_ib_get(adev, NULL, 256,
875 AMDGPU_IB_POOL_DIRECT, &ib);
876 if (r)
877 goto err0;
878
879 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
880 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
881 ib.ptr[1] = lower_32_bits(gpu_addr);
882 ib.ptr[2] = upper_32_bits(gpu_addr);
883 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
884 ib.ptr[4] = 0xDEADBEEF;
885 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
886 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
887 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
888 ib.length_dw = 8;
889
890 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
891 if (r)
892 goto err1;
893
894 r = dma_fence_wait_timeout(f, false, timeout);
895 if (r == 0) {
896 r = -ETIMEDOUT;
897 goto err1;
898 } else if (r < 0) {
899 goto err1;
900 }
901 tmp = le32_to_cpu(adev->wb.wb[index]);
902 if (tmp == 0xDEADBEEF)
903 r = 0;
904 else
905 r = -EINVAL;
906 err1:
907 amdgpu_ib_free(adev, &ib, NULL);
908 dma_fence_put(f);
909 err0:
910 amdgpu_device_wb_free(adev, index);
911 return r;
912 }
913
914 /**
915 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
916 *
917 * @ib: indirect buffer to fill with commands
918 * @pe: addr of the page entry
919 * @src: src addr to copy from
920 * @count: number of page entries to update
921 *
922 * Update PTEs by copying them from the GART using sDMA (CIK).
923 */
sdma_v3_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)924 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
925 uint64_t pe, uint64_t src,
926 unsigned count)
927 {
928 unsigned bytes = count * 8;
929
930 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
931 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
932 ib->ptr[ib->length_dw++] = bytes;
933 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
934 ib->ptr[ib->length_dw++] = lower_32_bits(src);
935 ib->ptr[ib->length_dw++] = upper_32_bits(src);
936 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
937 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
938 }
939
940 /**
941 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
942 *
943 * @ib: indirect buffer to fill with commands
944 * @pe: addr of the page entry
945 * @value: dst addr to write into pe
946 * @count: number of page entries to update
947 * @incr: increase next addr by incr bytes
948 *
949 * Update PTEs by writing them manually using sDMA (CIK).
950 */
sdma_v3_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)951 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
952 uint64_t value, unsigned count,
953 uint32_t incr)
954 {
955 unsigned ndw = count * 2;
956
957 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
958 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
959 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
960 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
961 ib->ptr[ib->length_dw++] = ndw;
962 for (; ndw > 0; ndw -= 2) {
963 ib->ptr[ib->length_dw++] = lower_32_bits(value);
964 ib->ptr[ib->length_dw++] = upper_32_bits(value);
965 value += incr;
966 }
967 }
968
969 /**
970 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
971 *
972 * @ib: indirect buffer to fill with commands
973 * @pe: addr of the page entry
974 * @addr: dst addr to write into pe
975 * @count: number of page entries to update
976 * @incr: increase next addr by incr bytes
977 * @flags: access flags
978 *
979 * Update the page tables using sDMA (CIK).
980 */
sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)981 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
982 uint64_t addr, unsigned count,
983 uint32_t incr, uint64_t flags)
984 {
985 /* for physically contiguous pages (vram) */
986 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
987 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
988 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
989 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
990 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
991 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
992 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
993 ib->ptr[ib->length_dw++] = incr; /* increment size */
994 ib->ptr[ib->length_dw++] = 0;
995 ib->ptr[ib->length_dw++] = count; /* number of entries */
996 }
997
998 /**
999 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1000 *
1001 * @ring: amdgpu_ring structure holding ring information
1002 * @ib: indirect buffer to fill with padding
1003 *
1004 */
sdma_v3_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1005 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1006 {
1007 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1008 u32 pad_count;
1009 int i;
1010
1011 pad_count = (-ib->length_dw) & 7;
1012 for (i = 0; i < pad_count; i++)
1013 if (sdma && sdma->burst_nop && (i == 0))
1014 ib->ptr[ib->length_dw++] =
1015 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1016 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1017 else
1018 ib->ptr[ib->length_dw++] =
1019 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1020 }
1021
1022 /**
1023 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1024 *
1025 * @ring: amdgpu_ring pointer
1026 *
1027 * Make sure all previous operations are completed (CIK).
1028 */
sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1029 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1030 {
1031 uint32_t seq = ring->fence_drv.sync_seq;
1032 uint64_t addr = ring->fence_drv.gpu_addr;
1033
1034 /* wait for idle */
1035 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1036 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1037 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1038 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1039 amdgpu_ring_write(ring, addr & 0xfffffffc);
1040 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1041 amdgpu_ring_write(ring, seq); /* reference */
1042 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1043 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1044 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1045 }
1046
1047 /**
1048 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1049 *
1050 * @ring: amdgpu_ring pointer
1051 * @vmid: vmid number to use
1052 * @pd_addr: address
1053 *
1054 * Update the page table base and flush the VM TLB
1055 * using sDMA (VI).
1056 */
sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1057 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1058 unsigned vmid, uint64_t pd_addr)
1059 {
1060 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1061
1062 /* wait for flush */
1063 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1064 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1065 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1066 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1067 amdgpu_ring_write(ring, 0);
1068 amdgpu_ring_write(ring, 0); /* reference */
1069 amdgpu_ring_write(ring, 0); /* mask */
1070 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1071 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1072 }
1073
sdma_v3_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1074 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1075 uint32_t reg, uint32_t val)
1076 {
1077 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1078 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1079 amdgpu_ring_write(ring, reg);
1080 amdgpu_ring_write(ring, val);
1081 }
1082
sdma_v3_0_early_init(void * handle)1083 static int sdma_v3_0_early_init(void *handle)
1084 {
1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086 int r;
1087
1088 switch (adev->asic_type) {
1089 case CHIP_STONEY:
1090 adev->sdma.num_instances = 1;
1091 break;
1092 default:
1093 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1094 break;
1095 }
1096
1097 r = sdma_v3_0_init_microcode(adev);
1098 if (r)
1099 return r;
1100
1101 sdma_v3_0_set_ring_funcs(adev);
1102 sdma_v3_0_set_buffer_funcs(adev);
1103 sdma_v3_0_set_vm_pte_funcs(adev);
1104 sdma_v3_0_set_irq_funcs(adev);
1105
1106 return 0;
1107 }
1108
sdma_v3_0_sw_init(void * handle)1109 static int sdma_v3_0_sw_init(void *handle)
1110 {
1111 struct amdgpu_ring *ring;
1112 int r, i;
1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115 /* SDMA trap event */
1116 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1117 &adev->sdma.trap_irq);
1118 if (r)
1119 return r;
1120
1121 /* SDMA Privileged inst */
1122 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1123 &adev->sdma.illegal_inst_irq);
1124 if (r)
1125 return r;
1126
1127 /* SDMA Privileged inst */
1128 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1129 &adev->sdma.illegal_inst_irq);
1130 if (r)
1131 return r;
1132
1133 for (i = 0; i < adev->sdma.num_instances; i++) {
1134 ring = &adev->sdma.instance[i].ring;
1135 ring->ring_obj = NULL;
1136 if (!amdgpu_sriov_vf(adev)) {
1137 ring->use_doorbell = true;
1138 ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1139 } else {
1140 ring->use_pollmem = true;
1141 }
1142
1143 sprintf(ring->name, "sdma%d", i);
1144 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1145 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1146 AMDGPU_SDMA_IRQ_INSTANCE1,
1147 AMDGPU_RING_PRIO_DEFAULT, NULL);
1148 if (r)
1149 return r;
1150 }
1151
1152 return r;
1153 }
1154
sdma_v3_0_sw_fini(void * handle)1155 static int sdma_v3_0_sw_fini(void *handle)
1156 {
1157 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158 int i;
1159
1160 for (i = 0; i < adev->sdma.num_instances; i++)
1161 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1162
1163 sdma_v3_0_free_microcode(adev);
1164 return 0;
1165 }
1166
sdma_v3_0_hw_init(void * handle)1167 static int sdma_v3_0_hw_init(void *handle)
1168 {
1169 int r;
1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171
1172 sdma_v3_0_init_golden_registers(adev);
1173
1174 r = sdma_v3_0_start(adev);
1175 if (r)
1176 return r;
1177
1178 return r;
1179 }
1180
sdma_v3_0_hw_fini(void * handle)1181 static int sdma_v3_0_hw_fini(void *handle)
1182 {
1183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184
1185 sdma_v3_0_ctx_switch_enable(adev, false);
1186 sdma_v3_0_enable(adev, false);
1187
1188 return 0;
1189 }
1190
sdma_v3_0_suspend(void * handle)1191 static int sdma_v3_0_suspend(void *handle)
1192 {
1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
1195 return sdma_v3_0_hw_fini(adev);
1196 }
1197
sdma_v3_0_resume(void * handle)1198 static int sdma_v3_0_resume(void *handle)
1199 {
1200 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1201
1202 return sdma_v3_0_hw_init(adev);
1203 }
1204
sdma_v3_0_is_idle(void * handle)1205 static bool sdma_v3_0_is_idle(void *handle)
1206 {
1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208 u32 tmp = RREG32(mmSRBM_STATUS2);
1209
1210 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1211 SRBM_STATUS2__SDMA1_BUSY_MASK))
1212 return false;
1213
1214 return true;
1215 }
1216
sdma_v3_0_wait_for_idle(void * handle)1217 static int sdma_v3_0_wait_for_idle(void *handle)
1218 {
1219 unsigned i;
1220 u32 tmp;
1221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223 for (i = 0; i < adev->usec_timeout; i++) {
1224 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1225 SRBM_STATUS2__SDMA1_BUSY_MASK);
1226
1227 if (!tmp)
1228 return 0;
1229 udelay(1);
1230 }
1231 return -ETIMEDOUT;
1232 }
1233
sdma_v3_0_check_soft_reset(void * handle)1234 static bool sdma_v3_0_check_soft_reset(void *handle)
1235 {
1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237 u32 srbm_soft_reset = 0;
1238 u32 tmp = RREG32(mmSRBM_STATUS2);
1239
1240 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1241 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1242 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1243 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1244 }
1245
1246 if (srbm_soft_reset) {
1247 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1248 return true;
1249 } else {
1250 adev->sdma.srbm_soft_reset = 0;
1251 return false;
1252 }
1253 }
1254
sdma_v3_0_pre_soft_reset(void * handle)1255 static int sdma_v3_0_pre_soft_reset(void *handle)
1256 {
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258 u32 srbm_soft_reset = 0;
1259
1260 if (!adev->sdma.srbm_soft_reset)
1261 return 0;
1262
1263 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1264
1265 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1266 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1267 sdma_v3_0_ctx_switch_enable(adev, false);
1268 sdma_v3_0_enable(adev, false);
1269 }
1270
1271 return 0;
1272 }
1273
sdma_v3_0_post_soft_reset(void * handle)1274 static int sdma_v3_0_post_soft_reset(void *handle)
1275 {
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277 u32 srbm_soft_reset = 0;
1278
1279 if (!adev->sdma.srbm_soft_reset)
1280 return 0;
1281
1282 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1283
1284 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1285 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1286 sdma_v3_0_gfx_resume(adev);
1287 sdma_v3_0_rlc_resume(adev);
1288 }
1289
1290 return 0;
1291 }
1292
sdma_v3_0_soft_reset(void * handle)1293 static int sdma_v3_0_soft_reset(void *handle)
1294 {
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 u32 srbm_soft_reset = 0;
1297 u32 tmp;
1298
1299 if (!adev->sdma.srbm_soft_reset)
1300 return 0;
1301
1302 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1303
1304 if (srbm_soft_reset) {
1305 tmp = RREG32(mmSRBM_SOFT_RESET);
1306 tmp |= srbm_soft_reset;
1307 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1308 WREG32(mmSRBM_SOFT_RESET, tmp);
1309 tmp = RREG32(mmSRBM_SOFT_RESET);
1310
1311 udelay(50);
1312
1313 tmp &= ~srbm_soft_reset;
1314 WREG32(mmSRBM_SOFT_RESET, tmp);
1315 tmp = RREG32(mmSRBM_SOFT_RESET);
1316
1317 /* Wait a little for things to settle down */
1318 udelay(50);
1319 }
1320
1321 return 0;
1322 }
1323
sdma_v3_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1324 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1325 struct amdgpu_irq_src *source,
1326 unsigned type,
1327 enum amdgpu_interrupt_state state)
1328 {
1329 u32 sdma_cntl;
1330
1331 switch (type) {
1332 case AMDGPU_SDMA_IRQ_INSTANCE0:
1333 switch (state) {
1334 case AMDGPU_IRQ_STATE_DISABLE:
1335 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1336 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1337 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1338 break;
1339 case AMDGPU_IRQ_STATE_ENABLE:
1340 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1342 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1343 break;
1344 default:
1345 break;
1346 }
1347 break;
1348 case AMDGPU_SDMA_IRQ_INSTANCE1:
1349 switch (state) {
1350 case AMDGPU_IRQ_STATE_DISABLE:
1351 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1352 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1353 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1354 break;
1355 case AMDGPU_IRQ_STATE_ENABLE:
1356 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1357 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1358 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1359 break;
1360 default:
1361 break;
1362 }
1363 break;
1364 default:
1365 break;
1366 }
1367 return 0;
1368 }
1369
sdma_v3_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1370 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1371 struct amdgpu_irq_src *source,
1372 struct amdgpu_iv_entry *entry)
1373 {
1374 u8 instance_id, queue_id;
1375
1376 instance_id = (entry->ring_id & 0x3) >> 0;
1377 queue_id = (entry->ring_id & 0xc) >> 2;
1378 DRM_DEBUG("IH: SDMA trap\n");
1379 switch (instance_id) {
1380 case 0:
1381 switch (queue_id) {
1382 case 0:
1383 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1384 break;
1385 case 1:
1386 /* XXX compute */
1387 break;
1388 case 2:
1389 /* XXX compute */
1390 break;
1391 }
1392 break;
1393 case 1:
1394 switch (queue_id) {
1395 case 0:
1396 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1397 break;
1398 case 1:
1399 /* XXX compute */
1400 break;
1401 case 2:
1402 /* XXX compute */
1403 break;
1404 }
1405 break;
1406 }
1407 return 0;
1408 }
1409
sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1410 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1411 struct amdgpu_irq_src *source,
1412 struct amdgpu_iv_entry *entry)
1413 {
1414 u8 instance_id, queue_id;
1415
1416 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1417 instance_id = (entry->ring_id & 0x3) >> 0;
1418 queue_id = (entry->ring_id & 0xc) >> 2;
1419
1420 if (instance_id <= 1 && queue_id == 0)
1421 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1422 return 0;
1423 }
1424
sdma_v3_0_update_sdma_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1425 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1426 struct amdgpu_device *adev,
1427 bool enable)
1428 {
1429 uint32_t temp, data;
1430 int i;
1431
1432 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1433 for (i = 0; i < adev->sdma.num_instances; i++) {
1434 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1435 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1436 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1437 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1438 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1439 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1440 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1441 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1442 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1443 if (data != temp)
1444 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1445 }
1446 } else {
1447 for (i = 0; i < adev->sdma.num_instances; i++) {
1448 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1449 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1454 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1455 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1456 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1457
1458 if (data != temp)
1459 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1460 }
1461 }
1462 }
1463
sdma_v3_0_update_sdma_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1464 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1465 struct amdgpu_device *adev,
1466 bool enable)
1467 {
1468 uint32_t temp, data;
1469 int i;
1470
1471 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1472 for (i = 0; i < adev->sdma.num_instances; i++) {
1473 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1474 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1475
1476 if (temp != data)
1477 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1478 }
1479 } else {
1480 for (i = 0; i < adev->sdma.num_instances; i++) {
1481 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1482 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1483
1484 if (temp != data)
1485 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1486 }
1487 }
1488 }
1489
sdma_v3_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1490 static int sdma_v3_0_set_clockgating_state(void *handle,
1491 enum amd_clockgating_state state)
1492 {
1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1494
1495 if (amdgpu_sriov_vf(adev))
1496 return 0;
1497
1498 switch (adev->asic_type) {
1499 case CHIP_FIJI:
1500 case CHIP_CARRIZO:
1501 case CHIP_STONEY:
1502 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1503 state == AMD_CG_STATE_GATE);
1504 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1505 state == AMD_CG_STATE_GATE);
1506 break;
1507 default:
1508 break;
1509 }
1510 return 0;
1511 }
1512
sdma_v3_0_set_powergating_state(void * handle,enum amd_powergating_state state)1513 static int sdma_v3_0_set_powergating_state(void *handle,
1514 enum amd_powergating_state state)
1515 {
1516 return 0;
1517 }
1518
sdma_v3_0_get_clockgating_state(void * handle,u64 * flags)1519 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)
1520 {
1521 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1522 int data;
1523
1524 if (amdgpu_sriov_vf(adev))
1525 *flags = 0;
1526
1527 /* AMD_CG_SUPPORT_SDMA_MGCG */
1528 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1529 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1530 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1531
1532 /* AMD_CG_SUPPORT_SDMA_LS */
1533 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1534 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1535 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1536 }
1537
1538 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1539 .name = "sdma_v3_0",
1540 .early_init = sdma_v3_0_early_init,
1541 .late_init = NULL,
1542 .sw_init = sdma_v3_0_sw_init,
1543 .sw_fini = sdma_v3_0_sw_fini,
1544 .hw_init = sdma_v3_0_hw_init,
1545 .hw_fini = sdma_v3_0_hw_fini,
1546 .suspend = sdma_v3_0_suspend,
1547 .resume = sdma_v3_0_resume,
1548 .is_idle = sdma_v3_0_is_idle,
1549 .wait_for_idle = sdma_v3_0_wait_for_idle,
1550 .check_soft_reset = sdma_v3_0_check_soft_reset,
1551 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1552 .post_soft_reset = sdma_v3_0_post_soft_reset,
1553 .soft_reset = sdma_v3_0_soft_reset,
1554 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1555 .set_powergating_state = sdma_v3_0_set_powergating_state,
1556 .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1557 .dump_ip_state = NULL,
1558 .print_ip_state = NULL,
1559 };
1560
1561 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1562 .type = AMDGPU_RING_TYPE_SDMA,
1563 .align_mask = 0xf,
1564 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1565 .support_64bit_ptrs = false,
1566 .secure_submission_supported = true,
1567 .get_rptr = sdma_v3_0_ring_get_rptr,
1568 .get_wptr = sdma_v3_0_ring_get_wptr,
1569 .set_wptr = sdma_v3_0_ring_set_wptr,
1570 .emit_frame_size =
1571 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1572 3 + /* hdp invalidate */
1573 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1574 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1575 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1576 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1577 .emit_ib = sdma_v3_0_ring_emit_ib,
1578 .emit_fence = sdma_v3_0_ring_emit_fence,
1579 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1580 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1581 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1582 .test_ring = sdma_v3_0_ring_test_ring,
1583 .test_ib = sdma_v3_0_ring_test_ib,
1584 .insert_nop = sdma_v3_0_ring_insert_nop,
1585 .pad_ib = sdma_v3_0_ring_pad_ib,
1586 .emit_wreg = sdma_v3_0_ring_emit_wreg,
1587 };
1588
sdma_v3_0_set_ring_funcs(struct amdgpu_device * adev)1589 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1590 {
1591 int i;
1592
1593 for (i = 0; i < adev->sdma.num_instances; i++) {
1594 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1595 adev->sdma.instance[i].ring.me = i;
1596 }
1597 }
1598
1599 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1600 .set = sdma_v3_0_set_trap_irq_state,
1601 .process = sdma_v3_0_process_trap_irq,
1602 };
1603
1604 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1605 .process = sdma_v3_0_process_illegal_inst_irq,
1606 };
1607
sdma_v3_0_set_irq_funcs(struct amdgpu_device * adev)1608 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1609 {
1610 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1611 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1612 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1613 }
1614
1615 /**
1616 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1617 *
1618 * @ib: indirect buffer to copy to
1619 * @src_offset: src GPU address
1620 * @dst_offset: dst GPU address
1621 * @byte_count: number of bytes to xfer
1622 * @copy_flags: unused
1623 *
1624 * Copy GPU buffers using the DMA engine (VI).
1625 * Used by the amdgpu ttm implementation to move pages if
1626 * registered as the asic copy callback.
1627 */
sdma_v3_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)1628 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1629 uint64_t src_offset,
1630 uint64_t dst_offset,
1631 uint32_t byte_count,
1632 uint32_t copy_flags)
1633 {
1634 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1635 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1636 ib->ptr[ib->length_dw++] = byte_count;
1637 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1638 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1639 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1640 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1641 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1642 }
1643
1644 /**
1645 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1646 *
1647 * @ib: indirect buffer to copy to
1648 * @src_data: value to write to buffer
1649 * @dst_offset: dst GPU address
1650 * @byte_count: number of bytes to xfer
1651 *
1652 * Fill GPU buffers using the DMA engine (VI).
1653 */
sdma_v3_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1654 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1655 uint32_t src_data,
1656 uint64_t dst_offset,
1657 uint32_t byte_count)
1658 {
1659 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1660 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1661 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1662 ib->ptr[ib->length_dw++] = src_data;
1663 ib->ptr[ib->length_dw++] = byte_count;
1664 }
1665
1666 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1667 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1668 .copy_num_dw = 7,
1669 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1670
1671 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1672 .fill_num_dw = 5,
1673 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1674 };
1675
sdma_v3_0_set_buffer_funcs(struct amdgpu_device * adev)1676 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1677 {
1678 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1679 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1680 }
1681
1682 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1683 .copy_pte_num_dw = 7,
1684 .copy_pte = sdma_v3_0_vm_copy_pte,
1685
1686 .write_pte = sdma_v3_0_vm_write_pte,
1687 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1688 };
1689
sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device * adev)1690 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1691 {
1692 unsigned i;
1693
1694 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1695 for (i = 0; i < adev->sdma.num_instances; i++) {
1696 adev->vm_manager.vm_pte_scheds[i] =
1697 &adev->sdma.instance[i].ring.sched;
1698 }
1699 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1700 }
1701
1702 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1703 {
1704 .type = AMD_IP_BLOCK_TYPE_SDMA,
1705 .major = 3,
1706 .minor = 0,
1707 .rev = 0,
1708 .funcs = &sdma_v3_0_ip_funcs,
1709 };
1710
1711 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1712 {
1713 .type = AMD_IP_BLOCK_TYPE_SDMA,
1714 .major = 3,
1715 .minor = 1,
1716 .rev = 0,
1717 .funcs = &sdma_v3_0_ip_funcs,
1718 };
1719