1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Richard Acayan. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10
11 #include "pinctrl-msm.h"
12
13 #define NORTH 0x00500000
14 #define SOUTH 0x00900000
15 #define WEST 0x00100000
16
17 #define REG_SIZE 0x1000
18 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
19 { \
20 .grp = PINCTRL_PINGROUP("gpio" #id, \
21 gpio##id##_pins, \
22 ARRAY_SIZE(gpio##id##_pins)), \
23 .funcs = (int[]){ \
24 msm_mux_gpio, /* gpio mode */ \
25 msm_mux_##f1, \
26 msm_mux_##f2, \
27 msm_mux_##f3, \
28 msm_mux_##f4, \
29 msm_mux_##f5, \
30 msm_mux_##f6, \
31 msm_mux_##f7, \
32 msm_mux_##f8, \
33 msm_mux_##f9 \
34 }, \
35 .nfuncs = 10, \
36 .ctl_reg = base + REG_SIZE * id, \
37 .io_reg = base + 0x4 + REG_SIZE * id, \
38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
39 .intr_status_reg = base + 0xc + REG_SIZE * id, \
40 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
41 .mux_bit = 2, \
42 .pull_bit = 0, \
43 .drv_bit = 6, \
44 .oe_bit = 9, \
45 .in_bit = 0, \
46 .out_bit = 1, \
47 .intr_enable_bit = 0, \
48 .intr_status_bit = 0, \
49 .intr_target_bit = 5, \
50 .intr_target_kpss_val = 3, \
51 .intr_raw_status_bit = 4, \
52 .intr_polarity_bit = 1, \
53 .intr_detection_bit = 2, \
54 .intr_detection_width = 2, \
55 }
56
57 /*
58 * A dummy pingroup is a pin group that cannot be assigned a function and has
59 * no registers to control or monitor it.
60 */
61 #define PINGROUP_DUMMY(id) \
62 { \
63 .grp = PINCTRL_PINGROUP("gpio" #id, \
64 gpio##id##_pins, \
65 ARRAY_SIZE(gpio##id##_pins)), \
66 .ctl_reg = 0, \
67 .io_reg = 0, \
68 .intr_cfg_reg = 0, \
69 .intr_status_reg = 0, \
70 .intr_target_reg = 0, \
71 .mux_bit = -1, \
72 .pull_bit = -1, \
73 .drv_bit = -1, \
74 .oe_bit = -1, \
75 .in_bit = -1, \
76 .out_bit = -1, \
77 .intr_enable_bit = -1, \
78 .intr_status_bit = -1, \
79 .intr_target_bit = -1, \
80 .intr_raw_status_bit = -1, \
81 .intr_polarity_bit = -1, \
82 .intr_detection_bit = -1, \
83 .intr_detection_width = -1, \
84 }
85
86 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
87 { \
88 .grp = PINCTRL_PINGROUP(#pg_name, \
89 pg_name##_pins, \
90 ARRAY_SIZE(pg_name##_pins)), \
91 .ctl_reg = ctl, \
92 .io_reg = 0, \
93 .intr_cfg_reg = 0, \
94 .intr_status_reg = 0, \
95 .intr_target_reg = 0, \
96 .mux_bit = -1, \
97 .pull_bit = pull, \
98 .drv_bit = drv, \
99 .oe_bit = -1, \
100 .in_bit = -1, \
101 .out_bit = -1, \
102 .intr_enable_bit = -1, \
103 .intr_status_bit = -1, \
104 .intr_target_bit = -1, \
105 .intr_raw_status_bit = -1, \
106 .intr_polarity_bit = -1, \
107 .intr_detection_bit = -1, \
108 .intr_detection_width = -1, \
109 }
110
111 #define UFS_RESET(pg_name, offset) \
112 { \
113 .grp = PINCTRL_PINGROUP(#pg_name, \
114 pg_name##_pins, \
115 ARRAY_SIZE(pg_name##_pins)), \
116 .ctl_reg = offset, \
117 .io_reg = offset + 0x4, \
118 .intr_cfg_reg = 0, \
119 .intr_status_reg = 0, \
120 .intr_target_reg = 0, \
121 .mux_bit = -1, \
122 .pull_bit = 3, \
123 .drv_bit = 0, \
124 .oe_bit = -1, \
125 .in_bit = -1, \
126 .out_bit = 0, \
127 .intr_enable_bit = -1, \
128 .intr_status_bit = -1, \
129 .intr_target_bit = -1, \
130 .intr_raw_status_bit = -1, \
131 .intr_polarity_bit = -1, \
132 .intr_detection_bit = -1, \
133 .intr_detection_width = -1, \
134 }
135
136 static const struct pinctrl_pin_desc sdm670_pins[] = {
137 PINCTRL_PIN(0, "GPIO_0"),
138 PINCTRL_PIN(1, "GPIO_1"),
139 PINCTRL_PIN(2, "GPIO_2"),
140 PINCTRL_PIN(3, "GPIO_3"),
141 PINCTRL_PIN(4, "GPIO_4"),
142 PINCTRL_PIN(5, "GPIO_5"),
143 PINCTRL_PIN(6, "GPIO_6"),
144 PINCTRL_PIN(7, "GPIO_7"),
145 PINCTRL_PIN(8, "GPIO_8"),
146 PINCTRL_PIN(9, "GPIO_9"),
147 PINCTRL_PIN(10, "GPIO_10"),
148 PINCTRL_PIN(11, "GPIO_11"),
149 PINCTRL_PIN(12, "GPIO_12"),
150 PINCTRL_PIN(13, "GPIO_13"),
151 PINCTRL_PIN(14, "GPIO_14"),
152 PINCTRL_PIN(15, "GPIO_15"),
153 PINCTRL_PIN(16, "GPIO_16"),
154 PINCTRL_PIN(17, "GPIO_17"),
155 PINCTRL_PIN(18, "GPIO_18"),
156 PINCTRL_PIN(19, "GPIO_19"),
157 PINCTRL_PIN(20, "GPIO_20"),
158 PINCTRL_PIN(21, "GPIO_21"),
159 PINCTRL_PIN(22, "GPIO_22"),
160 PINCTRL_PIN(23, "GPIO_23"),
161 PINCTRL_PIN(24, "GPIO_24"),
162 PINCTRL_PIN(25, "GPIO_25"),
163 PINCTRL_PIN(26, "GPIO_26"),
164 PINCTRL_PIN(27, "GPIO_27"),
165 PINCTRL_PIN(28, "GPIO_28"),
166 PINCTRL_PIN(29, "GPIO_29"),
167 PINCTRL_PIN(30, "GPIO_30"),
168 PINCTRL_PIN(31, "GPIO_31"),
169 PINCTRL_PIN(32, "GPIO_32"),
170 PINCTRL_PIN(33, "GPIO_33"),
171 PINCTRL_PIN(34, "GPIO_34"),
172 PINCTRL_PIN(35, "GPIO_35"),
173 PINCTRL_PIN(36, "GPIO_36"),
174 PINCTRL_PIN(37, "GPIO_37"),
175 PINCTRL_PIN(38, "GPIO_38"),
176 PINCTRL_PIN(39, "GPIO_39"),
177 PINCTRL_PIN(40, "GPIO_40"),
178 PINCTRL_PIN(41, "GPIO_41"),
179 PINCTRL_PIN(42, "GPIO_42"),
180 PINCTRL_PIN(43, "GPIO_43"),
181 PINCTRL_PIN(44, "GPIO_44"),
182 PINCTRL_PIN(45, "GPIO_45"),
183 PINCTRL_PIN(46, "GPIO_46"),
184 PINCTRL_PIN(47, "GPIO_47"),
185 PINCTRL_PIN(48, "GPIO_48"),
186 PINCTRL_PIN(49, "GPIO_49"),
187 PINCTRL_PIN(50, "GPIO_50"),
188 PINCTRL_PIN(51, "GPIO_51"),
189 PINCTRL_PIN(52, "GPIO_52"),
190 PINCTRL_PIN(53, "GPIO_53"),
191 PINCTRL_PIN(54, "GPIO_54"),
192 PINCTRL_PIN(55, "GPIO_55"),
193 PINCTRL_PIN(56, "GPIO_56"),
194 PINCTRL_PIN(57, "GPIO_57"),
195 PINCTRL_PIN(58, "GPIO_58"),
196 PINCTRL_PIN(59, "GPIO_59"),
197 PINCTRL_PIN(60, "GPIO_60"),
198 PINCTRL_PIN(61, "GPIO_61"),
199 PINCTRL_PIN(62, "GPIO_62"),
200 PINCTRL_PIN(63, "GPIO_63"),
201 PINCTRL_PIN(64, "GPIO_64"),
202 PINCTRL_PIN(65, "GPIO_65"),
203 PINCTRL_PIN(66, "GPIO_66"),
204 PINCTRL_PIN(67, "GPIO_67"),
205 PINCTRL_PIN(68, "GPIO_68"),
206 PINCTRL_PIN(69, "GPIO_69"),
207 PINCTRL_PIN(70, "GPIO_70"),
208 PINCTRL_PIN(71, "GPIO_71"),
209 PINCTRL_PIN(72, "GPIO_72"),
210 PINCTRL_PIN(73, "GPIO_73"),
211 PINCTRL_PIN(74, "GPIO_74"),
212 PINCTRL_PIN(75, "GPIO_75"),
213 PINCTRL_PIN(76, "GPIO_76"),
214 PINCTRL_PIN(77, "GPIO_77"),
215 PINCTRL_PIN(78, "GPIO_78"),
216 PINCTRL_PIN(79, "GPIO_79"),
217 PINCTRL_PIN(80, "GPIO_80"),
218 PINCTRL_PIN(81, "GPIO_81"),
219 PINCTRL_PIN(82, "GPIO_82"),
220 PINCTRL_PIN(83, "GPIO_83"),
221 PINCTRL_PIN(84, "GPIO_84"),
222 PINCTRL_PIN(85, "GPIO_85"),
223 PINCTRL_PIN(86, "GPIO_86"),
224 PINCTRL_PIN(87, "GPIO_87"),
225 PINCTRL_PIN(88, "GPIO_88"),
226 PINCTRL_PIN(89, "GPIO_89"),
227 PINCTRL_PIN(90, "GPIO_90"),
228 PINCTRL_PIN(91, "GPIO_91"),
229 PINCTRL_PIN(92, "GPIO_92"),
230 PINCTRL_PIN(93, "GPIO_93"),
231 PINCTRL_PIN(94, "GPIO_94"),
232 PINCTRL_PIN(95, "GPIO_95"),
233 PINCTRL_PIN(96, "GPIO_96"),
234 PINCTRL_PIN(97, "GPIO_97"),
235 PINCTRL_PIN(98, "GPIO_98"),
236 PINCTRL_PIN(99, "GPIO_99"),
237 PINCTRL_PIN(100, "GPIO_100"),
238 PINCTRL_PIN(101, "GPIO_101"),
239 PINCTRL_PIN(102, "GPIO_102"),
240 PINCTRL_PIN(103, "GPIO_103"),
241 PINCTRL_PIN(104, "GPIO_104"),
242 PINCTRL_PIN(105, "GPIO_105"),
243 PINCTRL_PIN(106, "GPIO_106"),
244 PINCTRL_PIN(107, "GPIO_107"),
245 PINCTRL_PIN(108, "GPIO_108"),
246 PINCTRL_PIN(109, "GPIO_109"),
247 PINCTRL_PIN(110, "GPIO_110"),
248 PINCTRL_PIN(111, "GPIO_111"),
249 PINCTRL_PIN(112, "GPIO_112"),
250 PINCTRL_PIN(113, "GPIO_113"),
251 PINCTRL_PIN(114, "GPIO_114"),
252 PINCTRL_PIN(115, "GPIO_115"),
253 PINCTRL_PIN(116, "GPIO_116"),
254 PINCTRL_PIN(117, "GPIO_117"),
255 PINCTRL_PIN(118, "GPIO_118"),
256 PINCTRL_PIN(119, "GPIO_119"),
257 PINCTRL_PIN(120, "GPIO_120"),
258 PINCTRL_PIN(121, "GPIO_121"),
259 PINCTRL_PIN(122, "GPIO_122"),
260 PINCTRL_PIN(123, "GPIO_123"),
261 PINCTRL_PIN(124, "GPIO_124"),
262 PINCTRL_PIN(125, "GPIO_125"),
263 PINCTRL_PIN(126, "GPIO_126"),
264 PINCTRL_PIN(127, "GPIO_127"),
265 PINCTRL_PIN(128, "GPIO_128"),
266 PINCTRL_PIN(129, "GPIO_129"),
267 PINCTRL_PIN(130, "GPIO_130"),
268 PINCTRL_PIN(131, "GPIO_131"),
269 PINCTRL_PIN(132, "GPIO_132"),
270 PINCTRL_PIN(133, "GPIO_133"),
271 PINCTRL_PIN(134, "GPIO_134"),
272 PINCTRL_PIN(135, "GPIO_135"),
273 PINCTRL_PIN(136, "GPIO_136"),
274 PINCTRL_PIN(137, "GPIO_137"),
275 PINCTRL_PIN(138, "GPIO_138"),
276 PINCTRL_PIN(139, "GPIO_139"),
277 PINCTRL_PIN(140, "GPIO_140"),
278 PINCTRL_PIN(141, "GPIO_141"),
279 PINCTRL_PIN(142, "GPIO_142"),
280 PINCTRL_PIN(143, "GPIO_143"),
281 PINCTRL_PIN(144, "GPIO_144"),
282 PINCTRL_PIN(145, "GPIO_145"),
283 PINCTRL_PIN(146, "GPIO_146"),
284 PINCTRL_PIN(147, "GPIO_147"),
285 PINCTRL_PIN(148, "GPIO_148"),
286 PINCTRL_PIN(149, "GPIO_149"),
287 PINCTRL_PIN(150, "UFS_RESET"),
288 PINCTRL_PIN(151, "SDC1_RCLK"),
289 PINCTRL_PIN(152, "SDC1_CLK"),
290 PINCTRL_PIN(153, "SDC1_CMD"),
291 PINCTRL_PIN(154, "SDC1_DATA"),
292 PINCTRL_PIN(155, "SDC2_CLK"),
293 PINCTRL_PIN(156, "SDC2_CMD"),
294 PINCTRL_PIN(157, "SDC2_DATA"),
295 };
296
297 #define DECLARE_MSM_GPIO_PINS(pin) \
298 static const unsigned int gpio##pin##_pins[] = { pin }
299 DECLARE_MSM_GPIO_PINS(0);
300 DECLARE_MSM_GPIO_PINS(1);
301 DECLARE_MSM_GPIO_PINS(2);
302 DECLARE_MSM_GPIO_PINS(3);
303 DECLARE_MSM_GPIO_PINS(4);
304 DECLARE_MSM_GPIO_PINS(5);
305 DECLARE_MSM_GPIO_PINS(6);
306 DECLARE_MSM_GPIO_PINS(7);
307 DECLARE_MSM_GPIO_PINS(8);
308 DECLARE_MSM_GPIO_PINS(9);
309 DECLARE_MSM_GPIO_PINS(10);
310 DECLARE_MSM_GPIO_PINS(11);
311 DECLARE_MSM_GPIO_PINS(12);
312 DECLARE_MSM_GPIO_PINS(13);
313 DECLARE_MSM_GPIO_PINS(14);
314 DECLARE_MSM_GPIO_PINS(15);
315 DECLARE_MSM_GPIO_PINS(16);
316 DECLARE_MSM_GPIO_PINS(17);
317 DECLARE_MSM_GPIO_PINS(18);
318 DECLARE_MSM_GPIO_PINS(19);
319 DECLARE_MSM_GPIO_PINS(20);
320 DECLARE_MSM_GPIO_PINS(21);
321 DECLARE_MSM_GPIO_PINS(22);
322 DECLARE_MSM_GPIO_PINS(23);
323 DECLARE_MSM_GPIO_PINS(24);
324 DECLARE_MSM_GPIO_PINS(25);
325 DECLARE_MSM_GPIO_PINS(26);
326 DECLARE_MSM_GPIO_PINS(27);
327 DECLARE_MSM_GPIO_PINS(28);
328 DECLARE_MSM_GPIO_PINS(29);
329 DECLARE_MSM_GPIO_PINS(30);
330 DECLARE_MSM_GPIO_PINS(31);
331 DECLARE_MSM_GPIO_PINS(32);
332 DECLARE_MSM_GPIO_PINS(33);
333 DECLARE_MSM_GPIO_PINS(34);
334 DECLARE_MSM_GPIO_PINS(35);
335 DECLARE_MSM_GPIO_PINS(36);
336 DECLARE_MSM_GPIO_PINS(37);
337 DECLARE_MSM_GPIO_PINS(38);
338 DECLARE_MSM_GPIO_PINS(39);
339 DECLARE_MSM_GPIO_PINS(40);
340 DECLARE_MSM_GPIO_PINS(41);
341 DECLARE_MSM_GPIO_PINS(42);
342 DECLARE_MSM_GPIO_PINS(43);
343 DECLARE_MSM_GPIO_PINS(44);
344 DECLARE_MSM_GPIO_PINS(45);
345 DECLARE_MSM_GPIO_PINS(46);
346 DECLARE_MSM_GPIO_PINS(47);
347 DECLARE_MSM_GPIO_PINS(48);
348 DECLARE_MSM_GPIO_PINS(49);
349 DECLARE_MSM_GPIO_PINS(50);
350 DECLARE_MSM_GPIO_PINS(51);
351 DECLARE_MSM_GPIO_PINS(52);
352 DECLARE_MSM_GPIO_PINS(53);
353 DECLARE_MSM_GPIO_PINS(54);
354 DECLARE_MSM_GPIO_PINS(55);
355 DECLARE_MSM_GPIO_PINS(56);
356 DECLARE_MSM_GPIO_PINS(57);
357 DECLARE_MSM_GPIO_PINS(58);
358 DECLARE_MSM_GPIO_PINS(59);
359 DECLARE_MSM_GPIO_PINS(60);
360 DECLARE_MSM_GPIO_PINS(61);
361 DECLARE_MSM_GPIO_PINS(62);
362 DECLARE_MSM_GPIO_PINS(63);
363 DECLARE_MSM_GPIO_PINS(64);
364 DECLARE_MSM_GPIO_PINS(65);
365 DECLARE_MSM_GPIO_PINS(66);
366 DECLARE_MSM_GPIO_PINS(67);
367 DECLARE_MSM_GPIO_PINS(68);
368 DECLARE_MSM_GPIO_PINS(69);
369 DECLARE_MSM_GPIO_PINS(70);
370 DECLARE_MSM_GPIO_PINS(71);
371 DECLARE_MSM_GPIO_PINS(72);
372 DECLARE_MSM_GPIO_PINS(73);
373 DECLARE_MSM_GPIO_PINS(74);
374 DECLARE_MSM_GPIO_PINS(75);
375 DECLARE_MSM_GPIO_PINS(76);
376 DECLARE_MSM_GPIO_PINS(77);
377 DECLARE_MSM_GPIO_PINS(78);
378 DECLARE_MSM_GPIO_PINS(79);
379 DECLARE_MSM_GPIO_PINS(80);
380 DECLARE_MSM_GPIO_PINS(81);
381 DECLARE_MSM_GPIO_PINS(82);
382 DECLARE_MSM_GPIO_PINS(83);
383 DECLARE_MSM_GPIO_PINS(84);
384 DECLARE_MSM_GPIO_PINS(85);
385 DECLARE_MSM_GPIO_PINS(86);
386 DECLARE_MSM_GPIO_PINS(87);
387 DECLARE_MSM_GPIO_PINS(88);
388 DECLARE_MSM_GPIO_PINS(89);
389 DECLARE_MSM_GPIO_PINS(90);
390 DECLARE_MSM_GPIO_PINS(91);
391 DECLARE_MSM_GPIO_PINS(92);
392 DECLARE_MSM_GPIO_PINS(93);
393 DECLARE_MSM_GPIO_PINS(94);
394 DECLARE_MSM_GPIO_PINS(95);
395 DECLARE_MSM_GPIO_PINS(96);
396 DECLARE_MSM_GPIO_PINS(97);
397 DECLARE_MSM_GPIO_PINS(98);
398 DECLARE_MSM_GPIO_PINS(99);
399 DECLARE_MSM_GPIO_PINS(100);
400 DECLARE_MSM_GPIO_PINS(101);
401 DECLARE_MSM_GPIO_PINS(102);
402 DECLARE_MSM_GPIO_PINS(103);
403 DECLARE_MSM_GPIO_PINS(104);
404 DECLARE_MSM_GPIO_PINS(105);
405 DECLARE_MSM_GPIO_PINS(106);
406 DECLARE_MSM_GPIO_PINS(107);
407 DECLARE_MSM_GPIO_PINS(108);
408 DECLARE_MSM_GPIO_PINS(109);
409 DECLARE_MSM_GPIO_PINS(110);
410 DECLARE_MSM_GPIO_PINS(111);
411 DECLARE_MSM_GPIO_PINS(112);
412 DECLARE_MSM_GPIO_PINS(113);
413 DECLARE_MSM_GPIO_PINS(114);
414 DECLARE_MSM_GPIO_PINS(115);
415 DECLARE_MSM_GPIO_PINS(116);
416 DECLARE_MSM_GPIO_PINS(117);
417 DECLARE_MSM_GPIO_PINS(118);
418 DECLARE_MSM_GPIO_PINS(119);
419 DECLARE_MSM_GPIO_PINS(120);
420 DECLARE_MSM_GPIO_PINS(121);
421 DECLARE_MSM_GPIO_PINS(122);
422 DECLARE_MSM_GPIO_PINS(123);
423 DECLARE_MSM_GPIO_PINS(124);
424 DECLARE_MSM_GPIO_PINS(125);
425 DECLARE_MSM_GPIO_PINS(126);
426 DECLARE_MSM_GPIO_PINS(127);
427 DECLARE_MSM_GPIO_PINS(128);
428 DECLARE_MSM_GPIO_PINS(129);
429 DECLARE_MSM_GPIO_PINS(130);
430 DECLARE_MSM_GPIO_PINS(131);
431 DECLARE_MSM_GPIO_PINS(132);
432 DECLARE_MSM_GPIO_PINS(133);
433 DECLARE_MSM_GPIO_PINS(134);
434 DECLARE_MSM_GPIO_PINS(135);
435 DECLARE_MSM_GPIO_PINS(136);
436 DECLARE_MSM_GPIO_PINS(137);
437 DECLARE_MSM_GPIO_PINS(138);
438 DECLARE_MSM_GPIO_PINS(139);
439 DECLARE_MSM_GPIO_PINS(140);
440 DECLARE_MSM_GPIO_PINS(141);
441 DECLARE_MSM_GPIO_PINS(142);
442 DECLARE_MSM_GPIO_PINS(143);
443 DECLARE_MSM_GPIO_PINS(144);
444 DECLARE_MSM_GPIO_PINS(145);
445 DECLARE_MSM_GPIO_PINS(146);
446 DECLARE_MSM_GPIO_PINS(147);
447 DECLARE_MSM_GPIO_PINS(148);
448 DECLARE_MSM_GPIO_PINS(149);
449
450 static const unsigned int ufs_reset_pins[] = { 150 };
451 static const unsigned int sdc1_rclk_pins[] = { 151 };
452 static const unsigned int sdc1_clk_pins[] = { 152 };
453 static const unsigned int sdc1_cmd_pins[] = { 153 };
454 static const unsigned int sdc1_data_pins[] = { 154 };
455 static const unsigned int sdc2_clk_pins[] = { 155 };
456 static const unsigned int sdc2_cmd_pins[] = { 156 };
457 static const unsigned int sdc2_data_pins[] = { 157 };
458
459 enum sdm670_functions {
460 msm_mux_gpio,
461 msm_mux_adsp_ext,
462 msm_mux_agera_pll,
463 msm_mux_atest_char,
464 msm_mux_atest_tsens,
465 msm_mux_atest_tsens2,
466 msm_mux_atest_usb1,
467 msm_mux_atest_usb10,
468 msm_mux_atest_usb11,
469 msm_mux_atest_usb12,
470 msm_mux_atest_usb13,
471 msm_mux_atest_usb2,
472 msm_mux_atest_usb20,
473 msm_mux_atest_usb21,
474 msm_mux_atest_usb22,
475 msm_mux_atest_usb23,
476 msm_mux_cam_mclk,
477 msm_mux_cci_async,
478 msm_mux_cci_i2c,
479 msm_mux_cci_timer0,
480 msm_mux_cci_timer1,
481 msm_mux_cci_timer2,
482 msm_mux_cci_timer3,
483 msm_mux_cci_timer4,
484 msm_mux_copy_gp,
485 msm_mux_copy_phase,
486 msm_mux_dbg_out,
487 msm_mux_ddr_bist,
488 msm_mux_ddr_pxi0,
489 msm_mux_ddr_pxi1,
490 msm_mux_ddr_pxi2,
491 msm_mux_ddr_pxi3,
492 msm_mux_edp_hot,
493 msm_mux_edp_lcd,
494 msm_mux_gcc_gp1,
495 msm_mux_gcc_gp2,
496 msm_mux_gcc_gp3,
497 msm_mux_gp_pdm0,
498 msm_mux_gp_pdm1,
499 msm_mux_gp_pdm2,
500 msm_mux_gps_tx,
501 msm_mux_jitter_bist,
502 msm_mux_ldo_en,
503 msm_mux_ldo_update,
504 msm_mux_lpass_slimbus,
505 msm_mux_m_voc,
506 msm_mux_mdp_vsync,
507 msm_mux_mdp_vsync0,
508 msm_mux_mdp_vsync1,
509 msm_mux_mdp_vsync2,
510 msm_mux_mdp_vsync3,
511 msm_mux_mss_lte,
512 msm_mux_nav_pps,
513 msm_mux_pa_indicator,
514 msm_mux_pci_e0,
515 msm_mux_pci_e1,
516 msm_mux_phase_flag,
517 msm_mux_pll_bist,
518 msm_mux_pll_bypassnl,
519 msm_mux_pll_reset,
520 msm_mux_pri_mi2s,
521 msm_mux_pri_mi2s_ws,
522 msm_mux_prng_rosc,
523 msm_mux_qdss_cti,
524 msm_mux_qdss,
525 msm_mux_qlink_enable,
526 msm_mux_qlink_request,
527 msm_mux_qua_mi2s,
528 msm_mux_qup0,
529 msm_mux_qup1,
530 msm_mux_qup10,
531 msm_mux_qup11,
532 msm_mux_qup12,
533 msm_mux_qup13,
534 msm_mux_qup14,
535 msm_mux_qup15,
536 msm_mux_qup2,
537 msm_mux_qup3,
538 msm_mux_qup4,
539 msm_mux_qup5,
540 msm_mux_qup6,
541 msm_mux_qup7,
542 msm_mux_qup8,
543 msm_mux_qup9,
544 msm_mux_qup_l4,
545 msm_mux_qup_l5,
546 msm_mux_qup_l6,
547 msm_mux_sd_write,
548 msm_mux_sdc4_clk,
549 msm_mux_sdc4_cmd,
550 msm_mux_sdc4_data,
551 msm_mux_sec_mi2s,
552 msm_mux_ter_mi2s,
553 msm_mux_tgu_ch0,
554 msm_mux_tgu_ch1,
555 msm_mux_tgu_ch2,
556 msm_mux_tgu_ch3,
557 msm_mux_tsif1_clk,
558 msm_mux_tsif1_data,
559 msm_mux_tsif1_en,
560 msm_mux_tsif1_error,
561 msm_mux_tsif1_sync,
562 msm_mux_tsif2_clk,
563 msm_mux_tsif2_data,
564 msm_mux_tsif2_en,
565 msm_mux_tsif2_error,
566 msm_mux_tsif2_sync,
567 msm_mux_uim1_clk,
568 msm_mux_uim1_data,
569 msm_mux_uim1_present,
570 msm_mux_uim1_reset,
571 msm_mux_uim2_clk,
572 msm_mux_uim2_data,
573 msm_mux_uim2_present,
574 msm_mux_uim2_reset,
575 msm_mux_uim_batt,
576 msm_mux_usb_phy,
577 msm_mux_vfr_1,
578 msm_mux_vsense_trigger,
579 msm_mux_wlan1_adc0,
580 msm_mux_wlan1_adc1,
581 msm_mux_wlan2_adc0,
582 msm_mux_wlan2_adc1,
583 msm_mux_wsa_clk,
584 msm_mux_wsa_data,
585 msm_mux__,
586 };
587
588 static const char * const gpio_groups[] = {
589 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
590 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
591 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
592 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
593 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
594 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
595 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
596 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
597 "gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76",
598 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
599 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
600 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
601 "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
602 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
603 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
604 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
605 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
606 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
607 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
608 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
609 "gpio147", "gpio148", "gpio149",
610 };
611 static const char * const qup0_groups[] = {
612 "gpio0", "gpio1", "gpio2", "gpio3",
613 };
614 static const char * const qup9_groups[] = {
615 "gpio4", "gpio5", "gpio6", "gpio7",
616 };
617 static const char * const qdss_cti_groups[] = {
618 "gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91",
619 };
620 static const char * const ddr_pxi0_groups[] = {
621 "gpio6", "gpio7",
622 };
623 static const char * const ddr_bist_groups[] = {
624 "gpio7", "gpio8", "gpio9", "gpio10",
625 };
626 static const char * const atest_tsens2_groups[] = {
627 "gpio7",
628 };
629 static const char * const vsense_trigger_groups[] = {
630 "gpio7",
631 };
632 static const char * const atest_usb1_groups[] = {
633 "gpio7",
634 };
635 static const char * const qup_l4_groups[] = {
636 "gpio8", "gpio35", "gpio75", "gpio105", "gpio123",
637 };
638 static const char * const gp_pdm1_groups[] = {
639 "gpio8", "gpio66",
640 };
641 static const char * const qup_l5_groups[] = {
642 "gpio9", "gpio36", "gpio76", "gpio106", "gpio124",
643 };
644 static const char * const mdp_vsync_groups[] = {
645 "gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
646 };
647 static const char * const qup_l6_groups[] = {
648 "gpio10", "gpio37", "gpio77", "gpio107", "gpio125",
649 };
650 static const char * const wlan2_adc1_groups[] = {
651 "gpio10",
652 };
653 static const char * const atest_usb11_groups[] = {
654 "gpio10",
655 };
656 static const char * const ddr_pxi2_groups[] = {
657 "gpio10", "gpio11",
658 };
659 static const char * const edp_lcd_groups[] = {
660 "gpio11",
661 };
662 static const char * const dbg_out_groups[] = {
663 "gpio11",
664 };
665 static const char * const wlan2_adc0_groups[] = {
666 "gpio11",
667 };
668 static const char * const atest_usb10_groups[] = {
669 "gpio11",
670 };
671 static const char * const m_voc_groups[] = {
672 "gpio12",
673 };
674 static const char * const tsif1_sync_groups[] = {
675 "gpio12",
676 };
677 static const char * const ddr_pxi3_groups[] = {
678 "gpio12", "gpio13",
679 };
680 static const char * const cam_mclk_groups[] = {
681 "gpio13", "gpio14", "gpio15", "gpio16",
682 };
683 static const char * const pll_bypassnl_groups[] = {
684 "gpio13",
685 };
686 static const char * const qdss_groups[] = {
687 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
688 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
689 "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
690 "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
691 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
692 "gpio123", "gpio124",
693 };
694 static const char * const pll_reset_groups[] = {
695 "gpio14",
696 };
697 static const char * const cci_i2c_groups[] = {
698 "gpio17", "gpio18", "gpio19", "gpio20",
699 };
700 static const char * const qup1_groups[] = {
701 "gpio17", "gpio18", "gpio19", "gpio20",
702 };
703 static const char * const cci_timer0_groups[] = {
704 "gpio21",
705 };
706 static const char * const gcc_gp2_groups[] = {
707 "gpio21",
708 };
709 static const char * const cci_timer1_groups[] = {
710 "gpio22",
711 };
712 static const char * const gcc_gp3_groups[] = {
713 "gpio22",
714 };
715 static const char * const cci_timer2_groups[] = {
716 "gpio23",
717 };
718 static const char * const cci_timer3_groups[] = {
719 "gpio24",
720 };
721 static const char * const cci_async_groups[] = {
722 "gpio24", "gpio25", "gpio26",
723 };
724 static const char * const cci_timer4_groups[] = {
725 "gpio25",
726 };
727 static const char * const jitter_bist_groups[] = {
728 "gpio26", "gpio35",
729 };
730 static const char * const qup2_groups[] = {
731 "gpio27", "gpio28", "gpio29", "gpio30",
732 };
733 static const char * const pll_bist_groups[] = {
734 "gpio27", "gpio36",
735 };
736 static const char * const agera_pll_groups[] = {
737 "gpio28", "gpio37",
738 };
739 static const char * const atest_tsens_groups[] = {
740 "gpio29",
741 };
742 static const char * const phase_flag_groups[] = {
743 "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
744 "gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96",
745 "gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139",
746 "gpio140", "gpio141", "gpio142", "gpio143",
747 };
748 static const char * const qup11_groups[] = {
749 "gpio31", "gpio32", "gpio33", "gpio34",
750 };
751 static const char * const qup14_groups[] = {
752 "gpio31", "gpio32", "gpio33", "gpio34",
753 };
754 static const char * const pci_e0_groups[] = {
755 "gpio35", "gpio36",
756 };
757 static const char * const usb_phy_groups[] = {
758 "gpio38",
759 };
760 static const char * const lpass_slimbus_groups[] = {
761 "gpio39",
762 };
763 static const char * const sd_write_groups[] = {
764 "gpio40",
765 };
766 static const char * const tsif1_error_groups[] = {
767 "gpio40",
768 };
769 static const char * const qup3_groups[] = {
770 "gpio41", "gpio42", "gpio43", "gpio44",
771 };
772 static const char * const qup6_groups[] = {
773 "gpio45", "gpio46", "gpio47", "gpio48",
774 };
775 static const char * const qup12_groups[] = {
776 "gpio49", "gpio50", "gpio51", "gpio52",
777 };
778 static const char * const qup10_groups[] = {
779 "gpio53", "gpio54", "gpio55", "gpio56",
780 };
781 static const char * const gp_pdm0_groups[] = {
782 "gpio54", "gpio95",
783 };
784 static const char * const wlan1_adc1_groups[] = {
785 "gpio54",
786 };
787 static const char * const atest_usb13_groups[] = {
788 "gpio54",
789 };
790 static const char * const ddr_pxi1_groups[] = {
791 "gpio54", "gpio55",
792 };
793 static const char * const wlan1_adc0_groups[] = {
794 "gpio55",
795 };
796 static const char * const atest_usb12_groups[] = {
797 "gpio55",
798 };
799 static const char * const qua_mi2s_groups[] = {
800 "gpio57",
801 };
802 static const char * const gcc_gp1_groups[] = {
803 "gpio57", "gpio78",
804 };
805 static const char * const pri_mi2s_groups[] = {
806 "gpio65", "gpio67", "gpio68",
807 };
808 static const char * const qup8_groups[] = {
809 "gpio65", "gpio66", "gpio67", "gpio68",
810 };
811 static const char * const wsa_clk_groups[] = {
812 "gpio65",
813 };
814 static const char * const pri_mi2s_ws_groups[] = {
815 "gpio66",
816 };
817 static const char * const wsa_data_groups[] = {
818 "gpio66",
819 };
820 static const char * const atest_usb2_groups[] = {
821 "gpio67",
822 };
823 static const char * const atest_usb23_groups[] = {
824 "gpio68",
825 };
826 static const char * const ter_mi2s_groups[] = {
827 "gpio75", "gpio76", "gpio77", "gpio78",
828 };
829 static const char * const atest_usb22_groups[] = {
830 "gpio75",
831 };
832 static const char * const atest_usb21_groups[] = {
833 "gpio76",
834 };
835 static const char * const atest_usb20_groups[] = {
836 "gpio77",
837 };
838 static const char * const sec_mi2s_groups[] = {
839 "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
840 };
841 static const char * const gp_pdm2_groups[] = {
842 "gpio79",
843 };
844 static const char * const qup15_groups[] = {
845 "gpio81", "gpio82", "gpio83", "gpio84",
846 };
847 static const char * const qup5_groups[] = {
848 "gpio85", "gpio86", "gpio87", "gpio88",
849 };
850 static const char * const copy_gp_groups[] = {
851 "gpio86",
852 };
853 static const char * const tsif1_clk_groups[] = {
854 "gpio89",
855 };
856 static const char * const qup4_groups[] = {
857 "gpio89", "gpio90", "gpio91", "gpio92",
858 };
859 static const char * const tgu_ch3_groups[] = {
860 "gpio89",
861 };
862 static const char * const tsif1_en_groups[] = {
863 "gpio90",
864 };
865 static const char * const mdp_vsync0_groups[] = {
866 "gpio90",
867 };
868 static const char * const mdp_vsync1_groups[] = {
869 "gpio90",
870 };
871 static const char * const mdp_vsync2_groups[] = {
872 "gpio90",
873 };
874 static const char * const mdp_vsync3_groups[] = {
875 "gpio90",
876 };
877 static const char * const tgu_ch0_groups[] = {
878 "gpio90",
879 };
880 static const char * const tsif1_data_groups[] = {
881 "gpio91",
882 };
883 static const char * const sdc4_cmd_groups[] = {
884 "gpio91",
885 };
886 static const char * const tgu_ch1_groups[] = {
887 "gpio91",
888 };
889 static const char * const tsif2_error_groups[] = {
890 "gpio92",
891 };
892 static const char * const vfr_1_groups[] = {
893 "gpio92",
894 };
895 static const char * const tgu_ch2_groups[] = {
896 "gpio92",
897 };
898 static const char * const sdc4_data_groups[] = {
899 "gpio92", "gpio94", "gpio95", "gpio96",
900 };
901 static const char * const tsif2_clk_groups[] = {
902 "gpio93",
903 };
904 static const char * const sdc4_clk_groups[] = {
905 "gpio93",
906 };
907 static const char * const qup7_groups[] = {
908 "gpio93", "gpio94", "gpio95", "gpio96",
909 };
910 static const char * const tsif2_en_groups[] = {
911 "gpio94",
912 };
913 static const char * const tsif2_data_groups[] = {
914 "gpio95",
915 };
916 static const char * const tsif2_sync_groups[] = {
917 "gpio96",
918 };
919 static const char * const ldo_en_groups[] = {
920 "gpio97",
921 };
922 static const char * const ldo_update_groups[] = {
923 "gpio98",
924 };
925 static const char * const prng_rosc_groups[] = {
926 "gpio99", "gpio102",
927 };
928 static const char * const pci_e1_groups[] = {
929 "gpio102", "gpio103",
930 };
931 static const char * const copy_phase_groups[] = {
932 "gpio103",
933 };
934 static const char * const uim2_data_groups[] = {
935 "gpio105",
936 };
937 static const char * const qup13_groups[] = {
938 "gpio105", "gpio106", "gpio107", "gpio108",
939 };
940 static const char * const uim2_clk_groups[] = {
941 "gpio106",
942 };
943 static const char * const uim2_reset_groups[] = {
944 "gpio107",
945 };
946 static const char * const uim2_present_groups[] = {
947 "gpio108",
948 };
949 static const char * const uim1_data_groups[] = {
950 "gpio109",
951 };
952 static const char * const uim1_clk_groups[] = {
953 "gpio110",
954 };
955 static const char * const uim1_reset_groups[] = {
956 "gpio111",
957 };
958 static const char * const uim1_present_groups[] = {
959 "gpio112",
960 };
961 static const char * const uim_batt_groups[] = {
962 "gpio113",
963 };
964 static const char * const edp_hot_groups[] = {
965 "gpio113",
966 };
967 static const char * const nav_pps_groups[] = {
968 "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
969 "gpio129", "gpio129", "gpio143", "gpio143",
970 };
971 static const char * const gps_tx_groups[] = {
972 "gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145",
973 };
974 static const char * const atest_char_groups[] = {
975 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
976 };
977 static const char * const adsp_ext_groups[] = {
978 "gpio118",
979 };
980 static const char * const qlink_request_groups[] = {
981 "gpio130",
982 };
983 static const char * const qlink_enable_groups[] = {
984 "gpio131",
985 };
986 static const char * const pa_indicator_groups[] = {
987 "gpio135",
988 };
989 static const char * const mss_lte_groups[] = {
990 "gpio144", "gpio145",
991 };
992
993 static const struct pinfunction sdm670_functions[] = {
994 MSM_PIN_FUNCTION(gpio),
995 MSM_PIN_FUNCTION(adsp_ext),
996 MSM_PIN_FUNCTION(agera_pll),
997 MSM_PIN_FUNCTION(atest_char),
998 MSM_PIN_FUNCTION(atest_tsens),
999 MSM_PIN_FUNCTION(atest_tsens2),
1000 MSM_PIN_FUNCTION(atest_usb1),
1001 MSM_PIN_FUNCTION(atest_usb10),
1002 MSM_PIN_FUNCTION(atest_usb11),
1003 MSM_PIN_FUNCTION(atest_usb12),
1004 MSM_PIN_FUNCTION(atest_usb13),
1005 MSM_PIN_FUNCTION(atest_usb2),
1006 MSM_PIN_FUNCTION(atest_usb20),
1007 MSM_PIN_FUNCTION(atest_usb21),
1008 MSM_PIN_FUNCTION(atest_usb22),
1009 MSM_PIN_FUNCTION(atest_usb23),
1010 MSM_PIN_FUNCTION(cam_mclk),
1011 MSM_PIN_FUNCTION(cci_async),
1012 MSM_PIN_FUNCTION(cci_i2c),
1013 MSM_PIN_FUNCTION(cci_timer0),
1014 MSM_PIN_FUNCTION(cci_timer1),
1015 MSM_PIN_FUNCTION(cci_timer2),
1016 MSM_PIN_FUNCTION(cci_timer3),
1017 MSM_PIN_FUNCTION(cci_timer4),
1018 MSM_PIN_FUNCTION(copy_gp),
1019 MSM_PIN_FUNCTION(copy_phase),
1020 MSM_PIN_FUNCTION(dbg_out),
1021 MSM_PIN_FUNCTION(ddr_bist),
1022 MSM_PIN_FUNCTION(ddr_pxi0),
1023 MSM_PIN_FUNCTION(ddr_pxi1),
1024 MSM_PIN_FUNCTION(ddr_pxi2),
1025 MSM_PIN_FUNCTION(ddr_pxi3),
1026 MSM_PIN_FUNCTION(edp_hot),
1027 MSM_PIN_FUNCTION(edp_lcd),
1028 MSM_PIN_FUNCTION(gcc_gp1),
1029 MSM_PIN_FUNCTION(gcc_gp2),
1030 MSM_PIN_FUNCTION(gcc_gp3),
1031 MSM_PIN_FUNCTION(gp_pdm0),
1032 MSM_PIN_FUNCTION(gp_pdm1),
1033 MSM_PIN_FUNCTION(gp_pdm2),
1034 MSM_PIN_FUNCTION(gps_tx),
1035 MSM_PIN_FUNCTION(jitter_bist),
1036 MSM_PIN_FUNCTION(ldo_en),
1037 MSM_PIN_FUNCTION(ldo_update),
1038 MSM_PIN_FUNCTION(lpass_slimbus),
1039 MSM_PIN_FUNCTION(m_voc),
1040 MSM_PIN_FUNCTION(mdp_vsync),
1041 MSM_PIN_FUNCTION(mdp_vsync0),
1042 MSM_PIN_FUNCTION(mdp_vsync1),
1043 MSM_PIN_FUNCTION(mdp_vsync2),
1044 MSM_PIN_FUNCTION(mdp_vsync3),
1045 MSM_PIN_FUNCTION(mss_lte),
1046 MSM_PIN_FUNCTION(nav_pps),
1047 MSM_PIN_FUNCTION(pa_indicator),
1048 MSM_PIN_FUNCTION(pci_e0),
1049 MSM_PIN_FUNCTION(pci_e1),
1050 MSM_PIN_FUNCTION(phase_flag),
1051 MSM_PIN_FUNCTION(pll_bist),
1052 MSM_PIN_FUNCTION(pll_bypassnl),
1053 MSM_PIN_FUNCTION(pll_reset),
1054 MSM_PIN_FUNCTION(pri_mi2s),
1055 MSM_PIN_FUNCTION(pri_mi2s_ws),
1056 MSM_PIN_FUNCTION(prng_rosc),
1057 MSM_PIN_FUNCTION(qdss_cti),
1058 MSM_PIN_FUNCTION(qdss),
1059 MSM_PIN_FUNCTION(qlink_enable),
1060 MSM_PIN_FUNCTION(qlink_request),
1061 MSM_PIN_FUNCTION(qua_mi2s),
1062 MSM_PIN_FUNCTION(qup0),
1063 MSM_PIN_FUNCTION(qup1),
1064 MSM_PIN_FUNCTION(qup10),
1065 MSM_PIN_FUNCTION(qup11),
1066 MSM_PIN_FUNCTION(qup12),
1067 MSM_PIN_FUNCTION(qup13),
1068 MSM_PIN_FUNCTION(qup14),
1069 MSM_PIN_FUNCTION(qup15),
1070 MSM_PIN_FUNCTION(qup2),
1071 MSM_PIN_FUNCTION(qup3),
1072 MSM_PIN_FUNCTION(qup4),
1073 MSM_PIN_FUNCTION(qup5),
1074 MSM_PIN_FUNCTION(qup6),
1075 MSM_PIN_FUNCTION(qup7),
1076 MSM_PIN_FUNCTION(qup8),
1077 MSM_PIN_FUNCTION(qup9),
1078 MSM_PIN_FUNCTION(qup_l4),
1079 MSM_PIN_FUNCTION(qup_l5),
1080 MSM_PIN_FUNCTION(qup_l6),
1081 MSM_PIN_FUNCTION(sdc4_clk),
1082 MSM_PIN_FUNCTION(sdc4_cmd),
1083 MSM_PIN_FUNCTION(sdc4_data),
1084 MSM_PIN_FUNCTION(sd_write),
1085 MSM_PIN_FUNCTION(sec_mi2s),
1086 MSM_PIN_FUNCTION(ter_mi2s),
1087 MSM_PIN_FUNCTION(tgu_ch0),
1088 MSM_PIN_FUNCTION(tgu_ch1),
1089 MSM_PIN_FUNCTION(tgu_ch2),
1090 MSM_PIN_FUNCTION(tgu_ch3),
1091 MSM_PIN_FUNCTION(tsif1_clk),
1092 MSM_PIN_FUNCTION(tsif1_data),
1093 MSM_PIN_FUNCTION(tsif1_en),
1094 MSM_PIN_FUNCTION(tsif1_error),
1095 MSM_PIN_FUNCTION(tsif1_sync),
1096 MSM_PIN_FUNCTION(tsif2_clk),
1097 MSM_PIN_FUNCTION(tsif2_data),
1098 MSM_PIN_FUNCTION(tsif2_en),
1099 MSM_PIN_FUNCTION(tsif2_error),
1100 MSM_PIN_FUNCTION(tsif2_sync),
1101 MSM_PIN_FUNCTION(uim1_clk),
1102 MSM_PIN_FUNCTION(uim1_data),
1103 MSM_PIN_FUNCTION(uim1_present),
1104 MSM_PIN_FUNCTION(uim1_reset),
1105 MSM_PIN_FUNCTION(uim2_clk),
1106 MSM_PIN_FUNCTION(uim2_data),
1107 MSM_PIN_FUNCTION(uim2_present),
1108 MSM_PIN_FUNCTION(uim2_reset),
1109 MSM_PIN_FUNCTION(uim_batt),
1110 MSM_PIN_FUNCTION(usb_phy),
1111 MSM_PIN_FUNCTION(vfr_1),
1112 MSM_PIN_FUNCTION(vsense_trigger),
1113 MSM_PIN_FUNCTION(wlan1_adc0),
1114 MSM_PIN_FUNCTION(wlan1_adc1),
1115 MSM_PIN_FUNCTION(wlan2_adc0),
1116 MSM_PIN_FUNCTION(wlan2_adc1),
1117 MSM_PIN_FUNCTION(wsa_clk),
1118 MSM_PIN_FUNCTION(wsa_data),
1119 };
1120
1121 /*
1122 * Each pin is individually controlled by its own group and gpios that cannot
1123 * be requested are represented by the PINGROUP_DUMMY macro so that the group
1124 * numbers and names correspond to their respective gpio. These dummy pins do
1125 * not have a valid set of pinfuncs or a valid ctl_reg and should not be
1126 * requested.
1127 */
1128 static const struct msm_pingroup sdm670_groups[] = {
1129 PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
1130 PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
1131 PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
1132 PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
1133 PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),
1134 PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),
1135 PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _),
1136 PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _),
1137 PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _),
1138 PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _),
1139 PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _),
1140 PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _),
1141 PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _),
1142 PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _),
1143 PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1144 PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _),
1145 PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _),
1146 PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _),
1147 PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1148 PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1149 PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1150 PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
1151 PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
1152 PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _),
1153 PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _),
1154 PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _),
1155 PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _),
1156 PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _),
1157 PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _),
1158 PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _),
1159 PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _),
1160 PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _),
1161 PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _),
1162 PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _),
1163 PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _),
1164 PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _),
1165 PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _),
1166 PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _),
1167 PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _),
1168 PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _),
1169 PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _),
1170 PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1171 PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1172 PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1173 PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1174 PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _),
1175 PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _),
1176 PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _),
1177 PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _),
1178 PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _),
1179 PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _),
1180 PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
1181 PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _),
1182 PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _),
1183 PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1184 PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _),
1185 PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _),
1186 PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _),
1187 PINGROUP_DUMMY(58),
1188 PINGROUP_DUMMY(59),
1189 PINGROUP_DUMMY(60),
1190 PINGROUP_DUMMY(61),
1191 PINGROUP_DUMMY(62),
1192 PINGROUP_DUMMY(63),
1193 PINGROUP_DUMMY(64),
1194 PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _),
1195 PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _),
1196 PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _),
1197 PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _),
1198 PINGROUP_DUMMY(69),
1199 PINGROUP_DUMMY(70),
1200 PINGROUP_DUMMY(71),
1201 PINGROUP_DUMMY(72),
1202 PINGROUP_DUMMY(73),
1203 PINGROUP_DUMMY(74),
1204 PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _),
1205 PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _),
1206 PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _),
1207 PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1208 PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _),
1209 PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _),
1210 PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1211 PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1212 PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1213 PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _),
1214 PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _),
1215 PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _),
1216 PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _),
1217 PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _),
1218 PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _),
1219 PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1220 PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _),
1221 PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _),
1222 PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _),
1223 PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _),
1224 PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _),
1225 PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _),
1226 PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _),
1227 PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _),
1228 PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _),
1229 PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _),
1230 PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _),
1231 PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _),
1232 PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _),
1233 PINGROUP_DUMMY(104),
1234 PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _),
1235 PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _),
1236 PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _),
1237 PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _),
1238 PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
1239 PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
1240 PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
1241 PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
1242 PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _),
1243 PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1244 PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1245 PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _),
1246 PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1247 PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _),
1248 PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1249 PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1250 PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1251 PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _),
1252 PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _),
1253 PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _),
1254 PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _),
1255 PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _),
1256 PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
1257 PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),
1258 PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),
1259 PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _),
1260 PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _),
1261 PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _),
1262 PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _),
1263 PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _),
1264 PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1265 PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
1266 PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _),
1267 PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _),
1268 PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _),
1269 PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _),
1270 PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _),
1271 PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _),
1272 PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _),
1273 PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1274 PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _),
1275 PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1276 PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1277 PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1278 PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1279 UFS_RESET(ufs_reset, 0x99d000),
1280 SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0),
1281 SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6),
1282 SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3),
1283 SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0),
1284 SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6),
1285 SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3),
1286 SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0),
1287 };
1288
1289 static const int sdm670_reserved_gpios[] = {
1290 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1
1291 };
1292
1293 static const struct msm_gpio_wakeirq_map sdm670_pdc_map[] = {
1294 { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 },
1295 { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 },
1296 { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 },
1297 { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 },
1298 { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 },
1299 { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 66, 66 },
1300 { 68, 67 }, { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 },
1301 { 84, 74 }, { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 },
1302 { 91, 79 }, { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 },
1303 { 101, 84 }, { 103, 85 }, { 115, 90 }, { 116, 91 }, { 117, 92 },
1304 { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 },
1305 { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 },
1306 { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 },
1307 };
1308
1309 static const struct msm_pinctrl_soc_data sdm670_pinctrl = {
1310 .pins = sdm670_pins,
1311 .npins = ARRAY_SIZE(sdm670_pins),
1312 .functions = sdm670_functions,
1313 .nfunctions = ARRAY_SIZE(sdm670_functions),
1314 .groups = sdm670_groups,
1315 .ngroups = ARRAY_SIZE(sdm670_groups),
1316 .ngpios = 151,
1317 .reserved_gpios = sdm670_reserved_gpios,
1318 .wakeirq_map = sdm670_pdc_map,
1319 .nwakeirq_map = ARRAY_SIZE(sdm670_pdc_map),
1320 .wakeirq_dual_edge_errata = true,
1321 };
1322
sdm670_pinctrl_probe(struct platform_device * pdev)1323 static int sdm670_pinctrl_probe(struct platform_device *pdev)
1324 {
1325 return msm_pinctrl_probe(pdev, &sdm670_pinctrl);
1326 }
1327
1328 static const struct of_device_id sdm670_pinctrl_of_match[] = {
1329 { .compatible = "qcom,sdm670-tlmm", },
1330 { },
1331 };
1332 MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match);
1333
1334 static struct platform_driver sdm670_pinctrl_driver = {
1335 .driver = {
1336 .name = "sdm670-pinctrl",
1337 .of_match_table = sdm670_pinctrl_of_match,
1338 },
1339 .probe = sdm670_pinctrl_probe,
1340 .remove = msm_pinctrl_remove,
1341 };
1342
sdm670_pinctrl_init(void)1343 static int __init sdm670_pinctrl_init(void)
1344 {
1345 return platform_driver_register(&sdm670_pinctrl_driver);
1346 }
1347 arch_initcall(sdm670_pinctrl_init);
1348
sdm670_pinctrl_exit(void)1349 static void __exit sdm670_pinctrl_exit(void)
1350 {
1351 platform_driver_unregister(&sdm670_pinctrl_driver);
1352 }
1353 module_exit(sdm670_pinctrl_exit);
1354
1355 MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver");
1356 MODULE_LICENSE("GPL");
1357