1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * Marvell Xenon SDHCI controller driver.
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/resource.h>
41 #include <sys/rman.h>
42 #include <sys/sysctl.h>
43 #include <sys/taskqueue.h>
44
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47
48 #include <dev/regulator/regulator.h>
49
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcbrvar.h>
52 #include <dev/mmc/mmcreg.h>
53
54 #include <dev/sdhci/sdhci.h>
55 #include <dev/sdhci/sdhci_xenon.h>
56
57 #include "mmcbr_if.h"
58 #include "sdhci_if.h"
59
60 #include "opt_mmccam.h"
61 #include "opt_soc.h"
62
63 #define MAX_SLOTS 6
64
65 static uint8_t
sdhci_xenon_read_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)66 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused,
67 bus_size_t off)
68 {
69 struct sdhci_xenon_softc *sc = device_get_softc(dev);
70
71 return (bus_read_1(sc->mem_res, off));
72 }
73
74 static void
sdhci_xenon_write_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint8_t val)75 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused,
76 bus_size_t off, uint8_t val)
77 {
78 struct sdhci_xenon_softc *sc = device_get_softc(dev);
79
80 bus_write_1(sc->mem_res, off, val);
81 }
82
83 static uint16_t
sdhci_xenon_read_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)84 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused,
85 bus_size_t off)
86 {
87 struct sdhci_xenon_softc *sc = device_get_softc(dev);
88
89 return (bus_read_2(sc->mem_res, off));
90 }
91
92 static void
sdhci_xenon_write_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint16_t val)93 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused,
94 bus_size_t off, uint16_t val)
95 {
96 struct sdhci_xenon_softc *sc = device_get_softc(dev);
97
98 bus_write_2(sc->mem_res, off, val);
99 }
100
101 static uint32_t
sdhci_xenon_read_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)102 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused,
103 bus_size_t off)
104 {
105 struct sdhci_xenon_softc *sc = device_get_softc(dev);
106
107 return bus_read_4(sc->mem_res, off);
108 }
109
110 static void
sdhci_xenon_write_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t val)111 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused,
112 bus_size_t off, uint32_t val)
113 {
114 struct sdhci_xenon_softc *sc = device_get_softc(dev);
115
116 bus_write_4(sc->mem_res, off, val);
117 }
118
119 static void
sdhci_xenon_read_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)120 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
121 bus_size_t off, uint32_t *data, bus_size_t count)
122 {
123 struct sdhci_xenon_softc *sc = device_get_softc(dev);
124
125 bus_read_multi_4(sc->mem_res, off, data, count);
126 }
127
128 static void
sdhci_xenon_write_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)129 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
130 bus_size_t off, uint32_t *data, bus_size_t count)
131 {
132 struct sdhci_xenon_softc *sc = device_get_softc(dev);
133
134 bus_write_multi_4(sc->mem_res, off, data, count);
135 }
136
137 static void
sdhci_xenon_intr(void * arg)138 sdhci_xenon_intr(void *arg)
139 {
140 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg;
141
142 sdhci_generic_intr(sc->slot);
143 }
144
145 static int
sdhci_xenon_get_ro(device_t bus,device_t dev)146 sdhci_xenon_get_ro(device_t bus, device_t dev)
147 {
148 struct sdhci_xenon_softc *sc = device_get_softc(bus);
149
150 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
151 }
152
153 static void
sdhci_xenon_set_uhs_timing(device_t brdev,struct sdhci_slot * slot)154 sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot)
155 {
156 const struct mmc_ios *ios;
157 uint16_t hostctrl2;
158
159 if (slot->version < SDHCI_SPEC_300)
160 return;
161
162 mtx_assert(&slot->mtx, MA_OWNED);
163 ios = &slot->host.ios;
164
165 /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */
166 hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2);
167 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
168 if (ios->clock > SD_SDR50_MAX) {
169 if (ios->timing == bus_timing_mmc_hs400 ||
170 ios->timing == bus_timing_mmc_hs400es)
171 hostctrl2 |= XENON_CTRL2_MMC_HS400;
172 else if (ios->timing == bus_timing_mmc_hs200)
173 hostctrl2 |= XENON_CTRL2_MMC_HS200;
174 else
175 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
176 }
177 else if (ios->clock > SD_SDR25_MAX)
178 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
179 else if (ios->clock > SD_SDR12_MAX) {
180 if (ios->timing == bus_timing_uhs_ddr50 ||
181 ios->timing == bus_timing_mmc_ddr52)
182 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
183 else
184 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
185 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
186 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
187 sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2);
188 }
189
190 static int
sdhci_xenon_phy_init(device_t brdev,struct mmc_ios * ios)191 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
192 {
193 int i;
194 struct sdhci_xenon_softc *sc;
195 uint32_t reg;
196
197 sc = device_get_softc(brdev);
198 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
199 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT;
200 switch (ios->timing) {
201 case bus_timing_normal:
202 case bus_timing_hs:
203 case bus_timing_uhs_sdr12:
204 case bus_timing_uhs_sdr25:
205 case bus_timing_uhs_sdr50:
206 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
207 break;
208 default:
209 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
210 }
211 if (sc->slow_mode)
212 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
213 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
214
215 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
216 reg |= XENON_PHY_INITIALIZATION;
217 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
218
219 /* Wait for the eMMC PHY init. */
220 for (i = 100; i > 0; i--) {
221 DELAY(100);
222
223 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
224 if ((reg & XENON_PHY_INITIALIZATION) == 0)
225 break;
226 }
227
228 if (i == 0) {
229 device_printf(brdev, "eMMC PHY failed to initialize\n");
230 return (ETIMEDOUT);
231 }
232
233 return (0);
234 }
235
236 static int
sdhci_xenon_phy_set(device_t brdev,struct mmc_ios * ios)237 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios)
238 {
239 struct sdhci_xenon_softc *sc;
240 uint32_t reg;
241
242 sc = device_get_softc(brdev);
243 /* Setup pad, set bit[28] and bits[26:24] */
244 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);
245 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
246 XENON_FC_QSP_RECEN | XENON_OEN_QSN);
247 /* All FC_XX_RECEIVCE should be set as CMOS Type */
248 reg |= XENON_FC_ALL_CMOS_RECEIVER;
249 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);
250
251 /* Set CMD and DQ Pull Up */
252 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
253 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU);
254 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD);
255 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
256
257 if (ios->timing == bus_timing_normal)
258 return (sdhci_xenon_phy_init(brdev, ios));
259
260 /* Clear SDIO mode, no SDIO support for now. */
261 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
262 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
263 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
264
265 /*
266 * Set preferred ZNR and ZPR value.
267 * The ZNR and ZPR value vary between different boards.
268 * Define them both in the DTS for the board!
269 */
270 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);
271 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
272 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr);
273 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);
274
275 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */
276 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
277 reg &= ~SDHCI_CLOCK_CARD_EN;
278 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
279
280 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);
281 switch (ios->timing) {
282 case bus_timing_mmc_hs400:
283 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
284 XENON_CMD_DDR_MODE;
285 reg &= ~XENON_DQ_ASYNC_MODE;
286 break;
287 case bus_timing_uhs_ddr50:
288 case bus_timing_mmc_ddr52:
289 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
290 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
291 break;
292 default:
293 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
294 XENON_CMD_DDR_MODE);
295 reg |= XENON_DQ_ASYNC_MODE;
296 }
297 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);
298
299 /* Enable SD clock. */
300 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
301 reg |= SDHCI_CLOCK_CARD_EN;
302 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
303
304 if (ios->timing == bus_timing_mmc_hs400)
305 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
306 XENON_LOGIC_TIMING_VALUE);
307 else {
308 /* Disable both SDHC Data Strobe and Enhanced Strobe. */
309 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);
310 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
311 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);
312
313 /* Clear Strobe line Pull down or Pull up. */
314 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
315 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU);
316 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
317 }
318
319 return (sdhci_xenon_phy_init(brdev, ios));
320 }
321
322 static int
sdhci_xenon_update_ios(device_t brdev,device_t reqdev)323 sdhci_xenon_update_ios(device_t brdev, device_t reqdev)
324 {
325 int err;
326 struct sdhci_xenon_softc *sc;
327 struct mmc_ios *ios;
328 struct sdhci_slot *slot;
329 uint32_t reg;
330
331 err = sdhci_generic_update_ios(brdev, reqdev);
332 if (err != 0)
333 return (err);
334
335 sc = device_get_softc(brdev);
336 slot = device_get_ivars(reqdev);
337 ios = &slot->host.ios;
338
339 switch (ios->power_mode) {
340 case power_on:
341 break;
342 case power_off:
343 if (bootverbose)
344 device_printf(sc->dev, "Powering down sd/mmc\n");
345
346 if (sc->vmmc_supply)
347 regulator_disable(sc->vmmc_supply);
348 if (sc->vqmmc_supply)
349 regulator_disable(sc->vqmmc_supply);
350 break;
351 case power_up:
352 if (bootverbose)
353 device_printf(sc->dev, "Powering up sd/mmc\n");
354
355 if (sc->vmmc_supply)
356 regulator_enable(sc->vmmc_supply);
357 if (sc->vqmmc_supply)
358 regulator_enable(sc->vqmmc_supply);
359 break;
360 };
361
362 /* Update the PHY settings. */
363 if (ios->clock != 0)
364 sdhci_xenon_phy_set(brdev, ios);
365
366 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) {
367 /* Enable SDCLK_IDLEOFF. */
368 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
369 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id);
370 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
371 }
372
373 return (0);
374 }
375
376 static int
sdhci_xenon_switch_vccq(device_t brdev,device_t reqdev)377 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev)
378 {
379 struct sdhci_xenon_softc *sc;
380 struct sdhci_slot *slot;
381 uint16_t hostctrl2;
382 int uvolt, err;
383
384 slot = device_get_ivars(reqdev);
385
386 if (slot->version < SDHCI_SPEC_300)
387 return (0);
388
389 sc = device_get_softc(brdev);
390
391 if (sc->vqmmc_supply == NULL && !sc->skip_regulators)
392 return (EOPNOTSUPP);
393
394 err = 0;
395
396 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
397 switch (slot->host.ios.vccq) {
398 case vccq_330:
399 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
400 return (0);
401 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
402 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);
403
404 if (!sc->skip_regulators) {
405 uvolt = 3300000;
406 err = regulator_set_voltage(sc->vqmmc_supply,
407 uvolt, uvolt);
408 if (err != 0) {
409 device_printf(sc->dev,
410 "Cannot set vqmmc to %d<->%d\n",
411 uvolt,
412 uvolt);
413 return (err);
414 }
415 }
416
417 /*
418 * According to the 'SD Host Controller Simplified
419 * Specification 4.20 the host driver should take more
420 * than 5ms for stable time of host voltage regulator
421 * from changing 1.8V Signaling Enable.
422 */
423 DELAY(5000);
424 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
425 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
426 return (0);
427 return (EAGAIN);
428 case vccq_180:
429 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
430 return (EINVAL);
431 }
432 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
433 return (0);
434 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
435 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);
436
437 if (!sc->skip_regulators) {
438 uvolt = 1800000;
439 err = regulator_set_voltage(sc->vqmmc_supply,
440 uvolt, uvolt);
441 if (err != 0) {
442 device_printf(sc->dev,
443 "Cannot set vqmmc to %d<->%d\n",
444 uvolt,
445 uvolt);
446 return (err);
447 }
448 }
449
450 /*
451 * According to the 'SD Host Controller Simplified
452 * Specification 4.20 the host driver should take more
453 * than 5ms for stable time of host voltage regulator
454 * from changing 1.8V Signaling Enable.
455 */
456 DELAY(5000);
457 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
458 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
459 return (0);
460 return (EAGAIN);
461 default:
462 device_printf(brdev,
463 "Attempt to set unsupported signaling voltage\n");
464 return (EINVAL);
465 }
466 }
467
468 static void
sdhci_xenon_parse_prop(device_t dev)469 sdhci_xenon_parse_prop(device_t dev)
470 {
471 struct sdhci_xenon_softc *sc;
472 uint32_t val;
473
474 sc = device_get_softc(dev);
475 val = 0;
476
477 if (device_get_property(dev, "quirks",
478 &val, sizeof(val), DEVICE_PROP_UINT32) > 0)
479 sc->slot->quirks = val;
480 sc->znr = XENON_ZNR_DEF_VALUE;
481 if (device_get_property(dev, "marvell,xenon-phy-znr",
482 &val, sizeof(val), DEVICE_PROP_UINT32) > 0)
483 sc->znr = val & XENON_ZNR_MASK;
484 sc->zpr = XENON_ZPR_DEF_VALUE;
485 if (device_get_property(dev, "marvell,xenon-phy-zpr",
486 &val, sizeof(val), DEVICE_PROP_UINT32) > 0)
487 sc->zpr = val & XENON_ZPR_MASK;
488 if (device_has_property(dev, "marvell,xenon-phy-slow-mode"))
489 sc->slow_mode = true;
490 }
491
492 int
sdhci_xenon_attach(device_t dev)493 sdhci_xenon_attach(device_t dev)
494 {
495 struct sdhci_xenon_softc *sc = device_get_softc(dev);
496 int err, rid;
497 uint32_t reg;
498
499 sc->dev = dev;
500 sc->slot_id = 0;
501
502 /* Allocate IRQ. */
503 rid = 0;
504 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
505 RF_ACTIVE);
506 if (sc->irq_res == NULL) {
507 device_printf(dev, "Can't allocate IRQ\n");
508 return (ENOMEM);
509 }
510
511 /* Allocate memory. */
512 rid = 0;
513 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
514 &rid, RF_ACTIVE);
515 if (sc->mem_res == NULL) {
516 bus_release_resource(dev, SYS_RES_IRQ,
517 rman_get_rid(sc->irq_res), sc->irq_res);
518 device_printf(dev, "Can't allocate memory for slot\n");
519 return (ENOMEM);
520 }
521
522 sdhci_xenon_parse_prop(dev);
523
524 sc->slot->max_clk = XENON_MMC_MAX_CLK;
525 if (sc->slot->host.f_max > 0)
526 sc->slot->max_clk = sc->slot->host.f_max;
527
528 if (sdhci_init_slot(dev, sc->slot, 0))
529 goto fail;
530
531 /* 1.2V signaling is not supported. */
532 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_120;
533
534 /* Disable UHS in case of the PHY slow mode. */
535 if (sc->slow_mode)
536 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_180;
537
538 /* Activate the interrupt */
539 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
540 NULL, sdhci_xenon_intr, sc, &sc->intrhand);
541 if (err) {
542 device_printf(dev, "Cannot setup IRQ\n");
543 goto fail;
544 }
545
546 /* Disable Auto Clock Gating. */
547 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
548 reg |= XENON_AUTO_CLKGATE_DISABLE;
549 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
550
551 /* Enable this SD controller. */
552 reg |= (1 << sc->slot_id);
553 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
554
555 /* Enable Parallel Transfer. */
556 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
557 reg |= (1 << sc->slot_id);
558 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
559
560 /* Enable Auto Clock Gating. */
561 reg &= ~XENON_AUTO_CLKGATE_DISABLE;
562 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
563
564 /* Disable SDCLK_IDLEOFF before the card initialization. */
565 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
566 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id));
567 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
568
569 /* Mask command conflict errors. */
570 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
571 reg |= XENON_MASK_CMD_CONFLICT_ERR;
572 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
573
574 /* Process cards detection. */
575 sdhci_start_slot(sc->slot);
576
577 return (0);
578
579 fail:
580 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
581 sc->irq_res);
582 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
583 sc->mem_res);
584 free(sc->slot, M_DEVBUF);
585 sc->slot = NULL;
586
587 return (ENXIO);
588 }
589
590 int
sdhci_xenon_detach(device_t dev)591 sdhci_xenon_detach(device_t dev)
592 {
593 struct sdhci_xenon_softc *sc = device_get_softc(dev);
594
595 bus_detach_children(dev);
596 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
597 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
598 sc->irq_res);
599 sdhci_cleanup_slot(sc->slot);
600 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
601 sc->mem_res);
602 free(sc->slot, M_DEVBUF);
603 sc->slot = NULL;
604
605 return (0);
606 }
607
608 static device_method_t sdhci_xenon_methods[] = {
609 /* Bus interface */
610 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
611 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
612
613 /* mmcbr_if */
614 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios),
615 DEVMETHOD(mmcbr_request, sdhci_generic_request),
616 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro),
617 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
618 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
619 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq),
620 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
621 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
622
623 /* SDHCI registers accessors */
624 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1),
625 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2),
626 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4),
627 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4),
628 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1),
629 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2),
630 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4),
631 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4),
632 DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing),
633
634 DEVMETHOD_END
635 };
636
637 DEFINE_CLASS_0(sdhci_xenon, sdhci_xenon_driver, sdhci_xenon_methods,
638 sizeof(struct sdhci_xenon_softc));
639
640 SDHCI_DEPEND(sdhci_xenon);
641 #ifndef MMCCAM
642 MMC_DECLARE_BRIDGE(sdhci_xenon);
643 #endif
644