1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/kobj.h>
36 #include <sys/libkern.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
42 #include <sys/rman.h>
43 #include <sys/sysctl.h>
44 #include <sys/taskqueue.h>
45 #include <sys/sbuf.h>
46
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49 #include <machine/stdarg.h>
50
51 #include <dev/mmc/bridge.h>
52 #include <dev/mmc/mmcreg.h>
53 #include <dev/mmc/mmcbrvar.h>
54
55 #include <dev/sdhci/sdhci.h>
56
57 #include <cam/cam.h>
58 #include <cam/cam_ccb.h>
59 #include <cam/cam_debug.h>
60 #include <cam/cam_sim.h>
61 #include <cam/cam_xpt_sim.h>
62
63 #include "mmcbr_if.h"
64 #include "sdhci_if.h"
65
66 #include "opt_mmccam.h"
67
68 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
69 "sdhci driver");
70
71 static int sdhci_debug = 0;
72 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
73 "Debug level");
74 u_int sdhci_quirk_clear = 0;
75 SYSCTL_UINT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
76 0, "Mask of quirks to clear");
77 u_int sdhci_quirk_set = 0;
78 SYSCTL_UINT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
79 "Mask of quirks to set");
80
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
84 #define RD_MULTI_4(slot, off, ptr, count) \
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
86
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
90 #define WR_MULTI_4(slot, off, ptr, count) \
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
92
93 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
94 static void sdhci_card_poll(void *arg);
95 static void sdhci_card_task(void *arg, int pending);
96 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
97 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
98 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
99 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
100 bool is_present);
101 static void sdhci_finish_command(struct sdhci_slot *slot);
102 static void sdhci_init(struct sdhci_slot *slot);
103 static void sdhci_read_block_pio(struct sdhci_slot *slot);
104 static void sdhci_req_done(struct sdhci_slot *slot);
105 static void sdhci_req_wakeup(struct mmc_request *req);
106 static void sdhci_retune(void *arg);
107 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
108 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
109 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
110 const struct mmc_data *data);
111 static void sdhci_start(struct sdhci_slot *slot);
112 static void sdhci_timeout(void *arg);
113 static void sdhci_start_command(struct sdhci_slot *slot,
114 struct mmc_command *cmd);
115 static void sdhci_start_data(struct sdhci_slot *slot,
116 const struct mmc_data *data);
117 static void sdhci_write_block_pio(struct sdhci_slot *slot);
118 static void sdhci_transfer_pio(struct sdhci_slot *slot);
119
120 #ifdef MMCCAM
121 /* CAM-related */
122 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb);
123 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
124 int proposed_clock);
125 static void sdhci_cam_poll(struct cam_sim *sim);
126 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
127 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
128 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
129 #endif
130
131 /* helper routines */
132 static int sdhci_dma_alloc(struct sdhci_slot *slot);
133 static void sdhci_dma_free(struct sdhci_slot *slot);
134 static void sdhci_dumpcaps(struct sdhci_slot *slot);
135 static void sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s);
136 static void sdhci_dumpregs(struct sdhci_slot *slot);
137 static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s);
138 static int sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS);
139 static int sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS);
140 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
141 int error);
142 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
143 __printflike(2, 3);
144 static int slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
145 const char * fmt, ...) __printflike(3, 4);
146 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
147
148 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
149 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
150 #define SDHCI_LOCK_INIT(_slot) \
151 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
152 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
153 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
154 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
155
156 #define SDHCI_DEFAULT_MAX_FREQ 50
157
158 #define SDHCI_200_MAX_DIVIDER 256
159 #define SDHCI_300_MAX_DIVIDER 2046
160
161 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
162 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
163
164 /*
165 * Broadcom BCM577xx Controller Constants
166 */
167 /* Maximum divider supported by the default clock source. */
168 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
169 /* Alternative clock's base frequency. */
170 #define BCM577XX_ALT_CLOCK_BASE 63000000
171
172 #define BCM577XX_HOST_CONTROL 0x198
173 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
174 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
175 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
176 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
177
178 static void
sdhci_getaddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)179 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
180 {
181
182 if (error != 0) {
183 printf("getaddr: error %d\n", error);
184 return;
185 }
186 *(bus_addr_t *)arg = segs[0].ds_addr;
187 }
188
189 static int
slot_printf(const struct sdhci_slot * slot,const char * fmt,...)190 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
191 {
192 char buf[128];
193 va_list ap;
194 int retval;
195
196 /*
197 * Make sure we print a single line all together rather than in two
198 * halves to avoid console gibberish bingo.
199 */
200 va_start(ap, fmt);
201 retval = vsnprintf(buf, sizeof(buf), fmt, ap);
202 va_end(ap);
203
204 retval += printf("%s-slot%d: %s",
205 device_get_nameunit(slot->bus), slot->num, buf);
206 return (retval);
207 }
208
209 static int
slot_sprintf(const struct sdhci_slot * slot,struct sbuf * s,const char * fmt,...)210 slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
211 const char * fmt, ...)
212 {
213 va_list ap;
214 int retval;
215
216 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num);
217
218 va_start(ap, fmt);
219 retval += sbuf_vprintf(s, fmt, ap);
220 va_end(ap);
221
222 return (retval);
223 }
224
225 static void
sdhci_dumpregs_buf(struct sdhci_slot * slot,struct sbuf * s)226 sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s)
227 {
228 slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n");
229
230 slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n",
231 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
232 slot_sprintf(slot, s, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
233 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
234 slot_sprintf(slot, s, "Argument: 0x%08x | Trn mode: 0x%08x\n",
235 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
236 slot_sprintf(slot, s, "Present: 0x%08x | Host ctl: 0x%08x\n",
237 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
238 slot_sprintf(slot, s, "Power: 0x%08x | Blk gap: 0x%08x\n",
239 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
240 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n",
241 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
242 slot_sprintf(slot, s, "Timeout: 0x%08x | Int stat: 0x%08x\n",
243 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
244 slot_sprintf(slot, s, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
245 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
246 slot_sprintf(slot, s, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
247 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
248 slot_sprintf(slot, s, "Caps: 0x%08x | Caps2: 0x%08x\n",
249 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
250 slot_sprintf(slot, s, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
251 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
252 slot_sprintf(slot, s, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
253 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
254
255 slot_sprintf(slot, s, "===========================================\n");
256 }
257
258 static void
sdhci_dumpregs(struct sdhci_slot * slot)259 sdhci_dumpregs(struct sdhci_slot *slot)
260 {
261 struct sbuf s;
262
263 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) {
264 slot_printf(slot, "sdhci_dumpregs: Failed to allocate memory for sbuf\n");
265 return;
266 }
267
268 sbuf_set_drain(&s, &sbuf_printf_drain, NULL);
269 sdhci_dumpregs_buf(slot, &s);
270 sbuf_finish(&s);
271 sbuf_delete(&s);
272 }
273
274 static int
sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS)275 sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS)
276 {
277 struct sdhci_slot *slot = arg1;
278 struct sbuf s;
279
280 sbuf_new_for_sysctl(&s, NULL, 1024, req);
281 sbuf_putc(&s, '\n');
282 sdhci_dumpregs_buf(slot, &s);
283 sbuf_finish(&s);
284 sbuf_delete(&s);
285
286 return (0);
287 }
288
289 static void
sdhci_dumpcaps_buf(struct sdhci_slot * slot,struct sbuf * s)290 sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s)
291 {
292 int host_caps = slot->host.caps;
293 int caps = slot->caps;
294
295 slot_sprintf(slot, s,
296 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
297 slot->max_clk / 1000000,
298 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
299 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
300 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
301 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
302 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
303 ((caps & SDHCI_CAN_VDD_180) &&
304 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
305 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
306 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
307 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
308 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
309 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
310 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
311 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
312 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
313 "removable");
314 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
315 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
316 slot_sprintf(slot, s, "eMMC:%s%s%s%s\n",
317 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
318 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
319 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
320 ((host_caps &
321 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
322 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
323 " HS400ES" : "");
324 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
325 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
326 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n",
327 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
328 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
329 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
330 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
331 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
332 if (slot->opt & SDHCI_TUNING_SUPPORTED)
333 slot_sprintf(slot, s,
334 "Re-tuning count %d secs, mode %d\n",
335 slot->retune_count, slot->retune_mode + 1);
336 }
337
338 static void
sdhci_dumpcaps(struct sdhci_slot * slot)339 sdhci_dumpcaps(struct sdhci_slot *slot)
340 {
341 struct sbuf s;
342
343 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) {
344 slot_printf(slot, "sdhci_dumpcaps: Failed to allocate memory for sbuf\n");
345 return;
346 }
347
348 sbuf_set_drain(&s, &sbuf_printf_drain, NULL);
349 sdhci_dumpcaps_buf(slot, &s);
350 sbuf_finish(&s);
351 sbuf_delete(&s);
352 }
353
354 static int
sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS)355 sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS)
356 {
357 struct sdhci_slot *slot = arg1;
358 struct sbuf s;
359
360 sbuf_new_for_sysctl(&s, NULL, 1024, req);
361 sbuf_putc(&s, '\n');
362 sdhci_dumpcaps_buf(slot, &s);
363 sbuf_finish(&s);
364 sbuf_delete(&s);
365
366 return (0);
367 }
368
369 static uint32_t
sdhci_tuning_intmask(const struct sdhci_slot * slot)370 sdhci_tuning_intmask(const struct sdhci_slot *slot)
371 {
372 uint32_t intmask;
373
374 intmask = 0;
375 if (slot->opt & SDHCI_TUNING_ENABLED) {
376 intmask |= SDHCI_INT_TUNEERR;
377 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
378 slot->retune_mode == SDHCI_RETUNE_MODE_3)
379 intmask |= SDHCI_INT_RETUNE;
380 }
381 return (intmask);
382 }
383
384 static void
sdhci_init(struct sdhci_slot * slot)385 sdhci_init(struct sdhci_slot *slot)
386 {
387
388 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
389
390 /* Enable interrupts. */
391 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
392 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
393 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
394 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
395 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
396 SDHCI_INT_ACMD12ERR;
397
398 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
399 !(slot->opt & SDHCI_NON_REMOVABLE)) {
400 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
401 }
402
403 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
404 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
405 }
406
407 static void
sdhci_set_clock(struct sdhci_slot * slot,uint32_t clock)408 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
409 {
410 uint32_t clk_base;
411 uint32_t clk_sel;
412 uint32_t res;
413 uint16_t clk;
414 uint16_t div;
415 int timeout;
416
417 if (clock == slot->clock)
418 return;
419 clock = SDHCI_SET_CLOCK(slot->bus, slot, clock);
420 slot->clock = clock;
421
422 /* Turn off the clock. */
423 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
424 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
425 /* If no clock requested - leave it so. */
426 if (clock == 0)
427 return;
428
429 /* Determine the clock base frequency */
430 clk_base = slot->max_clk;
431 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
432 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
433 BCM577XX_CTRL_CLKSEL_MASK;
434
435 /*
436 * Select clock source appropriate for the requested frequency.
437 */
438 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
439 clk_base = BCM577XX_ALT_CLOCK_BASE;
440 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
441 BCM577XX_CTRL_CLKSEL_SHIFT);
442 } else {
443 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
444 BCM577XX_CTRL_CLKSEL_SHIFT);
445 }
446
447 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
448 }
449
450 /* Recalculate timeout clock frequency based on the new sd clock. */
451 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
452 slot->timeout_clk = slot->clock / 1000;
453
454 if (slot->version < SDHCI_SPEC_300) {
455 /* Looking for highest freq <= clock. */
456 res = clk_base;
457 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
458 if (res <= clock)
459 break;
460 res >>= 1;
461 }
462 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
463 div >>= 1;
464 } else {
465 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
466 if (clock >= clk_base)
467 div = 0;
468 else {
469 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
470 if ((clk_base / div) <= clock)
471 break;
472 }
473 }
474 div >>= 1;
475 }
476
477 if (bootverbose || sdhci_debug)
478 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
479 div, clock, clk_base);
480
481 /* Now we have got divider, set it. */
482 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
483 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
484 << SDHCI_DIVIDER_HI_SHIFT;
485
486 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
487 /* Enable clock. */
488 clk |= SDHCI_CLOCK_INT_EN;
489 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
490 /* Wait up to 10 ms until it stabilize. */
491 timeout = 10;
492 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
493 & SDHCI_CLOCK_INT_STABLE)) {
494 if (timeout == 0) {
495 slot_printf(slot,
496 "Internal clock never stabilised.\n");
497 sdhci_dumpregs(slot);
498 return;
499 }
500 timeout--;
501 DELAY(1000);
502 }
503 /* Pass clock signal to the bus. */
504 clk |= SDHCI_CLOCK_CARD_EN;
505 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
506 }
507
508 static void
sdhci_set_power(struct sdhci_slot * slot,u_char power)509 sdhci_set_power(struct sdhci_slot *slot, u_char power)
510 {
511 int i;
512 uint8_t pwr;
513
514 if (slot->power == power)
515 return;
516
517 slot->power = power;
518
519 /* Turn off the power. */
520 pwr = 0;
521 WR1(slot, SDHCI_POWER_CONTROL, pwr);
522 /* If power down requested - leave it so. */
523 if (power == 0)
524 return;
525 /* Set voltage. */
526 switch (1 << power) {
527 case MMC_OCR_LOW_VOLTAGE:
528 pwr |= SDHCI_POWER_180;
529 break;
530 case MMC_OCR_290_300:
531 case MMC_OCR_300_310:
532 pwr |= SDHCI_POWER_300;
533 break;
534 case MMC_OCR_320_330:
535 case MMC_OCR_330_340:
536 pwr |= SDHCI_POWER_330;
537 break;
538 }
539 WR1(slot, SDHCI_POWER_CONTROL, pwr);
540 /*
541 * Turn on VDD1 power. Note that at least some Intel controllers can
542 * fail to enable bus power on the first try after transiting from D3
543 * to D0, so we give them up to 2 ms.
544 */
545 pwr |= SDHCI_POWER_ON;
546 for (i = 0; i < 20; i++) {
547 WR1(slot, SDHCI_POWER_CONTROL, pwr);
548 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
549 break;
550 DELAY(100);
551 }
552 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
553 slot_printf(slot, "Bus power failed to enable\n");
554
555 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
556 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
557 DELAY(10);
558 WR1(slot, SDHCI_POWER_CONTROL, pwr);
559 DELAY(300);
560 }
561 }
562
563 static void
sdhci_read_block_pio(struct sdhci_slot * slot)564 sdhci_read_block_pio(struct sdhci_slot *slot)
565 {
566 uint32_t data;
567 char *buffer;
568 size_t left;
569
570 buffer = slot->curcmd->data->data;
571 buffer += slot->offset;
572 /* Transfer one block at a time. */
573 #ifdef MMCCAM
574 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE)
575 left = min(slot->curcmd->data->block_size,
576 slot->curcmd->data->len - slot->offset);
577 else
578 #endif
579 left = min(512, slot->curcmd->data->len - slot->offset);
580 slot->offset += left;
581
582 /* If we are too fast, broken controllers return zeroes. */
583 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
584 DELAY(10);
585 /* Handle unaligned and aligned buffer cases. */
586 if ((intptr_t)buffer & 3) {
587 while (left > 3) {
588 data = RD4(slot, SDHCI_BUFFER);
589 buffer[0] = data;
590 buffer[1] = (data >> 8);
591 buffer[2] = (data >> 16);
592 buffer[3] = (data >> 24);
593 buffer += 4;
594 left -= 4;
595 }
596 } else {
597 RD_MULTI_4(slot, SDHCI_BUFFER,
598 (uint32_t *)buffer, left >> 2);
599 left &= 3;
600 }
601 /* Handle uneven size case. */
602 if (left > 0) {
603 data = RD4(slot, SDHCI_BUFFER);
604 while (left > 0) {
605 *(buffer++) = data;
606 data >>= 8;
607 left--;
608 }
609 }
610 }
611
612 static void
sdhci_write_block_pio(struct sdhci_slot * slot)613 sdhci_write_block_pio(struct sdhci_slot *slot)
614 {
615 uint32_t data = 0;
616 char *buffer;
617 size_t left;
618
619 buffer = slot->curcmd->data->data;
620 buffer += slot->offset;
621 /* Transfer one block at a time. */
622 #ifdef MMCCAM
623 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) {
624 left = min(slot->curcmd->data->block_size,
625 slot->curcmd->data->len - slot->offset);
626 } else
627 #endif
628 left = min(512, slot->curcmd->data->len - slot->offset);
629 slot->offset += left;
630
631 /* Handle unaligned and aligned buffer cases. */
632 if ((intptr_t)buffer & 3) {
633 while (left > 3) {
634 data = buffer[0] +
635 (buffer[1] << 8) +
636 (buffer[2] << 16) +
637 (buffer[3] << 24);
638 left -= 4;
639 buffer += 4;
640 WR4(slot, SDHCI_BUFFER, data);
641 }
642 } else {
643 WR_MULTI_4(slot, SDHCI_BUFFER,
644 (uint32_t *)buffer, left >> 2);
645 left &= 3;
646 }
647 /* Handle uneven size case. */
648 if (left > 0) {
649 while (left > 0) {
650 data <<= 8;
651 data += *(buffer++);
652 left--;
653 }
654 WR4(slot, SDHCI_BUFFER, data);
655 }
656 }
657
658 static void
sdhci_transfer_pio(struct sdhci_slot * slot)659 sdhci_transfer_pio(struct sdhci_slot *slot)
660 {
661
662 /* Read as many blocks as possible. */
663 if (slot->curcmd->data->flags & MMC_DATA_READ) {
664 while (RD4(slot, SDHCI_PRESENT_STATE) &
665 SDHCI_DATA_AVAILABLE) {
666 sdhci_read_block_pio(slot);
667 if (slot->offset >= slot->curcmd->data->len)
668 break;
669 }
670 } else {
671 while (RD4(slot, SDHCI_PRESENT_STATE) &
672 SDHCI_SPACE_AVAILABLE) {
673 sdhci_write_block_pio(slot);
674 if (slot->offset >= slot->curcmd->data->len)
675 break;
676 }
677 }
678 }
679
680 static void
sdhci_card_task(void * arg,int pending __unused)681 sdhci_card_task(void *arg, int pending __unused)
682 {
683 struct sdhci_slot *slot = arg;
684 #ifndef MMCCAM
685 device_t d;
686 #endif
687
688 SDHCI_LOCK(slot);
689 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
690 #ifdef MMCCAM
691 if (slot->card_present == 0) {
692 #else
693 if (slot->dev == NULL) {
694 #endif
695 /* If card is present - attach mmc bus. */
696 if (bootverbose || sdhci_debug)
697 slot_printf(slot, "Card inserted\n");
698 #ifdef MMCCAM
699 slot->card_present = 1;
700 mmccam_start_discovery(slot->sim);
701 SDHCI_UNLOCK(slot);
702 #else
703 SDHCI_UNLOCK(slot);
704 bus_topo_lock();
705 d = slot->dev = device_add_child(slot->bus, "mmc", DEVICE_UNIT_ANY);
706 if (d) {
707 device_set_ivars(d, slot);
708 (void)device_probe_and_attach(d);
709 }
710 bus_topo_unlock();
711 #endif
712 } else
713 SDHCI_UNLOCK(slot);
714 } else {
715 #ifdef MMCCAM
716 if (slot->card_present == 1) {
717 #else
718 if (slot->dev != NULL) {
719 d = slot->dev;
720 #endif
721 /* If no card present - detach mmc bus. */
722 if (bootverbose || sdhci_debug)
723 slot_printf(slot, "Card removed\n");
724 slot->dev = NULL;
725 #ifdef MMCCAM
726 slot->card_present = 0;
727 mmccam_start_discovery(slot->sim);
728 SDHCI_UNLOCK(slot);
729 #else
730 slot->intmask &= ~sdhci_tuning_intmask(slot);
731 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
732 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
733 slot->opt &= ~SDHCI_TUNING_ENABLED;
734 SDHCI_UNLOCK(slot);
735 callout_drain(&slot->retune_callout);
736 bus_topo_lock();
737 device_delete_child(slot->bus, d);
738 bus_topo_unlock();
739 #endif
740 } else
741 SDHCI_UNLOCK(slot);
742 }
743 }
744
745 static void
746 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
747 {
748 bool was_present;
749
750 /*
751 * If there was no card and now there is one, schedule the task to
752 * create the child device after a short delay. The delay is to
753 * debounce the card insert (sometimes the card detect pin stabilizes
754 * before the other pins have made good contact).
755 *
756 * If there was a card present and now it's gone, immediately schedule
757 * the task to delete the child device. No debouncing -- gone is gone,
758 * because once power is removed, a full card re-init is needed, and
759 * that happens by deleting and recreating the child device.
760 */
761 #ifdef MMCCAM
762 was_present = slot->card_present;
763 #else
764 was_present = slot->dev != NULL;
765 #endif
766 if (!was_present && is_present) {
767 taskqueue_enqueue_timeout(taskqueue_bus,
768 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
769 } else if (was_present && !is_present) {
770 taskqueue_enqueue(taskqueue_bus, &slot->card_task);
771 }
772 }
773
774 void
775 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
776 {
777
778 SDHCI_LOCK(slot);
779 sdhci_handle_card_present_locked(slot, is_present);
780 SDHCI_UNLOCK(slot);
781 }
782
783 static void
784 sdhci_card_poll(void *arg)
785 {
786 struct sdhci_slot *slot = arg;
787
788 sdhci_handle_card_present(slot,
789 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
790 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
791 sdhci_card_poll, slot);
792 }
793
794 static int
795 sdhci_dma_alloc(struct sdhci_slot *slot)
796 {
797 int err;
798
799 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
800 if (maxphys <= 1024 * 4)
801 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
802 else if (maxphys <= 1024 * 8)
803 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
804 else if (maxphys <= 1024 * 16)
805 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
806 else if (maxphys <= 1024 * 32)
807 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
808 else if (maxphys <= 1024 * 64)
809 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
810 else if (maxphys <= 1024 * 128)
811 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
812 else if (maxphys <= 1024 * 256)
813 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
814 else
815 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
816 }
817 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
818
819 /*
820 * Allocate the DMA tag for an SDMA bounce buffer.
821 * Note that the SDHCI specification doesn't state any alignment
822 * constraint for the SDMA system address. However, controllers
823 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when
824 * forming the actual address of data, requiring the SDMA buffer to
825 * be aligned to the SDMA boundary.
826 */
827 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
828 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
829 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
830 NULL, NULL, &slot->dmatag);
831 if (err != 0) {
832 slot_printf(slot, "Can't create DMA tag for SDMA\n");
833 return (err);
834 }
835 /* Allocate DMA memory for the SDMA bounce buffer. */
836 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
837 BUS_DMA_NOWAIT, &slot->dmamap);
838 if (err != 0) {
839 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
840 bus_dma_tag_destroy(slot->dmatag);
841 return (err);
842 }
843 /* Map the memory of the SDMA bounce buffer. */
844 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
845 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
846 &slot->paddr, 0);
847 if (err != 0 || slot->paddr == 0) {
848 slot_printf(slot, "Can't load DMA memory for SDMA\n");
849 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
850 bus_dma_tag_destroy(slot->dmatag);
851 if (err)
852 return (err);
853 else
854 return (EFAULT);
855 }
856
857 return (0);
858 }
859
860 static void
861 sdhci_dma_free(struct sdhci_slot *slot)
862 {
863
864 bus_dmamap_unload(slot->dmatag, slot->dmamap);
865 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
866 bus_dma_tag_destroy(slot->dmatag);
867 }
868
869 int
870 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
871 {
872 kobjop_desc_t kobj_desc;
873 kobj_method_t *kobj_method;
874 uint32_t caps, caps2, freq, host_caps;
875 int err;
876 char node_name[8];
877 struct sysctl_oid *node_oid;
878
879 SDHCI_LOCK_INIT(slot);
880
881 slot->num = num;
882 slot->bus = dev;
883
884 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
885 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
886 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
887 caps = slot->caps;
888 caps2 = slot->caps2;
889 } else {
890 caps = RD4(slot, SDHCI_CAPABILITIES);
891 if (slot->version >= SDHCI_SPEC_300)
892 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
893 else
894 caps2 = 0;
895 }
896 if (slot->version >= SDHCI_SPEC_300) {
897 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
898 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
899 slot_printf(slot,
900 "Driver doesn't support shared bus slots\n");
901 SDHCI_LOCK_DESTROY(slot);
902 return (ENXIO);
903 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
904 SDHCI_SLOTTYPE_EMBEDDED) {
905 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
906 }
907 }
908 /* Calculate base clock frequency. */
909 if (slot->version >= SDHCI_SPEC_300)
910 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
911 SDHCI_CLOCK_BASE_SHIFT;
912 else
913 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
914 SDHCI_CLOCK_BASE_SHIFT;
915 if (freq != 0)
916 slot->max_clk = freq * 1000000;
917 /*
918 * If the frequency wasn't in the capabilities and the hardware driver
919 * hasn't already set max_clk we're probably not going to work right
920 * with an assumption, so complain about it.
921 */
922 if (slot->max_clk == 0) {
923 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
924 slot_printf(slot, "Hardware doesn't specify base clock "
925 "frequency, using %dMHz as default.\n",
926 SDHCI_DEFAULT_MAX_FREQ);
927 }
928 /* Calculate/set timeout clock frequency. */
929 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
930 slot->timeout_clk = slot->max_clk / 1000;
931 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
932 slot->timeout_clk = 1000;
933 } else {
934 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
935 SDHCI_TIMEOUT_CLK_SHIFT;
936 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
937 slot->timeout_clk *= 1000;
938 }
939 /*
940 * If the frequency wasn't in the capabilities and the hardware driver
941 * hasn't already set timeout_clk we'll probably work okay using the
942 * max timeout, but still mention it.
943 */
944 if (slot->timeout_clk == 0) {
945 slot_printf(slot, "Hardware doesn't specify timeout clock "
946 "frequency, setting BROKEN_TIMEOUT quirk.\n");
947 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
948 }
949
950 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
951 slot->host.f_max = slot->max_clk;
952 slot->host.host_ocr = 0;
953 if (caps & SDHCI_CAN_VDD_330)
954 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
955 if (caps & SDHCI_CAN_VDD_300)
956 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
957 /*
958 * 1.8V VDD is not supposed to be used for removable cards. Hardware
959 * prior to v3.0 had no way to indicate embedded slots, but did
960 * sometimes support 1.8v for non-removable devices.
961 */
962 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 ||
963 (slot->opt & SDHCI_SLOT_EMBEDDED)))
964 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
965 if (slot->host.host_ocr == 0) {
966 slot_printf(slot, "Hardware doesn't report any "
967 "support voltages.\n");
968 }
969
970 host_caps = slot->host.caps;
971 host_caps |= MMC_CAP_4_BIT_DATA;
972 if (caps & SDHCI_CAN_DO_8BITBUS)
973 host_caps |= MMC_CAP_8_BIT_DATA;
974 if (caps & SDHCI_CAN_DO_HISPD)
975 host_caps |= MMC_CAP_HSPEED;
976 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
977 host_caps |= MMC_CAP_BOOT_NOACC;
978 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
979 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
980
981 /* Determine supported UHS-I and eMMC modes. */
982 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
983 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
984 if (caps2 & SDHCI_CAN_SDR104) {
985 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
986 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
987 host_caps |= MMC_CAP_MMC_HS200;
988 } else if (caps2 & SDHCI_CAN_SDR50)
989 host_caps |= MMC_CAP_UHS_SDR50;
990 if (caps2 & SDHCI_CAN_DDR50 &&
991 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
992 host_caps |= MMC_CAP_UHS_DDR50;
993 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
994 host_caps |= MMC_CAP_MMC_DDR52;
995 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
996 caps2 & SDHCI_CAN_MMC_HS400)
997 host_caps |= MMC_CAP_MMC_HS400;
998 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
999 caps2 & SDHCI_CAN_SDR104)
1000 host_caps |= MMC_CAP_MMC_HS400;
1001
1002 /*
1003 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
1004 * default NULL implementation.
1005 */
1006 kobj_desc = &sdhci_set_uhs_timing_desc;
1007 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1008 kobj_desc);
1009 if (kobj_method == &kobj_desc->deflt)
1010 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1011 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1012 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
1013
1014 #define SDHCI_CAP_MODES_TUNING(caps2) \
1015 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
1016 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
1017 MMC_CAP_MMC_HS400)
1018
1019 /*
1020 * Disable UHS-I and eMMC modes that require (re-)tuning if either
1021 * the tune or re-tune method is the default NULL implementation.
1022 */
1023 kobj_desc = &mmcbr_tune_desc;
1024 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1025 kobj_desc);
1026 if (kobj_method == &kobj_desc->deflt)
1027 goto no_tuning;
1028 kobj_desc = &mmcbr_retune_desc;
1029 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1030 kobj_desc);
1031 if (kobj_method == &kobj_desc->deflt) {
1032 no_tuning:
1033 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
1034 }
1035
1036 /* Allocate tuning structures and determine tuning parameters. */
1037 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
1038 slot->opt |= SDHCI_TUNING_SUPPORTED;
1039 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
1040 M_WAITOK);
1041 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
1042 M_WAITOK);
1043 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
1044 M_WAITOK);
1045 if (caps2 & SDHCI_TUNE_SDR50)
1046 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
1047 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
1048 SDHCI_RETUNE_MODES_SHIFT;
1049 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
1050 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
1051 SDHCI_RETUNE_CNT_SHIFT;
1052 if (slot->retune_count > 0xb) {
1053 slot_printf(slot, "Unknown re-tuning count "
1054 "%x, using 1 sec\n", slot->retune_count);
1055 slot->retune_count = 1;
1056 } else if (slot->retune_count != 0)
1057 slot->retune_count =
1058 1 << (slot->retune_count - 1);
1059 }
1060 }
1061
1062 #undef SDHCI_CAP_MODES_TUNING
1063
1064 /* Determine supported VCCQ signaling levels. */
1065 host_caps |= MMC_CAP_SIGNALING_330;
1066 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1067 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1068 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
1069 MMC_CAP_MMC_HS400_180))
1070 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
1071
1072 /*
1073 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
1074 * default NULL implementation. Disable 1.2 V support if it's the
1075 * generic SDHCI implementation.
1076 */
1077 kobj_desc = &mmcbr_switch_vccq_desc;
1078 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1079 kobj_desc);
1080 if (kobj_method == &kobj_desc->deflt)
1081 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
1082 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
1083 host_caps &= ~MMC_CAP_SIGNALING_120;
1084
1085 /* Determine supported driver types (type B is always mandatory). */
1086 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
1087 host_caps |= MMC_CAP_DRIVER_TYPE_A;
1088 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
1089 host_caps |= MMC_CAP_DRIVER_TYPE_C;
1090 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
1091 host_caps |= MMC_CAP_DRIVER_TYPE_D;
1092 slot->host.caps = host_caps;
1093
1094 /* Decide if we have usable DMA. */
1095 if (caps & SDHCI_CAN_DO_DMA)
1096 slot->opt |= SDHCI_HAVE_DMA;
1097
1098 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
1099 slot->opt &= ~SDHCI_HAVE_DMA;
1100 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
1101 slot->opt |= SDHCI_HAVE_DMA;
1102 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
1103 slot->opt |= SDHCI_NON_REMOVABLE;
1104
1105 /*
1106 * Use platform-provided transfer backend
1107 * with PIO as a fallback mechanism
1108 */
1109 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
1110 slot->opt &= ~SDHCI_HAVE_DMA;
1111
1112 if (slot->opt & SDHCI_HAVE_DMA) {
1113 err = sdhci_dma_alloc(slot);
1114 if (err != 0) {
1115 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1116 free(slot->tune_req, M_DEVBUF);
1117 free(slot->tune_cmd, M_DEVBUF);
1118 free(slot->tune_data, M_DEVBUF);
1119 }
1120 SDHCI_LOCK_DESTROY(slot);
1121 return (err);
1122 }
1123 }
1124
1125 if (bootverbose || sdhci_debug) {
1126 sdhci_dumpcaps(slot);
1127 sdhci_dumpregs(slot);
1128 }
1129
1130 slot->timeout = 10;
1131 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1132 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1133 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0,
1134 "Maximum timeout for SDHCI transfers (in secs)");
1135 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1136 TIMEOUT_TASK_INIT(taskqueue_bus, &slot->card_delayed_task, 0,
1137 sdhci_card_task, slot);
1138 callout_init(&slot->card_poll_callout, 1);
1139 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1140 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1141
1142 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1143 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1144 callout_reset(&slot->card_poll_callout,
1145 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1146 }
1147
1148 sdhci_init(slot);
1149
1150 snprintf(node_name, sizeof(node_name), "slot%d", slot->num);
1151
1152 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev),
1153 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1154 OID_AUTO, node_name, CTLFLAG_RW, 0, "slot specific node");
1155
1156 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1157 OID_AUTO, "quirks", CTLFLAG_RD, &slot->quirks, 0, "Slot quirks");
1158
1159 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev),
1160 SYSCTL_CHILDREN(node_oid), OID_AUTO, "debug", CTLFLAG_RW, 0,
1161 "Debugging node");
1162
1163 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1164 OID_AUTO, "dumpregs", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1165 slot, 0, &sdhci_syctl_dumpregs,
1166 "A", "Dump SDHCI registers");
1167
1168 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1169 OID_AUTO, "dumpcaps", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1170 slot, 0, &sdhci_syctl_dumpcaps,
1171 "A", "Dump SDHCI capabilites");
1172
1173 return (0);
1174 }
1175
1176 #ifndef MMCCAM
1177 void
1178 sdhci_start_slot(struct sdhci_slot *slot)
1179 {
1180
1181 sdhci_card_task(slot, 0);
1182 }
1183 #endif
1184
1185 int
1186 sdhci_cleanup_slot(struct sdhci_slot *slot)
1187 {
1188 device_t d;
1189
1190 callout_drain(&slot->timeout_callout);
1191 callout_drain(&slot->card_poll_callout);
1192 callout_drain(&slot->retune_callout);
1193 taskqueue_drain(taskqueue_bus, &slot->card_task);
1194 taskqueue_drain_timeout(taskqueue_bus, &slot->card_delayed_task);
1195
1196 SDHCI_LOCK(slot);
1197 d = slot->dev;
1198 slot->dev = NULL;
1199 SDHCI_UNLOCK(slot);
1200 if (d != NULL)
1201 device_delete_child(slot->bus, d);
1202
1203 SDHCI_LOCK(slot);
1204 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1205 SDHCI_UNLOCK(slot);
1206 if (slot->opt & SDHCI_HAVE_DMA)
1207 sdhci_dma_free(slot);
1208 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1209 free(slot->tune_req, M_DEVBUF);
1210 free(slot->tune_cmd, M_DEVBUF);
1211 free(slot->tune_data, M_DEVBUF);
1212 }
1213
1214 SDHCI_LOCK_DESTROY(slot);
1215
1216 return (0);
1217 }
1218
1219 int
1220 sdhci_generic_suspend(struct sdhci_slot *slot)
1221 {
1222
1223 /*
1224 * We expect the MMC layer to issue initial tuning after resume.
1225 * Otherwise, we'd need to indicate re-tuning including circuit reset
1226 * being required at least for re-tuning modes 1 and 2 ourselves.
1227 */
1228 callout_drain(&slot->retune_callout);
1229 SDHCI_LOCK(slot);
1230 slot->opt &= ~SDHCI_TUNING_ENABLED;
1231 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1232 SDHCI_UNLOCK(slot);
1233
1234 return (0);
1235 }
1236
1237 int
1238 sdhci_generic_resume(struct sdhci_slot *slot)
1239 {
1240
1241 SDHCI_LOCK(slot);
1242 sdhci_init(slot);
1243 SDHCI_UNLOCK(slot);
1244
1245 return (0);
1246 }
1247
1248 void
1249 sdhci_generic_reset(device_t brdev __unused, struct sdhci_slot *slot,
1250 uint8_t mask)
1251 {
1252 int timeout;
1253 uint32_t clock;
1254
1255 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
1256 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
1257 return;
1258 }
1259
1260 /* Some controllers need this kick or reset won't work. */
1261 if ((mask & SDHCI_RESET_ALL) == 0 &&
1262 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
1263 /* This is to force an update */
1264 clock = slot->clock;
1265 slot->clock = 0;
1266 sdhci_set_clock(slot, clock);
1267 }
1268
1269 if (mask & SDHCI_RESET_ALL) {
1270 slot->clock = 0;
1271 slot->power = 0;
1272 }
1273
1274 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
1275
1276 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
1277 /*
1278 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
1279 * specification. The reset bit has internal propagation delay,
1280 * so a fast read after write returns 0 even if reset process is
1281 * in progress. The workaround is to poll for 1 before polling
1282 * for 0. In the worst case, if we miss seeing it asserted the
1283 * time we spent waiting is enough to ensure the reset finishes.
1284 */
1285 timeout = 10000;
1286 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
1287 if (timeout <= 0)
1288 break;
1289 timeout--;
1290 DELAY(1);
1291 }
1292 }
1293
1294 /* Wait max 100 ms */
1295 timeout = 10000;
1296 /* Controller clears the bits when it's done */
1297 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
1298 if (timeout <= 0) {
1299 slot_printf(slot, "Reset 0x%x never completed.\n",
1300 mask);
1301 sdhci_dumpregs(slot);
1302 return;
1303 }
1304 timeout--;
1305 DELAY(10);
1306 }
1307 }
1308
1309 uint32_t
1310 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1311 {
1312
1313 if (slot->version >= SDHCI_SPEC_300)
1314 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1315 else
1316 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1317 }
1318
1319 bool
1320 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1321 {
1322
1323 if (slot->opt & SDHCI_NON_REMOVABLE)
1324 return true;
1325
1326 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1327 }
1328
1329 void
1330 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1331 {
1332 const struct mmc_ios *ios;
1333 uint16_t hostctrl2;
1334
1335 if (slot->version < SDHCI_SPEC_300)
1336 return;
1337
1338 SDHCI_ASSERT_LOCKED(slot);
1339 ios = &slot->host.ios;
1340 sdhci_set_clock(slot, 0);
1341 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1342 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1343 if (ios->clock > SD_SDR50_MAX) {
1344 if (ios->timing == bus_timing_mmc_hs400 ||
1345 ios->timing == bus_timing_mmc_hs400es)
1346 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1347 else
1348 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1349 }
1350 else if (ios->clock > SD_SDR25_MAX)
1351 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1352 else if (ios->clock > SD_SDR12_MAX) {
1353 if (ios->timing == bus_timing_uhs_ddr50 ||
1354 ios->timing == bus_timing_mmc_ddr52)
1355 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1356 else
1357 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1358 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1359 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1360 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1361 sdhci_set_clock(slot, ios->clock);
1362 }
1363
1364 int
1365 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1366 {
1367 struct sdhci_slot *slot = device_get_ivars(reqdev);
1368 struct mmc_ios *ios = &slot->host.ios;
1369
1370 SDHCI_LOCK(slot);
1371 /* Do full reset on bus power down to clear from any state. */
1372 if (ios->power_mode == power_off) {
1373 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1374 sdhci_init(slot);
1375 }
1376 /* Configure the bus. */
1377 sdhci_set_clock(slot, ios->clock);
1378 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1379 if (ios->bus_width == bus_width_8) {
1380 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1381 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1382 } else if (ios->bus_width == bus_width_4) {
1383 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1384 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1385 } else if (ios->bus_width == bus_width_1) {
1386 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1387 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1388 } else {
1389 panic("Invalid bus width: %d", ios->bus_width);
1390 }
1391 if (ios->clock > SD_SDR12_MAX &&
1392 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1393 slot->hostctrl |= SDHCI_CTRL_HISPD;
1394 else
1395 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1396 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1397 SDHCI_SET_UHS_TIMING(brdev, slot);
1398 /* Some controllers like reset after bus changes. */
1399 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1400 SDHCI_RESET(slot->bus, slot,
1401 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1402
1403 SDHCI_UNLOCK(slot);
1404 return (0);
1405 }
1406
1407 int
1408 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1409 {
1410 struct sdhci_slot *slot = device_get_ivars(reqdev);
1411 enum mmc_vccq vccq;
1412 int err;
1413 uint16_t hostctrl2;
1414
1415 if (slot->version < SDHCI_SPEC_300)
1416 return (0);
1417
1418 err = 0;
1419 vccq = slot->host.ios.vccq;
1420 SDHCI_LOCK(slot);
1421 sdhci_set_clock(slot, 0);
1422 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1423 switch (vccq) {
1424 case vccq_330:
1425 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1426 goto done;
1427 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1428 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1429 DELAY(5000);
1430 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1431 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1432 goto done;
1433 err = EAGAIN;
1434 break;
1435 case vccq_180:
1436 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1437 err = EINVAL;
1438 goto done;
1439 }
1440 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1441 goto done;
1442 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1443 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1444 DELAY(5000);
1445 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1446 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1447 goto done;
1448 err = EAGAIN;
1449 break;
1450 default:
1451 slot_printf(slot,
1452 "Attempt to set unsupported signaling voltage\n");
1453 err = EINVAL;
1454 break;
1455 }
1456 done:
1457 sdhci_set_clock(slot, slot->host.ios.clock);
1458 SDHCI_UNLOCK(slot);
1459 return (err);
1460 }
1461
1462 int
1463 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1464 {
1465 struct sdhci_slot *slot = device_get_ivars(reqdev);
1466 const struct mmc_ios *ios = &slot->host.ios;
1467 struct mmc_command *tune_cmd;
1468 struct mmc_data *tune_data;
1469 uint32_t opcode;
1470 int err;
1471
1472 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1473 return (0);
1474
1475 slot->retune_ticks = slot->retune_count * hz;
1476 opcode = MMC_SEND_TUNING_BLOCK;
1477 SDHCI_LOCK(slot);
1478 switch (ios->timing) {
1479 case bus_timing_mmc_hs400:
1480 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1481 SDHCI_UNLOCK(slot);
1482 return (EINVAL);
1483 case bus_timing_mmc_hs200:
1484 /*
1485 * In HS400 mode, controllers use the data strobe line to
1486 * latch data from the devices so periodic re-tuning isn't
1487 * expected to be required.
1488 */
1489 if (hs400)
1490 slot->retune_ticks = 0;
1491 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1492 break;
1493 case bus_timing_uhs_ddr50:
1494 case bus_timing_uhs_sdr104:
1495 break;
1496 case bus_timing_uhs_sdr50:
1497 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1498 break;
1499 SDHCI_UNLOCK(slot);
1500 return (0);
1501 default:
1502 slot_printf(slot, "Tuning requested but not required.\n");
1503 SDHCI_UNLOCK(slot);
1504 return (EINVAL);
1505 }
1506
1507 tune_cmd = slot->tune_cmd;
1508 memset(tune_cmd, 0, sizeof(*tune_cmd));
1509 tune_cmd->opcode = opcode;
1510 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1511 tune_data = tune_cmd->data = slot->tune_data;
1512 memset(tune_data, 0, sizeof(*tune_data));
1513 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1514 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1515 MMC_TUNING_LEN;
1516 tune_data->flags = MMC_DATA_READ;
1517 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1518
1519 slot->opt &= ~SDHCI_TUNING_ENABLED;
1520 err = sdhci_exec_tuning(slot, true);
1521 if (err == 0) {
1522 slot->opt |= SDHCI_TUNING_ENABLED;
1523 slot->intmask |= sdhci_tuning_intmask(slot);
1524 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1525 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1526 if (slot->retune_ticks) {
1527 callout_reset(&slot->retune_callout, slot->retune_ticks,
1528 sdhci_retune, slot);
1529 }
1530 }
1531 SDHCI_UNLOCK(slot);
1532 return (err);
1533 }
1534
1535 int
1536 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1537 {
1538 struct sdhci_slot *slot = device_get_ivars(reqdev);
1539 int err;
1540
1541 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1542 return (0);
1543
1544 /* HS400 must be tuned in HS200 mode. */
1545 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1546 return (EINVAL);
1547
1548 SDHCI_LOCK(slot);
1549 err = sdhci_exec_tuning(slot, reset);
1550 /*
1551 * There are two ways sdhci_exec_tuning() can fail:
1552 * EBUSY should not actually happen when requests are only issued
1553 * with the host properly acquired, and
1554 * EIO re-tuning failed (but it did work initially).
1555 *
1556 * In both cases, we should retry at later point if periodic re-tuning
1557 * is enabled. Note that due to slot->retune_req not being cleared in
1558 * these failure cases, the MMC layer should trigger another attempt at
1559 * re-tuning with the next request anyway, though.
1560 */
1561 if (slot->retune_ticks) {
1562 callout_reset(&slot->retune_callout, slot->retune_ticks,
1563 sdhci_retune, slot);
1564 }
1565 SDHCI_UNLOCK(slot);
1566 return (err);
1567 }
1568
1569 static int
1570 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1571 {
1572 struct mmc_request *tune_req;
1573 struct mmc_command *tune_cmd;
1574 int i;
1575 uint32_t intmask;
1576 uint16_t hostctrl2;
1577 u_char opt;
1578
1579 SDHCI_ASSERT_LOCKED(slot);
1580 if (slot->req != NULL)
1581 return (EBUSY);
1582
1583 /* Tuning doesn't work with DMA enabled. */
1584 opt = slot->opt;
1585 slot->opt = opt & ~SDHCI_HAVE_DMA;
1586
1587 /*
1588 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1589 * kind of interrupt we receive in response to a tuning request.
1590 */
1591 intmask = slot->intmask;
1592 slot->intmask = SDHCI_INT_DATA_AVAIL;
1593 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1594 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1595
1596 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1597 if (reset)
1598 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1599 else
1600 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1601 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1602
1603 tune_req = slot->tune_req;
1604 tune_cmd = slot->tune_cmd;
1605 for (i = 0; i < MMC_TUNING_MAX; i++) {
1606 memset(tune_req, 0, sizeof(*tune_req));
1607 tune_req->cmd = tune_cmd;
1608 tune_req->done = sdhci_req_wakeup;
1609 tune_req->done_data = slot;
1610 slot->req = tune_req;
1611 slot->flags = 0;
1612 sdhci_start(slot);
1613 while (!(tune_req->flags & MMC_REQ_DONE))
1614 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1615 if (!(tune_req->flags & MMC_TUNE_DONE))
1616 break;
1617 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1618 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1619 break;
1620 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1621 DELAY(1000);
1622 }
1623
1624 /*
1625 * Restore DMA usage and interrupts.
1626 * Note that the interrupt aggregation code might have cleared
1627 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1628 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1629 * doesn't lose these.
1630 */
1631 slot->opt = opt;
1632 slot->intmask = intmask;
1633 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1634 SDHCI_INT_RESPONSE);
1635 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1636
1637 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1638 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1639 slot->retune_req = 0;
1640 return (0);
1641 }
1642
1643 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1644 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1645 SDHCI_CTRL2_SAMPLING_CLOCK));
1646 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1647 return (EIO);
1648 }
1649
1650 static void
1651 sdhci_retune(void *arg)
1652 {
1653 struct sdhci_slot *slot = arg;
1654
1655 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1656 }
1657
1658 #ifdef MMCCAM
1659 static void
1660 sdhci_req_done(struct sdhci_slot *slot)
1661 {
1662 union ccb *ccb;
1663
1664 if (__predict_false(sdhci_debug > 1))
1665 slot_printf(slot, "%s\n", __func__);
1666 if (slot->ccb != NULL && slot->curcmd != NULL) {
1667 callout_stop(&slot->timeout_callout);
1668 ccb = slot->ccb;
1669 slot->ccb = NULL;
1670 slot->curcmd = NULL;
1671
1672 /* Tell CAM the request is finished */
1673 struct ccb_mmcio *mmcio;
1674 mmcio = &ccb->mmcio;
1675
1676 ccb->ccb_h.status =
1677 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1678 xpt_done(ccb);
1679 }
1680 }
1681 #else
1682 static void
1683 sdhci_req_done(struct sdhci_slot *slot)
1684 {
1685 struct mmc_request *req;
1686
1687 if (slot->req != NULL && slot->curcmd != NULL) {
1688 callout_stop(&slot->timeout_callout);
1689 req = slot->req;
1690 slot->req = NULL;
1691 slot->curcmd = NULL;
1692 req->done(req);
1693 }
1694 }
1695 #endif
1696
1697 static void
1698 sdhci_req_wakeup(struct mmc_request *req)
1699 {
1700
1701 req->flags |= MMC_REQ_DONE;
1702 wakeup(req);
1703 }
1704
1705 static void
1706 sdhci_timeout(void *arg)
1707 {
1708 struct sdhci_slot *slot = arg;
1709
1710 if (slot->curcmd != NULL) {
1711 slot_printf(slot, "Controller timeout\n");
1712 sdhci_dumpregs(slot);
1713 SDHCI_RESET(slot->bus, slot,
1714 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1715 slot->curcmd->error = MMC_ERR_TIMEOUT;
1716 sdhci_req_done(slot);
1717 } else {
1718 slot_printf(slot, "Spurious timeout - no active command\n");
1719 }
1720 }
1721
1722 static void
1723 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data)
1724 {
1725 uint16_t mode;
1726
1727 if (data == NULL)
1728 return;
1729
1730 mode = SDHCI_TRNS_BLK_CNT_EN;
1731 if (data->len > 512 || data->block_count > 1) {
1732 mode |= SDHCI_TRNS_MULTI;
1733 if (data->block_count == 0 && __predict_true(
1734 #ifdef MMCCAM
1735 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION &&
1736 #else
1737 slot->req->stop != NULL &&
1738 #endif
1739 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1740 mode |= SDHCI_TRNS_ACMD12;
1741 }
1742 if (data->flags & MMC_DATA_READ)
1743 mode |= SDHCI_TRNS_READ;
1744 if (slot->flags & SDHCI_USE_DMA)
1745 mode |= SDHCI_TRNS_DMA;
1746
1747 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1748 }
1749
1750 static void
1751 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1752 {
1753 int flags, timeout;
1754 uint32_t mask;
1755
1756 slot->curcmd = cmd;
1757 slot->cmd_done = 0;
1758
1759 cmd->error = MMC_ERR_NONE;
1760
1761 /* This flags combination is not supported by controller. */
1762 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1763 slot_printf(slot, "Unsupported response type!\n");
1764 cmd->error = MMC_ERR_FAILED;
1765 sdhci_req_done(slot);
1766 return;
1767 }
1768
1769 /*
1770 * Do not issue command if there is no card, clock or power.
1771 * Controller will not detect timeout without clock active.
1772 */
1773 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1774 slot->power == 0 ||
1775 slot->clock == 0) {
1776 slot_printf(slot,
1777 "Cannot issue a command (power=%d clock=%d)\n",
1778 slot->power, slot->clock);
1779 cmd->error = MMC_ERR_FAILED;
1780 sdhci_req_done(slot);
1781 return;
1782 }
1783 /* Always wait for free CMD bus. */
1784 mask = SDHCI_CMD_INHIBIT;
1785 /* Wait for free DAT if we have data or busy signal. */
1786 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1787 mask |= SDHCI_DAT_INHIBIT;
1788 /*
1789 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1790 * that these latter are also special in that SDHCI_CMD_DATA should
1791 * be set below but no actual data is ever read from the controller.
1792 */
1793 #ifdef MMCCAM
1794 if (cmd == &slot->ccb->mmcio.stop ||
1795 #else
1796 if (cmd == slot->req->stop ||
1797 #endif
1798 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1799 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1800 mask &= ~SDHCI_DAT_INHIBIT;
1801 /*
1802 * Wait for bus no more then 250 ms. Typically there will be no wait
1803 * here at all, but when writing a crash dump we may be bypassing the
1804 * host platform's interrupt handler, and in some cases that handler
1805 * may be working around hardware quirks such as not respecting r1b
1806 * busy indications. In those cases, this wait-loop serves the purpose
1807 * of waiting for the prior command and data transfers to be done, and
1808 * SD cards are allowed to take up to 250ms for write and erase ops.
1809 * (It's usually more like 20-30ms in the real world.)
1810 */
1811 timeout = 250;
1812 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1813 if (timeout == 0) {
1814 slot_printf(slot, "Controller never released "
1815 "inhibit bit(s).\n");
1816 sdhci_dumpregs(slot);
1817 cmd->error = MMC_ERR_FAILED;
1818 sdhci_req_done(slot);
1819 return;
1820 }
1821 timeout--;
1822 DELAY(1000);
1823 }
1824
1825 /* Prepare command flags. */
1826 if (!(cmd->flags & MMC_RSP_PRESENT))
1827 flags = SDHCI_CMD_RESP_NONE;
1828 else if (cmd->flags & MMC_RSP_136)
1829 flags = SDHCI_CMD_RESP_LONG;
1830 else if (cmd->flags & MMC_RSP_BUSY)
1831 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1832 else
1833 flags = SDHCI_CMD_RESP_SHORT;
1834 if (cmd->flags & MMC_RSP_CRC)
1835 flags |= SDHCI_CMD_CRC;
1836 if (cmd->flags & MMC_RSP_OPCODE)
1837 flags |= SDHCI_CMD_INDEX;
1838 if (cmd->data != NULL)
1839 flags |= SDHCI_CMD_DATA;
1840 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1841 flags |= SDHCI_CMD_TYPE_ABORT;
1842 /* Prepare data. */
1843 sdhci_start_data(slot, cmd->data);
1844 /*
1845 * Interrupt aggregation: To reduce total number of interrupts
1846 * group response interrupt with data interrupt when possible.
1847 * If there going to be data interrupt, mask response one.
1848 */
1849 if (slot->data_done == 0) {
1850 WR4(slot, SDHCI_SIGNAL_ENABLE,
1851 slot->intmask &= ~SDHCI_INT_RESPONSE);
1852 }
1853 /* Set command argument. */
1854 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1855 /* Set data transfer mode. */
1856 sdhci_set_transfer_mode(slot, cmd->data);
1857 if (__predict_false(sdhci_debug > 1))
1858 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n",
1859 cmd->opcode, flags);
1860
1861 /* Start command. */
1862 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1863 /* Start timeout callout. */
1864 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1865 sdhci_timeout, slot);
1866 }
1867
1868 static void
1869 sdhci_finish_command(struct sdhci_slot *slot)
1870 {
1871 int i;
1872 uint32_t val;
1873 uint8_t extra;
1874
1875 if (__predict_false(sdhci_debug > 1))
1876 slot_printf(slot, "%s: called, err %d flags %#04x\n",
1877 __func__, slot->curcmd->error, slot->curcmd->flags);
1878 slot->cmd_done = 1;
1879 /*
1880 * Interrupt aggregation: Restore command interrupt.
1881 * Main restore point for the case when command interrupt
1882 * happened first.
1883 */
1884 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1885 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1886 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1887 SDHCI_INT_RESPONSE);
1888 /* In case of error - reset host and return. */
1889 if (slot->curcmd->error) {
1890 if (slot->curcmd->error == MMC_ERR_BADCRC)
1891 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1892 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
1893 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
1894 sdhci_start(slot);
1895 return;
1896 }
1897 /* If command has response - fetch it. */
1898 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1899 if (slot->curcmd->flags & MMC_RSP_136) {
1900 /* CRC is stripped so we need one byte shift. */
1901 extra = 0;
1902 for (i = 0; i < 4; i++) {
1903 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1904 if (slot->quirks &
1905 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1906 slot->curcmd->resp[3 - i] = val;
1907 else {
1908 slot->curcmd->resp[3 - i] =
1909 (val << 8) | extra;
1910 extra = val >> 24;
1911 }
1912 }
1913 } else
1914 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1915 }
1916 if (__predict_false(sdhci_debug > 1))
1917 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n",
1918 slot->curcmd->resp[0], slot->curcmd->resp[1],
1919 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1920
1921 /* If data ready - finish. */
1922 if (slot->data_done)
1923 sdhci_start(slot);
1924 }
1925
1926 static void
1927 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data)
1928 {
1929 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout;
1930 uint8_t div;
1931
1932 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1933 slot->data_done = 1;
1934 return;
1935 }
1936
1937 slot->data_done = 0;
1938
1939 /* Calculate and set data timeout.*/
1940 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1941 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1942 div = 0xE;
1943 } else {
1944 target_timeout = 1000000;
1945 div = 0;
1946 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1947 while (current_timeout < target_timeout && div < 0xE) {
1948 ++div;
1949 current_timeout <<= 1;
1950 }
1951 /* Compensate for an off-by-one error in the CaFe chip.*/
1952 if (div < 0xE &&
1953 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1954 ++div;
1955 }
1956 }
1957 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1958
1959 if (data == NULL)
1960 return;
1961
1962 /* Use DMA if possible. */
1963 if ((slot->opt & SDHCI_HAVE_DMA))
1964 slot->flags |= SDHCI_USE_DMA;
1965 /* If data is small, broken DMA may return zeroes instead of data. */
1966 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1967 (data->len <= 512))
1968 slot->flags &= ~SDHCI_USE_DMA;
1969 /* Some controllers require even block sizes. */
1970 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1971 ((data->len) & 0x3))
1972 slot->flags &= ~SDHCI_USE_DMA;
1973 /* Load DMA buffer. */
1974 if (slot->flags & SDHCI_USE_DMA) {
1975 sdma_bbufsz = slot->sdma_bbufsz;
1976 if (data->flags & MMC_DATA_READ)
1977 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1978 BUS_DMASYNC_PREREAD);
1979 else {
1980 memcpy(slot->dmamem, data->data, ulmin(data->len,
1981 sdma_bbufsz));
1982 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1983 BUS_DMASYNC_PREWRITE);
1984 }
1985 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1986 /*
1987 * Interrupt aggregation: Mask border interrupt for the last
1988 * bounce buffer and unmask otherwise.
1989 */
1990 if (data->len == sdma_bbufsz)
1991 slot->intmask &= ~SDHCI_INT_DMA_END;
1992 else
1993 slot->intmask |= SDHCI_INT_DMA_END;
1994 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1995 }
1996 /* Current data offset for both PIO and DMA. */
1997 slot->offset = 0;
1998 #ifdef MMCCAM
1999 if (data->flags & MMC_DATA_BLOCK_SIZE) {
2000 /* Set block size and request border interrupts on the SDMA boundary. */
2001 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size);
2002 blkcnt = data->block_count;
2003 if (__predict_false(sdhci_debug > 0))
2004 slot_printf(slot, "SDIO Custom block params: blksz: "
2005 "%#10x, blk cnt: %#10x\n", blksz, blkcnt);
2006 } else
2007 #endif
2008 {
2009 /* Set block size and request border interrupts on the SDMA boundary. */
2010 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
2011 blkcnt = howmany(data->len, 512);
2012 }
2013
2014 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
2015 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
2016 if (__predict_false(sdhci_debug > 1))
2017 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
2018 blksz, blkcnt);
2019 }
2020
2021 void
2022 sdhci_finish_data(struct sdhci_slot *slot)
2023 {
2024 struct mmc_data *data = slot->curcmd->data;
2025 size_t left;
2026
2027 /* Interrupt aggregation: Restore command interrupt.
2028 * Auxiliary restore point for the case when data interrupt
2029 * happened first. */
2030 if (!slot->cmd_done) {
2031 WR4(slot, SDHCI_SIGNAL_ENABLE,
2032 slot->intmask |= SDHCI_INT_RESPONSE);
2033 }
2034 /* Unload rest of data from DMA buffer. */
2035 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
2036 slot->curcmd->data != NULL) {
2037 if (data->flags & MMC_DATA_READ) {
2038 left = data->len - slot->offset;
2039 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2040 BUS_DMASYNC_POSTREAD);
2041 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2042 ulmin(left, slot->sdma_bbufsz));
2043 } else
2044 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2045 BUS_DMASYNC_POSTWRITE);
2046 }
2047 slot->data_done = 1;
2048 /* If there was error - reset the host. */
2049 if (slot->curcmd->error) {
2050 if (slot->curcmd->error == MMC_ERR_BADCRC)
2051 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2052 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2053 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2054 sdhci_start(slot);
2055 return;
2056 }
2057 /* If we already have command response - finish. */
2058 if (slot->cmd_done)
2059 sdhci_start(slot);
2060 }
2061
2062 #ifdef MMCCAM
2063 static void
2064 sdhci_start(struct sdhci_slot *slot)
2065 {
2066 union ccb *ccb;
2067 struct ccb_mmcio *mmcio;
2068
2069 ccb = slot->ccb;
2070 if (ccb == NULL)
2071 return;
2072
2073 mmcio = &ccb->mmcio;
2074 if (!(slot->flags & CMD_STARTED)) {
2075 slot->flags |= CMD_STARTED;
2076 sdhci_start_command(slot, &mmcio->cmd);
2077 return;
2078 }
2079
2080 /*
2081 * Old stack doesn't use this!
2082 * Enabling this code causes significant performance degradation
2083 * and IRQ storms on BBB, Wandboard behaves fine.
2084 * Not using this code does no harm...
2085 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
2086 slot->flags |= STOP_STARTED;
2087 sdhci_start_command(slot, &mmcio->stop);
2088 return;
2089 }
2090 */
2091 if (__predict_false(sdhci_debug > 1))
2092 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
2093 if (mmcio->cmd.error == 0 &&
2094 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
2095 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2096 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2097 }
2098
2099 sdhci_req_done(slot);
2100 }
2101 #else
2102 static void
2103 sdhci_start(struct sdhci_slot *slot)
2104 {
2105 const struct mmc_request *req;
2106
2107 req = slot->req;
2108 if (req == NULL)
2109 return;
2110
2111 if (!(slot->flags & CMD_STARTED)) {
2112 slot->flags |= CMD_STARTED;
2113 sdhci_start_command(slot, req->cmd);
2114 return;
2115 }
2116 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
2117 !(slot->flags & STOP_STARTED) && req->stop) {
2118 slot->flags |= STOP_STARTED;
2119 sdhci_start_command(slot, req->stop);
2120 return;
2121 }
2122 if (__predict_false(sdhci_debug > 1))
2123 slot_printf(slot, "result: %d\n", req->cmd->error);
2124 if (!req->cmd->error &&
2125 ((slot->curcmd == req->stop &&
2126 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
2127 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2128 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2129 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2130 }
2131
2132 sdhci_req_done(slot);
2133 }
2134 #endif
2135
2136 int
2137 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
2138 struct mmc_request *req)
2139 {
2140 struct sdhci_slot *slot = device_get_ivars(reqdev);
2141
2142 SDHCI_LOCK(slot);
2143 if (slot->req != NULL) {
2144 SDHCI_UNLOCK(slot);
2145 return (EBUSY);
2146 }
2147 if (__predict_false(sdhci_debug > 1)) {
2148 slot_printf(slot,
2149 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
2150 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
2151 (req->cmd->data)?(u_int)req->cmd->data->len:0,
2152 (req->cmd->data)?req->cmd->data->flags:0);
2153 }
2154 slot->req = req;
2155 slot->flags = 0;
2156 sdhci_start(slot);
2157 SDHCI_UNLOCK(slot);
2158 if (dumping) {
2159 while (slot->req != NULL) {
2160 sdhci_generic_intr(slot);
2161 DELAY(10);
2162 }
2163 }
2164 return (0);
2165 }
2166
2167 int
2168 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
2169 {
2170 struct sdhci_slot *slot = device_get_ivars(reqdev);
2171 uint32_t val;
2172
2173 SDHCI_LOCK(slot);
2174 val = RD4(slot, SDHCI_PRESENT_STATE);
2175 SDHCI_UNLOCK(slot);
2176 return (!(val & SDHCI_WRITE_PROTECT));
2177 }
2178
2179 int
2180 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
2181 {
2182 struct sdhci_slot *slot = device_get_ivars(reqdev);
2183 int err = 0;
2184
2185 SDHCI_LOCK(slot);
2186 while (slot->bus_busy)
2187 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
2188 slot->bus_busy++;
2189 /* Activate led. */
2190 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2191 SDHCI_UNLOCK(slot);
2192 return (err);
2193 }
2194
2195 int
2196 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
2197 {
2198 struct sdhci_slot *slot = device_get_ivars(reqdev);
2199
2200 SDHCI_LOCK(slot);
2201 /* Deactivate led. */
2202 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2203 slot->bus_busy--;
2204 wakeup(slot);
2205 SDHCI_UNLOCK(slot);
2206 return (0);
2207 }
2208
2209 static void
2210 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
2211 {
2212
2213 if (!slot->curcmd) {
2214 slot_printf(slot, "Got command interrupt 0x%08x, but "
2215 "there is no active command.\n", intmask);
2216 sdhci_dumpregs(slot);
2217 return;
2218 }
2219 if (intmask & SDHCI_INT_TIMEOUT)
2220 slot->curcmd->error = MMC_ERR_TIMEOUT;
2221 else if (intmask & SDHCI_INT_CRC)
2222 slot->curcmd->error = MMC_ERR_BADCRC;
2223 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
2224 slot->curcmd->error = MMC_ERR_FIFO;
2225
2226 sdhci_finish_command(slot);
2227 }
2228
2229 static void
2230 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
2231 {
2232 struct mmc_data *data;
2233 size_t left;
2234 uint32_t sdma_bbufsz;
2235
2236 if (!slot->curcmd) {
2237 slot_printf(slot, "Got data interrupt 0x%08x, but "
2238 "there is no active command.\n", intmask);
2239 sdhci_dumpregs(slot);
2240 return;
2241 }
2242 if (slot->curcmd->data == NULL &&
2243 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2244 slot_printf(slot, "Got data interrupt 0x%08x, but "
2245 "there is no active data operation.\n",
2246 intmask);
2247 sdhci_dumpregs(slot);
2248 return;
2249 }
2250 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2251 slot->curcmd->error = MMC_ERR_TIMEOUT;
2252 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
2253 slot->curcmd->error = MMC_ERR_BADCRC;
2254 if (slot->curcmd->data == NULL &&
2255 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2256 SDHCI_INT_DMA_END))) {
2257 slot_printf(slot, "Got data interrupt 0x%08x, but "
2258 "there is busy-only command.\n", intmask);
2259 sdhci_dumpregs(slot);
2260 slot->curcmd->error = MMC_ERR_INVALID;
2261 }
2262 if (slot->curcmd->error) {
2263 /* No need to continue after any error. */
2264 goto done;
2265 }
2266
2267 /* Handle tuning completion interrupt. */
2268 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
2269 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2270 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2271 slot->req->flags |= MMC_TUNE_DONE;
2272 sdhci_finish_command(slot);
2273 sdhci_finish_data(slot);
2274 return;
2275 }
2276 /* Handle PIO interrupt. */
2277 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
2278 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2279 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2280 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2281 &intmask);
2282 slot->flags |= PLATFORM_DATA_STARTED;
2283 } else
2284 sdhci_transfer_pio(slot);
2285 }
2286 /* Handle DMA border. */
2287 if (intmask & SDHCI_INT_DMA_END) {
2288 data = slot->curcmd->data;
2289 sdma_bbufsz = slot->sdma_bbufsz;
2290
2291 /* Unload DMA buffer ... */
2292 left = data->len - slot->offset;
2293 if (data->flags & MMC_DATA_READ) {
2294 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2295 BUS_DMASYNC_POSTREAD);
2296 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2297 ulmin(left, sdma_bbufsz));
2298 } else {
2299 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2300 BUS_DMASYNC_POSTWRITE);
2301 }
2302 /* ... and reload it again. */
2303 slot->offset += sdma_bbufsz;
2304 left = data->len - slot->offset;
2305 if (data->flags & MMC_DATA_READ) {
2306 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2307 BUS_DMASYNC_PREREAD);
2308 } else {
2309 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2310 ulmin(left, sdma_bbufsz));
2311 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2312 BUS_DMASYNC_PREWRITE);
2313 }
2314 /*
2315 * Interrupt aggregation: Mask border interrupt for the last
2316 * bounce buffer.
2317 */
2318 if (left == sdma_bbufsz) {
2319 slot->intmask &= ~SDHCI_INT_DMA_END;
2320 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2321 }
2322 /* Restart DMA. */
2323 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2324 }
2325 /* We have got all data. */
2326 if (intmask & SDHCI_INT_DATA_END) {
2327 if (slot->flags & PLATFORM_DATA_STARTED) {
2328 slot->flags &= ~PLATFORM_DATA_STARTED;
2329 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2330 } else
2331 sdhci_finish_data(slot);
2332 }
2333 done:
2334 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2335 if (slot->flags & PLATFORM_DATA_STARTED) {
2336 slot->flags &= ~PLATFORM_DATA_STARTED;
2337 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2338 } else
2339 sdhci_finish_data(slot);
2340 }
2341 }
2342
2343 static void
2344 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
2345 {
2346
2347 if (!slot->curcmd) {
2348 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2349 "there is no active command.\n", acmd_err);
2350 sdhci_dumpregs(slot);
2351 return;
2352 }
2353 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2354 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2355 }
2356
2357 void
2358 sdhci_generic_intr(struct sdhci_slot *slot)
2359 {
2360 uint32_t intmask, present;
2361 uint16_t val16;
2362
2363 SDHCI_LOCK(slot);
2364 /* Read slot interrupt status. */
2365 intmask = RD4(slot, SDHCI_INT_STATUS);
2366 if (intmask == 0 || intmask == 0xffffffff) {
2367 SDHCI_UNLOCK(slot);
2368 return;
2369 }
2370 if (__predict_false(sdhci_debug > 2))
2371 slot_printf(slot, "Interrupt %#x\n", intmask);
2372
2373 /* Handle tuning error interrupt. */
2374 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2375 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2376 slot_printf(slot, "Tuning error indicated\n");
2377 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2378 if (slot->curcmd) {
2379 slot->curcmd->error = MMC_ERR_BADCRC;
2380 sdhci_finish_command(slot);
2381 }
2382 }
2383 /* Handle re-tuning interrupt. */
2384 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2385 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2386 /* Handle card presence interrupts. */
2387 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2388 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2389 slot->intmask &=
2390 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2391 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2392 SDHCI_INT_CARD_INSERT;
2393 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2394 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2395 WR4(slot, SDHCI_INT_STATUS, intmask &
2396 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2397 sdhci_handle_card_present_locked(slot, present);
2398 }
2399 /* Handle command interrupts. */
2400 if (intmask & SDHCI_INT_CMD_MASK) {
2401 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2402 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2403 }
2404 /* Handle data interrupts. */
2405 if (intmask & SDHCI_INT_DATA_MASK) {
2406 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2407 /* Don't call data_irq in case of errored command. */
2408 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2409 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2410 }
2411 /* Handle AutoCMD12 error interrupt. */
2412 if (intmask & SDHCI_INT_ACMD12ERR) {
2413 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2414 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2415 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2416 sdhci_acmd_irq(slot, val16);
2417 }
2418 /* Handle bus power interrupt. */
2419 if (intmask & SDHCI_INT_BUS_POWER) {
2420 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2421 slot_printf(slot, "Card is consuming too much power!\n");
2422 }
2423 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2424 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2425 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2426 /* The rest is unknown. */
2427 if (intmask) {
2428 WR4(slot, SDHCI_INT_STATUS, intmask);
2429 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2430 intmask);
2431 sdhci_dumpregs(slot);
2432 }
2433
2434 SDHCI_UNLOCK(slot);
2435 }
2436
2437 int
2438 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2439 uintptr_t *result)
2440 {
2441 const struct sdhci_slot *slot = device_get_ivars(child);
2442
2443 switch (which) {
2444 default:
2445 return (EINVAL);
2446 case MMCBR_IVAR_BUS_MODE:
2447 *result = slot->host.ios.bus_mode;
2448 break;
2449 case MMCBR_IVAR_BUS_WIDTH:
2450 *result = slot->host.ios.bus_width;
2451 break;
2452 case MMCBR_IVAR_CHIP_SELECT:
2453 *result = slot->host.ios.chip_select;
2454 break;
2455 case MMCBR_IVAR_CLOCK:
2456 *result = slot->host.ios.clock;
2457 break;
2458 case MMCBR_IVAR_F_MIN:
2459 *result = slot->host.f_min;
2460 break;
2461 case MMCBR_IVAR_F_MAX:
2462 *result = slot->host.f_max;
2463 break;
2464 case MMCBR_IVAR_HOST_OCR:
2465 *result = slot->host.host_ocr;
2466 break;
2467 case MMCBR_IVAR_MODE:
2468 *result = slot->host.mode;
2469 break;
2470 case MMCBR_IVAR_OCR:
2471 *result = slot->host.ocr;
2472 break;
2473 case MMCBR_IVAR_POWER_MODE:
2474 *result = slot->host.ios.power_mode;
2475 break;
2476 case MMCBR_IVAR_VDD:
2477 *result = slot->host.ios.vdd;
2478 break;
2479 case MMCBR_IVAR_RETUNE_REQ:
2480 if (slot->opt & SDHCI_TUNING_ENABLED) {
2481 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2482 *result = retune_req_reset;
2483 break;
2484 }
2485 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2486 *result = retune_req_normal;
2487 break;
2488 }
2489 }
2490 *result = retune_req_none;
2491 break;
2492 case MMCBR_IVAR_VCCQ:
2493 *result = slot->host.ios.vccq;
2494 break;
2495 case MMCBR_IVAR_CAPS:
2496 *result = slot->host.caps;
2497 break;
2498 case MMCBR_IVAR_TIMING:
2499 *result = slot->host.ios.timing;
2500 break;
2501 case MMCBR_IVAR_MAX_DATA:
2502 /*
2503 * Re-tuning modes 1 and 2 restrict the maximum data length
2504 * per read/write command to 4 MiB.
2505 */
2506 if (slot->opt & SDHCI_TUNING_ENABLED &&
2507 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2508 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2509 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2510 break;
2511 }
2512 *result = 65535;
2513 break;
2514 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2515 /*
2516 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2517 */
2518 *result = 1000000;
2519 break;
2520 }
2521 return (0);
2522 }
2523
2524 int
2525 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2526 uintptr_t value)
2527 {
2528 struct sdhci_slot *slot = device_get_ivars(child);
2529 uint32_t clock, max_clock;
2530 int i;
2531
2532 if (sdhci_debug > 1)
2533 slot_printf(slot, "%s: var=%d\n", __func__, which);
2534 switch (which) {
2535 default:
2536 return (EINVAL);
2537 case MMCBR_IVAR_BUS_MODE:
2538 slot->host.ios.bus_mode = value;
2539 break;
2540 case MMCBR_IVAR_BUS_WIDTH:
2541 slot->host.ios.bus_width = value;
2542 break;
2543 case MMCBR_IVAR_CHIP_SELECT:
2544 slot->host.ios.chip_select = value;
2545 break;
2546 case MMCBR_IVAR_CLOCK:
2547 if (value > 0) {
2548 max_clock = slot->max_clk;
2549 clock = max_clock;
2550
2551 if (slot->version < SDHCI_SPEC_300) {
2552 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2553 i <<= 1) {
2554 if (clock <= value)
2555 break;
2556 clock >>= 1;
2557 }
2558 } else {
2559 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2560 i += 2) {
2561 if (clock <= value)
2562 break;
2563 clock = max_clock / (i + 2);
2564 }
2565 }
2566
2567 slot->host.ios.clock = clock;
2568 } else
2569 slot->host.ios.clock = 0;
2570 break;
2571 case MMCBR_IVAR_MODE:
2572 slot->host.mode = value;
2573 break;
2574 case MMCBR_IVAR_OCR:
2575 slot->host.ocr = value;
2576 break;
2577 case MMCBR_IVAR_POWER_MODE:
2578 slot->host.ios.power_mode = value;
2579 break;
2580 case MMCBR_IVAR_VDD:
2581 slot->host.ios.vdd = value;
2582 break;
2583 case MMCBR_IVAR_VCCQ:
2584 slot->host.ios.vccq = value;
2585 break;
2586 case MMCBR_IVAR_TIMING:
2587 slot->host.ios.timing = value;
2588 break;
2589 case MMCBR_IVAR_CAPS:
2590 case MMCBR_IVAR_HOST_OCR:
2591 case MMCBR_IVAR_F_MIN:
2592 case MMCBR_IVAR_F_MAX:
2593 case MMCBR_IVAR_MAX_DATA:
2594 case MMCBR_IVAR_RETUNE_REQ:
2595 return (EINVAL);
2596 }
2597 return (0);
2598 }
2599
2600 #ifdef MMCCAM
2601 void
2602 sdhci_start_slot(struct sdhci_slot *slot)
2603 {
2604
2605 if ((slot->devq = cam_simq_alloc(1)) == NULL)
2606 goto fail;
2607
2608 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2609 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2610 "sdhci_slot", slot, device_get_unit(slot->bus),
2611 &slot->sim_mtx, 1, 1, slot->devq);
2612
2613 if (slot->sim == NULL) {
2614 cam_simq_free(slot->devq);
2615 slot_printf(slot, "cannot allocate CAM SIM\n");
2616 goto fail;
2617 }
2618
2619 mtx_lock(&slot->sim_mtx);
2620 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2621 slot_printf(slot, "cannot register SCSI pass-through bus\n");
2622 cam_sim_free(slot->sim, FALSE);
2623 cam_simq_free(slot->devq);
2624 mtx_unlock(&slot->sim_mtx);
2625 goto fail;
2626 }
2627 mtx_unlock(&slot->sim_mtx);
2628
2629 /* End CAM-specific init */
2630 slot->card_present = 0;
2631 sdhci_card_task(slot, 0);
2632 return;
2633
2634 fail:
2635 if (slot->sim != NULL) {
2636 mtx_lock(&slot->sim_mtx);
2637 xpt_bus_deregister(cam_sim_path(slot->sim));
2638 cam_sim_free(slot->sim, FALSE);
2639 mtx_unlock(&slot->sim_mtx);
2640 }
2641
2642 if (slot->devq != NULL)
2643 cam_simq_free(slot->devq);
2644 }
2645
2646 void
2647 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb)
2648 {
2649 struct sdhci_slot *slot;
2650
2651 slot = cam_sim_softc(sim);
2652 if (slot == NULL) {
2653 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2654 xpt_done(ccb);
2655 return;
2656 }
2657
2658 mtx_assert(&slot->sim_mtx, MA_OWNED);
2659
2660 switch (ccb->ccb_h.func_code) {
2661 case XPT_PATH_INQ:
2662 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, maxphys);
2663 break;
2664
2665 case XPT_MMC_GET_TRAN_SETTINGS:
2666 case XPT_GET_TRAN_SETTINGS:
2667 {
2668 struct ccb_trans_settings *cts = &ccb->cts;
2669 uint32_t max_data;
2670
2671 if (sdhci_debug > 1)
2672 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2673
2674 cts->protocol = PROTO_MMCSD;
2675 cts->protocol_version = 1;
2676 cts->transport = XPORT_MMCSD;
2677 cts->transport_version = 1;
2678 cts->xport_specific.valid = 0;
2679 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2680 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2681 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2682 cts->proto_specific.mmc.host_caps = slot->host.caps;
2683 /*
2684 * Re-tuning modes 1 and 2 restrict the maximum data length
2685 * per read/write command to 4 MiB.
2686 */
2687 if (slot->opt & SDHCI_TUNING_ENABLED &&
2688 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2689 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2690 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2691 } else {
2692 max_data = 65535;
2693 }
2694 cts->proto_specific.mmc.host_max_data = max_data;
2695
2696 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2697 ccb->ccb_h.status = CAM_REQ_CMP;
2698 break;
2699 }
2700 case XPT_MMC_SET_TRAN_SETTINGS:
2701 case XPT_SET_TRAN_SETTINGS:
2702 if (sdhci_debug > 1)
2703 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2704 sdhci_cam_settran_settings(slot, ccb);
2705 ccb->ccb_h.status = CAM_REQ_CMP;
2706 break;
2707 case XPT_RESET_BUS:
2708 if (sdhci_debug > 1)
2709 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2710 ccb->ccb_h.status = CAM_REQ_CMP;
2711 break;
2712 case XPT_MMC_IO:
2713 /*
2714 * Here is the HW-dependent part of
2715 * sending the command to the underlying h/w
2716 * At some point in the future an interrupt comes.
2717 * Then the request will be marked as completed.
2718 */
2719 if (__predict_false(sdhci_debug > 1))
2720 slot_printf(slot, "Got XPT_MMC_IO\n");
2721 ccb->ccb_h.status = CAM_REQ_INPROG;
2722
2723 sdhci_cam_request(cam_sim_softc(sim), ccb);
2724 return;
2725 default:
2726 ccb->ccb_h.status = CAM_REQ_INVALID;
2727 break;
2728 }
2729 xpt_done(ccb);
2730 return;
2731 }
2732
2733 void
2734 sdhci_cam_poll(struct cam_sim *sim)
2735 {
2736 sdhci_generic_intr(cam_sim_softc(sim));
2737 }
2738
2739 static int
2740 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
2741 int proposed_clock)
2742 {
2743 int max_clock, clock, i;
2744
2745 if (proposed_clock == 0)
2746 return 0;
2747 max_clock = slot->max_clk;
2748 clock = max_clock;
2749
2750 if (slot->version < SDHCI_SPEC_300) {
2751 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) {
2752 if (clock <= proposed_clock)
2753 break;
2754 clock >>= 1;
2755 }
2756 } else {
2757 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) {
2758 if (clock <= proposed_clock)
2759 break;
2760 clock = max_clock / (i + 2);
2761 }
2762 }
2763 return clock;
2764 }
2765
2766 static int
2767 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb)
2768 {
2769 struct mmc_ios *ios;
2770 const struct mmc_ios *new_ios;
2771 const struct ccb_trans_settings_mmc *cts;
2772
2773 ios = &slot->host.ios;
2774 cts = &ccb->cts.proto_specific.mmc;
2775 new_ios = &cts->ios;
2776
2777 /* Update only requested fields */
2778 if (cts->ios_valid & MMC_CLK) {
2779 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2780 if (sdhci_debug > 1)
2781 slot_printf(slot, "Clock => %d\n", ios->clock);
2782 }
2783 if (cts->ios_valid & MMC_VDD) {
2784 ios->vdd = new_ios->vdd;
2785 if (sdhci_debug > 1)
2786 slot_printf(slot, "VDD => %d\n", ios->vdd);
2787 }
2788 if (cts->ios_valid & MMC_CS) {
2789 ios->chip_select = new_ios->chip_select;
2790 if (sdhci_debug > 1)
2791 slot_printf(slot, "CS => %d\n", ios->chip_select);
2792 }
2793 if (cts->ios_valid & MMC_BW) {
2794 ios->bus_width = new_ios->bus_width;
2795 if (sdhci_debug > 1)
2796 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2797 }
2798 if (cts->ios_valid & MMC_PM) {
2799 ios->power_mode = new_ios->power_mode;
2800 if (sdhci_debug > 1)
2801 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2802 }
2803 if (cts->ios_valid & MMC_BT) {
2804 ios->timing = new_ios->timing;
2805 if (sdhci_debug > 1)
2806 slot_printf(slot, "Timing => %d\n", ios->timing);
2807 }
2808 if (cts->ios_valid & MMC_BM) {
2809 ios->bus_mode = new_ios->bus_mode;
2810 if (sdhci_debug > 1)
2811 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2812 }
2813 if (cts->ios_valid & MMC_VCCQ) {
2814 ios->vccq = new_ios->vccq;
2815 if (sdhci_debug > 1)
2816 slot_printf(slot, "VCCQ => %d\n", ios->vccq);
2817 }
2818
2819 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2820 return (sdhci_cam_update_ios(slot));
2821 }
2822
2823 static int
2824 sdhci_cam_update_ios(struct sdhci_slot *slot)
2825 {
2826 struct mmc_ios *ios = &slot->host.ios;
2827
2828 if (sdhci_debug > 1)
2829 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2830 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2831 SDHCI_LOCK(slot);
2832 /* Do full reset on bus power down to clear from any state. */
2833 if (ios->power_mode == power_off) {
2834 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2835 sdhci_init(slot);
2836 }
2837 /* Configure the bus. */
2838 sdhci_set_clock(slot, ios->clock);
2839 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2840 if (ios->bus_width == bus_width_8) {
2841 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2842 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2843 } else if (ios->bus_width == bus_width_4) {
2844 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2845 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2846 } else if (ios->bus_width == bus_width_1) {
2847 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2848 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2849 } else {
2850 panic("Invalid bus width: %d", ios->bus_width);
2851 }
2852 if (ios->timing == bus_timing_hs &&
2853 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2854 slot->hostctrl |= SDHCI_CTRL_HISPD;
2855 else
2856 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2857 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2858 /* Some controllers like reset after bus changes. */
2859 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2860 SDHCI_RESET(slot->bus, slot,
2861 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2862
2863 SDHCI_UNLOCK(slot);
2864 return (0);
2865 }
2866
2867 static int
2868 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb)
2869 {
2870 const struct ccb_mmcio *mmcio;
2871
2872 mmcio = &ccb->mmcio;
2873
2874 SDHCI_LOCK(slot);
2875 /* if (slot->req != NULL) {
2876 SDHCI_UNLOCK(slot);
2877 return (EBUSY);
2878 }
2879 */
2880 if (__predict_false(sdhci_debug > 1)) {
2881 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x "
2882 "blksz=%zu blkcnt=%zu\n",
2883 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2884 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2885 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0,
2886 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0,
2887 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0);
2888 }
2889 if (mmcio->cmd.data != NULL) {
2890 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2891 panic("data->len = %d, data->flags = %d -- something is b0rked",
2892 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2893 }
2894 slot->ccb = ccb;
2895 slot->flags = 0;
2896 sdhci_start(slot);
2897 SDHCI_UNLOCK(slot);
2898 return (0);
2899 }
2900 #endif /* MMCCAM */
2901
2902 MODULE_VERSION(sdhci, SDHCI_VERSION);
2903