1 /*-
2 * Copyright (c) 2017 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 #include <sys/param.h>
27 #include <sys/systm.h>
28 #include <sys/bus.h>
29 #include <sys/kernel.h>
30 #include <sys/lock.h>
31 #include <sys/module.h>
32 #include <sys/mutex.h>
33 #include <sys/resource.h>
34 #include <sys/rman.h>
35 #include <sys/sysctl.h>
36 #include <sys/taskqueue.h>
37
38 #include <machine/bus.h>
39 #include <machine/resource.h>
40
41 #include <contrib/dev/acpica/include/acpi.h>
42 #include <dev/acpica/acpivar.h>
43
44 #include <dev/mmc/bridge.h>
45 #include <dev/mmc/mmcreg.h>
46
47 #include <dev/sdhci/sdhci.h>
48
49 #include "mmcbr_if.h"
50 #include "sdhci_if.h"
51
52 #define SDHCI_AMD_RESET_DLL_REG 0x908
53
54 static const struct sdhci_acpi_device {
55 const char* hid;
56 int uid;
57 const char *desc;
58 u_int quirks;
59 } sdhci_acpi_devices[] = {
60 { "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
61 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
62 SDHCI_QUIRK_WAIT_WHILE_BUSY |
63 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
64 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
65 { "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller",
66 SDHCI_QUIRK_WAIT_WHILE_BUSY |
67 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
68 { "80860F16", 0, "Intel Bay Trail/Braswell SDXC Controller",
69 SDHCI_QUIRK_WAIT_WHILE_BUSY |
70 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
71 { "80865ACA", 0, "Intel Apollo Lake SDXC Controller",
72 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
73 SDHCI_QUIRK_WAIT_WHILE_BUSY |
74 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
75 { "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",
76 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
77 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
78 SDHCI_QUIRK_WAIT_WHILE_BUSY |
79 SDHCI_QUIRK_MMC_DDR52 |
80 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
81 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
82 { "AMDI0040", 0, "AMD eMMC 5.0 Controller",
83 SDHCI_QUIRK_32BIT_DMA_SIZE |
84 SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 },
85 { NULL, 0, NULL, 0}
86 };
87
88 static char *sdhci_ids[] = {
89 "80860F14",
90 "80860F16",
91 "80865ACA",
92 "80865ACC",
93 "AMDI0040",
94 NULL
95 };
96
97 struct sdhci_acpi_softc {
98 struct sdhci_slot slot;
99 struct resource *mem_res; /* Memory resource */
100 struct resource *irq_res; /* IRQ resource */
101 void *intrhand; /* Interrupt handle */
102 const struct sdhci_acpi_device *acpi_dev;
103 };
104
105 static void sdhci_acpi_intr(void *arg);
106 static int sdhci_acpi_detach(device_t dev);
107
108 static uint8_t
sdhci_acpi_read_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)109 sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused,
110 bus_size_t off)
111 {
112 struct sdhci_acpi_softc *sc = device_get_softc(dev);
113
114 bus_barrier(sc->mem_res, 0, 0xFF,
115 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
116 return bus_read_1(sc->mem_res, off);
117 }
118
119 static void
sdhci_acpi_write_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint8_t val)120 sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused,
121 bus_size_t off, uint8_t val)
122 {
123 struct sdhci_acpi_softc *sc = device_get_softc(dev);
124
125 bus_barrier(sc->mem_res, 0, 0xFF,
126 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
127 bus_write_1(sc->mem_res, off, val);
128 }
129
130 static uint16_t
sdhci_acpi_read_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)131 sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused,
132 bus_size_t off)
133 {
134 struct sdhci_acpi_softc *sc = device_get_softc(dev);
135
136 bus_barrier(sc->mem_res, 0, 0xFF,
137 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
138 return bus_read_2(sc->mem_res, off);
139 }
140
141 static void
sdhci_acpi_write_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint16_t val)142 sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused,
143 bus_size_t off, uint16_t val)
144 {
145 struct sdhci_acpi_softc *sc = device_get_softc(dev);
146
147 bus_barrier(sc->mem_res, 0, 0xFF,
148 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
149 bus_write_2(sc->mem_res, off, val);
150 }
151
152 static uint32_t
sdhci_acpi_read_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)153 sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused,
154 bus_size_t off)
155 {
156 struct sdhci_acpi_softc *sc = device_get_softc(dev);
157
158 bus_barrier(sc->mem_res, 0, 0xFF,
159 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
160 return bus_read_4(sc->mem_res, off);
161 }
162
163 static void
sdhci_acpi_write_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t val)164 sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused,
165 bus_size_t off, uint32_t val)
166 {
167 struct sdhci_acpi_softc *sc = device_get_softc(dev);
168
169 bus_barrier(sc->mem_res, 0, 0xFF,
170 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
171 bus_write_4(sc->mem_res, off, val);
172 }
173
174 static void
sdhci_acpi_read_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)175 sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
176 bus_size_t off, uint32_t *data, bus_size_t count)
177 {
178 struct sdhci_acpi_softc *sc = device_get_softc(dev);
179
180 bus_read_multi_stream_4(sc->mem_res, off, data, count);
181 }
182
183 static void
sdhci_acpi_write_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)184 sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
185 bus_size_t off, uint32_t *data, bus_size_t count)
186 {
187 struct sdhci_acpi_softc *sc = device_get_softc(dev);
188
189 bus_write_multi_stream_4(sc->mem_res, off, data, count);
190 }
191
192 static void
sdhci_acpi_set_uhs_timing(device_t dev,struct sdhci_slot * slot)193 sdhci_acpi_set_uhs_timing(device_t dev, struct sdhci_slot *slot)
194 {
195 const struct sdhci_acpi_softc *sc;
196 const struct sdhci_acpi_device *acpi_dev;
197 const struct mmc_ios *ios;
198 device_t bus;
199 uint16_t old_timing;
200 enum mmc_bus_timing timing;
201
202 bus = slot->bus;
203 old_timing = SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2);
204 old_timing &= SDHCI_CTRL2_UHS_MASK;
205 sdhci_generic_set_uhs_timing(dev, slot);
206
207 sc = device_get_softc(dev);
208 acpi_dev = sc->acpi_dev;
209 /*
210 * AMDI0040 controllers require SDHCI_CTRL2_SAMPLING_CLOCK to be
211 * disabled when switching from HS200 to high speed and to always
212 * be turned on again when tuning for HS400. In the later case,
213 * an AMD-specific DLL reset additionally is needed.
214 */
215 if (strcmp(acpi_dev->hid, "AMDI0040") == 0 && acpi_dev->uid == 0) {
216 ios = &slot->host.ios;
217 timing = ios->timing;
218 if (old_timing == SDHCI_CTRL2_UHS_SDR104 &&
219 timing == bus_timing_hs)
220 SDHCI_WRITE_2(bus, slot, SDHCI_HOST_CONTROL2,
221 SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2) &
222 ~SDHCI_CTRL2_SAMPLING_CLOCK);
223 if (ios->clock > SD_SDR50_MAX &&
224 old_timing != SDHCI_CTRL2_MMC_HS400 &&
225 timing == bus_timing_mmc_hs400) {
226 SDHCI_WRITE_2(bus, slot, SDHCI_HOST_CONTROL2,
227 SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2) |
228 SDHCI_CTRL2_SAMPLING_CLOCK);
229 SDHCI_WRITE_4(bus, slot, SDHCI_AMD_RESET_DLL_REG,
230 0x40003210);
231 DELAY(20);
232 SDHCI_WRITE_4(bus, slot, SDHCI_AMD_RESET_DLL_REG,
233 0x40033210);
234 }
235 }
236 }
237
238 static const struct sdhci_acpi_device *
sdhci_acpi_find_device(device_t dev)239 sdhci_acpi_find_device(device_t dev)
240 {
241 char *hid;
242 int i, uid;
243 ACPI_HANDLE handle;
244 ACPI_STATUS status;
245 int rv;
246
247 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids, &hid);
248 if (rv > 0)
249 return (NULL);
250
251 handle = acpi_get_handle(dev);
252 status = acpi_GetInteger(handle, "_UID", &uid);
253 if (ACPI_FAILURE(status))
254 uid = 0;
255
256 for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) {
257 if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0)
258 continue;
259 if ((sdhci_acpi_devices[i].uid != 0) &&
260 (sdhci_acpi_devices[i].uid != uid))
261 continue;
262 return (&sdhci_acpi_devices[i]);
263 }
264
265 return (NULL);
266 }
267
268 static int
sdhci_acpi_probe(device_t dev)269 sdhci_acpi_probe(device_t dev)
270 {
271 const struct sdhci_acpi_device *acpi_dev;
272
273 acpi_dev = sdhci_acpi_find_device(dev);
274 if (acpi_dev == NULL)
275 return (ENXIO);
276
277 device_set_desc(dev, acpi_dev->desc);
278
279 return (BUS_PROBE_DEFAULT);
280 }
281
282 static int
sdhci_acpi_attach(device_t dev)283 sdhci_acpi_attach(device_t dev)
284 {
285 struct sdhci_acpi_softc *sc = device_get_softc(dev);
286 int rid, err;
287 u_int quirks;
288 const struct sdhci_acpi_device *acpi_dev;
289
290 acpi_dev = sdhci_acpi_find_device(dev);
291 if (acpi_dev == NULL)
292 return (ENXIO);
293
294 sc->acpi_dev = acpi_dev;
295 quirks = acpi_dev->quirks;
296
297 /* Allocate IRQ. */
298 rid = 0;
299 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
300 RF_ACTIVE);
301 if (sc->irq_res == NULL) {
302 device_printf(dev, "can't allocate IRQ\n");
303 return (ENOMEM);
304 }
305
306 rid = 0;
307 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
308 &rid, RF_ACTIVE);
309 if (sc->mem_res == NULL) {
310 device_printf(dev, "can't allocate memory resource for slot\n");
311 sdhci_acpi_detach(dev);
312 return (ENOMEM);
313 }
314
315 /*
316 * Intel Bay Trail and Braswell eMMC controllers share the same IDs,
317 * but while with these former DDR52 is affected by the VLI54 erratum,
318 * these latter require the timeout clock to be hardcoded to 1 MHz.
319 */
320 if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
321 SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
322 SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
323 quirks |= SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
324 quirks &= ~sdhci_quirk_clear;
325 quirks |= sdhci_quirk_set;
326 sc->slot.quirks = quirks;
327
328 err = sdhci_init_slot(dev, &sc->slot, 0);
329 if (err) {
330 device_printf(dev, "failed to init slot\n");
331 sdhci_acpi_detach(dev);
332 return (err);
333 }
334
335 /* Activate the interrupt */
336 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
337 NULL, sdhci_acpi_intr, sc, &sc->intrhand);
338 if (err) {
339 device_printf(dev, "can't setup IRQ\n");
340 sdhci_acpi_detach(dev);
341 return (err);
342 }
343
344 /* Process cards detection. */
345 sdhci_start_slot(&sc->slot);
346
347 return (0);
348 }
349
350 static int
sdhci_acpi_detach(device_t dev)351 sdhci_acpi_detach(device_t dev)
352 {
353 struct sdhci_acpi_softc *sc = device_get_softc(dev);
354
355 if (sc->intrhand)
356 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
357 if (sc->irq_res)
358 bus_release_resource(dev, SYS_RES_IRQ,
359 rman_get_rid(sc->irq_res), sc->irq_res);
360
361 if (sc->mem_res) {
362 sdhci_cleanup_slot(&sc->slot);
363 bus_release_resource(dev, SYS_RES_MEMORY,
364 rman_get_rid(sc->mem_res), sc->mem_res);
365 }
366
367 return (0);
368 }
369
370 static int
sdhci_acpi_shutdown(device_t dev)371 sdhci_acpi_shutdown(device_t dev)
372 {
373
374 return (0);
375 }
376
377 static int
sdhci_acpi_suspend(device_t dev)378 sdhci_acpi_suspend(device_t dev)
379 {
380 struct sdhci_acpi_softc *sc = device_get_softc(dev);
381 int err;
382
383 err = bus_generic_suspend(dev);
384 if (err)
385 return (err);
386 sdhci_generic_suspend(&sc->slot);
387 return (0);
388 }
389
390 static int
sdhci_acpi_resume(device_t dev)391 sdhci_acpi_resume(device_t dev)
392 {
393 struct sdhci_acpi_softc *sc = device_get_softc(dev);
394 int err;
395
396 sdhci_generic_resume(&sc->slot);
397 err = bus_generic_resume(dev);
398 if (err)
399 return (err);
400 return (0);
401 }
402
403 static void
sdhci_acpi_intr(void * arg)404 sdhci_acpi_intr(void *arg)
405 {
406 struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg;
407
408 sdhci_generic_intr(&sc->slot);
409 }
410
411 static device_method_t sdhci_methods[] = {
412 /* device_if */
413 DEVMETHOD(device_probe, sdhci_acpi_probe),
414 DEVMETHOD(device_attach, sdhci_acpi_attach),
415 DEVMETHOD(device_detach, sdhci_acpi_detach),
416 DEVMETHOD(device_shutdown, sdhci_acpi_shutdown),
417 DEVMETHOD(device_suspend, sdhci_acpi_suspend),
418 DEVMETHOD(device_resume, sdhci_acpi_resume),
419
420 /* Bus interface */
421 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
422 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
423 DEVMETHOD(bus_add_child, bus_generic_add_child),
424
425 /* mmcbr_if */
426 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
427 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
428 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
429 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
430 DEVMETHOD(mmcbr_request, sdhci_generic_request),
431 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
432 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
433 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
434
435 /* SDHCI accessors */
436 DEVMETHOD(sdhci_read_1, sdhci_acpi_read_1),
437 DEVMETHOD(sdhci_read_2, sdhci_acpi_read_2),
438 DEVMETHOD(sdhci_read_4, sdhci_acpi_read_4),
439 DEVMETHOD(sdhci_read_multi_4, sdhci_acpi_read_multi_4),
440 DEVMETHOD(sdhci_write_1, sdhci_acpi_write_1),
441 DEVMETHOD(sdhci_write_2, sdhci_acpi_write_2),
442 DEVMETHOD(sdhci_write_4, sdhci_acpi_write_4),
443 DEVMETHOD(sdhci_write_multi_4, sdhci_acpi_write_multi_4),
444 DEVMETHOD(sdhci_set_uhs_timing, sdhci_acpi_set_uhs_timing),
445
446 DEVMETHOD_END
447 };
448
449 static driver_t sdhci_acpi_driver = {
450 "sdhci_acpi",
451 sdhci_methods,
452 sizeof(struct sdhci_acpi_softc),
453 };
454
455 DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, NULL, NULL);
456 SDHCI_DEPEND(sdhci_acpi);
457
458 #ifndef MMCCAM
459 MMC_DECLARE_BRIDGE(sdhci_acpi);
460 #endif
461