1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * System Control and Power Interface (SCPI) Protocol based clock driver
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/of.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/scpi_protocol.h>
15
16 struct scpi_clk {
17 u32 id;
18 struct clk_hw hw;
19 struct scpi_dvfs_info *info;
20 struct scpi_ops *scpi_ops;
21 };
22
23 #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
24
25 static struct platform_device *cpufreq_dev;
26
scpi_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)27 static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29 {
30 struct scpi_clk *clk = to_scpi_clk(hw);
31
32 return clk->scpi_ops->clk_get_val(clk->id);
33 }
34
scpi_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)35 static int scpi_clk_determine_rate(struct clk_hw *hw,
36 struct clk_rate_request *req)
37 {
38 /*
39 * We can't figure out what rate it will be, so just return the
40 * rate back to the caller. scpi_clk_recalc_rate() will be called
41 * after the rate is set and we'll know what rate the clock is
42 * running at then.
43 */
44 return 0;
45 }
46
scpi_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)47 static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
48 unsigned long parent_rate)
49 {
50 struct scpi_clk *clk = to_scpi_clk(hw);
51
52 return clk->scpi_ops->clk_set_val(clk->id, rate);
53 }
54
55 static const struct clk_ops scpi_clk_ops = {
56 .recalc_rate = scpi_clk_recalc_rate,
57 .determine_rate = scpi_clk_determine_rate,
58 .set_rate = scpi_clk_set_rate,
59 };
60
61 /* find closest match to given frequency in OPP table */
__scpi_dvfs_round_rate(struct scpi_clk * clk,unsigned long rate)62 static long __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
63 {
64 int idx;
65 unsigned long fmin = 0, fmax = ~0, ftmp;
66 const struct scpi_opp *opp = clk->info->opps;
67
68 for (idx = 0; idx < clk->info->count; idx++, opp++) {
69 ftmp = opp->freq;
70 if (ftmp >= rate) {
71 if (ftmp <= fmax)
72 fmax = ftmp;
73 break;
74 } else if (ftmp >= fmin) {
75 fmin = ftmp;
76 }
77 }
78 return fmax != ~0 ? fmax : fmin;
79 }
80
scpi_dvfs_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)81 static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
82 unsigned long parent_rate)
83 {
84 struct scpi_clk *clk = to_scpi_clk(hw);
85 int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
86 const struct scpi_opp *opp;
87
88 if (idx < 0)
89 return 0;
90
91 opp = clk->info->opps + idx;
92 return opp->freq;
93 }
94
scpi_dvfs_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)95 static int scpi_dvfs_determine_rate(struct clk_hw *hw,
96 struct clk_rate_request *req)
97 {
98 struct scpi_clk *clk = to_scpi_clk(hw);
99
100 req->rate = __scpi_dvfs_round_rate(clk, req->rate);
101
102 return 0;
103 }
104
__scpi_find_dvfs_index(struct scpi_clk * clk,unsigned long rate)105 static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
106 {
107 int idx, max_opp = clk->info->count;
108 const struct scpi_opp *opp = clk->info->opps;
109
110 for (idx = 0; idx < max_opp; idx++, opp++)
111 if (opp->freq == rate)
112 return idx;
113 return -EINVAL;
114 }
115
scpi_dvfs_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)116 static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
117 unsigned long parent_rate)
118 {
119 struct scpi_clk *clk = to_scpi_clk(hw);
120 int ret = __scpi_find_dvfs_index(clk, rate);
121
122 if (ret < 0)
123 return ret;
124 return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
125 }
126
127 static const struct clk_ops scpi_dvfs_ops = {
128 .recalc_rate = scpi_dvfs_recalc_rate,
129 .determine_rate = scpi_dvfs_determine_rate,
130 .set_rate = scpi_dvfs_set_rate,
131 };
132
133 static const struct of_device_id scpi_clk_match[] __maybe_unused = {
134 { .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
135 { .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
136 {}
137 };
138
139 static int
scpi_clk_ops_init(struct device * dev,const struct of_device_id * match,struct scpi_clk * sclk,const char * name)140 scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
141 struct scpi_clk *sclk, const char *name)
142 {
143 struct clk_init_data init;
144 unsigned long min = 0, max = 0;
145 int ret;
146
147 init.name = name;
148 init.flags = 0;
149 init.num_parents = 0;
150 init.ops = match->data;
151 sclk->hw.init = &init;
152 sclk->scpi_ops = get_scpi_ops();
153
154 if (init.ops == &scpi_dvfs_ops) {
155 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
156 if (IS_ERR(sclk->info))
157 return PTR_ERR(sclk->info);
158 } else if (init.ops == &scpi_clk_ops) {
159 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
160 return -EINVAL;
161 } else {
162 return -EINVAL;
163 }
164
165 ret = devm_clk_hw_register(dev, &sclk->hw);
166 if (!ret && max)
167 clk_hw_set_rate_range(&sclk->hw, min, max);
168 return ret;
169 }
170
171 struct scpi_clk_data {
172 struct scpi_clk **clk;
173 unsigned int clk_num;
174 };
175
176 static struct clk_hw *
scpi_of_clk_src_get(struct of_phandle_args * clkspec,void * data)177 scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
178 {
179 struct scpi_clk *sclk;
180 struct scpi_clk_data *clk_data = data;
181 unsigned int idx = clkspec->args[0], count;
182
183 for (count = 0; count < clk_data->clk_num; count++) {
184 sclk = clk_data->clk[count];
185 if (idx == sclk->id)
186 return &sclk->hw;
187 }
188
189 return ERR_PTR(-EINVAL);
190 }
191
scpi_clk_add(struct device * dev,struct device_node * np,const struct of_device_id * match)192 static int scpi_clk_add(struct device *dev, struct device_node *np,
193 const struct of_device_id *match)
194 {
195 int idx, count, err;
196 struct scpi_clk_data *clk_data;
197
198 count = of_property_count_strings(np, "clock-output-names");
199 if (count < 0) {
200 dev_err(dev, "%pOFn: invalid clock output count\n", np);
201 return -EINVAL;
202 }
203
204 clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
205 if (!clk_data)
206 return -ENOMEM;
207
208 clk_data->clk_num = count;
209 clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
210 GFP_KERNEL);
211 if (!clk_data->clk)
212 return -ENOMEM;
213
214 for (idx = 0; idx < count; idx++) {
215 struct scpi_clk *sclk;
216 const char *name;
217 u32 val;
218
219 sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
220 if (!sclk)
221 return -ENOMEM;
222
223 if (of_property_read_string_index(np, "clock-output-names",
224 idx, &name)) {
225 dev_err(dev, "invalid clock name @ %pOFn\n", np);
226 return -EINVAL;
227 }
228
229 if (of_property_read_u32_index(np, "clock-indices",
230 idx, &val)) {
231 dev_err(dev, "invalid clock index @ %pOFn\n", np);
232 return -EINVAL;
233 }
234
235 sclk->id = val;
236
237 err = scpi_clk_ops_init(dev, match, sclk, name);
238 if (err) {
239 dev_err(dev, "failed to register clock '%s'\n", name);
240 return err;
241 }
242
243 dev_dbg(dev, "Registered clock '%s'\n", name);
244 clk_data->clk[idx] = sclk;
245 }
246
247 return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data);
248 }
249
scpi_clocks_remove(struct platform_device * pdev)250 static void scpi_clocks_remove(struct platform_device *pdev)
251 {
252 struct device *dev = &pdev->dev;
253 struct device_node *child, *np = dev->of_node;
254
255 if (cpufreq_dev) {
256 platform_device_unregister(cpufreq_dev);
257 cpufreq_dev = NULL;
258 }
259
260 for_each_available_child_of_node(np, child)
261 of_clk_del_provider(np);
262 }
263
scpi_clocks_probe(struct platform_device * pdev)264 static int scpi_clocks_probe(struct platform_device *pdev)
265 {
266 int ret;
267 struct device *dev = &pdev->dev;
268 struct device_node *child, *np = dev->of_node;
269 const struct of_device_id *match;
270
271 if (!get_scpi_ops())
272 return -ENXIO;
273
274 for_each_available_child_of_node(np, child) {
275 match = of_match_node(scpi_clk_match, child);
276 if (!match)
277 continue;
278 ret = scpi_clk_add(dev, child, match);
279 if (ret) {
280 scpi_clocks_remove(pdev);
281 of_node_put(child);
282 return ret;
283 }
284
285 if (match->data != &scpi_dvfs_ops)
286 continue;
287 /* Add the virtual cpufreq device if it's DVFS clock provider */
288 cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
289 -1, NULL, 0);
290 if (IS_ERR(cpufreq_dev))
291 pr_warn("unable to register cpufreq device");
292 }
293 return 0;
294 }
295
296 static const struct of_device_id scpi_clocks_ids[] = {
297 { .compatible = "arm,scpi-clocks", },
298 {}
299 };
300 MODULE_DEVICE_TABLE(of, scpi_clocks_ids);
301
302 static struct platform_driver scpi_clocks_driver = {
303 .driver = {
304 .name = "scpi_clocks",
305 .of_match_table = scpi_clocks_ids,
306 },
307 .probe = scpi_clocks_probe,
308 .remove = scpi_clocks_remove,
309 };
310 module_platform_driver(scpi_clocks_driver);
311
312 MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
313 MODULE_DESCRIPTION("ARM SCPI clock driver");
314 MODULE_LICENSE("GPL v2");
315