1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 #define MBOX_DOWN_MSG 1
20 #define MBOX_UP_MSG 2
21
22 /* AF/PF: PF initiated, PF/VF VF initiated */
23 #define MBOX_DOWN_RX_START 0
24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27 /* AF/PF: AF initiated, PF/VF PF initiated */
28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29 #define MBOX_UP_RX_SIZE SZ_1K
30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31 #define MBOX_UP_TX_SIZE SZ_1K
32
33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34 # error "incorrect mailbox area sizes"
35 #endif
36
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38
39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
40
41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
42
43 /* Mailbox directions */
44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
52
53 struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
55 void *hwbase;
56 spinlock_t mbox_lock;
57 u16 msg_size; /* Total msg size to be sent */
58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
59 u16 num_msgs; /* No of msgs sent or waiting for response */
60 u16 msgs_acked; /* No of msgs for which response is received */
61 };
62
63 struct otx2_mbox {
64 struct pci_dev *pdev;
65 void *hwbase; /* Mbox region advertised by HW */
66 void *reg_base;/* CSR base for this dev */
67 u64 trigger; /* Trigger mbox notification */
68 u16 tr_shift; /* Mbox trigger shift */
69 u64 rx_start; /* Offset of Rx region in mbox memory */
70 u64 tx_start; /* Offset of Tx region in mbox memory */
71 u16 rx_size; /* Size of Rx region */
72 u16 tx_size; /* Size of Tx region */
73 u16 ndevs; /* The number of peers */
74 struct otx2_mbox_dev *dev;
75 };
76
77 /* Header which precedes all mbox messages */
78 struct mbox_hdr {
79 u64 msg_size; /* Total msgs size embedded */
80 u16 num_msgs; /* No of msgs embedded */
81 };
82
83 /* Header which precedes every msg and is also part of it */
84 struct mbox_msghdr {
85 u16 pcifunc; /* Who's sending this msg */
86 u16 id; /* Mbox message ID */
87 #define OTX2_MBOX_REQ_SIG (0xdead)
88 #define OTX2_MBOX_RSP_SIG (0xbeef)
89 u16 sig; /* Signature, for validating corrupted msgs */
90 #define OTX2_MBOX_VERSION (0x000a)
91 u16 ver; /* Version of msg's structure for this ID */
92 u16 next_msgoff; /* Offset of next msg within mailbox region */
93 int rc; /* Msg process'ed response code */
94 };
95
96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
98 void otx2_mbox_destroy(struct otx2_mbox *mbox);
99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
100 struct pci_dev *pdev, void __force *reg_base,
101 int direction, int ndevs);
102
103 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
104 struct pci_dev *pdev, void __force *reg_base,
105 int direction, int ndevs, unsigned long *bmap);
106 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
107 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid);
108 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
109 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
110 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
111 int size, int size_rsp);
112 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
113 struct mbox_msghdr *msg);
114 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
115 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
116 u16 pcifunc, u16 id);
117 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
118 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)119 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
120 int devid, int size)
121 {
122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
123 }
124
125 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid);
126
127 /* Mailbox message types */
128 #define MBOX_MSG_MASK 0xFFFF
129 #define MBOX_MSG_INVALID 0xFFFE
130 #define MBOX_MSG_MAX 0xFFFF
131
132 #define MBOX_MESSAGES \
133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
134 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
135 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
136 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
137 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
138 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
142 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
143 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
144 msg_rsp) \
145 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
146 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
147 M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \
148 M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \
149 M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \
150 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
151 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
152 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
153 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
154 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
155 cgx_mac_addr_set_or_get) \
156 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
157 cgx_mac_addr_set_or_get) \
158 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
159 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
160 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
161 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
162 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
163 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
164 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
165 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
166 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
167 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
168 cgx_pause_frm_cfg) \
169 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
170 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
171 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
172 cgx_mac_addr_add_rsp) \
173 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
174 msg_rsp) \
175 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
176 cgx_max_dmac_entries_get_rsp) \
177 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
178 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
179 cgx_set_link_mode_rsp) \
180 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
181 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
182 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
183 cgx_features_info_msg) \
184 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
185 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
186 msg_rsp) \
187 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
188 cgx_mac_addr_update_rsp) \
189 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
190 cgx_pfc_rsp) \
191 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
192 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
193 npa_lf_alloc_req, npa_lf_alloc_rsp) \
194 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
195 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
196 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
197 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
198 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
199 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
200 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
201 msg_rsp) \
202 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
203 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
204 cpt_rd_wr_reg_msg) \
205 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
206 cpt_inline_ipsec_cfg_msg, msg_rsp) \
207 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
208 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
209 msg_rsp) \
210 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
211 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
212 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
213 cpt_flt_eng_info_rsp) \
214 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
215 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
216 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
217 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
218 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
219 npc_mcam_alloc_entry_rsp) \
220 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
221 npc_mcam_free_entry_req, msg_rsp) \
222 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
223 npc_mcam_write_entry_req, msg_rsp) \
224 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
225 npc_mcam_ena_dis_entry_req, msg_rsp) \
226 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
227 npc_mcam_ena_dis_entry_req, msg_rsp) \
228 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
229 npc_mcam_shift_entry_rsp) \
230 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
231 npc_mcam_alloc_counter_req, \
232 npc_mcam_alloc_counter_rsp) \
233 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
234 npc_mcam_oper_counter_req, msg_rsp) \
235 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
236 npc_mcam_unmap_counter_req, msg_rsp) \
237 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
238 npc_mcam_oper_counter_req, msg_rsp) \
239 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
240 npc_mcam_oper_counter_req, \
241 npc_mcam_oper_counter_rsp) \
242 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
243 npc_mcam_alloc_and_write_entry_req, \
244 npc_mcam_alloc_and_write_entry_rsp) \
245 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
246 msg_req, npc_get_kex_cfg_rsp) \
247 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
248 npc_install_flow_req, npc_install_flow_rsp) \
249 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
250 npc_delete_flow_req, npc_delete_flow_rsp) \
251 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
252 npc_mcam_read_entry_req, \
253 npc_mcam_read_entry_rsp) \
254 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
255 npc_set_pkind, msg_rsp) \
256 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
257 msg_req, npc_mcam_read_base_rule_rsp) \
258 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
259 npc_mcam_get_stats_req, \
260 npc_mcam_get_stats_rsp) \
261 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
262 npc_get_field_hash_info_req, \
263 npc_get_field_hash_info_rsp) \
264 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
265 npc_get_field_status_req, \
266 npc_get_field_status_rsp) \
267 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
268 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
269 nix_lf_alloc_req, nix_lf_alloc_rsp) \
270 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
271 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
272 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
273 hwctx_disable_req, msg_rsp) \
274 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
275 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
276 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
277 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
278 nix_txschq_config) \
279 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
280 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
281 nix_vtag_config_rsp) \
282 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
283 nix_rss_flowkey_cfg, \
284 nix_rss_flowkey_cfg_rsp) \
285 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
286 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
287 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
288 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
289 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
290 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
291 nix_mark_format_cfg, \
292 nix_mark_format_cfg_rsp) \
293 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
294 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
295 nix_lso_format_cfg, \
296 nix_lso_format_cfg_rsp) \
297 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
298 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
299 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
300 nix_bp_cfg_rsp) \
301 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
302 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
303 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
304 nix_inline_ipsec_cfg, msg_rsp) \
305 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
306 nix_inline_ipsec_lf_cfg, msg_rsp) \
307 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
308 nix_cn10k_aq_enq_rsp) \
309 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
310 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
311 nix_bandprof_alloc_rsp) \
312 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
313 msg_rsp) \
314 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
315 nix_bandprof_get_hwinfo_rsp) \
316 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
317 msg_req, nix_inline_ipsec_cfg) \
318 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
319 nix_mcast_grp_create_rsp) \
320 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
321 msg_rsp) \
322 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
323 nix_mcast_grp_update_req, \
324 nix_mcast_grp_update_rsp) \
325 M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \
326 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
327 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
328 mcs_alloc_rsrc_rsp) \
329 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
330 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
331 msg_rsp) \
332 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
333 msg_rsp) \
334 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
335 msg_rsp) \
336 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
337 msg_rsp) \
338 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
339 msg_rsp) \
340 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
341 msg_rsp) \
342 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
343 msg_rsp) \
344 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
345 msg_rsp) \
346 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
347 msg_rsp) \
348 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
349 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
350 mcs_flowid_stats) \
351 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
352 mcs_secy_stats) \
353 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
354 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
355 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
356 mcs_port_stats) \
357 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
358 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
359 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
360 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
361 msg_rsp) \
362 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
363 mcs_alloc_ctrl_pkt_rule_req, \
364 mcs_alloc_ctrl_pkt_rule_rsp) \
365 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
366 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
367 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
368 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
369 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
370 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
371 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
372 mcs_port_cfg_get_rsp) \
373 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
374 mcs_custom_tag_cfg_get_req, \
375 mcs_custom_tag_cfg_get_rsp)
376
377 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
378 #define MBOX_UP_CGX_MESSAGES \
379 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
380
381 #define MBOX_UP_CPT_MESSAGES \
382 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
383
384 #define MBOX_UP_MCS_MESSAGES \
385 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
386
387 #define MBOX_UP_REP_MESSAGES \
388 M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \
389
390 enum {
391 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
392 MBOX_MESSAGES
393 MBOX_UP_CGX_MESSAGES
394 MBOX_UP_CPT_MESSAGES
395 MBOX_UP_MCS_MESSAGES
396 MBOX_UP_REP_MESSAGES
397 #undef M
398 };
399
400 /* Mailbox message formats */
401
402 #define RVU_DEFAULT_PF_FUNC 0xFFFF
403
404 /* Generic request msg used for those mbox messages which
405 * don't send any data in the request.
406 */
407 struct msg_req {
408 struct mbox_msghdr hdr;
409 };
410
411 /* Generic response msg used an ack or response for those mbox
412 * messages which don't have a specific rsp msg format.
413 */
414 struct msg_rsp {
415 struct mbox_msghdr hdr;
416 };
417
418 /* RVU mailbox error codes
419 * Range 256 - 300.
420 */
421 enum rvu_af_status {
422 RVU_INVALID_VF_ID = -256,
423 };
424
425 struct ready_msg_rsp {
426 struct mbox_msghdr hdr;
427 u16 sclk_freq; /* SCLK frequency (in MHz) */
428 u16 rclk_freq; /* RCLK frequency (in MHz) */
429 };
430
431 /* Structure for requesting resource provisioning.
432 * 'modify' flag to be used when either requesting more
433 * or to detach partial of a certain resource type.
434 * Rest of the fields specify how many of what type to
435 * be attached.
436 * To request LFs from two blocks of same type this mailbox
437 * can be sent twice as below:
438 * struct rsrc_attach *attach;
439 * .. Allocate memory for message ..
440 * attach->cptlfs = 3; <3 LFs from CPT0>
441 * .. Send message ..
442 * .. Allocate memory for message ..
443 * attach->modify = 1;
444 * attach->cpt_blkaddr = BLKADDR_CPT1;
445 * attach->cptlfs = 2; <2 LFs from CPT1>
446 * .. Send message ..
447 */
448 struct rsrc_attach {
449 struct mbox_msghdr hdr;
450 u8 modify:1;
451 u8 npalf:1;
452 u8 nixlf:1;
453 u16 sso;
454 u16 ssow;
455 u16 timlfs;
456 u16 cptlfs;
457 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
458 };
459
460 /* Structure for relinquishing resources.
461 * 'partial' flag to be used when relinquishing all resources
462 * but only of a certain type. If not set, all resources of all
463 * types provisioned to the RVU function will be detached.
464 */
465 struct rsrc_detach {
466 struct mbox_msghdr hdr;
467 u8 partial:1;
468 u8 npalf:1;
469 u8 nixlf:1;
470 u8 sso:1;
471 u8 ssow:1;
472 u8 timlfs:1;
473 u8 cptlfs:1;
474 };
475
476 /* Number of resources available to the caller.
477 * In reply to MBOX_MSG_FREE_RSRC_CNT.
478 */
479 struct free_rsrcs_rsp {
480 struct mbox_msghdr hdr;
481 u16 schq[NIX_TXSCH_LVL_CNT];
482 u16 sso;
483 u16 tim;
484 u16 ssow;
485 u16 cpt;
486 u8 npa;
487 u8 nix;
488 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
489 u8 nix1;
490 u8 cpt1;
491 u8 ree0;
492 u8 ree1;
493 };
494
495 #define MSIX_VECTOR_INVALID 0xFFFF
496 #define MAX_RVU_BLKLF_CNT 256
497
498 struct msix_offset_rsp {
499 struct mbox_msghdr hdr;
500 u16 npa_msixoff;
501 u16 nix_msixoff;
502 u16 sso;
503 u16 ssow;
504 u16 timlfs;
505 u16 cptlfs;
506 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
507 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
508 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
509 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
510 u16 cpt1_lfs;
511 u16 ree0_lfs;
512 u16 ree1_lfs;
513 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
514 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
515 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
516 };
517
518 struct get_hw_cap_rsp {
519 struct mbox_msghdr hdr;
520 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
521 u8 nix_shaping; /* Is shaping and coloring supported */
522 u8 npc_hash_extract; /* Is hash extract supported */
523 };
524
525 /* CGX mbox message formats */
526
527 struct cgx_stats_rsp {
528 struct mbox_msghdr hdr;
529 #define CGX_RX_STATS_COUNT 9
530 #define CGX_TX_STATS_COUNT 18
531 u64 rx_stats[CGX_RX_STATS_COUNT];
532 u64 tx_stats[CGX_TX_STATS_COUNT];
533 };
534
535 struct cgx_fec_stats_rsp {
536 struct mbox_msghdr hdr;
537 u64 fec_corr_blks;
538 u64 fec_uncorr_blks;
539 };
540 /* Structure for requesting the operation for
541 * setting/getting mac address in the CGX interface
542 */
543 struct cgx_mac_addr_set_or_get {
544 struct mbox_msghdr hdr;
545 u8 mac_addr[ETH_ALEN];
546 u32 index;
547 };
548
549 /* Structure for requesting the operation to
550 * add DMAC filter entry into CGX interface
551 */
552 struct cgx_mac_addr_add_req {
553 struct mbox_msghdr hdr;
554 u8 mac_addr[ETH_ALEN];
555 };
556
557 /* Structure for response against the operation to
558 * add DMAC filter entry into CGX interface
559 */
560 struct cgx_mac_addr_add_rsp {
561 struct mbox_msghdr hdr;
562 u32 index;
563 };
564
565 /* Structure for requesting the operation to
566 * delete DMAC filter entry from CGX interface
567 */
568 struct cgx_mac_addr_del_req {
569 struct mbox_msghdr hdr;
570 u32 index;
571 };
572
573 /* Structure for response against the operation to
574 * get maximum supported DMAC filter entries
575 */
576 struct cgx_max_dmac_entries_get_rsp {
577 struct mbox_msghdr hdr;
578 u32 max_dmac_filters;
579 };
580
581 struct cgx_link_user_info {
582 uint64_t link_up:1;
583 uint64_t full_duplex:1;
584 uint64_t lmac_type_id:4;
585 uint64_t speed:20; /* speed in Mbps */
586 uint64_t an:1; /* AN supported or not */
587 uint64_t fec:2; /* FEC type if enabled else 0 */
588 #define LMACTYPE_STR_LEN 16
589 char lmac_type[LMACTYPE_STR_LEN];
590 };
591
592 struct cgx_link_info_msg {
593 struct mbox_msghdr hdr;
594 struct cgx_link_user_info link_info;
595 };
596
597 struct cgx_pause_frm_cfg {
598 struct mbox_msghdr hdr;
599 u8 set;
600 /* set = 1 if the request is to config pause frames */
601 /* set = 0 if the request is to fetch pause frames config */
602 u8 rx_pause;
603 u8 tx_pause;
604 };
605
606 enum fec_type {
607 OTX2_FEC_NONE,
608 OTX2_FEC_BASER,
609 OTX2_FEC_RS,
610 OTX2_FEC_STATS_CNT = 2,
611 OTX2_FEC_OFF,
612 };
613
614 struct fec_mode {
615 struct mbox_msghdr hdr;
616 int fec;
617 };
618
619 struct sfp_eeprom_s {
620 #define SFP_EEPROM_SIZE 256
621 u16 sff_id;
622 u8 buf[SFP_EEPROM_SIZE];
623 u64 reserved;
624 };
625
626 struct phy_s {
627 struct {
628 u64 can_change_mod_type:1;
629 u64 mod_type:1;
630 u64 has_fec_stats:1;
631 } misc;
632 struct fec_stats_s {
633 u32 rsfec_corr_cws;
634 u32 rsfec_uncorr_cws;
635 u32 brfec_corr_blks;
636 u32 brfec_uncorr_blks;
637 } fec_stats;
638 };
639
640 struct cgx_lmac_fwdata_s {
641 u16 rw_valid;
642 u64 supported_fec;
643 u64 supported_an;
644 u64 supported_link_modes;
645 /* only applicable if AN is supported */
646 u64 advertised_fec;
647 u64 advertised_link_modes;
648 /* Only applicable if SFP/QSFP slot is present */
649 struct sfp_eeprom_s sfp_eeprom;
650 struct phy_s phy;
651 #define LMAC_FWDATA_RESERVED_MEM 1021
652 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
653 };
654
655 struct cgx_fw_data {
656 struct mbox_msghdr hdr;
657 struct cgx_lmac_fwdata_s fwdata;
658 };
659
660 struct cgx_set_link_mode_args {
661 u32 speed;
662 u8 duplex;
663 u8 an;
664 u8 ports;
665 u64 mode;
666 };
667
668 struct cgx_set_link_mode_req {
669 #define AUTONEG_UNKNOWN 0xff
670 struct mbox_msghdr hdr;
671 struct cgx_set_link_mode_args args;
672 };
673
674 struct cgx_set_link_mode_rsp {
675 struct mbox_msghdr hdr;
676 int status;
677 };
678
679 struct cgx_mac_addr_reset_req {
680 struct mbox_msghdr hdr;
681 u32 index;
682 };
683
684 struct cgx_mac_addr_update_req {
685 struct mbox_msghdr hdr;
686 u8 mac_addr[ETH_ALEN];
687 u32 index;
688 };
689
690 struct cgx_mac_addr_update_rsp {
691 struct mbox_msghdr hdr;
692 u32 index;
693 };
694
695 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
696 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
697 /* flow control from physical link higig2 messages */
698 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
699 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
700 #define RVU_MAC_VERSION BIT_ULL(4)
701 #define RVU_MAC_CGX BIT_ULL(5)
702 #define RVU_MAC_RPM BIT_ULL(6)
703
704 struct cgx_features_info_msg {
705 struct mbox_msghdr hdr;
706 u64 lmac_features;
707 };
708
709 struct rpm_stats_rsp {
710 struct mbox_msghdr hdr;
711 #define RPM_RX_STATS_COUNT 43
712 #define RPM_TX_STATS_COUNT 34
713 u64 rx_stats[RPM_RX_STATS_COUNT];
714 u64 tx_stats[RPM_TX_STATS_COUNT];
715 };
716
717 struct cgx_pfc_cfg {
718 struct mbox_msghdr hdr;
719 u8 rx_pause;
720 u8 tx_pause;
721 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
722 };
723
724 struct cgx_pfc_rsp {
725 struct mbox_msghdr hdr;
726 u8 rx_pause;
727 u8 tx_pause;
728 };
729
730 /* NPA mbox message formats */
731
732 struct npc_set_pkind {
733 struct mbox_msghdr hdr;
734 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
735 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
736 u64 mode;
737 #define PKIND_TX BIT_ULL(0)
738 #define PKIND_RX BIT_ULL(1)
739 u8 dir;
740 u8 pkind; /* valid only in case custom flag */
741 u8 var_len_off; /* Offset of custom header length field.
742 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
743 */
744 u8 var_len_off_mask; /* Mask for length with in offset */
745 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
746 };
747
748 /* NPA mbox message formats */
749
750 /* NPA mailbox error codes
751 * Range 301 - 400.
752 */
753 enum npa_af_status {
754 NPA_AF_ERR_PARAM = -301,
755 NPA_AF_ERR_AQ_FULL = -302,
756 NPA_AF_ERR_AQ_ENQUEUE = -303,
757 NPA_AF_ERR_AF_LF_INVALID = -304,
758 NPA_AF_ERR_AF_LF_ALLOC = -305,
759 NPA_AF_ERR_LF_RESET = -306,
760 };
761
762 /* For NPA LF context alloc and init */
763 struct npa_lf_alloc_req {
764 struct mbox_msghdr hdr;
765 int node;
766 int aura_sz; /* No of auras */
767 u32 nr_pools; /* No of pools */
768 u64 way_mask;
769 };
770
771 struct npa_lf_alloc_rsp {
772 struct mbox_msghdr hdr;
773 u32 stack_pg_ptrs; /* No of ptrs per stack page */
774 u32 stack_pg_bytes; /* Size of stack page */
775 u16 qints; /* NPA_AF_CONST::QINTS */
776 u8 cache_lines; /*BATCH ALLOC DMA */
777 };
778
779 /* NPA AQ enqueue msg */
780 struct npa_aq_enq_req {
781 struct mbox_msghdr hdr;
782 u32 aura_id;
783 u8 ctype;
784 u8 op;
785 union {
786 /* Valid when op == WRITE/INIT and ctype == AURA.
787 * LF fills the pool_id in aura.pool_addr. AF will translate
788 * the pool_id to pool context pointer.
789 */
790 struct npa_aura_s aura;
791 /* Valid when op == WRITE/INIT and ctype == POOL */
792 struct npa_pool_s pool;
793 };
794 /* Mask data when op == WRITE (1=write, 0=don't write) */
795 union {
796 /* Valid when op == WRITE and ctype == AURA */
797 struct npa_aura_s aura_mask;
798 /* Valid when op == WRITE and ctype == POOL */
799 struct npa_pool_s pool_mask;
800 };
801 };
802
803 struct npa_aq_enq_rsp {
804 struct mbox_msghdr hdr;
805 union {
806 /* Valid when op == READ and ctype == AURA */
807 struct npa_aura_s aura;
808 /* Valid when op == READ and ctype == POOL */
809 struct npa_pool_s pool;
810 };
811 };
812
813 /* Disable all contexts of type 'ctype' */
814 struct hwctx_disable_req {
815 struct mbox_msghdr hdr;
816 u8 ctype;
817 };
818
819 /* NIX mbox message formats */
820
821 /* NIX mailbox error codes
822 * Range 401 - 500.
823 */
824 enum nix_af_status {
825 NIX_AF_ERR_PARAM = -401,
826 NIX_AF_ERR_AQ_FULL = -402,
827 NIX_AF_ERR_AQ_ENQUEUE = -403,
828 NIX_AF_ERR_AF_LF_INVALID = -404,
829 NIX_AF_ERR_AF_LF_ALLOC = -405,
830 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
831 NIX_AF_ERR_TLX_INVALID = -407,
832 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
833 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
834 NIX_AF_ERR_FRS_INVALID = -410,
835 NIX_AF_ERR_RX_LINK_INVALID = -411,
836 NIX_AF_INVAL_TXSCHQ_CFG = -412,
837 NIX_AF_SMQ_FLUSH_FAILED = -413,
838 NIX_AF_ERR_LF_RESET = -414,
839 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
840 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
841 NIX_AF_ERR_MARK_CFG_FAIL = -417,
842 NIX_AF_ERR_LSO_CFG_FAIL = -418,
843 NIX_AF_INVAL_NPA_PF_FUNC = -419,
844 NIX_AF_INVAL_SSO_PF_FUNC = -420,
845 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
846 NIX_AF_ERR_RX_VTAG_INUSE = -422,
847 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
848 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
849 NIX_AF_ERR_INVALID_NIXBLK = -425,
850 NIX_AF_ERR_INVALID_BANDPROF = -426,
851 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
852 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
853 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
854 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
855 NIX_AF_ERR_LINK_CREDITS = -431,
856 NIX_AF_ERR_INVALID_BPID = -434,
857 NIX_AF_ERR_INVALID_BPID_REQ = -435,
858 NIX_AF_ERR_INVALID_MCAST_GRP = -436,
859 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
860 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,
861 };
862
863 /* For NIX RX vtag action */
864 enum nix_rx_vtag0_type {
865 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
866 NIX_AF_LFX_RX_VTAG_TYPE1,
867 NIX_AF_LFX_RX_VTAG_TYPE2,
868 NIX_AF_LFX_RX_VTAG_TYPE3,
869 NIX_AF_LFX_RX_VTAG_TYPE4,
870 NIX_AF_LFX_RX_VTAG_TYPE5,
871 NIX_AF_LFX_RX_VTAG_TYPE6,
872 NIX_AF_LFX_RX_VTAG_TYPE7,
873 };
874
875 /* For NIX LF context alloc and init */
876 struct nix_lf_alloc_req {
877 struct mbox_msghdr hdr;
878 int node;
879 u32 rq_cnt; /* No of receive queues */
880 u32 sq_cnt; /* No of send queues */
881 u32 cq_cnt; /* No of completion queues */
882 u8 xqe_sz;
883 u16 rss_sz;
884 u8 rss_grps;
885 u16 npa_func;
886 u16 sso_func;
887 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
888 u64 way_mask;
889 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
890 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
891 u64 flags;
892 };
893
894 struct nix_lf_alloc_rsp {
895 struct mbox_msghdr hdr;
896 u16 sqb_size;
897 u16 rx_chan_base;
898 u16 tx_chan_base;
899 u8 rx_chan_cnt; /* total number of RX channels */
900 u8 tx_chan_cnt; /* total number of TX channels */
901 u8 lso_tsov4_idx;
902 u8 lso_tsov6_idx;
903 u8 mac_addr[ETH_ALEN];
904 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
905 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
906 u16 cints; /* NIX_AF_CONST2::CINTS */
907 u16 qints; /* NIX_AF_CONST2::QINTS */
908 u8 cgx_links; /* No. of CGX links present in HW */
909 u8 lbk_links; /* No. of LBK links present in HW */
910 u8 sdp_links; /* No. of SDP links present in HW */
911 u8 tx_link; /* Transmit channel link number */
912 };
913
914 struct nix_lf_free_req {
915 struct mbox_msghdr hdr;
916 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
917 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
918 u64 flags;
919 };
920
921 /* CN10K NIX AQ enqueue msg */
922 struct nix_cn10k_aq_enq_req {
923 struct mbox_msghdr hdr;
924 u32 qidx;
925 u8 ctype;
926 u8 op;
927 union {
928 struct nix_cn10k_rq_ctx_s rq;
929 struct nix_cn10k_sq_ctx_s sq;
930 struct nix_cq_ctx_s cq;
931 struct nix_rsse_s rss;
932 struct nix_rx_mce_s mce;
933 struct nix_bandprof_s prof;
934 };
935 union {
936 struct nix_cn10k_rq_ctx_s rq_mask;
937 struct nix_cn10k_sq_ctx_s sq_mask;
938 struct nix_cq_ctx_s cq_mask;
939 struct nix_rsse_s rss_mask;
940 struct nix_rx_mce_s mce_mask;
941 struct nix_bandprof_s prof_mask;
942 };
943 };
944
945 struct nix_cn10k_aq_enq_rsp {
946 struct mbox_msghdr hdr;
947 union {
948 struct nix_cn10k_rq_ctx_s rq;
949 struct nix_cn10k_sq_ctx_s sq;
950 struct nix_cq_ctx_s cq;
951 struct nix_rsse_s rss;
952 struct nix_rx_mce_s mce;
953 struct nix_bandprof_s prof;
954 };
955 };
956
957 /* NIX AQ enqueue msg */
958 struct nix_aq_enq_req {
959 struct mbox_msghdr hdr;
960 u32 qidx;
961 u8 ctype;
962 u8 op;
963 union {
964 struct nix_rq_ctx_s rq;
965 struct nix_sq_ctx_s sq;
966 struct nix_cq_ctx_s cq;
967 struct nix_rsse_s rss;
968 struct nix_rx_mce_s mce;
969 struct nix_bandprof_s prof;
970 };
971 union {
972 struct nix_rq_ctx_s rq_mask;
973 struct nix_sq_ctx_s sq_mask;
974 struct nix_cq_ctx_s cq_mask;
975 struct nix_rsse_s rss_mask;
976 struct nix_rx_mce_s mce_mask;
977 struct nix_bandprof_s prof_mask;
978 };
979 };
980
981 struct nix_aq_enq_rsp {
982 struct mbox_msghdr hdr;
983 union {
984 struct nix_rq_ctx_s rq;
985 struct nix_sq_ctx_s sq;
986 struct nix_cq_ctx_s cq;
987 struct nix_rsse_s rss;
988 struct nix_rx_mce_s mce;
989 struct nix_bandprof_s prof;
990 };
991 };
992
993 /* Tx scheduler/shaper mailbox messages */
994
995 #define MAX_TXSCHQ_PER_FUNC 128
996
997 struct nix_txsch_alloc_req {
998 struct mbox_msghdr hdr;
999 /* Scheduler queue count request at each level */
1000 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
1001 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
1002 };
1003
1004 struct nix_txsch_alloc_rsp {
1005 struct mbox_msghdr hdr;
1006 /* Scheduler queue count allocated at each level */
1007 u16 schq_contig[NIX_TXSCH_LVL_CNT];
1008 u16 schq[NIX_TXSCH_LVL_CNT];
1009 /* Scheduler queue list allocated at each level */
1010 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1011 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1012 u8 aggr_level; /* Traffic aggregation scheduler level */
1013 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
1014 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
1015 };
1016
1017 struct nix_txsch_free_req {
1018 struct mbox_msghdr hdr;
1019 #define TXSCHQ_FREE_ALL BIT_ULL(0)
1020 u16 flags;
1021 /* Scheduler queue level to be freed */
1022 u16 schq_lvl;
1023 /* List of scheduler queues to be freed */
1024 u16 schq;
1025 };
1026
1027 struct nix_txschq_config {
1028 struct mbox_msghdr hdr;
1029 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1030 u8 read;
1031 #define TXSCHQ_IDX_SHIFT 16
1032 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
1033 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1034 u8 num_regs;
1035 #define MAX_REGS_PER_MBOX_MSG 20
1036 u64 reg[MAX_REGS_PER_MBOX_MSG];
1037 u64 regval[MAX_REGS_PER_MBOX_MSG];
1038 /* All 0's => overwrite with new value */
1039 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1040 };
1041
1042 struct nix_vtag_config {
1043 struct mbox_msghdr hdr;
1044 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1045 u8 vtag_size;
1046 /* cfg_type is '0' for tx vlan cfg
1047 * cfg_type is '1' for rx vlan cfg
1048 */
1049 u8 cfg_type;
1050 union {
1051 /* valid when cfg_type is '0' */
1052 struct {
1053 u64 vtag0;
1054 u64 vtag1;
1055
1056 /* cfg_vtag0 & cfg_vtag1 fields are valid
1057 * when free_vtag0 & free_vtag1 are '0's.
1058 */
1059 /* cfg_vtag0 = 1 to configure vtag0 */
1060 u8 cfg_vtag0 :1;
1061 /* cfg_vtag1 = 1 to configure vtag1 */
1062 u8 cfg_vtag1 :1;
1063
1064 /* vtag0_idx & vtag1_idx are only valid when
1065 * both cfg_vtag0 & cfg_vtag1 are '0's,
1066 * these fields are used along with free_vtag0
1067 * & free_vtag1 to free the nix lf's tx_vlan
1068 * configuration.
1069 *
1070 * Denotes the indices of tx_vtag def registers
1071 * that needs to be cleared and freed.
1072 */
1073 int vtag0_idx;
1074 int vtag1_idx;
1075
1076 /* free_vtag0 & free_vtag1 fields are valid
1077 * when cfg_vtag0 & cfg_vtag1 are '0's.
1078 */
1079 /* free_vtag0 = 1 clears vtag0 configuration
1080 * vtag0_idx denotes the index to be cleared.
1081 */
1082 u8 free_vtag0 :1;
1083 /* free_vtag1 = 1 clears vtag1 configuration
1084 * vtag1_idx denotes the index to be cleared.
1085 */
1086 u8 free_vtag1 :1;
1087 } tx;
1088
1089 /* valid when cfg_type is '1' */
1090 struct {
1091 /* rx vtag type index, valid values are in 0..7 range */
1092 u8 vtag_type;
1093 /* rx vtag strip */
1094 u8 strip_vtag :1;
1095 /* rx vtag capture */
1096 u8 capture_vtag :1;
1097 } rx;
1098 };
1099 };
1100
1101 struct nix_vtag_config_rsp {
1102 struct mbox_msghdr hdr;
1103 int vtag0_idx;
1104 int vtag1_idx;
1105 /* Indices of tx_vtag def registers used to configure
1106 * tx vtag0 & vtag1 headers, these indices are valid
1107 * when nix_vtag_config mbox requested for vtag0 and/
1108 * or vtag1 configuration.
1109 */
1110 };
1111
1112 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1113
1114 struct nix_rss_flowkey_cfg {
1115 struct mbox_msghdr hdr;
1116 int mcam_index; /* MCAM entry index to modify */
1117 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1118 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1119 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1120 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1121 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1122 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1123 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1124 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1125 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1126 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1127 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1128 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1129 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1130 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1131 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1132 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1133 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1134 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1135 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1136 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1137 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1138 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1139 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1140 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1141 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1142 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1143 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1144 u32 flowkey_cfg; /* Flowkey types selected */
1145 u8 group; /* RSS context or group */
1146 };
1147
1148 struct nix_rss_flowkey_cfg_rsp {
1149 struct mbox_msghdr hdr;
1150 u8 alg_idx; /* Selected algo index */
1151 };
1152
1153 struct nix_set_mac_addr {
1154 struct mbox_msghdr hdr;
1155 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1156 };
1157
1158 struct nix_get_mac_addr_rsp {
1159 struct mbox_msghdr hdr;
1160 u8 mac_addr[ETH_ALEN];
1161 };
1162
1163 struct nix_mark_format_cfg {
1164 struct mbox_msghdr hdr;
1165 u8 offset;
1166 u8 y_mask;
1167 u8 y_val;
1168 u8 r_mask;
1169 u8 r_val;
1170 };
1171
1172 struct nix_mark_format_cfg_rsp {
1173 struct mbox_msghdr hdr;
1174 u8 mark_format_idx;
1175 };
1176
1177 struct nix_rx_mode {
1178 struct mbox_msghdr hdr;
1179 #define NIX_RX_MODE_UCAST BIT(0)
1180 #define NIX_RX_MODE_PROMISC BIT(1)
1181 #define NIX_RX_MODE_ALLMULTI BIT(2)
1182 #define NIX_RX_MODE_USE_MCE BIT(3)
1183 u16 mode;
1184 };
1185
1186 struct nix_rx_cfg {
1187 struct mbox_msghdr hdr;
1188 #define NIX_RX_OL3_VERIFY BIT(0)
1189 #define NIX_RX_OL4_VERIFY BIT(1)
1190 #define NIX_RX_DROP_RE BIT(2)
1191 u8 len_verify; /* Outer L3/L4 len check */
1192 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1193 u8 csum_verify; /* Outer L4 checksum verification */
1194 };
1195
1196 struct nix_frs_cfg {
1197 struct mbox_msghdr hdr;
1198 u8 update_smq; /* Update SMQ's min/max lens */
1199 u8 update_minlen; /* Set minlen also */
1200 u8 sdp_link; /* Set SDP RX link */
1201 u16 maxlen;
1202 u16 minlen;
1203 };
1204
1205 struct nix_lso_format_cfg {
1206 struct mbox_msghdr hdr;
1207 u64 field_mask;
1208 #define NIX_LSO_FIELD_MAX 8
1209 u64 fields[NIX_LSO_FIELD_MAX];
1210 };
1211
1212 struct nix_lso_format_cfg_rsp {
1213 struct mbox_msghdr hdr;
1214 u8 lso_format_idx;
1215 };
1216
1217 struct nix_bp_cfg_req {
1218 struct mbox_msghdr hdr;
1219 u16 chan_base; /* Starting channel number */
1220 u8 chan_cnt; /* Number of channels */
1221 u8 bpid_per_chan;
1222 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1223 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1224 };
1225
1226 /* Maximum channels any single NIX interface can have */
1227 #define NIX_MAX_BPID_CHAN 256
1228 struct nix_bp_cfg_rsp {
1229 struct mbox_msghdr hdr;
1230 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1231 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1232 };
1233
1234 struct nix_mcast_grp_create_req {
1235 struct mbox_msghdr hdr;
1236 #define NIX_MCAST_INGRESS 0
1237 #define NIX_MCAST_EGRESS 1
1238 u8 dir;
1239 u8 reserved[11];
1240 /* Reserving few bytes for future requirement */
1241 };
1242
1243 struct nix_mcast_grp_create_rsp {
1244 struct mbox_msghdr hdr;
1245 /* This mcast_grp_idx should be passed during MCAM
1246 * write entry for multicast. AF will identify the
1247 * corresponding multicast table index associated
1248 * with the group id and program the same to MCAM entry.
1249 * This group id is also needed during group delete
1250 * and update request.
1251 */
1252 u32 mcast_grp_idx;
1253 };
1254
1255 struct nix_mcast_grp_destroy_req {
1256 struct mbox_msghdr hdr;
1257 /* Group id returned by nix_mcast_grp_create_rsp */
1258 u32 mcast_grp_idx;
1259 /* If AF is requesting for destroy, then set
1260 * it to '1'. Otherwise keep it to '0'
1261 */
1262 u8 is_af;
1263 };
1264
1265 struct nix_mcast_grp_update_req {
1266 struct mbox_msghdr hdr;
1267 /* Group id returned by nix_mcast_grp_create_rsp */
1268 u32 mcast_grp_idx;
1269 /* Number of multicast/mirror entries requested */
1270 u32 num_mce_entry;
1271 #define NIX_MCE_ENTRY_MAX 64
1272 #define NIX_RX_RQ 0
1273 #define NIX_RX_RSS 1
1274 /* Receive queue or RSS index within pf_func */
1275 u32 rq_rss_index[NIX_MCE_ENTRY_MAX];
1276 /* pcifunc is required for both ingress and egress multicast */
1277 u16 pcifunc[NIX_MCE_ENTRY_MAX];
1278 /* channel is required for egress multicast */
1279 u16 channel[NIX_MCE_ENTRY_MAX];
1280 #define NIX_MCAST_OP_ADD_ENTRY 0
1281 #define NIX_MCAST_OP_DEL_ENTRY 1
1282 /* Destination type. 0:Receive queue, 1:RSS*/
1283 u8 dest_type[NIX_MCE_ENTRY_MAX];
1284 u8 op;
1285 /* If AF is requesting for update, then set
1286 * it to '1'. Otherwise keep it to '0'
1287 */
1288 u8 is_af;
1289 };
1290
1291 struct nix_mcast_grp_update_rsp {
1292 struct mbox_msghdr hdr;
1293 u32 mce_start_index;
1294 };
1295
1296 /* Global NIX inline IPSec configuration */
1297 struct nix_inline_ipsec_cfg {
1298 struct mbox_msghdr hdr;
1299 u32 cpt_credit;
1300 struct {
1301 u8 egrp;
1302 u16 opcode;
1303 u16 param1;
1304 u16 param2;
1305 } gen_cfg;
1306 struct {
1307 u16 cpt_pf_func;
1308 u8 cpt_slot;
1309 } inst_qsel;
1310 u8 enable;
1311 u16 bpid;
1312 u32 credit_th;
1313 };
1314
1315 /* Per NIX LF inline IPSec configuration */
1316 struct nix_inline_ipsec_lf_cfg {
1317 struct mbox_msghdr hdr;
1318 u64 sa_base_addr;
1319 struct {
1320 u32 tag_const;
1321 u16 lenm1_max;
1322 u8 sa_pow2_size;
1323 u8 tt;
1324 } ipsec_cfg0;
1325 struct {
1326 u32 sa_idx_max;
1327 u8 sa_idx_w;
1328 } ipsec_cfg1;
1329 u8 enable;
1330 };
1331
1332 struct nix_hw_info {
1333 struct mbox_msghdr hdr;
1334 u16 rsvs16;
1335 u16 max_mtu;
1336 u16 min_mtu;
1337 u32 rpm_dwrr_mtu;
1338 u32 sdp_dwrr_mtu;
1339 u32 lbk_dwrr_mtu;
1340 u32 rsvd32[1];
1341 u64 rsvd[15]; /* Add reserved fields for future expansion */
1342 };
1343
1344 struct nix_bandprof_alloc_req {
1345 struct mbox_msghdr hdr;
1346 /* Count of profiles needed per layer */
1347 u16 prof_count[BAND_PROF_NUM_LAYERS];
1348 };
1349
1350 struct nix_bandprof_alloc_rsp {
1351 struct mbox_msghdr hdr;
1352 u16 prof_count[BAND_PROF_NUM_LAYERS];
1353
1354 /* There is no need to allocate morethan 1 bandwidth profile
1355 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1356 * profiles to 64 per PF_FUNC.
1357 */
1358 #define MAX_BANDPROF_PER_PFFUNC 64
1359 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1360 };
1361
1362 struct nix_bandprof_free_req {
1363 struct mbox_msghdr hdr;
1364 u8 free_all;
1365 u16 prof_count[BAND_PROF_NUM_LAYERS];
1366 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1367 };
1368
1369 struct nix_bandprof_get_hwinfo_rsp {
1370 struct mbox_msghdr hdr;
1371 u16 prof_count[BAND_PROF_NUM_LAYERS];
1372 u32 policer_timeunit;
1373 };
1374
1375 struct nix_stats_req {
1376 struct mbox_msghdr hdr;
1377 u8 reset;
1378 u16 pcifunc;
1379 u64 rsvd;
1380 };
1381
1382 struct nix_stats_rsp {
1383 struct mbox_msghdr hdr;
1384 u16 pcifunc;
1385 struct {
1386 u64 octs;
1387 u64 ucast;
1388 u64 bcast;
1389 u64 mcast;
1390 u64 drop;
1391 u64 drop_octs;
1392 u64 drop_mcast;
1393 u64 drop_bcast;
1394 u64 err;
1395 u64 rsvd[5];
1396 } rx;
1397 struct {
1398 u64 ucast;
1399 u64 bcast;
1400 u64 mcast;
1401 u64 drop;
1402 u64 octs;
1403 } tx;
1404 };
1405
1406 /* NPC mbox message structs */
1407
1408 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1409 #define NPC_MCAM_INVALID_MAP 0xFFFF
1410
1411 /* NPC mailbox error codes
1412 * Range 701 - 800.
1413 */
1414 enum npc_af_status {
1415 NPC_MCAM_INVALID_REQ = -701,
1416 NPC_MCAM_ALLOC_DENIED = -702,
1417 NPC_MCAM_ALLOC_FAILED = -703,
1418 NPC_MCAM_PERM_DENIED = -704,
1419 NPC_FLOW_INTF_INVALID = -707,
1420 NPC_FLOW_CHAN_INVALID = -708,
1421 NPC_FLOW_NO_NIXLF = -709,
1422 NPC_FLOW_NOT_SUPPORTED = -710,
1423 NPC_FLOW_VF_PERM_DENIED = -711,
1424 NPC_FLOW_VF_NOT_INIT = -712,
1425 NPC_FLOW_VF_OVERLAP = -713,
1426 };
1427
1428 struct npc_mcam_alloc_entry_req {
1429 struct mbox_msghdr hdr;
1430 #define NPC_MAX_NONCONTIG_ENTRIES 256
1431 u8 contig; /* Contiguous entries ? */
1432 #define NPC_MCAM_ANY_PRIO 0
1433 #define NPC_MCAM_LOWER_PRIO 1
1434 #define NPC_MCAM_HIGHER_PRIO 2
1435 u8 priority; /* Lower or higher w.r.t ref_entry */
1436 u16 ref_entry;
1437 u16 count; /* Number of entries requested */
1438 };
1439
1440 struct npc_mcam_alloc_entry_rsp {
1441 struct mbox_msghdr hdr;
1442 u16 entry; /* Entry allocated or start index if contiguous.
1443 * Invalid incase of non-contiguous.
1444 */
1445 u16 count; /* Number of entries allocated */
1446 u16 free_count; /* Number of entries available */
1447 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1448 };
1449
1450 struct npc_mcam_free_entry_req {
1451 struct mbox_msghdr hdr;
1452 u16 entry; /* Entry index to be freed */
1453 u8 all; /* If all entries allocated to this PFVF to be freed */
1454 };
1455
1456 struct mcam_entry {
1457 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1458 u64 kw[NPC_MAX_KWS_IN_KEY];
1459 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1460 u64 action;
1461 u64 vtag_action;
1462 };
1463
1464 struct npc_mcam_write_entry_req {
1465 struct mbox_msghdr hdr;
1466 struct mcam_entry entry_data;
1467 u16 entry; /* MCAM entry to write this match key */
1468 u16 cntr; /* Counter for this MCAM entry */
1469 u8 intf; /* Rx or Tx interface */
1470 u8 enable_entry;/* Enable this MCAM entry ? */
1471 u8 set_cntr; /* Set counter for this entry ? */
1472 };
1473
1474 /* Enable/Disable a given entry */
1475 struct npc_mcam_ena_dis_entry_req {
1476 struct mbox_msghdr hdr;
1477 u16 entry;
1478 };
1479
1480 struct npc_mcam_shift_entry_req {
1481 struct mbox_msghdr hdr;
1482 #define NPC_MCAM_MAX_SHIFTS 64
1483 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1484 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1485 u16 shift_count; /* Number of entries to shift */
1486 };
1487
1488 struct npc_mcam_shift_entry_rsp {
1489 struct mbox_msghdr hdr;
1490 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1491 };
1492
1493 struct npc_mcam_alloc_counter_req {
1494 struct mbox_msghdr hdr;
1495 u8 contig; /* Contiguous counters ? */
1496 #define NPC_MAX_NONCONTIG_COUNTERS 64
1497 u16 count; /* Number of counters requested */
1498 };
1499
1500 struct npc_mcam_alloc_counter_rsp {
1501 struct mbox_msghdr hdr;
1502 u16 cntr; /* Counter allocated or start index if contiguous.
1503 * Invalid incase of non-contiguous.
1504 */
1505 u16 count; /* Number of counters allocated */
1506 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1507 };
1508
1509 struct npc_mcam_oper_counter_req {
1510 struct mbox_msghdr hdr;
1511 u16 cntr; /* Free a counter or clear/fetch it's stats */
1512 };
1513
1514 struct npc_mcam_oper_counter_rsp {
1515 struct mbox_msghdr hdr;
1516 u64 stat; /* valid only while fetching counter's stats */
1517 };
1518
1519 struct npc_mcam_unmap_counter_req {
1520 struct mbox_msghdr hdr;
1521 u16 cntr;
1522 u16 entry; /* Entry and counter to be unmapped */
1523 u8 all; /* Unmap all entries using this counter ? */
1524 };
1525
1526 struct npc_mcam_alloc_and_write_entry_req {
1527 struct mbox_msghdr hdr;
1528 struct mcam_entry entry_data;
1529 u16 ref_entry;
1530 u8 priority; /* Lower or higher w.r.t ref_entry */
1531 u8 intf; /* Rx or Tx interface */
1532 u8 enable_entry;/* Enable this MCAM entry ? */
1533 u8 alloc_cntr; /* Allocate counter and map ? */
1534 };
1535
1536 struct npc_mcam_alloc_and_write_entry_rsp {
1537 struct mbox_msghdr hdr;
1538 u16 entry;
1539 u16 cntr;
1540 };
1541
1542 struct npc_get_kex_cfg_rsp {
1543 struct mbox_msghdr hdr;
1544 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1545 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1546 #define NPC_MAX_INTF 2
1547 #define NPC_MAX_LID 8
1548 #define NPC_MAX_LT 16
1549 #define NPC_MAX_LD 2
1550 #define NPC_MAX_LFL 16
1551 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1552 u64 kex_ld_flags[NPC_MAX_LD];
1553 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1554 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1555 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1556 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1557 #define MKEX_NAME_LEN 128
1558 u8 mkex_pfl_name[MKEX_NAME_LEN];
1559 };
1560
1561 struct ptp_get_cap_rsp {
1562 struct mbox_msghdr hdr;
1563 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
1564 u64 cap;
1565 };
1566
1567 struct get_rep_cnt_rsp {
1568 struct mbox_msghdr hdr;
1569 u16 rep_cnt;
1570 u16 rep_pf_map[64];
1571 u64 rsvd;
1572 };
1573
1574 struct esw_cfg_req {
1575 struct mbox_msghdr hdr;
1576 u8 ena;
1577 u64 rsvd;
1578 };
1579
1580 struct rep_evt_data {
1581 u8 port_state;
1582 u8 vf_state;
1583 u16 rx_mode;
1584 u16 rx_flags;
1585 u16 mtu;
1586 u8 mac[ETH_ALEN];
1587 u64 rsvd[5];
1588 };
1589
1590 struct rep_event {
1591 struct mbox_msghdr hdr;
1592 u16 pcifunc;
1593 #define RVU_EVENT_PORT_STATE BIT_ULL(0)
1594 #define RVU_EVENT_PFVF_STATE BIT_ULL(1)
1595 #define RVU_EVENT_MTU_CHANGE BIT_ULL(2)
1596 #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3)
1597 #define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4)
1598 u16 event;
1599 struct rep_evt_data evt_data;
1600 };
1601
1602 struct flow_msg {
1603 unsigned char dmac[6];
1604 unsigned char smac[6];
1605 __be16 etype;
1606 __be16 vlan_etype;
1607 __be16 vlan_tci;
1608 union {
1609 __be32 ip4src;
1610 __be32 ip6src[4];
1611 };
1612 union {
1613 __be32 ip4dst;
1614 __be32 ip6dst[4];
1615 };
1616 union {
1617 __be32 spi;
1618 };
1619
1620 u8 tos;
1621 u8 ip_ver;
1622 u8 ip_proto;
1623 u8 tc;
1624 __be16 sport;
1625 __be16 dport;
1626 union {
1627 u8 ip_flag;
1628 u8 next_header;
1629 };
1630 __be16 vlan_itci;
1631 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)
1632 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)
1633 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8)
1634 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)
1635 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)
1636 u32 mpls_lse[4];
1637 u8 icmp_type;
1638 u8 icmp_code;
1639 __be16 tcp_flags;
1640 u16 sq_id;
1641 };
1642
1643 struct npc_install_flow_req {
1644 struct mbox_msghdr hdr;
1645 struct flow_msg packet;
1646 struct flow_msg mask;
1647 u64 features;
1648 u16 entry;
1649 u16 channel;
1650 u16 chan_mask;
1651 u8 intf;
1652 u8 set_cntr; /* If counter is available set counter for this entry ? */
1653 u8 default_rule;
1654 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1655 u16 vf;
1656 /* action */
1657 u32 index;
1658 u16 match_id;
1659 u8 flow_key_alg;
1660 u8 op;
1661 /* vtag rx action */
1662 u8 vtag0_type;
1663 u8 vtag0_valid;
1664 u8 vtag1_type;
1665 u8 vtag1_valid;
1666 /* vtag tx action */
1667 u16 vtag0_def;
1668 u8 vtag0_op;
1669 u16 vtag1_def;
1670 u8 vtag1_op;
1671 /* old counter value */
1672 u16 cntr_val;
1673 };
1674
1675 struct npc_install_flow_rsp {
1676 struct mbox_msghdr hdr;
1677 int counter; /* negative if no counter else counter number */
1678 };
1679
1680 struct npc_delete_flow_req {
1681 struct mbox_msghdr hdr;
1682 u16 entry;
1683 u16 start;/*Disable range of entries */
1684 u16 end;
1685 u8 all; /* PF + VFs */
1686 };
1687
1688 struct npc_delete_flow_rsp {
1689 struct mbox_msghdr hdr;
1690 u16 cntr_val;
1691 };
1692
1693 struct npc_mcam_read_entry_req {
1694 struct mbox_msghdr hdr;
1695 u16 entry; /* MCAM entry to read */
1696 };
1697
1698 struct npc_mcam_read_entry_rsp {
1699 struct mbox_msghdr hdr;
1700 struct mcam_entry entry_data;
1701 u8 intf;
1702 u8 enable;
1703 };
1704
1705 struct npc_mcam_read_base_rule_rsp {
1706 struct mbox_msghdr hdr;
1707 struct mcam_entry entry;
1708 };
1709
1710 struct npc_mcam_get_stats_req {
1711 struct mbox_msghdr hdr;
1712 u16 entry; /* mcam entry */
1713 };
1714
1715 struct npc_mcam_get_stats_rsp {
1716 struct mbox_msghdr hdr;
1717 u64 stat; /* counter stats */
1718 u8 stat_ena; /* enabled */
1719 };
1720
1721 struct npc_get_field_hash_info_req {
1722 struct mbox_msghdr hdr;
1723 u8 intf;
1724 };
1725
1726 struct npc_get_field_hash_info_rsp {
1727 struct mbox_msghdr hdr;
1728 u64 secret_key[3];
1729 #define NPC_MAX_HASH 2
1730 #define NPC_MAX_HASH_MASK 2
1731 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1732 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1733 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1734 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1735 };
1736
1737 enum ptp_op {
1738 PTP_OP_ADJFINE = 0,
1739 PTP_OP_GET_CLOCK = 1,
1740 PTP_OP_GET_TSTMP = 2,
1741 PTP_OP_SET_THRESH = 3,
1742 PTP_OP_PPS_ON = 4,
1743 PTP_OP_ADJTIME = 5,
1744 PTP_OP_SET_CLOCK = 6,
1745 };
1746
1747 struct ptp_req {
1748 struct mbox_msghdr hdr;
1749 u8 op;
1750 s64 scaled_ppm;
1751 u64 thresh;
1752 u64 period;
1753 int pps_on;
1754 s64 delta;
1755 u64 clk;
1756 };
1757
1758 struct ptp_rsp {
1759 struct mbox_msghdr hdr;
1760 u64 clk;
1761 u64 tsc;
1762 };
1763
1764 struct npc_get_field_status_req {
1765 struct mbox_msghdr hdr;
1766 u8 intf;
1767 u8 field;
1768 };
1769
1770 struct npc_get_field_status_rsp {
1771 struct mbox_msghdr hdr;
1772 u8 enable;
1773 };
1774
1775 struct set_vf_perm {
1776 struct mbox_msghdr hdr;
1777 u16 vf;
1778 #define RESET_VF_PERM BIT_ULL(0)
1779 #define VF_TRUSTED BIT_ULL(1)
1780 u64 flags;
1781 };
1782
1783 struct lmtst_tbl_setup_req {
1784 struct mbox_msghdr hdr;
1785 u64 dis_sched_early_comp :1;
1786 u64 sch_ena :1;
1787 u64 dis_line_pref :1;
1788 u64 ssow_pf_func :13;
1789 u16 base_pcifunc;
1790 u8 use_local_lmt_region;
1791 u64 lmt_iova;
1792 u64 rsvd[4];
1793 };
1794
1795 struct ndc_sync_op {
1796 struct mbox_msghdr hdr;
1797 u8 nix_lf_tx_sync;
1798 u8 nix_lf_rx_sync;
1799 u8 npa_lf_sync;
1800 };
1801
1802 /* CPT mailbox error codes
1803 * Range 901 - 1000.
1804 */
1805 enum cpt_af_status {
1806 CPT_AF_ERR_PARAM = -901,
1807 CPT_AF_ERR_GRP_INVALID = -902,
1808 CPT_AF_ERR_LF_INVALID = -903,
1809 CPT_AF_ERR_ACCESS_DENIED = -904,
1810 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1811 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1812 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1813 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1814 };
1815
1816 /* CPT mbox message formats */
1817 struct cpt_rd_wr_reg_msg {
1818 struct mbox_msghdr hdr;
1819 u64 reg_offset;
1820 u64 *ret_val;
1821 u64 val;
1822 u8 is_write;
1823 int blkaddr;
1824 };
1825
1826 struct cpt_lf_alloc_req_msg {
1827 struct mbox_msghdr hdr;
1828 u16 nix_pf_func;
1829 u16 sso_pf_func;
1830 u16 eng_grpmsk;
1831 u8 blkaddr;
1832 u8 ctx_ilen_valid : 1;
1833 u8 ctx_ilen : 7;
1834 };
1835
1836 #define CPT_INLINE_INBOUND 0
1837 #define CPT_INLINE_OUTBOUND 1
1838
1839 /* Mailbox message request format for CPT IPsec
1840 * inline inbound and outbound configuration.
1841 */
1842 struct cpt_inline_ipsec_cfg_msg {
1843 struct mbox_msghdr hdr;
1844 u8 enable;
1845 u8 slot;
1846 u8 dir;
1847 u8 sso_pf_func_ovrd;
1848 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1849 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1850 };
1851
1852 /* Mailbox message request and response format for CPT stats. */
1853 struct cpt_sts_req {
1854 struct mbox_msghdr hdr;
1855 u8 blkaddr;
1856 };
1857
1858 struct cpt_sts_rsp {
1859 struct mbox_msghdr hdr;
1860 u64 inst_req_pc;
1861 u64 inst_lat_pc;
1862 u64 rd_req_pc;
1863 u64 rd_lat_pc;
1864 u64 rd_uc_pc;
1865 u64 active_cycles_pc;
1866 u64 ctx_mis_pc;
1867 u64 ctx_hit_pc;
1868 u64 ctx_aop_pc;
1869 u64 ctx_aop_lat_pc;
1870 u64 ctx_ifetch_pc;
1871 u64 ctx_ifetch_lat_pc;
1872 u64 ctx_ffetch_pc;
1873 u64 ctx_ffetch_lat_pc;
1874 u64 ctx_wback_pc;
1875 u64 ctx_wback_lat_pc;
1876 u64 ctx_psh_pc;
1877 u64 ctx_psh_lat_pc;
1878 u64 ctx_err;
1879 u64 ctx_enc_id;
1880 u64 ctx_flush_timer;
1881 u64 rxc_time;
1882 u64 rxc_time_cfg;
1883 u64 rxc_active_sts;
1884 u64 rxc_zombie_sts;
1885 u64 busy_sts_ae;
1886 u64 free_sts_ae;
1887 u64 busy_sts_se;
1888 u64 free_sts_se;
1889 u64 busy_sts_ie;
1890 u64 free_sts_ie;
1891 u64 exe_err_info;
1892 u64 cptclk_cnt;
1893 u64 diag;
1894 u64 rxc_dfrg;
1895 u64 x2p_link_cfg0;
1896 u64 x2p_link_cfg1;
1897 };
1898
1899 /* Mailbox message request format to configure reassembly timeout. */
1900 struct cpt_rxc_time_cfg_req {
1901 struct mbox_msghdr hdr;
1902 int blkaddr;
1903 u32 step;
1904 u16 zombie_thres;
1905 u16 zombie_limit;
1906 u16 active_thres;
1907 u16 active_limit;
1908 };
1909
1910 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1911 struct cpt_inst_lmtst_req {
1912 struct mbox_msghdr hdr;
1913 u64 inst[8];
1914 u64 rsvd;
1915 };
1916
1917 /* Mailbox message format to request for CPT LF reset */
1918 struct cpt_lf_rst_req {
1919 struct mbox_msghdr hdr;
1920 u32 slot;
1921 u32 rsvd;
1922 };
1923
1924 /* Mailbox message format to request for CPT faulted engines */
1925 struct cpt_flt_eng_info_req {
1926 struct mbox_msghdr hdr;
1927 int blkaddr;
1928 bool reset;
1929 u32 rsvd;
1930 };
1931
1932 struct cpt_flt_eng_info_rsp {
1933 struct mbox_msghdr hdr;
1934 #define CPT_AF_MAX_FLT_INT_VECS 3
1935 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS];
1936 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS];
1937 u64 rsvd;
1938 };
1939
1940 struct sdp_node_info {
1941 /* Node to which this PF belons to */
1942 u8 node_id;
1943 u8 max_vfs;
1944 u8 num_pf_rings;
1945 u8 pf_srn;
1946 #define SDP_MAX_VFS 128
1947 u8 vf_rings[SDP_MAX_VFS];
1948 };
1949
1950 struct sdp_chan_info_msg {
1951 struct mbox_msghdr hdr;
1952 struct sdp_node_info info;
1953 };
1954
1955 struct sdp_get_chan_info_msg {
1956 struct mbox_msghdr hdr;
1957 u16 chan_base;
1958 u16 num_chan;
1959 };
1960
1961 /* CGX mailbox error codes
1962 * Range 1101 - 1200.
1963 */
1964 enum cgx_af_status {
1965 LMAC_AF_ERR_INVALID_PARAM = -1101,
1966 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1967 LMAC_AF_ERR_PERM_DENIED = -1103,
1968 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
1969 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1970 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1971 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1972 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1973 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1974 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1975 };
1976
1977 enum mcs_direction {
1978 MCS_RX,
1979 MCS_TX,
1980 };
1981
1982 enum mcs_rsrc_type {
1983 MCS_RSRC_TYPE_FLOWID,
1984 MCS_RSRC_TYPE_SECY,
1985 MCS_RSRC_TYPE_SC,
1986 MCS_RSRC_TYPE_SA,
1987 };
1988
1989 struct mcs_alloc_rsrc_req {
1990 struct mbox_msghdr hdr;
1991 u8 rsrc_type;
1992 u8 rsrc_cnt; /* Resources count */
1993 u8 mcs_id; /* MCS block ID */
1994 u8 dir; /* Macsec ingress or egress side */
1995 u8 all; /* Allocate all resource type one each */
1996 u64 rsvd;
1997 };
1998
1999 struct mcs_alloc_rsrc_rsp {
2000 struct mbox_msghdr hdr;
2001 u8 flow_ids[128]; /* Index of reserved entries */
2002 u8 secy_ids[128];
2003 u8 sc_ids[128];
2004 u8 sa_ids[256];
2005 u8 rsrc_type;
2006 u8 rsrc_cnt; /* No of entries reserved */
2007 u8 mcs_id;
2008 u8 dir;
2009 u8 all;
2010 u8 rsvd[256]; /* reserved fields for future expansion */
2011 };
2012
2013 struct mcs_free_rsrc_req {
2014 struct mbox_msghdr hdr;
2015 u8 rsrc_id; /* Index of the entry to be freed */
2016 u8 rsrc_type;
2017 u8 mcs_id;
2018 u8 dir;
2019 u8 all; /* Free all the cam resources */
2020 u64 rsvd;
2021 };
2022
2023 struct mcs_flowid_entry_write_req {
2024 struct mbox_msghdr hdr;
2025 u64 data[4];
2026 u64 mask[4];
2027 u64 sci; /* CNF10K-B for tx_secy_mem_map */
2028 u8 flow_id;
2029 u8 secy_id; /* secyid for which flowid is mapped */
2030 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
2031 u8 ena; /* Enable tcam entry */
2032 u8 ctrl_pkt;
2033 u8 mcs_id;
2034 u8 dir;
2035 u64 rsvd;
2036 };
2037
2038 struct mcs_secy_plcy_write_req {
2039 struct mbox_msghdr hdr;
2040 u64 plcy;
2041 u8 secy_id;
2042 u8 mcs_id;
2043 u8 dir;
2044 u64 rsvd;
2045 };
2046
2047 /* RX SC_CAM mapping */
2048 struct mcs_rx_sc_cam_write_req {
2049 struct mbox_msghdr hdr;
2050 u64 sci; /* SCI */
2051 u64 secy_id; /* secy index mapped to SC */
2052 u8 sc_id; /* SC CAM entry index */
2053 u8 mcs_id;
2054 u64 rsvd;
2055 };
2056
2057 struct mcs_sa_plcy_write_req {
2058 struct mbox_msghdr hdr;
2059 u64 plcy[2][9]; /* Support 2 SA policy */
2060 u8 sa_index[2];
2061 u8 sa_cnt;
2062 u8 mcs_id;
2063 u8 dir;
2064 u64 rsvd;
2065 };
2066
2067 struct mcs_tx_sc_sa_map {
2068 struct mbox_msghdr hdr;
2069 u8 sa_index0;
2070 u8 sa_index1;
2071 u8 rekey_ena;
2072 u8 sa_index0_vld;
2073 u8 sa_index1_vld;
2074 u8 tx_sa_active;
2075 u64 sectag_sci;
2076 u8 sc_id; /* used as index for SA_MEM_MAP */
2077 u8 mcs_id;
2078 u64 rsvd;
2079 };
2080
2081 struct mcs_rx_sc_sa_map {
2082 struct mbox_msghdr hdr;
2083 u8 sa_index;
2084 u8 sa_in_use;
2085 u8 sc_id;
2086 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
2087 u8 mcs_id;
2088 u64 rsvd;
2089 };
2090
2091 struct mcs_flowid_ena_dis_entry {
2092 struct mbox_msghdr hdr;
2093 u8 flow_id;
2094 u8 ena;
2095 u8 mcs_id;
2096 u8 dir;
2097 u64 rsvd;
2098 };
2099
2100 struct mcs_pn_table_write_req {
2101 struct mbox_msghdr hdr;
2102 u64 next_pn;
2103 u8 pn_id;
2104 u8 mcs_id;
2105 u8 dir;
2106 u64 rsvd;
2107 };
2108
2109 struct mcs_hw_info {
2110 struct mbox_msghdr hdr;
2111 u8 num_mcs_blks; /* Number of MCS blocks */
2112 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
2113 u8 secy_entries; /* RX/TX SECY entries per mcs block */
2114 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
2115 u16 sa_entries; /* PN table entries = SA entries */
2116 u64 rsvd[16];
2117 };
2118
2119 struct mcs_set_active_lmac {
2120 struct mbox_msghdr hdr;
2121 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
2122 u8 mcs_id;
2123 u16 chan_base; /* MCS channel base */
2124 u64 rsvd;
2125 };
2126
2127 struct mcs_set_lmac_mode {
2128 struct mbox_msghdr hdr;
2129 u8 mode; /* 1:Bypass 0:Operational */
2130 u8 lmac_id;
2131 u8 mcs_id;
2132 u64 rsvd;
2133 };
2134
2135 struct mcs_port_reset_req {
2136 struct mbox_msghdr hdr;
2137 u8 reset;
2138 u8 mcs_id;
2139 u8 port_id;
2140 u64 rsvd;
2141 };
2142
2143 struct mcs_port_cfg_set_req {
2144 struct mbox_msghdr hdr;
2145 u8 cstm_tag_rel_mode_sel;
2146 u8 custom_hdr_enb;
2147 u8 fifo_skid;
2148 u8 port_mode;
2149 u8 port_id;
2150 u8 mcs_id;
2151 u64 rsvd;
2152 };
2153
2154 struct mcs_port_cfg_get_req {
2155 struct mbox_msghdr hdr;
2156 u8 port_id;
2157 u8 mcs_id;
2158 u64 rsvd;
2159 };
2160
2161 struct mcs_port_cfg_get_rsp {
2162 struct mbox_msghdr hdr;
2163 u8 cstm_tag_rel_mode_sel;
2164 u8 custom_hdr_enb;
2165 u8 fifo_skid;
2166 u8 port_mode;
2167 u8 port_id;
2168 u8 mcs_id;
2169 u64 rsvd;
2170 };
2171
2172 struct mcs_custom_tag_cfg_get_req {
2173 struct mbox_msghdr hdr;
2174 u8 mcs_id;
2175 u8 dir;
2176 u64 rsvd;
2177 };
2178
2179 struct mcs_custom_tag_cfg_get_rsp {
2180 struct mbox_msghdr hdr;
2181 u16 cstm_etype[8];
2182 u8 cstm_indx[8];
2183 u8 cstm_etype_en;
2184 u8 mcs_id;
2185 u8 dir;
2186 u64 rsvd;
2187 };
2188
2189 /* MCS mailbox error codes
2190 * Range 1201 - 1300.
2191 */
2192 enum mcs_af_status {
2193 MCS_AF_ERR_INVALID_MCSID = -1201,
2194 MCS_AF_ERR_NOT_MAPPED = -1202,
2195 };
2196
2197 struct mcs_set_pn_threshold {
2198 struct mbox_msghdr hdr;
2199 u64 threshold;
2200 u8 xpn; /* '1' for setting xpn threshold */
2201 u8 mcs_id;
2202 u8 dir;
2203 u64 rsvd;
2204 };
2205
2206 enum mcs_ctrl_pkt_rulew_type {
2207 MCS_CTRL_PKT_RULE_TYPE_ETH,
2208 MCS_CTRL_PKT_RULE_TYPE_DA,
2209 MCS_CTRL_PKT_RULE_TYPE_RANGE,
2210 MCS_CTRL_PKT_RULE_TYPE_COMBO,
2211 MCS_CTRL_PKT_RULE_TYPE_MAC,
2212 };
2213
2214 struct mcs_alloc_ctrl_pkt_rule_req {
2215 struct mbox_msghdr hdr;
2216 u8 rule_type;
2217 u8 mcs_id; /* MCS block ID */
2218 u8 dir; /* Macsec ingress or egress side */
2219 u64 rsvd;
2220 };
2221
2222 struct mcs_alloc_ctrl_pkt_rule_rsp {
2223 struct mbox_msghdr hdr;
2224 u8 rule_idx;
2225 u8 rule_type;
2226 u8 mcs_id;
2227 u8 dir;
2228 u64 rsvd;
2229 };
2230
2231 struct mcs_free_ctrl_pkt_rule_req {
2232 struct mbox_msghdr hdr;
2233 u8 rule_idx;
2234 u8 rule_type;
2235 u8 mcs_id;
2236 u8 dir;
2237 u8 all;
2238 u64 rsvd;
2239 };
2240
2241 struct mcs_ctrl_pkt_rule_write_req {
2242 struct mbox_msghdr hdr;
2243 u64 data0;
2244 u64 data1;
2245 u64 data2;
2246 u8 rule_idx;
2247 u8 rule_type;
2248 u8 mcs_id;
2249 u8 dir;
2250 u64 rsvd;
2251 };
2252
2253 struct mcs_stats_req {
2254 struct mbox_msghdr hdr;
2255 u8 id;
2256 u8 mcs_id;
2257 u8 dir;
2258 u64 rsvd;
2259 };
2260
2261 struct mcs_flowid_stats {
2262 struct mbox_msghdr hdr;
2263 u64 tcam_hit_cnt;
2264 u64 rsvd;
2265 };
2266
2267 struct mcs_secy_stats {
2268 struct mbox_msghdr hdr;
2269 u64 ctl_pkt_bcast_cnt;
2270 u64 ctl_pkt_mcast_cnt;
2271 u64 ctl_pkt_ucast_cnt;
2272 u64 ctl_octet_cnt;
2273 u64 unctl_pkt_bcast_cnt;
2274 u64 unctl_pkt_mcast_cnt;
2275 u64 unctl_pkt_ucast_cnt;
2276 u64 unctl_octet_cnt;
2277 /* Valid only for RX */
2278 u64 octet_decrypted_cnt;
2279 u64 octet_validated_cnt;
2280 u64 pkt_port_disabled_cnt;
2281 u64 pkt_badtag_cnt;
2282 u64 pkt_nosa_cnt;
2283 u64 pkt_nosaerror_cnt;
2284 u64 pkt_tagged_ctl_cnt;
2285 u64 pkt_untaged_cnt;
2286 u64 pkt_ctl_cnt; /* CN10K-B */
2287 u64 pkt_notag_cnt; /* CNF10K-B */
2288 /* Valid only for TX */
2289 u64 octet_encrypted_cnt;
2290 u64 octet_protected_cnt;
2291 u64 pkt_noactivesa_cnt;
2292 u64 pkt_toolong_cnt;
2293 u64 pkt_untagged_cnt;
2294 u64 rsvd[4];
2295 };
2296
2297 struct mcs_port_stats {
2298 struct mbox_msghdr hdr;
2299 u64 tcam_miss_cnt;
2300 u64 parser_err_cnt;
2301 u64 preempt_err_cnt; /* CNF10K-B */
2302 u64 sectag_insert_err_cnt;
2303 u64 rsvd[4];
2304 };
2305
2306 /* Only for CN10K-B */
2307 struct mcs_sa_stats {
2308 struct mbox_msghdr hdr;
2309 /* RX */
2310 u64 pkt_invalid_cnt;
2311 u64 pkt_nosaerror_cnt;
2312 u64 pkt_notvalid_cnt;
2313 u64 pkt_ok_cnt;
2314 u64 pkt_nosa_cnt;
2315 /* TX */
2316 u64 pkt_encrypt_cnt;
2317 u64 pkt_protected_cnt;
2318 u64 rsvd[4];
2319 };
2320
2321 struct mcs_sc_stats {
2322 struct mbox_msghdr hdr;
2323 /* RX */
2324 u64 hit_cnt;
2325 u64 pkt_invalid_cnt;
2326 u64 pkt_late_cnt;
2327 u64 pkt_notvalid_cnt;
2328 u64 pkt_unchecked_cnt;
2329 u64 pkt_delay_cnt; /* CNF10K-B */
2330 u64 pkt_ok_cnt; /* CNF10K-B */
2331 u64 octet_decrypt_cnt; /* CN10K-B */
2332 u64 octet_validate_cnt; /* CN10K-B */
2333 /* TX */
2334 u64 pkt_encrypt_cnt;
2335 u64 pkt_protected_cnt;
2336 u64 octet_encrypt_cnt; /* CN10K-B */
2337 u64 octet_protected_cnt; /* CN10K-B */
2338 u64 rsvd[4];
2339 };
2340
2341 struct mcs_clear_stats {
2342 struct mbox_msghdr hdr;
2343 #define MCS_FLOWID_STATS 0
2344 #define MCS_SECY_STATS 1
2345 #define MCS_SC_STATS 2
2346 #define MCS_SA_STATS 3
2347 #define MCS_PORT_STATS 4
2348 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2349 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2350 u8 mcs_id;
2351 u8 dir;
2352 u8 all; /* All resources stats mapped to PF are cleared */
2353 };
2354
2355 struct mcs_intr_cfg {
2356 struct mbox_msghdr hdr;
2357 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2358 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2359 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2360 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2361 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2362 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2363 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2364 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2365 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2366 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2367 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2368 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2369 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2370 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2371 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2372 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2373 u64 intr_mask; /* Interrupt enable mask */
2374 u8 mcs_id;
2375 u8 lmac_id;
2376 u64 rsvd;
2377 };
2378
2379 struct mcs_intr_info {
2380 struct mbox_msghdr hdr;
2381 u64 intr_mask;
2382 int sa_id;
2383 u8 mcs_id;
2384 u8 lmac_id;
2385 u64 rsvd;
2386 };
2387
2388 #endif /* MBOX_H */
2389