1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip Successive Approximation Register (SAR) A/D Converter
4 * Copyright (C) 2014 Rockchip Electronics Co., Ltd.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/module.h>
9 #include <linux/mutex.h>
10 #include <linux/platform_device.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/reset.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23
24 #define SARADC_DATA 0x00
25
26 #define SARADC_STAS 0x04
27 #define SARADC_STAS_BUSY BIT(0)
28
29 #define SARADC_CTRL 0x08
30 #define SARADC_CTRL_IRQ_STATUS BIT(6)
31 #define SARADC_CTRL_IRQ_ENABLE BIT(5)
32 #define SARADC_CTRL_POWER_CTRL BIT(3)
33 #define SARADC_CTRL_CHN_MASK 0x7
34
35 #define SARADC_DLY_PU_SOC 0x0c
36 #define SARADC_DLY_PU_SOC_MASK 0x3f
37
38 #define SARADC_TIMEOUT msecs_to_jiffies(100)
39 #define SARADC_MAX_CHANNELS 8
40
41 /* v2 registers */
42 #define SARADC2_CONV_CON 0x000
43 #define SARADC_T_PD_SOC 0x004
44 #define SARADC_T_DAS_SOC 0x00c
45 #define SARADC2_END_INT_EN 0x104
46 #define SARADC2_ST_CON 0x108
47 #define SARADC2_STATUS 0x10c
48 #define SARADC2_END_INT_ST 0x110
49 #define SARADC2_DATA_BASE 0x120
50
51 #define SARADC2_EN_END_INT BIT(0)
52 #define SARADC2_START BIT(4)
53 #define SARADC2_SINGLE_MODE BIT(5)
54
55 #define SARADC2_CONV_CHANNELS GENMASK(3, 0)
56
57 struct rockchip_saradc;
58
59 struct rockchip_saradc_data {
60 const struct iio_chan_spec *channels;
61 int num_channels;
62 unsigned long clk_rate;
63 void (*start)(struct rockchip_saradc *info, int chn);
64 int (*read)(struct rockchip_saradc *info);
65 void (*power_down)(struct rockchip_saradc *info);
66 };
67
68 struct rockchip_saradc {
69 void __iomem *regs;
70 struct clk *pclk;
71 struct clk *clk;
72 struct completion completion;
73 struct regulator *vref;
74 /* lock to protect against multiple access to the device */
75 struct mutex lock;
76 int uv_vref;
77 struct reset_control *reset;
78 const struct rockchip_saradc_data *data;
79 u16 last_val;
80 const struct iio_chan_spec *last_chan;
81 struct notifier_block nb;
82 };
83
84 static void rockchip_saradc_reset_controller(struct reset_control *reset);
85
rockchip_saradc_start_v1(struct rockchip_saradc * info,int chn)86 static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
87 {
88 /* 8 clock periods as delay between power up and start cmd */
89 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
90 /* Select the channel to be used and trigger conversion */
91 writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
92 SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
93 }
94
rockchip_saradc_start_v2(struct rockchip_saradc * info,int chn)95 static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
96 {
97 int val;
98
99 if (info->reset)
100 rockchip_saradc_reset_controller(info->reset);
101
102 writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
103 writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
104 val = FIELD_PREP(SARADC2_EN_END_INT, 1);
105 val |= SARADC2_EN_END_INT << 16;
106 writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
107 val = FIELD_PREP(SARADC2_START, 1) |
108 FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
109 FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
110 val |= (SARADC2_START | SARADC2_SINGLE_MODE | SARADC2_CONV_CHANNELS) << 16;
111 writel(val, info->regs + SARADC2_CONV_CON);
112 }
113
rockchip_saradc_start(struct rockchip_saradc * info,int chn)114 static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
115 {
116 info->data->start(info, chn);
117 }
118
rockchip_saradc_read_v1(struct rockchip_saradc * info)119 static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
120 {
121 return readl_relaxed(info->regs + SARADC_DATA);
122 }
123
rockchip_saradc_read_v2(struct rockchip_saradc * info)124 static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
125 {
126 int offset;
127
128 /* Clear irq */
129 writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
130
131 offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
132
133 return readl_relaxed(info->regs + offset);
134 }
135
rockchip_saradc_read(struct rockchip_saradc * info)136 static int rockchip_saradc_read(struct rockchip_saradc *info)
137 {
138 return info->data->read(info);
139 }
140
rockchip_saradc_power_down_v1(struct rockchip_saradc * info)141 static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
142 {
143 writel_relaxed(0, info->regs + SARADC_CTRL);
144 }
145
rockchip_saradc_power_down(struct rockchip_saradc * info)146 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
147 {
148 if (info->data->power_down)
149 info->data->power_down(info);
150 }
151
rockchip_saradc_conversion(struct rockchip_saradc * info,struct iio_chan_spec const * chan)152 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
153 struct iio_chan_spec const *chan)
154 {
155 reinit_completion(&info->completion);
156
157 info->last_chan = chan;
158 rockchip_saradc_start(info, chan->channel);
159
160 if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
161 return -ETIMEDOUT;
162
163 return 0;
164 }
165
rockchip_saradc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)166 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
167 struct iio_chan_spec const *chan,
168 int *val, int *val2, long mask)
169 {
170 struct rockchip_saradc *info = iio_priv(indio_dev);
171 int ret;
172
173 switch (mask) {
174 case IIO_CHAN_INFO_RAW:
175 mutex_lock(&info->lock);
176
177 ret = rockchip_saradc_conversion(info, chan);
178 if (ret) {
179 rockchip_saradc_power_down(info);
180 mutex_unlock(&info->lock);
181 return ret;
182 }
183
184 *val = info->last_val;
185 mutex_unlock(&info->lock);
186 return IIO_VAL_INT;
187 case IIO_CHAN_INFO_SCALE:
188 *val = info->uv_vref / 1000;
189 *val2 = chan->scan_type.realbits;
190 return IIO_VAL_FRACTIONAL_LOG2;
191 default:
192 return -EINVAL;
193 }
194 }
195
rockchip_saradc_isr(int irq,void * dev_id)196 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
197 {
198 struct rockchip_saradc *info = dev_id;
199
200 /* Read value */
201 info->last_val = rockchip_saradc_read(info);
202 info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
203
204 rockchip_saradc_power_down(info);
205
206 complete(&info->completion);
207
208 return IRQ_HANDLED;
209 }
210
211 static const struct iio_info rockchip_saradc_iio_info = {
212 .read_raw = rockchip_saradc_read_raw,
213 };
214
215 #define SARADC_CHANNEL(_index, _id, _res) { \
216 .type = IIO_VOLTAGE, \
217 .indexed = 1, \
218 .channel = _index, \
219 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
220 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
221 .datasheet_name = _id, \
222 .scan_index = _index, \
223 .scan_type = { \
224 .sign = 'u', \
225 .realbits = _res, \
226 .storagebits = 16, \
227 .endianness = IIO_CPU, \
228 }, \
229 }
230
231 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
232 SARADC_CHANNEL(0, "adc0", 10),
233 SARADC_CHANNEL(1, "adc1", 10),
234 SARADC_CHANNEL(2, "adc2", 10),
235 };
236
237 static const struct rockchip_saradc_data saradc_data = {
238 .channels = rockchip_saradc_iio_channels,
239 .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
240 .clk_rate = 1000000,
241 .start = rockchip_saradc_start_v1,
242 .read = rockchip_saradc_read_v1,
243 .power_down = rockchip_saradc_power_down_v1,
244 };
245
246 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
247 SARADC_CHANNEL(0, "adc0", 12),
248 SARADC_CHANNEL(1, "adc1", 12),
249 };
250
251 static const struct rockchip_saradc_data rk3066_tsadc_data = {
252 .channels = rockchip_rk3066_tsadc_iio_channels,
253 .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
254 .clk_rate = 50000,
255 .start = rockchip_saradc_start_v1,
256 .read = rockchip_saradc_read_v1,
257 .power_down = rockchip_saradc_power_down_v1,
258 };
259
260 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
261 SARADC_CHANNEL(0, "adc0", 10),
262 SARADC_CHANNEL(1, "adc1", 10),
263 SARADC_CHANNEL(2, "adc2", 10),
264 SARADC_CHANNEL(3, "adc3", 10),
265 SARADC_CHANNEL(4, "adc4", 10),
266 SARADC_CHANNEL(5, "adc5", 10),
267 };
268
269 static const struct rockchip_saradc_data rk3399_saradc_data = {
270 .channels = rockchip_rk3399_saradc_iio_channels,
271 .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
272 .clk_rate = 1000000,
273 .start = rockchip_saradc_start_v1,
274 .read = rockchip_saradc_read_v1,
275 .power_down = rockchip_saradc_power_down_v1,
276 };
277
278 static const struct iio_chan_spec rockchip_rk3528_saradc_iio_channels[] = {
279 SARADC_CHANNEL(0, "adc0", 10),
280 SARADC_CHANNEL(1, "adc1", 10),
281 SARADC_CHANNEL(2, "adc2", 10),
282 SARADC_CHANNEL(3, "adc3", 10),
283 };
284
285 static const struct rockchip_saradc_data rk3528_saradc_data = {
286 .channels = rockchip_rk3528_saradc_iio_channels,
287 .num_channels = ARRAY_SIZE(rockchip_rk3528_saradc_iio_channels),
288 .clk_rate = 1000000,
289 .start = rockchip_saradc_start_v2,
290 .read = rockchip_saradc_read_v2,
291 };
292
293 static const struct iio_chan_spec rockchip_rk3562_saradc_iio_channels[] = {
294 SARADC_CHANNEL(0, "adc0", 10),
295 SARADC_CHANNEL(1, "adc1", 10),
296 SARADC_CHANNEL(2, "adc2", 10),
297 SARADC_CHANNEL(3, "adc3", 10),
298 SARADC_CHANNEL(4, "adc4", 10),
299 SARADC_CHANNEL(5, "adc5", 10),
300 SARADC_CHANNEL(6, "adc6", 10),
301 SARADC_CHANNEL(7, "adc7", 10),
302 };
303
304 static const struct rockchip_saradc_data rk3562_saradc_data = {
305 .channels = rockchip_rk3562_saradc_iio_channels,
306 .num_channels = ARRAY_SIZE(rockchip_rk3562_saradc_iio_channels),
307 .clk_rate = 1000000,
308 .start = rockchip_saradc_start_v2,
309 .read = rockchip_saradc_read_v2,
310 };
311
312 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
313 SARADC_CHANNEL(0, "adc0", 10),
314 SARADC_CHANNEL(1, "adc1", 10),
315 SARADC_CHANNEL(2, "adc2", 10),
316 SARADC_CHANNEL(3, "adc3", 10),
317 SARADC_CHANNEL(4, "adc4", 10),
318 SARADC_CHANNEL(5, "adc5", 10),
319 SARADC_CHANNEL(6, "adc6", 10),
320 SARADC_CHANNEL(7, "adc7", 10),
321 };
322
323 static const struct rockchip_saradc_data rk3568_saradc_data = {
324 .channels = rockchip_rk3568_saradc_iio_channels,
325 .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
326 .clk_rate = 1000000,
327 .start = rockchip_saradc_start_v1,
328 .read = rockchip_saradc_read_v1,
329 .power_down = rockchip_saradc_power_down_v1,
330 };
331
332 static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
333 SARADC_CHANNEL(0, "adc0", 12),
334 SARADC_CHANNEL(1, "adc1", 12),
335 SARADC_CHANNEL(2, "adc2", 12),
336 SARADC_CHANNEL(3, "adc3", 12),
337 SARADC_CHANNEL(4, "adc4", 12),
338 SARADC_CHANNEL(5, "adc5", 12),
339 SARADC_CHANNEL(6, "adc6", 12),
340 SARADC_CHANNEL(7, "adc7", 12),
341 };
342
343 static const struct rockchip_saradc_data rk3588_saradc_data = {
344 .channels = rockchip_rk3588_saradc_iio_channels,
345 .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
346 .clk_rate = 1000000,
347 .start = rockchip_saradc_start_v2,
348 .read = rockchip_saradc_read_v2,
349 };
350
351 static const struct of_device_id rockchip_saradc_match[] = {
352 {
353 .compatible = "rockchip,saradc",
354 .data = &saradc_data,
355 }, {
356 .compatible = "rockchip,rk3066-tsadc",
357 .data = &rk3066_tsadc_data,
358 }, {
359 .compatible = "rockchip,rk3399-saradc",
360 .data = &rk3399_saradc_data,
361 }, {
362 .compatible = "rockchip,rk3528-saradc",
363 .data = &rk3528_saradc_data,
364 }, {
365 .compatible = "rockchip,rk3562-saradc",
366 .data = &rk3562_saradc_data,
367 }, {
368 .compatible = "rockchip,rk3568-saradc",
369 .data = &rk3568_saradc_data,
370 }, {
371 .compatible = "rockchip,rk3588-saradc",
372 .data = &rk3588_saradc_data,
373 },
374 { }
375 };
376 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
377
378 /*
379 * Reset SARADC Controller.
380 */
rockchip_saradc_reset_controller(struct reset_control * reset)381 static void rockchip_saradc_reset_controller(struct reset_control *reset)
382 {
383 reset_control_assert(reset);
384 usleep_range(10, 20);
385 reset_control_deassert(reset);
386 }
387
rockchip_saradc_regulator_disable(void * data)388 static void rockchip_saradc_regulator_disable(void *data)
389 {
390 struct rockchip_saradc *info = data;
391
392 regulator_disable(info->vref);
393 }
394
rockchip_saradc_trigger_handler(int irq,void * p)395 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
396 {
397 struct iio_poll_func *pf = p;
398 struct iio_dev *i_dev = pf->indio_dev;
399 struct rockchip_saradc *info = iio_priv(i_dev);
400 /*
401 * @values: each channel takes an u16 value
402 * @timestamp: will be 8-byte aligned automatically
403 */
404 struct {
405 u16 values[SARADC_MAX_CHANNELS];
406 aligned_s64 timestamp;
407 } data;
408 int ret;
409 int i, j = 0;
410
411 memset(&data, 0, sizeof(data));
412
413 mutex_lock(&info->lock);
414
415 iio_for_each_active_channel(i_dev, i) {
416 const struct iio_chan_spec *chan = &i_dev->channels[i];
417
418 ret = rockchip_saradc_conversion(info, chan);
419 if (ret) {
420 rockchip_saradc_power_down(info);
421 goto out;
422 }
423
424 data.values[j] = info->last_val;
425 j++;
426 }
427
428 iio_push_to_buffers_with_ts(i_dev, &data, sizeof(data),
429 iio_get_time_ns(i_dev));
430 out:
431 mutex_unlock(&info->lock);
432
433 iio_trigger_notify_done(i_dev->trig);
434
435 return IRQ_HANDLED;
436 }
437
rockchip_saradc_volt_notify(struct notifier_block * nb,unsigned long event,void * data)438 static int rockchip_saradc_volt_notify(struct notifier_block *nb,
439 unsigned long event, void *data)
440 {
441 struct rockchip_saradc *info =
442 container_of(nb, struct rockchip_saradc, nb);
443
444 if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
445 info->uv_vref = (unsigned long)data;
446
447 return NOTIFY_OK;
448 }
449
rockchip_saradc_regulator_unreg_notifier(void * data)450 static void rockchip_saradc_regulator_unreg_notifier(void *data)
451 {
452 struct rockchip_saradc *info = data;
453
454 regulator_unregister_notifier(info->vref, &info->nb);
455 }
456
rockchip_saradc_probe(struct platform_device * pdev)457 static int rockchip_saradc_probe(struct platform_device *pdev)
458 {
459 const struct rockchip_saradc_data *match_data;
460 struct rockchip_saradc *info = NULL;
461 struct device_node *np = pdev->dev.of_node;
462 struct iio_dev *indio_dev = NULL;
463 int ret;
464 int irq;
465
466 if (!np)
467 return -ENODEV;
468
469 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
470 if (!indio_dev)
471 return dev_err_probe(&pdev->dev, -ENOMEM,
472 "failed allocating iio device\n");
473
474 info = iio_priv(indio_dev);
475
476 match_data = of_device_get_match_data(&pdev->dev);
477 if (!match_data)
478 return dev_err_probe(&pdev->dev, -ENODEV,
479 "failed to match device\n");
480
481 info->data = match_data;
482
483 /* Sanity check for possible later IP variants with more channels */
484 if (info->data->num_channels > SARADC_MAX_CHANNELS)
485 return dev_err_probe(&pdev->dev, -EINVAL,
486 "max channels exceeded");
487
488 info->regs = devm_platform_ioremap_resource(pdev, 0);
489 if (IS_ERR(info->regs))
490 return PTR_ERR(info->regs);
491
492 /*
493 * The reset should be an optional property, as it should work
494 * with old devicetrees as well
495 */
496 info->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
497 "saradc-apb");
498 if (IS_ERR(info->reset)) {
499 ret = PTR_ERR(info->reset);
500 return dev_err_probe(&pdev->dev, ret, "failed to get saradc-apb\n");
501 }
502
503 init_completion(&info->completion);
504
505 irq = platform_get_irq(pdev, 0);
506 if (irq < 0)
507 return irq;
508
509 ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
510 0, dev_name(&pdev->dev), info);
511 if (ret < 0) {
512 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
513 return ret;
514 }
515
516 info->vref = devm_regulator_get(&pdev->dev, "vref");
517 if (IS_ERR(info->vref))
518 return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
519 "failed to get regulator\n");
520
521 if (info->reset)
522 rockchip_saradc_reset_controller(info->reset);
523
524 ret = regulator_enable(info->vref);
525 if (ret < 0)
526 return dev_err_probe(&pdev->dev, ret,
527 "failed to enable vref regulator\n");
528
529 ret = devm_add_action_or_reset(&pdev->dev,
530 rockchip_saradc_regulator_disable, info);
531 if (ret)
532 return dev_err_probe(&pdev->dev, ret,
533 "failed to register devm action\n");
534
535 ret = regulator_get_voltage(info->vref);
536 if (ret < 0)
537 return ret;
538
539 info->uv_vref = ret;
540
541 info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
542 if (IS_ERR(info->pclk))
543 return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
544 "failed to get pclk\n");
545
546 info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
547 if (IS_ERR(info->clk))
548 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
549 "failed to get adc clock\n");
550 /*
551 * Use a default value for the converter clock.
552 * This may become user-configurable in the future.
553 */
554 ret = clk_set_rate(info->clk, info->data->clk_rate);
555 if (ret < 0)
556 return dev_err_probe(&pdev->dev, ret,
557 "failed to set adc clk rate\n");
558
559 platform_set_drvdata(pdev, indio_dev);
560
561 indio_dev->name = dev_name(&pdev->dev);
562 indio_dev->info = &rockchip_saradc_iio_info;
563 indio_dev->modes = INDIO_DIRECT_MODE;
564
565 indio_dev->channels = info->data->channels;
566 indio_dev->num_channels = info->data->num_channels;
567 ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
568 rockchip_saradc_trigger_handler,
569 NULL);
570 if (ret)
571 return ret;
572
573 info->nb.notifier_call = rockchip_saradc_volt_notify;
574 ret = regulator_register_notifier(info->vref, &info->nb);
575 if (ret)
576 return ret;
577
578 ret = devm_add_action_or_reset(&pdev->dev,
579 rockchip_saradc_regulator_unreg_notifier,
580 info);
581 if (ret)
582 return ret;
583
584 mutex_init(&info->lock);
585
586 return devm_iio_device_register(&pdev->dev, indio_dev);
587 }
588
rockchip_saradc_suspend(struct device * dev)589 static int rockchip_saradc_suspend(struct device *dev)
590 {
591 struct iio_dev *indio_dev = dev_get_drvdata(dev);
592 struct rockchip_saradc *info = iio_priv(indio_dev);
593
594 clk_disable_unprepare(info->clk);
595 clk_disable_unprepare(info->pclk);
596 regulator_disable(info->vref);
597
598 return 0;
599 }
600
rockchip_saradc_resume(struct device * dev)601 static int rockchip_saradc_resume(struct device *dev)
602 {
603 struct iio_dev *indio_dev = dev_get_drvdata(dev);
604 struct rockchip_saradc *info = iio_priv(indio_dev);
605 int ret;
606
607 ret = regulator_enable(info->vref);
608 if (ret)
609 return ret;
610
611 ret = clk_prepare_enable(info->pclk);
612 if (ret)
613 return ret;
614
615 ret = clk_prepare_enable(info->clk);
616 if (ret)
617 clk_disable_unprepare(info->pclk);
618
619 return ret;
620 }
621
622 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
623 rockchip_saradc_suspend,
624 rockchip_saradc_resume);
625
626 static struct platform_driver rockchip_saradc_driver = {
627 .probe = rockchip_saradc_probe,
628 .driver = {
629 .name = "rockchip-saradc",
630 .of_match_table = rockchip_saradc_match,
631 .pm = pm_sleep_ptr(&rockchip_saradc_pm_ops),
632 },
633 };
634
635 module_platform_driver(rockchip_saradc_driver);
636
637 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
638 MODULE_DESCRIPTION("Rockchip SARADC driver");
639 MODULE_LICENSE("GPL v2");
640