1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
3 // All rights reserved.
4 //
5 // tegra210_i2s.c - Tegra210 I2S driver
6
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/of_graph.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <sound/core.h>
16 #include <sound/pcm_params.h>
17 #include <sound/simple_card_utils.h>
18 #include <sound/soc.h>
19 #include "tegra210_i2s.h"
20 #include "tegra_cif.h"
21
22 static const struct reg_default tegra210_i2s_reg_defaults[] = {
23 { TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
24 { TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
25 { TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
26 { TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
27 { TEGRA210_I2S_CG, 0x1 },
28 { TEGRA210_I2S_TIMING, 0x0000001f },
29 { TEGRA210_I2S_ENABLE, 0x1 },
30 /*
31 * Below update does not have any effect on Tegra186 and Tegra194.
32 * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
33 * is required to select i2s4b for it to be functional for I2S
34 * operation.
35 */
36 { TEGRA210_I2S_CYA, 0x1 },
37 };
38
39 static const struct reg_default tegra264_i2s_reg_defaults[] = {
40 { TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
41 { TEGRA210_I2S_RX_CIF_CTRL, 0x00003f00 },
42 { TEGRA264_I2S_TX_INT_MASK, 0x00000003 },
43 { TEGRA264_I2S_TX_CIF_CTRL, 0x00003f00 },
44 { TEGRA264_I2S_CG, 0x1 },
45 { TEGRA264_I2S_TIMING, 0x0000001f },
46 { TEGRA264_I2S_ENABLE, 0x1 },
47 { TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE, 0x1 },
48 { TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE, 0x1 },
49 };
50
tegra210_i2s_set_slot_ctrl(struct tegra210_i2s * i2s,unsigned int total_slots,unsigned int tx_slot_mask,unsigned int rx_slot_mask)51 static void tegra210_i2s_set_slot_ctrl(struct tegra210_i2s *i2s,
52 unsigned int total_slots,
53 unsigned int tx_slot_mask,
54 unsigned int rx_slot_mask)
55 {
56 regmap_write(i2s->regmap, TEGRA210_I2S_SLOT_CTRL + i2s->soc_data->i2s_ctrl_offset,
57 total_slots - 1);
58 regmap_write(i2s->regmap, TEGRA210_I2S_TX_SLOT_CTRL + i2s->soc_data->tx_offset,
59 tx_slot_mask);
60 regmap_write(i2s->regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask);
61 }
62
tegra210_i2s_set_clock_rate(struct device * dev,unsigned int clock_rate)63 static int tegra210_i2s_set_clock_rate(struct device *dev,
64 unsigned int clock_rate)
65 {
66 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
67 unsigned int val;
68 int err;
69
70 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val);
71
72 /* No need to set rates if I2S is being operated in slave */
73 if (!(val & I2S_CTRL_MASTER_EN))
74 return 0;
75
76 err = clk_set_rate(i2s->clk_i2s, clock_rate);
77 if (err) {
78 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
79 clock_rate, err);
80 return err;
81 }
82
83 if (!IS_ERR(i2s->clk_sync_input)) {
84 /*
85 * Other I/O modules in AHUB can use i2s bclk as reference
86 * clock. Below sets sync input clock rate as per bclk,
87 * which can be used as input to other I/O modules.
88 */
89 err = clk_set_rate(i2s->clk_sync_input, clock_rate);
90 if (err) {
91 dev_err(dev,
92 "can't set I2S sync input rate %u, err = %d\n",
93 clock_rate, err);
94 return err;
95 }
96 }
97
98 return 0;
99 }
100
tegra210_i2s_sw_reset(struct snd_soc_component * compnt,int stream)101 static int tegra210_i2s_sw_reset(struct snd_soc_component *compnt,
102 int stream)
103 {
104 struct device *dev = compnt->dev;
105 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
106 unsigned int reset_mask = I2S_SOFT_RESET_MASK;
107 unsigned int reset_en = I2S_SOFT_RESET_EN;
108 unsigned int reset_reg, cif_reg, stream_reg;
109 unsigned int cif_ctrl, stream_ctrl, i2s_ctrl, val;
110 int err;
111
112 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
113 reset_reg = TEGRA210_I2S_RX_SOFT_RESET;
114 cif_reg = TEGRA210_I2S_RX_CIF_CTRL;
115 stream_reg = TEGRA210_I2S_RX_CTRL;
116 } else {
117 reset_reg = TEGRA210_I2S_TX_SOFT_RESET + i2s->soc_data->tx_offset;
118 cif_reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset;
119 stream_reg = TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset;
120 }
121
122 /* Store CIF and I2S control values */
123 regmap_read(i2s->regmap, cif_reg, &cif_ctrl);
124 regmap_read(i2s->regmap, stream_reg, &stream_ctrl);
125 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &i2s_ctrl);
126
127 /* Reset to make sure the previous transactions are clean */
128 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);
129
130 err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,
131 !(val & reset_mask & reset_en),
132 10, 10000);
133 if (err) {
134 dev_err(dev, "timeout: failed to reset I2S for %s\n",
135 snd_pcm_direction_name(stream));
136 return err;
137 }
138
139 /* Restore CIF and I2S control values */
140 regmap_write(i2s->regmap, cif_reg, cif_ctrl);
141 regmap_write(i2s->regmap, stream_reg, stream_ctrl);
142 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, i2s_ctrl);
143
144 return 0;
145 }
146
tegra210_i2s_init(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)147 static int tegra210_i2s_init(struct snd_soc_dapm_widget *w,
148 struct snd_kcontrol *kcontrol, int event)
149 {
150 struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm);
151 struct device *dev = compnt->dev;
152 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
153 unsigned int val, status_reg;
154 int stream;
155 int err;
156
157 if (w->reg == TEGRA210_I2S_RX_ENABLE) {
158 stream = SNDRV_PCM_STREAM_PLAYBACK;
159 status_reg = TEGRA210_I2S_RX_STATUS;
160 } else if (w->reg == (TEGRA210_I2S_TX_ENABLE + i2s->soc_data->tx_offset)) {
161 stream = SNDRV_PCM_STREAM_CAPTURE;
162 status_reg = TEGRA210_I2S_TX_STATUS + i2s->soc_data->tx_offset;
163 } else {
164 return -EINVAL;
165 }
166
167 /* Ensure I2S is in disabled state before new session */
168 err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,
169 !(val & I2S_EN_MASK & I2S_EN),
170 10, 10000);
171 if (err) {
172 dev_err(dev, "timeout: previous I2S %s is still active\n",
173 snd_pcm_direction_name(stream));
174 return err;
175 }
176
177 return tegra210_i2s_sw_reset(compnt, stream);
178 }
179
tegra210_i2s_runtime_suspend(struct device * dev)180 static int tegra210_i2s_runtime_suspend(struct device *dev)
181 {
182 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
183
184 regcache_cache_only(i2s->regmap, true);
185 regcache_mark_dirty(i2s->regmap);
186
187 clk_disable_unprepare(i2s->clk_i2s);
188
189 return 0;
190 }
191
tegra210_i2s_runtime_resume(struct device * dev)192 static int tegra210_i2s_runtime_resume(struct device *dev)
193 {
194 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
195 int err;
196
197 err = clk_prepare_enable(i2s->clk_i2s);
198 if (err) {
199 dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err);
200 return err;
201 }
202
203 regcache_cache_only(i2s->regmap, false);
204 regcache_sync(i2s->regmap);
205
206 return 0;
207 }
208
tegra210_i2s_set_data_offset(struct tegra210_i2s * i2s,unsigned int data_offset)209 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
210 unsigned int data_offset)
211 {
212 /* Capture path */
213 regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset,
214 I2S_CTRL_DATA_OFFSET_MASK,
215 data_offset << I2S_DATA_SHIFT);
216
217 /* Playback path */
218 regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,
219 I2S_CTRL_DATA_OFFSET_MASK,
220 data_offset << I2S_DATA_SHIFT);
221 }
222
tegra210_i2s_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)223 static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
224 unsigned int fmt)
225 {
226 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
227 unsigned int mask, val;
228
229 mask = I2S_CTRL_MASTER_EN_MASK;
230 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
231 case SND_SOC_DAIFMT_BC_FC:
232 val = 0;
233 break;
234 case SND_SOC_DAIFMT_BP_FP:
235 val = I2S_CTRL_MASTER_EN;
236 break;
237 default:
238 return -EINVAL;
239 }
240
241 mask |= I2S_CTRL_FRAME_FMT_MASK | I2S_CTRL_LRCK_POL_MASK;
242 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
243 case SND_SOC_DAIFMT_DSP_A:
244 val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
245 val |= I2S_CTRL_LRCK_POL_HIGH;
246 tegra210_i2s_set_data_offset(i2s, 1);
247 break;
248 case SND_SOC_DAIFMT_DSP_B:
249 val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
250 val |= I2S_CTRL_LRCK_POL_HIGH;
251 tegra210_i2s_set_data_offset(i2s, 0);
252 break;
253 /* I2S mode has data offset of 1 */
254 case SND_SOC_DAIFMT_I2S:
255 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
256 val |= I2S_CTRL_LRCK_POL_LOW;
257 tegra210_i2s_set_data_offset(i2s, 1);
258 break;
259 /*
260 * For RJ mode data offset is dependent on the sample size
261 * and the bclk ratio, and so is set when hw_params is called.
262 */
263 case SND_SOC_DAIFMT_RIGHT_J:
264 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
265 val |= I2S_CTRL_LRCK_POL_HIGH;
266 break;
267 case SND_SOC_DAIFMT_LEFT_J:
268 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
269 val |= I2S_CTRL_LRCK_POL_HIGH;
270 tegra210_i2s_set_data_offset(i2s, 0);
271 break;
272 default:
273 return -EINVAL;
274 }
275
276 mask |= I2S_CTRL_EDGE_CTRL_MASK;
277 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
278 case SND_SOC_DAIFMT_NB_NF:
279 val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
280 break;
281 case SND_SOC_DAIFMT_NB_IF:
282 val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
283 val ^= I2S_CTRL_LRCK_POL_MASK;
284 break;
285 case SND_SOC_DAIFMT_IB_NF:
286 val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
287 break;
288 case SND_SOC_DAIFMT_IB_IF:
289 val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
290 val ^= I2S_CTRL_LRCK_POL_MASK;
291 break;
292 default:
293 return -EINVAL;
294 }
295
296 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset,
297 mask, val);
298
299 i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
300
301 return 0;
302 }
303
tegra210_i2s_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)304 static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai,
305 unsigned int tx_mask, unsigned int rx_mask,
306 int slots, int slot_width)
307 {
308 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
309
310 /* Copy the required tx and rx mask */
311 i2s->tx_mask = (tx_mask > i2s->soc_data->slot_mask) ?
312 i2s->soc_data->slot_mask : tx_mask;
313 i2s->rx_mask = (rx_mask > i2s->soc_data->slot_mask) ?
314 i2s->soc_data->slot_mask : rx_mask;
315
316 return 0;
317 }
318
tegra210_i2s_get_loopback(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)319 static int tegra210_i2s_get_loopback(struct snd_kcontrol *kcontrol,
320 struct snd_ctl_elem_value *ucontrol)
321 {
322 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
323 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
324
325 ucontrol->value.integer.value[0] = i2s->loopback;
326
327 return 0;
328 }
329
tegra210_i2s_put_loopback(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)330 static int tegra210_i2s_put_loopback(struct snd_kcontrol *kcontrol,
331 struct snd_ctl_elem_value *ucontrol)
332 {
333 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
334 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
335 int value = ucontrol->value.integer.value[0];
336
337 if (value == i2s->loopback)
338 return 0;
339
340 i2s->loopback = value;
341
342 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset,
343 I2S_CTRL_LPBK_MASK, i2s->loopback << I2S_CTRL_LPBK_SHIFT);
344
345 return 1;
346 }
347
tegra210_i2s_get_fsync_width(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)348 static int tegra210_i2s_get_fsync_width(struct snd_kcontrol *kcontrol,
349 struct snd_ctl_elem_value *ucontrol)
350 {
351 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
352 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
353
354 ucontrol->value.integer.value[0] = i2s->fsync_width;
355
356 return 0;
357 }
358
tegra210_i2s_put_fsync_width(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)359 static int tegra210_i2s_put_fsync_width(struct snd_kcontrol *kcontrol,
360 struct snd_ctl_elem_value *ucontrol)
361 {
362 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
363 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
364 int value = ucontrol->value.integer.value[0];
365
366 if (value == i2s->fsync_width)
367 return 0;
368
369 i2s->fsync_width = value;
370
371 /*
372 * Frame sync width is used only for FSYNC modes and not
373 * applicable for LRCK modes. Reset value for this field is "0",
374 * which means the width is one bit clock wide.
375 * The width requirement may depend on the codec and in such
376 * cases mixer control is used to update custom values. A value
377 * of "N" here means, width is "N + 1" bit clock wide.
378 */
379 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset,
380 i2s->soc_data->fsync_width_mask,
381 i2s->fsync_width << i2s->soc_data->fsync_width_shift);
382
383 return 1;
384 }
385
tegra210_i2s_cget_stereo_to_mono(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)386 static int tegra210_i2s_cget_stereo_to_mono(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_value *ucontrol)
388 {
389 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
390 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
391
392 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH];
393
394 return 0;
395 }
396
tegra210_i2s_cput_stereo_to_mono(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)397 static int tegra210_i2s_cput_stereo_to_mono(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_value *ucontrol)
399 {
400 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
401 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
402 unsigned int value = ucontrol->value.enumerated.item[0];
403
404 if (value == i2s->stereo_to_mono[I2S_TX_PATH])
405 return 0;
406
407 i2s->stereo_to_mono[I2S_TX_PATH] = value;
408
409 return 1;
410 }
411
tegra210_i2s_cget_mono_to_stereo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)412 static int tegra210_i2s_cget_mono_to_stereo(struct snd_kcontrol *kcontrol,
413 struct snd_ctl_elem_value *ucontrol)
414 {
415 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
416 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
417
418 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH];
419
420 return 0;
421 }
422
tegra210_i2s_cput_mono_to_stereo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)423 static int tegra210_i2s_cput_mono_to_stereo(struct snd_kcontrol *kcontrol,
424 struct snd_ctl_elem_value *ucontrol)
425 {
426 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
427 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
428 unsigned int value = ucontrol->value.enumerated.item[0];
429
430 if (value == i2s->mono_to_stereo[I2S_TX_PATH])
431 return 0;
432
433 i2s->mono_to_stereo[I2S_TX_PATH] = value;
434
435 return 1;
436 }
437
tegra210_i2s_pget_stereo_to_mono(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)438 static int tegra210_i2s_pget_stereo_to_mono(struct snd_kcontrol *kcontrol,
439 struct snd_ctl_elem_value *ucontrol)
440 {
441 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
442 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
443
444 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH];
445
446 return 0;
447 }
448
tegra210_i2s_pput_stereo_to_mono(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)449 static int tegra210_i2s_pput_stereo_to_mono(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_value *ucontrol)
451 {
452 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
453 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
454 unsigned int value = ucontrol->value.enumerated.item[0];
455
456 if (value == i2s->stereo_to_mono[I2S_RX_PATH])
457 return 0;
458
459 i2s->stereo_to_mono[I2S_RX_PATH] = value;
460
461 return 1;
462 }
463
tegra210_i2s_pget_mono_to_stereo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)464 static int tegra210_i2s_pget_mono_to_stereo(struct snd_kcontrol *kcontrol,
465 struct snd_ctl_elem_value *ucontrol)
466 {
467 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
468 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
469
470 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH];
471
472 return 0;
473 }
474
tegra210_i2s_pput_mono_to_stereo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)475 static int tegra210_i2s_pput_mono_to_stereo(struct snd_kcontrol *kcontrol,
476 struct snd_ctl_elem_value *ucontrol)
477 {
478 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
479 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
480 unsigned int value = ucontrol->value.enumerated.item[0];
481
482 if (value == i2s->mono_to_stereo[I2S_RX_PATH])
483 return 0;
484
485 i2s->mono_to_stereo[I2S_RX_PATH] = value;
486
487 return 1;
488 }
489
tegra210_i2s_pget_fifo_th(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)490 static int tegra210_i2s_pget_fifo_th(struct snd_kcontrol *kcontrol,
491 struct snd_ctl_elem_value *ucontrol)
492 {
493 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
494 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
495
496 ucontrol->value.integer.value[0] = i2s->rx_fifo_th;
497
498 return 0;
499 }
500
tegra210_i2s_pput_fifo_th(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)501 static int tegra210_i2s_pput_fifo_th(struct snd_kcontrol *kcontrol,
502 struct snd_ctl_elem_value *ucontrol)
503 {
504 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
505 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
506 int value = ucontrol->value.integer.value[0];
507
508 if (value == i2s->rx_fifo_th)
509 return 0;
510
511 i2s->rx_fifo_th = value;
512
513 return 1;
514 }
515
tegra210_i2s_get_bclk_ratio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)516 static int tegra210_i2s_get_bclk_ratio(struct snd_kcontrol *kcontrol,
517 struct snd_ctl_elem_value *ucontrol)
518 {
519 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
520 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
521
522 ucontrol->value.integer.value[0] = i2s->bclk_ratio;
523
524 return 0;
525 }
526
tegra210_i2s_put_bclk_ratio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)527 static int tegra210_i2s_put_bclk_ratio(struct snd_kcontrol *kcontrol,
528 struct snd_ctl_elem_value *ucontrol)
529 {
530 struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
531 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
532 int value = ucontrol->value.integer.value[0];
533
534 if (value == i2s->bclk_ratio)
535 return 0;
536
537 i2s->bclk_ratio = value;
538
539 return 1;
540 }
541
tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)542 static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
543 unsigned int ratio)
544 {
545 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
546
547 i2s->bclk_ratio = ratio;
548
549 return 0;
550 }
551
tegra210_i2s_set_timing_params(struct device * dev,unsigned int sample_size,unsigned int srate,unsigned int channels)552 static int tegra210_i2s_set_timing_params(struct device *dev,
553 unsigned int sample_size,
554 unsigned int srate,
555 unsigned int channels)
556 {
557 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
558 unsigned int val, bit_count, bclk_rate, num_bclk = sample_size;
559 int err;
560
561 if (i2s->bclk_ratio)
562 num_bclk *= i2s->bclk_ratio;
563
564 if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)
565 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);
566
567 /* I2S bit clock rate */
568 bclk_rate = srate * channels * num_bclk;
569
570 err = tegra210_i2s_set_clock_rate(dev, bclk_rate);
571 if (err) {
572 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
573 bclk_rate, err);
574 return err;
575 }
576
577 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val);
578
579 /*
580 * For LRCK mode, channel bit count depends on number of bit clocks
581 * on the left channel, where as for FSYNC mode bit count depends on
582 * the number of bit clocks in both left and right channels for DSP
583 * mode or the number of bit clocks in one TDM frame.
584 *
585 */
586 switch (val & I2S_CTRL_FRAME_FMT_MASK) {
587 case I2S_CTRL_FRAME_FMT_LRCK_MODE:
588 bit_count = (bclk_rate / (srate * 2)) - 1;
589 break;
590 case I2S_CTRL_FRAME_FMT_FSYNC_MODE:
591 bit_count = (bclk_rate / srate) - 1;
592
593 tegra210_i2s_set_slot_ctrl(i2s, channels,
594 i2s->tx_mask, i2s->rx_mask);
595 break;
596 default:
597 dev_err(dev, "invalid I2S frame format\n");
598 return -EINVAL;
599 }
600
601 if (bit_count > I2S_TIMING_CH_BIT_CNT_MASK) {
602 dev_err(dev, "invalid I2S channel bit count %u\n", bit_count);
603 return -EINVAL;
604 }
605
606 regmap_write(i2s->regmap, TEGRA210_I2S_TIMING + i2s->soc_data->i2s_ctrl_offset,
607 bit_count << I2S_TIMING_CH_BIT_CNT_SHIFT);
608
609 return 0;
610 }
611
tegra210_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)612 static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream,
613 struct snd_pcm_hw_params *params,
614 struct snd_soc_dai *dai)
615 {
616 struct device *dev = dai->dev;
617 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
618 unsigned int sample_size, channels, srate, val, reg, path;
619 struct tegra_cif_conf cif_conf;
620 snd_pcm_format_t sample_format;
621
622 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
623
624 channels = params_channels(params);
625 if (channels < 1) {
626 dev_err(dev, "invalid I2S %d channel configuration\n",
627 channels);
628 return -EINVAL;
629 }
630
631 cif_conf.audio_ch = channels;
632 cif_conf.client_ch = channels;
633 if (i2s->client_channels)
634 cif_conf.client_ch = i2s->client_channels;
635
636 /* AHUB CIF Audio bits configs */
637 switch (params_format(params)) {
638 case SNDRV_PCM_FORMAT_S8:
639 cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
640 break;
641 case SNDRV_PCM_FORMAT_S16_LE:
642 cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
643 break;
644 case SNDRV_PCM_FORMAT_S24_LE:
645 case SNDRV_PCM_FORMAT_S32_LE:
646 cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
647 break;
648 default:
649 dev_err(dev, "unsupported params audio bit format!\n");
650 return -EOPNOTSUPP;
651 }
652
653 sample_format = params_format(params);
654 if (i2s->client_sample_format >= 0)
655 sample_format = (snd_pcm_format_t)i2s->client_sample_format;
656
657 /*
658 * Format of the I2S for sending/receiving the audio
659 * to/from external device.
660 */
661 switch (sample_format) {
662 case SNDRV_PCM_FORMAT_S8:
663 val = I2S_BITS_8;
664 sample_size = 8;
665 cif_conf.client_bits = TEGRA_ACIF_BITS_8;
666 break;
667 case SNDRV_PCM_FORMAT_S16_LE:
668 val = I2S_BITS_16;
669 sample_size = 16;
670 cif_conf.client_bits = TEGRA_ACIF_BITS_16;
671 break;
672 case SNDRV_PCM_FORMAT_S24_LE:
673 val = I2S_BITS_24;
674 sample_size = 32;
675 cif_conf.client_bits = TEGRA_ACIF_BITS_24;
676 break;
677 case SNDRV_PCM_FORMAT_S32_LE:
678 val = I2S_BITS_32;
679 sample_size = 32;
680 cif_conf.client_bits = TEGRA_ACIF_BITS_32;
681 break;
682 default:
683 dev_err(dev, "unsupported client bit format!\n");
684 return -EOPNOTSUPP;
685 }
686
687 /* Program sample size */
688 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset,
689 I2S_CTRL_BIT_SIZE_MASK, val);
690
691 srate = params_rate(params);
692
693 /* For playback I2S RX-CIF and for capture TX-CIF is used */
694 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
695 path = I2S_RX_PATH;
696 else
697 path = I2S_TX_PATH;
698
699 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
700 unsigned int max_th;
701
702 /* FIFO threshold in terms of frames */
703 max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
704
705 if (i2s->rx_fifo_th > max_th)
706 i2s->rx_fifo_th = max_th;
707
708 cif_conf.threshold = i2s->rx_fifo_th;
709
710 reg = TEGRA210_I2S_RX_CIF_CTRL;
711 } else {
712 reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset;
713 }
714
715 cif_conf.mono_conv = i2s->mono_to_stereo[path];
716 cif_conf.stereo_conv = i2s->stereo_to_mono[path];
717
718 if (i2s->soc_data->max_ch == TEGRA264_I2S_MAX_CHANNEL)
719 tegra264_set_cif(i2s->regmap, reg, &cif_conf);
720 else
721 tegra_set_cif(i2s->regmap, reg, &cif_conf);
722
723 return tegra210_i2s_set_timing_params(dev, sample_size, srate,
724 cif_conf.client_ch);
725 }
726
727 static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = {
728 .set_fmt = tegra210_i2s_set_fmt,
729 .hw_params = tegra210_i2s_hw_params,
730 .set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio,
731 .set_tdm_slot = tegra210_i2s_set_tdm_slot,
732 };
733
734 static struct snd_soc_dai_driver tegra210_i2s_dais[] = {
735 {
736 .name = "I2S-CIF",
737 .playback = {
738 .stream_name = "CIF-Playback",
739 .channels_min = 1,
740 .channels_max = 16,
741 .rates = SNDRV_PCM_RATE_8000_192000,
742 .formats = SNDRV_PCM_FMTBIT_S8 |
743 SNDRV_PCM_FMTBIT_S16_LE |
744 SNDRV_PCM_FMTBIT_S24_LE |
745 SNDRV_PCM_FMTBIT_S32_LE,
746 },
747 .capture = {
748 .stream_name = "CIF-Capture",
749 .channels_min = 1,
750 .channels_max = 16,
751 .rates = SNDRV_PCM_RATE_8000_192000,
752 .formats = SNDRV_PCM_FMTBIT_S8 |
753 SNDRV_PCM_FMTBIT_S16_LE |
754 SNDRV_PCM_FMTBIT_S24_LE |
755 SNDRV_PCM_FMTBIT_S32_LE,
756 },
757 },
758 {
759 .name = "I2S-DAP",
760 .playback = {
761 .stream_name = "DAP-Playback",
762 .channels_min = 1,
763 .channels_max = 16,
764 .rates = SNDRV_PCM_RATE_8000_192000,
765 .formats = SNDRV_PCM_FMTBIT_S8 |
766 SNDRV_PCM_FMTBIT_S16_LE |
767 SNDRV_PCM_FMTBIT_S24_LE |
768 SNDRV_PCM_FMTBIT_S32_LE,
769 },
770 .capture = {
771 .stream_name = "DAP-Capture",
772 .channels_min = 1,
773 .channels_max = 16,
774 .rates = SNDRV_PCM_RATE_8000_192000,
775 .formats = SNDRV_PCM_FMTBIT_S8 |
776 SNDRV_PCM_FMTBIT_S16_LE |
777 SNDRV_PCM_FMTBIT_S24_LE |
778 SNDRV_PCM_FMTBIT_S32_LE,
779 },
780 .ops = &tegra210_i2s_dai_ops,
781 .symmetric_rate = 1,
782 },
783 };
784
785 static const char * const tegra210_i2s_stereo_conv_text[] = {
786 "CH0", "CH1", "AVG",
787 };
788
789 static const char * const tegra210_i2s_mono_conv_text[] = {
790 "Zero", "Copy",
791 };
792
793 static const struct soc_enum tegra210_i2s_mono_conv_enum =
794 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_mono_conv_text),
795 tegra210_i2s_mono_conv_text);
796
797 static const struct soc_enum tegra210_i2s_stereo_conv_enum =
798 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_stereo_conv_text),
799 tegra210_i2s_stereo_conv_text);
800
801 static const struct snd_kcontrol_new tegra210_i2s_controls[] = {
802 SOC_SINGLE_EXT("Loopback", 0, 0, 1, 0, tegra210_i2s_get_loopback,
803 tegra210_i2s_put_loopback),
804 SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0,
805 tegra210_i2s_get_fsync_width,
806 tegra210_i2s_put_fsync_width),
807 SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum,
808 tegra210_i2s_cget_stereo_to_mono,
809 tegra210_i2s_cput_stereo_to_mono),
810 SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum,
811 tegra210_i2s_cget_mono_to_stereo,
812 tegra210_i2s_cput_mono_to_stereo),
813 SOC_ENUM_EXT("Playback Stereo To Mono", tegra210_i2s_stereo_conv_enum,
814 tegra210_i2s_pget_mono_to_stereo,
815 tegra210_i2s_pput_mono_to_stereo),
816 SOC_ENUM_EXT("Playback Mono To Stereo", tegra210_i2s_mono_conv_enum,
817 tegra210_i2s_pget_stereo_to_mono,
818 tegra210_i2s_pput_stereo_to_mono),
819 SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
820 0, tegra210_i2s_pget_fifo_th, tegra210_i2s_pput_fifo_th),
821 SOC_SINGLE_EXT("BCLK Ratio", 0, 0, INT_MAX, 0,
822 tegra210_i2s_get_bclk_ratio,
823 tegra210_i2s_put_bclk_ratio),
824 };
825
826 #define TEGRA_I2S_WIDGETS(tx_enable_reg) \
827 SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE, \
828 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), \
829 SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, tx_enable_reg, \
830 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU), \
831 SND_SOC_DAPM_MIC("MIC", NULL), \
832 SND_SOC_DAPM_SPK("SPK", NULL),
833
834 static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = {
835 TEGRA_I2S_WIDGETS(TEGRA210_I2S_TX_ENABLE)
836 };
837
838 static const struct snd_soc_dapm_widget tegra264_i2s_widgets[] = {
839 TEGRA_I2S_WIDGETS(TEGRA264_I2S_TX_ENABLE)
840 };
841
842 static const struct snd_soc_dapm_route tegra210_i2s_routes[] = {
843 /* Playback route from XBAR */
844 { "XBAR-Playback", NULL, "XBAR-TX" },
845 { "CIF-Playback", NULL, "XBAR-Playback" },
846 { "RX", NULL, "CIF-Playback" },
847 { "DAP-Playback", NULL, "RX" },
848 { "SPK", NULL, "DAP-Playback" },
849 /* Capture route to XBAR */
850 { "XBAR-RX", NULL, "XBAR-Capture" },
851 { "XBAR-Capture", NULL, "CIF-Capture" },
852 { "CIF-Capture", NULL, "TX" },
853 { "TX", NULL, "DAP-Capture" },
854 { "DAP-Capture", NULL, "MIC" },
855 };
856
857 static const struct snd_soc_component_driver tegra210_i2s_cmpnt = {
858 .dapm_widgets = tegra210_i2s_widgets,
859 .num_dapm_widgets = ARRAY_SIZE(tegra210_i2s_widgets),
860 .dapm_routes = tegra210_i2s_routes,
861 .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes),
862 .controls = tegra210_i2s_controls,
863 .num_controls = ARRAY_SIZE(tegra210_i2s_controls),
864 };
865
866 static const struct snd_soc_component_driver tegra264_i2s_cmpnt = {
867 .dapm_widgets = tegra264_i2s_widgets,
868 .num_dapm_widgets = ARRAY_SIZE(tegra264_i2s_widgets),
869 .dapm_routes = tegra210_i2s_routes,
870 .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes),
871 .controls = tegra210_i2s_controls,
872 .num_controls = ARRAY_SIZE(tegra210_i2s_controls),
873 };
874
tegra210_i2s_wr_reg(struct device * dev,unsigned int reg)875 static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg)
876 {
877 switch (reg) {
878 case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET:
879 case TEGRA210_I2S_RX_INT_MASK ... TEGRA210_I2S_RX_CLK_TRIM:
880 case TEGRA210_I2S_TX_ENABLE ... TEGRA210_I2S_TX_SOFT_RESET:
881 case TEGRA210_I2S_TX_INT_MASK ... TEGRA210_I2S_TX_CLK_TRIM:
882 case TEGRA210_I2S_ENABLE ... TEGRA210_I2S_CG:
883 case TEGRA210_I2S_CTRL ... TEGRA210_I2S_CYA:
884 return true;
885 default:
886 return false;
887 }
888 }
889
tegra210_i2s_rd_reg(struct device * dev,unsigned int reg)890 static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg)
891 {
892 if (tegra210_i2s_wr_reg(dev, reg))
893 return true;
894
895 switch (reg) {
896 case TEGRA210_I2S_RX_STATUS:
897 case TEGRA210_I2S_RX_INT_STATUS:
898 case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
899 case TEGRA210_I2S_TX_STATUS:
900 case TEGRA210_I2S_TX_INT_STATUS:
901 case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
902 case TEGRA210_I2S_STATUS:
903 case TEGRA210_I2S_INT_STATUS:
904 return true;
905 default:
906 return false;
907 }
908 }
909
tegra210_i2s_volatile_reg(struct device * dev,unsigned int reg)910 static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg)
911 {
912 switch (reg) {
913 case TEGRA210_I2S_RX_STATUS:
914 case TEGRA210_I2S_RX_INT_STATUS:
915 case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
916 case TEGRA210_I2S_TX_STATUS:
917 case TEGRA210_I2S_TX_INT_STATUS:
918 case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
919 case TEGRA210_I2S_STATUS:
920 case TEGRA210_I2S_INT_STATUS:
921 case TEGRA210_I2S_RX_SOFT_RESET:
922 case TEGRA210_I2S_TX_SOFT_RESET:
923 return true;
924 default:
925 return false;
926 }
927 }
928
tegra264_i2s_wr_reg(struct device * dev,unsigned int reg)929 static bool tegra264_i2s_wr_reg(struct device *dev, unsigned int reg)
930 {
931 switch (reg) {
932 case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET:
933 case TEGRA210_I2S_RX_INT_MASK ... TEGRA264_I2S_RX_CYA:
934 case TEGRA264_I2S_TX_ENABLE ... TEGRA264_I2S_TX_SOFT_RESET:
935 case TEGRA264_I2S_TX_INT_MASK ... TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE:
936 case TEGRA264_I2S_TX_FIFO_THRESHOLD ... TEGRA264_I2S_TX_CYA:
937 case TEGRA264_I2S_ENABLE ... TEGRA264_I2S_CG:
938 case TEGRA264_I2S_INT_SET ... TEGRA264_I2S_INT_MASK:
939 case TEGRA264_I2S_CTRL ... TEGRA264_I2S_CYA:
940 return true;
941 default:
942 return false;
943 };
944 }
945
tegra264_i2s_rd_reg(struct device * dev,unsigned int reg)946 static bool tegra264_i2s_rd_reg(struct device *dev, unsigned int reg)
947 {
948 if (tegra264_i2s_wr_reg(dev, reg))
949 return true;
950
951 switch (reg) {
952 case TEGRA210_I2S_RX_STATUS:
953 case TEGRA210_I2S_RX_INT_STATUS:
954 case TEGRA264_I2S_RX_CIF_FIFO_STATUS:
955 case TEGRA264_I2S_TX_STATUS:
956 case TEGRA264_I2S_TX_INT_STATUS:
957 case TEGRA264_I2S_TX_FIFO_RD_DATA:
958 case TEGRA264_I2S_TX_CIF_FIFO_STATUS:
959 case TEGRA264_I2S_STATUS:
960 case TEGRA264_I2S_INT_STATUS:
961 case TEGRA264_I2S_PIO_MODE_ENABLE:
962 case TEGRA264_I2S_PAD_MACRO_STATUS:
963 return true;
964 default:
965 return false;
966 };
967 }
968
tegra264_i2s_volatile_reg(struct device * dev,unsigned int reg)969 static bool tegra264_i2s_volatile_reg(struct device *dev, unsigned int reg)
970 {
971 switch (reg) {
972 case TEGRA210_I2S_RX_SOFT_RESET:
973 case TEGRA210_I2S_RX_STATUS:
974 case TEGRA210_I2S_RX_INT_STATUS:
975 case TEGRA264_I2S_RX_CIF_FIFO_STATUS:
976 case TEGRA264_I2S_TX_STATUS:
977 case TEGRA264_I2S_TX_INT_STATUS:
978 case TEGRA264_I2S_TX_FIFO_RD_DATA:
979 case TEGRA264_I2S_TX_CIF_FIFO_STATUS:
980 case TEGRA264_I2S_STATUS:
981 case TEGRA264_I2S_INT_STATUS:
982 case TEGRA264_I2S_TX_SOFT_RESET:
983 case TEGRA264_I2S_PAD_MACRO_STATUS:
984 return true;
985 default:
986 return false;
987 };
988 }
989
990 static const struct regmap_config tegra210_regmap_conf = {
991 .reg_bits = 32,
992 .reg_stride = 4,
993 .val_bits = 32,
994 .max_register = TEGRA210_I2S_CYA,
995 .writeable_reg = tegra210_i2s_wr_reg,
996 .readable_reg = tegra210_i2s_rd_reg,
997 .volatile_reg = tegra210_i2s_volatile_reg,
998 .reg_defaults = tegra210_i2s_reg_defaults,
999 .num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults),
1000 .cache_type = REGCACHE_FLAT,
1001 };
1002
1003 /*
1004 * The AHUB HW modules are interconnected with CIF which are capable of
1005 * supporting Channel and Sample bit format conversion. This needs different
1006 * CIF Audio and client configuration. As one of the config comes from
1007 * params_channels() or params_format(), the extra configuration is passed from
1008 * CIF Port of DT I2S node which can help to perform this conversion.
1009 *
1010 * 4ch audio = 4ch client = 2ch 2ch
1011 * -----> ADMAIF -----------> CIF -------------> I2S ---->
1012 */
tegra210_parse_client_convert(struct device * dev)1013 static void tegra210_parse_client_convert(struct device *dev)
1014 {
1015 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
1016 struct device_node *ports, *ep;
1017 struct simple_util_data data = {};
1018 int cif_port = 0;
1019
1020 ports = of_get_child_by_name(dev->of_node, "ports");
1021 if (ports) {
1022 ep = of_graph_get_endpoint_by_regs(ports, cif_port, -1);
1023 if (ep) {
1024 simple_util_parse_convert(ep, NULL, &data);
1025 of_node_put(ep);
1026 }
1027 of_node_put(ports);
1028 }
1029
1030 if (data.convert_channels)
1031 i2s->client_channels = data.convert_channels;
1032
1033 if (data.convert_sample_format)
1034 i2s->client_sample_format = simple_util_get_sample_fmt(&data);
1035 }
1036
1037 static const struct regmap_config tegra264_regmap_conf = {
1038 .reg_bits = 32,
1039 .reg_stride = 4,
1040 .val_bits = 32,
1041 .max_register = TEGRA264_I2S_PAD_MACRO_STATUS,
1042 .writeable_reg = tegra264_i2s_wr_reg,
1043 .readable_reg = tegra264_i2s_rd_reg,
1044 .volatile_reg = tegra264_i2s_volatile_reg,
1045 .reg_defaults = tegra264_i2s_reg_defaults,
1046 .num_reg_defaults = ARRAY_SIZE(tegra264_i2s_reg_defaults),
1047 .cache_type = REGCACHE_FLAT,
1048 };
1049
tegra210_i2s_probe(struct platform_device * pdev)1050 static int tegra210_i2s_probe(struct platform_device *pdev)
1051 {
1052 struct device *dev = &pdev->dev;
1053 struct tegra210_i2s *i2s;
1054 void __iomem *regs;
1055 int err, id;
1056
1057 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
1058 if (!i2s)
1059 return -ENOMEM;
1060
1061 i2s->soc_data = of_device_get_match_data(&pdev->dev);
1062 i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;
1063 i2s->tx_mask = i2s->soc_data->slot_mask;
1064 i2s->rx_mask = i2s->soc_data->slot_mask;
1065 i2s->loopback = false;
1066 i2s->client_sample_format = -EINVAL;
1067
1068 dev_set_drvdata(dev, i2s);
1069
1070 i2s->clk_i2s = devm_clk_get(dev, "i2s");
1071 if (IS_ERR(i2s->clk_i2s)) {
1072 dev_err(dev, "can't retrieve I2S bit clock\n");
1073 return PTR_ERR(i2s->clk_i2s);
1074 }
1075
1076 /*
1077 * Not an error, as this clock is needed only when some other I/O
1078 * requires input clock from current I2S instance, which is
1079 * configurable from DT.
1080 */
1081 i2s->clk_sync_input = devm_clk_get(dev, "sync_input");
1082 if (IS_ERR(i2s->clk_sync_input))
1083 dev_dbg(dev, "can't retrieve I2S sync input clock\n");
1084
1085 regs = devm_platform_ioremap_resource(pdev, 0);
1086 if (IS_ERR(regs))
1087 return PTR_ERR(regs);
1088
1089 i2s->regmap = devm_regmap_init_mmio(dev, regs,
1090 i2s->soc_data->regmap_conf);
1091 if (IS_ERR(i2s->regmap)) {
1092 dev_err(dev, "regmap init failed\n");
1093 return PTR_ERR(i2s->regmap);
1094 }
1095
1096 tegra210_parse_client_convert(dev);
1097
1098 regcache_cache_only(i2s->regmap, true);
1099
1100 /* Update the dais max channel as per soc */
1101 for (id = 0; id < ARRAY_SIZE(tegra210_i2s_dais); id++) {
1102 tegra210_i2s_dais[id].playback.channels_max = i2s->soc_data->max_ch;
1103 tegra210_i2s_dais[id].capture.channels_max = i2s->soc_data->max_ch;
1104 }
1105
1106 err = devm_snd_soc_register_component(dev, i2s->soc_data->i2s_cmpnt,
1107 tegra210_i2s_dais,
1108 ARRAY_SIZE(tegra210_i2s_dais));
1109 if (err) {
1110 dev_err(dev, "can't register I2S component, err: %d\n", err);
1111 return err;
1112 }
1113
1114 pm_runtime_enable(dev);
1115
1116 return 0;
1117 }
1118
tegra210_i2s_remove(struct platform_device * pdev)1119 static void tegra210_i2s_remove(struct platform_device *pdev)
1120 {
1121 pm_runtime_disable(&pdev->dev);
1122 }
1123
1124 static const struct dev_pm_ops tegra210_i2s_pm_ops = {
1125 RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend,
1126 tegra210_i2s_runtime_resume, NULL)
1127 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1128 };
1129
1130 static const struct tegra_i2s_soc_data soc_data_tegra210 = {
1131 .regmap_conf = &tegra210_regmap_conf,
1132 .i2s_cmpnt = &tegra210_i2s_cmpnt,
1133 .max_ch = TEGRA210_I2S_MAX_CHANNEL,
1134 .tx_offset = TEGRA210_I2S_TX_OFFSET,
1135 .i2s_ctrl_offset = TEGRA210_I2S_CTRL_OFFSET,
1136 .fsync_width_mask = I2S_CTRL_FSYNC_WIDTH_MASK,
1137 .fsync_width_shift = I2S_FSYNC_WIDTH_SHIFT,
1138 .slot_mask = DEFAULT_I2S_SLOT_MASK,
1139 };
1140
1141 static const struct tegra_i2s_soc_data soc_data_tegra264 = {
1142 .regmap_conf = &tegra264_regmap_conf,
1143 .i2s_cmpnt = &tegra264_i2s_cmpnt,
1144 .max_ch = TEGRA264_I2S_MAX_CHANNEL,
1145 .tx_offset = TEGRA264_I2S_TX_OFFSET,
1146 .i2s_ctrl_offset = TEGRA264_I2S_CTRL_OFFSET,
1147 .fsync_width_mask = TEGRA264_I2S_CTRL_FSYNC_WIDTH_MASK,
1148 .fsync_width_shift = TEGRA264_I2S_FSYNC_WIDTH_SHIFT,
1149 .slot_mask = TEGRA264_DEFAULT_I2S_SLOT_MASK,
1150 };
1151
1152 static const struct of_device_id tegra210_i2s_of_match[] = {
1153 { .compatible = "nvidia,tegra210-i2s", .data = &soc_data_tegra210 },
1154 { .compatible = "nvidia,tegra264-i2s", .data = &soc_data_tegra264 },
1155 {},
1156 };
1157 MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match);
1158
1159 static struct platform_driver tegra210_i2s_driver = {
1160 .driver = {
1161 .name = "tegra210-i2s",
1162 .of_match_table = tegra210_i2s_of_match,
1163 .pm = pm_ptr(&tegra210_i2s_pm_ops),
1164 },
1165 .probe = tegra210_i2s_probe,
1166 .remove = tegra210_i2s_remove,
1167 };
1168 module_platform_driver(tegra210_i2s_driver)
1169
1170 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
1171 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");
1172 MODULE_LICENSE("GPL v2");
1173