1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
5 *
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory (Department of Computer Science and
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
9 * DARPA SSITH research programme.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 /*
34 * Intel Stratix 10 Service Layer
35 */
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/rman.h>
44 #include <sys/timeet.h>
45 #include <sys/timetc.h>
46 #include <sys/conf.h>
47 #include <sys/uio.h>
48 #include <sys/vmem.h>
49
50 #include <vm/vm.h>
51 #include <vm/pmap.h>
52
53 #include <dev/fdt/simplebus.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
57
58 #include <arm64/intel/intel-smc.h>
59 #include <arm64/intel/stratix10-svc.h>
60
61 #include <machine/bus.h>
62 #include <machine/cpu.h>
63 #include <machine/intr.h>
64
65 struct s10_svc_softc {
66 device_t dev;
67 vmem_t *vmem;
68 intel_smc_callfn_t callfn;
69 };
70
71 static int
s10_data_claim(struct s10_svc_softc * sc)72 s10_data_claim(struct s10_svc_softc *sc)
73 {
74 struct arm_smccc_res res;
75 register_t a0, a1, a2;
76 int ret;
77
78 ret = 0;
79
80 while (1) {
81 a0 = INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE;
82 a1 = 0;
83 a2 = 0;
84
85 ret = sc->callfn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
86 if (ret == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
87 continue;
88
89 break;
90 }
91
92 return (ret);
93 }
94
95 int
s10_svc_send(device_t dev,struct s10_svc_msg * msg)96 s10_svc_send(device_t dev, struct s10_svc_msg *msg)
97 {
98 struct s10_svc_softc *sc;
99 struct arm_smccc_res res;
100 register_t a0, a1, a2;
101 int ret;
102
103 sc = device_get_softc(dev);
104
105 a0 = 0;
106 a1 = 0;
107 a2 = 0;
108
109 switch (msg->command) {
110 case COMMAND_RECONFIG:
111 a0 = INTEL_SIP_SMC_FPGA_CONFIG_START;
112 a1 = msg->flags;
113 break;
114 case COMMAND_RECONFIG_DATA_SUBMIT:
115 a0 = INTEL_SIP_SMC_FPGA_CONFIG_WRITE;
116 a1 = (uint64_t)msg->payload;
117 a2 = (uint64_t)msg->payload_length;
118 break;
119 case COMMAND_RECONFIG_DATA_CLAIM:
120 ret = s10_data_claim(sc);
121 return (ret);
122 default:
123 return (-1);
124 }
125
126 ret = sc->callfn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
127
128 return (ret);
129 }
130
131 int
s10_svc_allocate_memory(device_t dev,struct s10_svc_mem * mem,int size)132 s10_svc_allocate_memory(device_t dev, struct s10_svc_mem *mem, int size)
133 {
134 struct s10_svc_softc *sc;
135
136 sc = device_get_softc(dev);
137
138 if (size <= 0)
139 return (EINVAL);
140
141 if (vmem_alloc(sc->vmem, size,
142 M_FIRSTFIT | M_NOWAIT, &mem->paddr)) {
143 device_printf(dev, "Can't allocate memory\n");
144 return (ENOMEM);
145 }
146
147 mem->size = size;
148 mem->fill = 0;
149 mem->vaddr = (vm_offset_t)pmap_mapdev(mem->paddr, mem->size);
150
151 return (0);
152 }
153
154 void
s10_svc_free_memory(device_t dev,struct s10_svc_mem * mem)155 s10_svc_free_memory(device_t dev, struct s10_svc_mem *mem)
156 {
157 struct s10_svc_softc *sc;
158
159 sc = device_get_softc(dev);
160
161 vmem_free(sc->vmem, mem->paddr, mem->size);
162 }
163
164 static int
s10_get_memory(struct s10_svc_softc * sc)165 s10_get_memory(struct s10_svc_softc *sc)
166 {
167 struct arm_smccc_res res;
168 vmem_addr_t addr;
169 vmem_size_t size;
170 vmem_t *vmem;
171
172 sc->callfn(INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM,
173 0, 0, 0, 0, 0, 0, 0, &res);
174 if (res.a0 != INTEL_SIP_SMC_STATUS_OK)
175 return (ENXIO);
176
177 vmem = vmem_create("stratix10 vmem", 0, 0, PAGE_SIZE,
178 PAGE_SIZE, M_BESTFIT | M_WAITOK);
179 if (vmem == NULL)
180 return (ENXIO);
181
182 addr = res.a1;
183 size = res.a2;
184
185 device_printf(sc->dev, "Shared memory address 0x%lx size 0x%lx\n",
186 addr, size);
187
188 vmem_add(vmem, addr, size, 0);
189
190 sc->vmem = vmem;
191
192 return (0);
193 }
194
195 static intel_smc_callfn_t
s10_svc_get_callfn(struct s10_svc_softc * sc,phandle_t node)196 s10_svc_get_callfn(struct s10_svc_softc *sc, phandle_t node)
197 {
198 char method[16];
199
200 if ((OF_getprop(node, "method", method, sizeof(method))) > 0) {
201 if (strcmp(method, "hvc") == 0)
202 return (arm_smccc_hvc);
203 else if (strcmp(method, "smc") == 0)
204 return (arm_smccc_smc);
205 else
206 device_printf(sc->dev,
207 "Invalid method \"%s\"\n", method);
208 } else
209 device_printf(sc->dev, "SMC method not provided\n");
210
211 return (NULL);
212 }
213
214 static int
s10_svc_probe(device_t dev)215 s10_svc_probe(device_t dev)
216 {
217
218 if (!ofw_bus_status_okay(dev))
219 return (ENXIO);
220
221 if (!ofw_bus_is_compatible(dev, "intel,stratix10-svc"))
222 return (ENXIO);
223
224 device_set_desc(dev, "Stratix 10 SVC");
225
226 return (BUS_PROBE_DEFAULT);
227 }
228
229 static int
s10_svc_attach(device_t dev)230 s10_svc_attach(device_t dev)
231 {
232 struct s10_svc_softc *sc;
233 phandle_t node;
234
235 node = ofw_bus_get_node(dev);
236
237 sc = device_get_softc(dev);
238 sc->dev = dev;
239
240 if (device_get_unit(dev) != 0)
241 return (ENXIO);
242
243 sc->callfn = s10_svc_get_callfn(sc, node);
244 if (sc->callfn == NULL)
245 return (ENXIO);
246
247 if (s10_get_memory(sc) != 0)
248 return (ENXIO);
249
250 return (0);
251 }
252
253 static device_method_t s10_svc_methods[] = {
254 DEVMETHOD(device_probe, s10_svc_probe),
255 DEVMETHOD(device_attach, s10_svc_attach),
256 { 0, 0 }
257 };
258
259 static driver_t s10_svc_driver = {
260 "s10_svc",
261 s10_svc_methods,
262 sizeof(struct s10_svc_softc),
263 };
264
265 EARLY_DRIVER_MODULE(s10_svc, simplebus, s10_svc_driver, 0, 0,
266 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
267