1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel Core SoC Power Management Controller Header File 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 10 */ 11 12 #ifndef PMC_CORE_H 13 #define PMC_CORE_H 14 15 #include <linux/acpi.h> 16 #include <linux/bits.h> 17 #include <linux/platform_device.h> 18 19 struct telem_endpoint; 20 21 #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) 22 23 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 24 #define MAX_NUM_PMC 3 25 #define S0IX_BLK_SIZE 4 26 27 /* PCH query */ 28 #define LPM_HEADER_OFFSET 1 29 #define LPM_REG_COUNT 28 30 #define LPM_MODE_OFFSET 1 31 32 /* Sunrise Point Power Management Controller PCI Device ID */ 33 #define SPT_PMC_PCI_DEVICE_ID 0x9d21 34 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 35 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c 36 #define SPT_PMC_PM_CFG_OFFSET 0x18 37 #define SPT_PMC_PM_STS_OFFSET 0x1c 38 #define SPT_PMC_MTPMC_OFFSET 0x20 39 #define SPT_PMC_MFPMC_OFFSET 0x38 40 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 41 #define SPT_PMC_VRIC1_OFFSET 0x31c 42 #define SPT_PMC_MPHY_CORE_STS_0 0x1143 43 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 44 #define SPT_PMC_MPHY_COM_STS_0 0x1155 45 #define SPT_PMC_MMIO_REG_LEN 0x1000 46 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 47 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 48 #define MTPMC_MASK 0xffff0000 49 #define PPFEAR_MAX_NUM_ENTRIES 12 50 #define SPT_PPFEAR_NUM_ENTRIES 5 51 #define SPT_PMC_READ_DISABLE_BIT 0x16 52 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 53 #define NUM_RETRIES 100 54 #define SPT_NUM_IP_IGN_ALLOWED 17 55 56 #define SPT_PMC_LTR_CUR_PLT 0x350 57 #define SPT_PMC_LTR_CUR_ASLT 0x354 58 #define SPT_PMC_LTR_SPA 0x360 59 #define SPT_PMC_LTR_SPB 0x364 60 #define SPT_PMC_LTR_SATA 0x368 61 #define SPT_PMC_LTR_GBE 0x36C 62 #define SPT_PMC_LTR_XHCI 0x370 63 #define SPT_PMC_LTR_RESERVED 0x374 64 #define SPT_PMC_LTR_ME 0x378 65 #define SPT_PMC_LTR_EVA 0x37C 66 #define SPT_PMC_LTR_SPC 0x380 67 #define SPT_PMC_LTR_AZ 0x384 68 #define SPT_PMC_LTR_LPSS 0x38C 69 #define SPT_PMC_LTR_CAM 0x390 70 #define SPT_PMC_LTR_SPD 0x394 71 #define SPT_PMC_LTR_SPE 0x398 72 #define SPT_PMC_LTR_ESPI 0x39C 73 #define SPT_PMC_LTR_SCC 0x3A0 74 #define SPT_PMC_LTR_ISH 0x3A4 75 76 /* Sunrise Point: PGD PFET Enable Ack Status Registers */ 77 enum ppfear_regs { 78 SPT_PMC_XRAM_PPFEAR0A = 0x590, 79 SPT_PMC_XRAM_PPFEAR0B, 80 SPT_PMC_XRAM_PPFEAR0C, 81 SPT_PMC_XRAM_PPFEAR0D, 82 SPT_PMC_XRAM_PPFEAR1A, 83 }; 84 85 #define SPT_PMC_BIT_PMC BIT(0) 86 #define SPT_PMC_BIT_OPI BIT(1) 87 #define SPT_PMC_BIT_SPI BIT(2) 88 #define SPT_PMC_BIT_XHCI BIT(3) 89 #define SPT_PMC_BIT_SPA BIT(4) 90 #define SPT_PMC_BIT_SPB BIT(5) 91 #define SPT_PMC_BIT_SPC BIT(6) 92 #define SPT_PMC_BIT_GBE BIT(7) 93 94 #define SPT_PMC_BIT_SATA BIT(0) 95 #define SPT_PMC_BIT_HDA_PGD0 BIT(1) 96 #define SPT_PMC_BIT_HDA_PGD1 BIT(2) 97 #define SPT_PMC_BIT_HDA_PGD2 BIT(3) 98 #define SPT_PMC_BIT_HDA_PGD3 BIT(4) 99 #define SPT_PMC_BIT_RSVD_0B BIT(5) 100 #define SPT_PMC_BIT_LPSS BIT(6) 101 #define SPT_PMC_BIT_LPC BIT(7) 102 103 #define SPT_PMC_BIT_SMB BIT(0) 104 #define SPT_PMC_BIT_ISH BIT(1) 105 #define SPT_PMC_BIT_P2SB BIT(2) 106 #define SPT_PMC_BIT_DFX BIT(3) 107 #define SPT_PMC_BIT_SCC BIT(4) 108 #define SPT_PMC_BIT_RSVD_0C BIT(5) 109 #define SPT_PMC_BIT_FUSE BIT(6) 110 #define SPT_PMC_BIT_CAMREA BIT(7) 111 112 #define SPT_PMC_BIT_RSVD_0D BIT(0) 113 #define SPT_PMC_BIT_USB3_OTG BIT(1) 114 #define SPT_PMC_BIT_EXI BIT(2) 115 #define SPT_PMC_BIT_CSE BIT(3) 116 #define SPT_PMC_BIT_CSME_KVM BIT(4) 117 #define SPT_PMC_BIT_CSME_PMT BIT(5) 118 #define SPT_PMC_BIT_CSME_CLINK BIT(6) 119 #define SPT_PMC_BIT_CSME_PTIO BIT(7) 120 121 #define SPT_PMC_BIT_CSME_USBR BIT(0) 122 #define SPT_PMC_BIT_CSME_SUSRAM BIT(1) 123 #define SPT_PMC_BIT_CSME_SMT BIT(2) 124 #define SPT_PMC_BIT_RSVD_1A BIT(3) 125 #define SPT_PMC_BIT_CSME_SMS2 BIT(4) 126 #define SPT_PMC_BIT_CSME_SMS1 BIT(5) 127 #define SPT_PMC_BIT_CSME_RTC BIT(6) 128 #define SPT_PMC_BIT_CSME_PSF BIT(7) 129 130 #define SPT_PMC_BIT_MPHY_LANE0 BIT(0) 131 #define SPT_PMC_BIT_MPHY_LANE1 BIT(1) 132 #define SPT_PMC_BIT_MPHY_LANE2 BIT(2) 133 #define SPT_PMC_BIT_MPHY_LANE3 BIT(3) 134 #define SPT_PMC_BIT_MPHY_LANE4 BIT(4) 135 #define SPT_PMC_BIT_MPHY_LANE5 BIT(5) 136 #define SPT_PMC_BIT_MPHY_LANE6 BIT(6) 137 #define SPT_PMC_BIT_MPHY_LANE7 BIT(7) 138 139 #define SPT_PMC_BIT_MPHY_LANE8 BIT(0) 140 #define SPT_PMC_BIT_MPHY_LANE9 BIT(1) 141 #define SPT_PMC_BIT_MPHY_LANE10 BIT(2) 142 #define SPT_PMC_BIT_MPHY_LANE11 BIT(3) 143 #define SPT_PMC_BIT_MPHY_LANE12 BIT(4) 144 #define SPT_PMC_BIT_MPHY_LANE13 BIT(5) 145 #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) 146 #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) 147 148 #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) 149 #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) 150 #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 151 #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 152 153 #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) 154 #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) 155 156 /* Cannonlake Power Management Controller register offsets */ 157 #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 158 #define CNP_PMC_PM_CFG_OFFSET 0x1818 159 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C 160 #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C 161 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ 162 #define CNP_PMC_HOST_PPFEAR0A 0x1D90 163 164 #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) 165 166 #define CNP_PMC_MMIO_REG_LEN 0x2000 167 #define CNP_PPFEAR_NUM_ENTRIES 8 168 #define CNP_PMC_READ_DISABLE_BIT 22 169 #define CNP_NUM_IP_IGN_ALLOWED 19 170 #define CNP_PMC_LTR_CUR_PLT 0x1B50 171 #define CNP_PMC_LTR_CUR_ASLT 0x1B54 172 #define CNP_PMC_LTR_SPA 0x1B60 173 #define CNP_PMC_LTR_SPB 0x1B64 174 #define CNP_PMC_LTR_SATA 0x1B68 175 #define CNP_PMC_LTR_GBE 0x1B6C 176 #define CNP_PMC_LTR_XHCI 0x1B70 177 #define CNP_PMC_LTR_RESERVED 0x1B74 178 #define CNP_PMC_LTR_ME 0x1B78 179 #define CNP_PMC_LTR_EVA 0x1B7C 180 #define CNP_PMC_LTR_SPC 0x1B80 181 #define CNP_PMC_LTR_AZ 0x1B84 182 #define CNP_PMC_LTR_LPSS 0x1B8C 183 #define CNP_PMC_LTR_CAM 0x1B90 184 #define CNP_PMC_LTR_SPD 0x1B94 185 #define CNP_PMC_LTR_SPE 0x1B98 186 #define CNP_PMC_LTR_ESPI 0x1B9C 187 #define CNP_PMC_LTR_SCC 0x1BA0 188 #define CNP_PMC_LTR_ISH 0x1BA4 189 #define CNP_PMC_LTR_CNV 0x1BF0 190 #define CNP_PMC_LTR_EMMC 0x1BF4 191 #define CNP_PMC_LTR_UFSX2 0x1BF8 192 193 #define LTR_DECODED_VAL GENMASK(9, 0) 194 #define LTR_DECODED_SCALE GENMASK(12, 10) 195 #define LTR_REQ_SNOOP BIT(15) 196 #define LTR_REQ_NONSNOOP BIT(31) 197 198 #define ICL_PPFEAR_NUM_ENTRIES 9 199 #define ICL_NUM_IP_IGN_ALLOWED 20 200 #define ICL_PMC_LTR_WIGIG 0x1BFC 201 #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 202 203 #define LPM_MAX_NUM_MODES 8 204 #define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 } 205 206 #define GET_X2_COUNTER(v) ((v) >> 1) 207 #define LPM_STS_LATCH_MODE BIT(31) 208 209 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A 210 #define TGL_PMC_LTR_THC0 0x1C04 211 #define TGL_PMC_LTR_THC1 0x1C08 212 #define TGL_NUM_IP_IGN_ALLOWED 23 213 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ 214 215 #define ADL_PMC_LTR_SPF 0x1C00 216 #define ADL_NUM_IP_IGN_ALLOWED 23 217 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 218 219 /* 220 * Tigerlake Power Management Controller register offsets 221 */ 222 #define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34 223 #define TGL_LPM_EN_OFFSET 0x1C78 224 #define TGL_LPM_RESIDENCY_OFFSET 0x1C80 225 226 /* Tigerlake Low Power Mode debug registers */ 227 #define TGL_LPM_STATUS_OFFSET 0x1C3C 228 #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C 229 #define TGL_LPM_PRI_OFFSET 0x1C7C 230 #define TGL_LPM_NUM_MAPS 6 231 232 /* Tigerlake PSON residency register */ 233 #define TGL_PSON_RESIDENCY_OFFSET 0x18f8 234 #define TGL_PSON_RES_COUNTER_STEP 0x7A 235 236 /* Extended Test Mode Register 3 (CNL and later) */ 237 #define ETR3_OFFSET 0x1048 238 #define ETR3_CF9GR BIT(20) 239 #define ETR3_CF9LOCK BIT(31) 240 241 /* Extended Test Mode Register LPM bits (TGL and later */ 242 #define ETR3_CLEAR_LPM_EVENTS BIT(28) 243 244 /* Alder Lake Power Management Controller register offsets */ 245 #define ADL_LPM_EN_OFFSET 0x179C 246 #define ADL_LPM_RESIDENCY_OFFSET 0x17A4 247 #define ADL_LPM_NUM_MODES 2 248 #define ADL_LPM_NUM_MAPS 14 249 250 /* Alder Lake Low Power Mode debug registers */ 251 #define ADL_LPM_STATUS_OFFSET 0x170C 252 #define ADL_LPM_PRI_OFFSET 0x17A0 253 #define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 254 #define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 255 256 /* Meteor Lake Power Management Controller register offsets */ 257 #define MTL_LPM_EN_OFFSET 0x1798 258 #define MTL_LPM_RESIDENCY_OFFSET 0x17A0 259 260 /* Meteor Lake Low Power Mode debug registers */ 261 #define MTL_LPM_PRI_OFFSET 0x179C 262 #define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8 263 #define MTL_LPM_STATUS_OFFSET 0x1700 264 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C 265 #define MTL_PMC_LTR_IOE_PMC 0x1C0C 266 #define MTL_PMC_LTR_ESE 0x1BAC 267 #define MTL_PMC_LTR_RESERVED 0x1BA4 268 #define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4 269 #define MTL_SOCM_NUM_IP_IGN_ALLOWED 25 270 #define MTL_SOC_PMC_MMIO_REG_LEN 0x2708 271 #define MTL_PMC_LTR_SPG 0x1B74 272 #define ARL_SOCS_PMC_LTR_RESERVED 0x1B88 273 #define ARL_SOCS_NUM_IP_IGN_ALLOWED 26 274 #define ARL_PMC_LTR_DMI3 0x1BE4 275 #define ARL_PCH_PMC_MMIO_REG_LEN 0x2720 276 277 /* Meteor Lake PGD PFET Enable Ack Status */ 278 #define MTL_SOCM_PPFEAR_NUM_ENTRIES 8 279 #define MTL_IOE_PPFEAR_NUM_ENTRIES 10 280 #define ARL_SOCS_PPFEAR_NUM_ENTRIES 9 281 282 /* Die C6 from PUNIT telemetry */ 283 #define MTL_PMT_DMU_DIE_C6_OFFSET 15 284 #define MTL_PMT_DMU_GUID 0x1A067102 285 #define ARL_PMT_DMU_GUID 0x1A06A000 286 287 #define LNL_PMC_MMIO_REG_LEN 0x2708 288 #define LNL_PMC_LTR_OSSE 0x1B88 289 #define LNL_NUM_IP_IGN_ALLOWED 27 290 #define LNL_PPFEAR_NUM_ENTRIES 12 291 #define LNL_S0IX_BLOCKER_OFFSET 0x2004 292 293 /* Panther Lake Power Management Controller register offsets */ 294 #define PTL_LPM_NUM_MAPS 14 295 #define PTL_PMC_LTR_SATA2 0x1B90 296 #define PTL_PMC_LTR_PMC 0x1BA8 297 #define PTL_PMC_LTR_CUR_ASLT 0x1C28 298 #define PTL_PMC_LTR_CUR_PLT 0x1C2C 299 #define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8 300 301 /* SSRAM PMC Device ID */ 302 /* LNL */ 303 #define PMC_DEVID_LNL_SOCM 0xa87f 304 305 /* PTL */ 306 #define PMC_DEVID_PTL_PCDH 0xe37f 307 #define PMC_DEVID_PTL_PCDP 0xe47f 308 309 /* ARL */ 310 #define PMC_DEVID_ARL_SOCM 0x777f 311 #define PMC_DEVID_ARL_SOCS 0xae7f 312 #define PMC_DEVID_ARL_IOEP 0x7ecf 313 #define PMC_DEVID_ARL_PCHS 0x7f27 314 315 /* MTL */ 316 #define PMC_DEVID_MTL_SOCM 0x7e7f 317 #define PMC_DEVID_MTL_IOEP 0x7ecf 318 #define PMC_DEVID_MTL_IOEM 0x7ebf 319 320 extern const char *pmc_lpm_modes[]; 321 322 struct pmc_bit_map { 323 const char *name; 324 u32 bit_mask; 325 u8 blk; 326 }; 327 328 /** 329 * struct pmc_reg_map - Structure used to define parameter unique to a 330 PCH family 331 * @pfear_sts: Maps name of IP block to PPFEAR* bit 332 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit 333 * @pll_sts: Maps name of PLL to corresponding bit status 334 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info 335 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets 336 * @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter 337 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency 338 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit 339 * @regmap_length: Length of memory to map from PWRMBASE address to access 340 * @ppfear0_offset: PWRMBASE offset to read PPFEAR* 341 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from 342 * PPFEAR 343 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register 344 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE 345 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* 346 * @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter 347 * 348 * Each PCH has unique set of register offsets and bit indexes. This structure 349 * captures them to have a common implementation. 350 */ 351 struct pmc_reg_map { 352 const struct pmc_bit_map **pfear_sts; 353 const struct pmc_bit_map *mphy_sts; 354 const struct pmc_bit_map *pll_sts; 355 const struct pmc_bit_map **slps0_dbg_maps; 356 const struct pmc_bit_map *ltr_show_sts; 357 const struct pmc_bit_map *msr_sts; 358 const struct pmc_bit_map **lpm_sts; 359 const struct pmc_bit_map **s0ix_blocker_maps; 360 const u32 slp_s0_offset; 361 const int slp_s0_res_counter_step; 362 const u32 ltr_ignore_offset; 363 const int regmap_length; 364 const u32 ppfear0_offset; 365 const int ppfear_buckets; 366 const u32 pm_cfg_offset; 367 const int pm_read_disable_bit; 368 const u32 slps0_dbg_offset; 369 const u32 ltr_ignore_max; 370 const u32 pm_vric1_offset; 371 const u32 s0ix_blocker_offset; 372 /* Low Power Mode registers */ 373 const int lpm_num_maps; 374 const int lpm_num_modes; 375 const int lpm_res_counter_step_x2; 376 const u32 lpm_sts_latch_en_offset; 377 const u32 lpm_en_offset; 378 const u32 lpm_priority_offset; 379 const u32 lpm_residency_offset; 380 const u32 lpm_status_offset; 381 const u32 lpm_live_status_offset; 382 const u32 etr3_offset; 383 const u8 *lpm_reg_index; 384 const u32 pson_residency_offset; 385 const u32 pson_residency_counter_step; 386 }; 387 388 /** 389 * struct pmc_info - Structure to keep pmc info 390 * @devid: device id of the pmc device 391 * @map: pointer to a pmc_reg_map struct that contains platform 392 * specific attributes 393 */ 394 struct pmc_info { 395 u32 guid; 396 u16 devid; 397 const struct pmc_reg_map *map; 398 }; 399 400 /** 401 * struct pmc - pmc private info structure 402 * @base_addr: contains pmc base address 403 * @regbase: pointer to io-remapped memory location 404 * @map: pointer to pmc_reg_map struct that contains platform 405 * specific attributes 406 * @lpm_req_regs: List of substate requirements 407 * @ltr_ign: Holds LTR ignore data while suspended 408 * 409 * pmc contains info about one power management controller device. 410 */ 411 struct pmc { 412 u64 base_addr; 413 void __iomem *regbase; 414 const struct pmc_reg_map *map; 415 u32 *lpm_req_regs; 416 u32 ltr_ign; 417 }; 418 419 /** 420 * struct pmc_dev - pmc device structure 421 * @devs: pointer to an array of pmc pointers 422 * @pdev: pointer to platform_device struct 423 * @crystal_freq: crystal frequency from cpuid 424 * @dbgfs_dir: path to debugfs interface 425 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers 426 * used to read MPHY PG and PLL status are available 427 * @mutex_lock: mutex to complete one transcation 428 * @pkgc_res_cnt: Array of PKGC residency counters 429 * @num_of_pkgc: Number of PKGC 430 * @s0ix_counter: S0ix residency (step adjusted) 431 * @num_lpm_modes: Count of enabled modes 432 * @lpm_en_modes: Array of enabled modes from lowest to highest priority 433 * @suspend: Function to perform platform specific suspend 434 * @resume: Function to perform platform specific resume 435 * 436 * pmc_dev contains info about power management controller device. 437 */ 438 struct pmc_dev { 439 struct pmc *pmcs[MAX_NUM_PMC]; 440 struct dentry *dbgfs_dir; 441 struct platform_device *pdev; 442 unsigned int crystal_freq; 443 int pmc_xram_read_bit; 444 struct mutex lock; /* generic mutex lock for PMC Core */ 445 446 u64 s0ix_counter; 447 int num_lpm_modes; 448 int lpm_en_modes[LPM_MAX_NUM_MODES]; 449 void (*suspend)(struct pmc_dev *pmcdev); 450 int (*resume)(struct pmc_dev *pmcdev); 451 452 u64 *pkgc_res_cnt; 453 u8 num_of_pkgc; 454 455 bool has_die_c6; 456 u32 die_c6_offset; 457 struct telem_endpoint *punit_ep; 458 struct pmc_info *regmap_list; 459 }; 460 461 enum pmc_index { 462 PMC_IDX_MAIN, 463 PMC_IDX_IOE, 464 PMC_IDX_PCH, 465 PMC_IDX_MAX 466 }; 467 468 /** 469 * struct pmc_dev_info - Structure to keep PMC device info 470 * @pci_func: Function number of the primary PMC 471 * @dmu_guid: Die Management Unit GUID 472 * @regmap_list: Pointer to a list of pmc_info structure that could be 473 * available for the platform. When set, this field implies 474 * SSRAM support. 475 * @map: Pointer to a pmc_reg_map struct that contains platform 476 * specific attributes of the primary PMC 477 * @suspend: Function to perform platform specific suspend 478 * @resume: Function to perform platform specific resume 479 * @init: Function to perform platform specific init action 480 */ 481 struct pmc_dev_info { 482 u8 pci_func; 483 u32 dmu_guid; 484 struct pmc_info *regmap_list; 485 const struct pmc_reg_map *map; 486 void (*suspend)(struct pmc_dev *pmcdev); 487 int (*resume)(struct pmc_dev *pmcdev); 488 int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info); 489 }; 490 491 extern const struct pmc_bit_map msr_map[]; 492 extern const struct pmc_bit_map cnp_pfear_map[]; 493 extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; 494 extern const struct pmc_bit_map cnp_ltr_show_map[]; 495 extern const struct pmc_reg_map cnp_reg_map; 496 extern const struct pmc_bit_map tgl_signal_status_map[]; 497 extern const struct pmc_reg_map adl_reg_map; 498 extern const struct pmc_bit_map mtl_socm_pfear_map[]; 499 extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; 500 extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; 501 extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; 502 extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; 503 extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; 504 extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; 505 extern const struct pmc_bit_map mtl_socm_signal_status_map[]; 506 extern const struct pmc_reg_map mtl_socm_reg_map; 507 extern const struct pmc_reg_map mtl_ioep_reg_map; 508 509 void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); 510 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore); 511 512 int pmc_core_resume_common(struct pmc_dev *pmcdev); 513 int get_primary_reg_base(struct pmc *pmc); 514 void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); 515 void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid); 516 void pmc_core_set_device_d3(unsigned int device); 517 518 int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info); 519 520 extern struct pmc_dev_info spt_pmc_dev; 521 extern struct pmc_dev_info cnp_pmc_dev; 522 extern struct pmc_dev_info icl_pmc_dev; 523 extern struct pmc_dev_info tgl_l_pmc_dev; 524 extern struct pmc_dev_info tgl_pmc_dev; 525 extern struct pmc_dev_info adl_pmc_dev; 526 extern struct pmc_dev_info mtl_pmc_dev; 527 extern struct pmc_dev_info arl_pmc_dev; 528 extern struct pmc_dev_info arl_h_pmc_dev; 529 extern struct pmc_dev_info lnl_pmc_dev; 530 extern struct pmc_dev_info ptl_pmc_dev; 531 532 void cnl_suspend(struct pmc_dev *pmcdev); 533 int cnl_resume(struct pmc_dev *pmcdev); 534 535 #define pmc_for_each_mode(mode, pmcdev) \ 536 for (unsigned int __i = 0, __cond; \ 537 __cond = __i < (pmcdev)->num_lpm_modes, \ 538 __cond && ((mode) = (pmcdev)->lpm_en_modes[__i]), \ 539 __cond; \ 540 __i++) 541 542 #define DEFINE_PMC_CORE_ATTR_WRITE(__name) \ 543 static int __name ## _open(struct inode *inode, struct file *file) \ 544 { \ 545 return single_open(file, __name ## _show, inode->i_private); \ 546 } \ 547 \ 548 static const struct file_operations __name ## _fops = { \ 549 .owner = THIS_MODULE, \ 550 .open = __name ## _open, \ 551 .read = seq_read, \ 552 .write = __name ## _write, \ 553 .release = single_release, \ 554 } 555 556 #endif /* PMC_CORE_H */ 557