xref: /linux/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h (revision c2933b2befe25309f4c5cfbea0ca80909735fd76)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
6 
7 /* This header file defines the Admin Queue commands, error codes and
8  * descriptor format. It is shared between Firmware and Software.
9  */
10 
11 #define ICE_MAX_VSI			768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM	0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX	9728
14 
15 #define ICE_RXQ_CTX_SIZE_DWORDS		8
16 #define ICE_RXQ_CTX_SZ			(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
17 #define ICE_TXQ_CTX_SZ			22
18 
19 typedef struct __packed { u8 buf[ICE_RXQ_CTX_SZ]; } ice_rxq_ctx_buf_t;
20 typedef struct __packed { u8 buf[ICE_TXQ_CTX_SZ]; } ice_txq_ctx_buf_t;
21 
22 struct ice_aqc_generic {
23 	__le32 param0;
24 	__le32 param1;
25 	__le32 addr_high;
26 	__le32 addr_low;
27 };
28 
29 /* Get version (direct 0x0001) */
30 struct ice_aqc_get_ver {
31 	__le32 rom_ver;
32 	__le32 fw_build;
33 	u8 fw_branch;
34 	u8 fw_major;
35 	u8 fw_minor;
36 	u8 fw_patch;
37 	u8 api_branch;
38 	u8 api_major;
39 	u8 api_minor;
40 	u8 api_patch;
41 };
42 
43 /* Send driver version (indirect 0x0002) */
44 struct ice_aqc_driver_ver {
45 	u8 major_ver;
46 	u8 minor_ver;
47 	u8 build_ver;
48 	u8 subbuild_ver;
49 	u8 reserved[4];
50 	__le32 addr_high;
51 	__le32 addr_low;
52 };
53 
54 /* Queue Shutdown (direct 0x0003) */
55 struct ice_aqc_q_shutdown {
56 	u8 driver_unloading;
57 #define ICE_AQC_DRIVER_UNLOADING	BIT(0)
58 	u8 reserved[15];
59 };
60 
61 /* Request resource ownership (direct 0x0008)
62  * Release resource ownership (direct 0x0009)
63  */
64 struct ice_aqc_req_res {
65 	__le16 res_id;
66 #define ICE_AQC_RES_ID_NVM		1
67 #define ICE_AQC_RES_ID_SDP		2
68 #define ICE_AQC_RES_ID_CHNG_LOCK	3
69 #define ICE_AQC_RES_ID_GLBL_LOCK	4
70 	__le16 access_type;
71 #define ICE_AQC_RES_ACCESS_READ		1
72 #define ICE_AQC_RES_ACCESS_WRITE	2
73 
74 	/* Upon successful completion, FW writes this value and driver is
75 	 * expected to release resource before timeout. This value is provided
76 	 * in milliseconds.
77 	 */
78 	__le32 timeout;
79 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS	3000
80 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS	180000
81 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS	1000
82 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS	3000
83 	/* For SDP: pin ID of the SDP */
84 	__le32 res_number;
85 	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
86 	__le16 status;
87 #define ICE_AQ_RES_GLBL_SUCCESS		0
88 #define ICE_AQ_RES_GLBL_IN_PROG		1
89 #define ICE_AQ_RES_GLBL_DONE		2
90 	u8 reserved[2];
91 };
92 
93 /* Get function capabilities (indirect 0x000A)
94  * Get device capabilities (indirect 0x000B)
95  */
96 struct ice_aqc_list_caps {
97 	u8 cmd_flags;
98 	u8 pf_index;
99 	u8 reserved[2];
100 	__le32 count;
101 	__le32 addr_high;
102 	__le32 addr_low;
103 };
104 
105 /* Device/Function buffer entry, repeated per reported capability */
106 struct ice_aqc_list_caps_elem {
107 	__le16 cap;
108 #define ICE_AQC_CAPS_VALID_FUNCTIONS			0x0005
109 #define ICE_AQC_CAPS_SRIOV				0x0012
110 #define ICE_AQC_CAPS_VF					0x0013
111 #define ICE_AQC_CAPS_VSI				0x0017
112 #define ICE_AQC_CAPS_DCB				0x0018
113 #define ICE_AQC_CAPS_RSS				0x0040
114 #define ICE_AQC_CAPS_RXQS				0x0041
115 #define ICE_AQC_CAPS_TXQS				0x0042
116 #define ICE_AQC_CAPS_MSIX				0x0043
117 #define ICE_AQC_CAPS_FD					0x0045
118 #define ICE_AQC_CAPS_1588				0x0046
119 #define ICE_AQC_CAPS_MAX_MTU				0x0047
120 #define ICE_AQC_CAPS_NVM_VER				0x0048
121 #define ICE_AQC_CAPS_PENDING_NVM_VER			0x0049
122 #define ICE_AQC_CAPS_OROM_VER				0x004A
123 #define ICE_AQC_CAPS_PENDING_OROM_VER			0x004B
124 #define ICE_AQC_CAPS_NET_VER				0x004C
125 #define ICE_AQC_CAPS_PENDING_NET_VER			0x004D
126 #define ICE_AQC_CAPS_RDMA				0x0051
127 #define ICE_AQC_CAPS_SENSOR_READING			0x0067
128 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076
129 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077
130 #define ICE_AQC_CAPS_NVM_MGMT				0x0080
131 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE		0x0085
132 #define ICE_AQC_CAPS_NAC_TOPOLOGY			0x0087
133 #define ICE_AQC_CAPS_FW_LAG_SUPPORT			0x0092
134 #define ICE_AQC_BIT_ROCEV2_LAG				0x01
135 #define ICE_AQC_BIT_SRIOV_LAG				0x02
136 
137 	u8 major_ver;
138 	u8 minor_ver;
139 	/* Number of resources described by this capability */
140 	__le32 number;
141 	/* Only meaningful for some types of resources */
142 	__le32 logical_id;
143 	/* Only meaningful for some types of resources */
144 	__le32 phys_id;
145 	__le64 rsvd1;
146 	__le64 rsvd2;
147 };
148 
149 /* Manage MAC address, read command - indirect (0x0107)
150  * This struct is also used for the response
151  */
152 struct ice_aqc_manage_mac_read {
153 	__le16 flags; /* Zeroed by device driver */
154 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID		BIT(4)
155 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID		BIT(5)
156 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID		BIT(6)
157 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID		BIT(7)
158 #define ICE_AQC_MAN_MAC_READ_S			4
159 #define ICE_AQC_MAN_MAC_READ_M			(0xF << ICE_AQC_MAN_MAC_READ_S)
160 	u8 rsvd[2];
161 	u8 num_addr; /* Used in response */
162 	u8 rsvd1[3];
163 	__le32 addr_high;
164 	__le32 addr_low;
165 };
166 
167 /* Response buffer format for manage MAC read command */
168 struct ice_aqc_manage_mac_read_resp {
169 	u8 lport_num;
170 	u8 addr_type;
171 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN		0
172 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL		1
173 	u8 mac_addr[ETH_ALEN];
174 };
175 
176 /* Manage MAC address, write command - direct (0x0108) */
177 struct ice_aqc_manage_mac_write {
178 	u8 rsvd;
179 	u8 flags;
180 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN		BIT(0)
181 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP	BIT(1)
182 #define ICE_AQC_MAN_MAC_WR_S		6
183 #define ICE_AQC_MAN_MAC_WR_M		ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
184 #define ICE_AQC_MAN_MAC_UPDATE_LAA	0
185 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL	BIT(ICE_AQC_MAN_MAC_WR_S)
186 	/* byte stream in network order */
187 	u8 mac_addr[ETH_ALEN];
188 	__le32 addr_high;
189 	__le32 addr_low;
190 };
191 
192 /* Clear PXE Command and response (direct 0x0110) */
193 struct ice_aqc_clear_pxe {
194 	u8 rx_cnt;
195 #define ICE_AQC_CLEAR_PXE_RX_CNT		0x2
196 	u8 reserved[15];
197 };
198 
199 /* Get switch configuration (0x0200) */
200 struct ice_aqc_get_sw_cfg {
201 	/* Reserved for command and copy of request flags for response */
202 	__le16 flags;
203 	/* First desc in case of command and next_elem in case of response
204 	 * In case of response, if it is not zero, means all the configuration
205 	 * was not returned and new command shall be sent with this value in
206 	 * the 'first desc' field
207 	 */
208 	__le16 element;
209 	/* Reserved for command, only used for response */
210 	__le16 num_elems;
211 	__le16 rsvd;
212 	__le32 addr_high;
213 	__le32 addr_low;
214 };
215 
216 /* Each entry in the response buffer is of the following type: */
217 struct ice_aqc_get_sw_cfg_resp_elem {
218 	/* VSI/Port Number */
219 	__le16 vsi_port_num;
220 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S	0
221 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M	\
222 			(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
223 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S	14
224 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M	(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
225 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT	0
226 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT	1
227 #define ICE_AQC_GET_SW_CONF_RESP_VSI		2
228 
229 	/* SWID VSI/Port belongs to */
230 	__le16 swid;
231 
232 	/* Bit 14..0 : PF/VF number VSI belongs to
233 	 * Bit 15 : VF indication bit
234 	 */
235 	__le16 pf_vf_num;
236 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S	0
237 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M	\
238 				(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
239 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF		BIT(15)
240 };
241 
242 /* Loopback port parameter mode values. */
243 enum ice_local_fwd_mode {
244 	ICE_LOCAL_FWD_MODE_ENABLED = 0,
245 	ICE_LOCAL_FWD_MODE_DISABLED = 1,
246 	ICE_LOCAL_FWD_MODE_PRIORITIZED = 2,
247 };
248 
249 /* Set Port parameters, (direct, 0x0203) */
250 struct ice_aqc_set_port_params {
251 	__le16 cmd_flags;
252 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA	BIT(2)
253 	__le16 bad_frame_vsi;
254 	__le16 swid;
255 #define ICE_AQC_PORT_SWID_VALID			BIT(15)
256 #define ICE_AQC_PORT_SWID_M			0xFF
257 	u8 local_fwd_mode;
258 #define ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID BIT(2)
259 	u8 reserved[9];
260 };
261 
262 /* These resource type defines are used for all switch resource
263  * commands where a resource type is required, such as:
264  * Get Resource Allocation command (indirect 0x0204)
265  * Allocate Resources command (indirect 0x0208)
266  * Free Resources command (indirect 0x0209)
267  * Get Allocated Resource Descriptors Command (indirect 0x020A)
268  * Share Resource command (indirect 0x020B)
269  */
270 #define ICE_AQC_RES_TYPE_VSI_LIST_REP			0x03
271 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE			0x04
272 #define ICE_AQC_RES_TYPE_RECIPE				0x05
273 #define ICE_AQC_RES_TYPE_SWID				0x07
274 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK		0x21
275 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES	0x22
276 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES		0x23
277 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID		0x58
278 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM		0x59
279 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID		0x60
280 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM		0x61
281 
282 #define ICE_AQC_RES_TYPE_FLAG_SHARED			BIT(7)
283 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM		BIT(12)
284 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX		BIT(13)
285 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED		BIT(14)
286 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL		BIT(15)
287 
288 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED			0x00
289 
290 #define ICE_AQC_RES_TYPE_S	0
291 #define ICE_AQC_RES_TYPE_M	(0x07F << ICE_AQC_RES_TYPE_S)
292 
293 /* Allocate Resources command (indirect 0x0208)
294  * Free Resources command (indirect 0x0209)
295  * Share Resource command (indirect 0x020B)
296  */
297 struct ice_aqc_alloc_free_res_cmd {
298 	__le16 num_entries; /* Number of Resource entries */
299 	u8 reserved[6];
300 	__le32 addr_high;
301 	__le32 addr_low;
302 };
303 
304 /* Resource descriptor */
305 struct ice_aqc_res_elem {
306 	union {
307 		__le16 sw_resp;
308 		__le16 flu_resp;
309 	} e;
310 };
311 
312 /* Buffer for Allocate/Free Resources commands */
313 struct ice_aqc_alloc_free_res_elem {
314 	__le16 res_type; /* Types defined above cmd 0x0204 */
315 #define ICE_AQC_RES_TYPE_SHARED_S	7
316 #define ICE_AQC_RES_TYPE_SHARED_M	(0x1 << ICE_AQC_RES_TYPE_SHARED_S)
317 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S	8
318 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M	\
319 				(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
320 	__le16 num_elems;
321 	struct ice_aqc_res_elem elem[];
322 };
323 
324 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
325 struct ice_aqc_set_vlan_mode {
326 	u8 reserved;
327 	u8 l2tag_prio_tagging;
328 #define ICE_AQ_VLAN_PRIO_TAG_S			0
329 #define ICE_AQ_VLAN_PRIO_TAG_M			(0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
330 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED	0x0
331 #define ICE_AQ_VLAN_PRIO_TAG_STAG		0x1
332 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG		0x2
333 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN		0x3
334 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG		0x4
335 #define ICE_AQ_VLAN_PRIO_TAG_MAX		0x4
336 #define ICE_AQ_VLAN_PRIO_TAG_ERROR		0x7
337 	u8 l2tag_reserved[64];
338 	u8 rdma_packet;
339 #define ICE_AQ_VLAN_RDMA_TAG_S			0
340 #define ICE_AQ_VLAN_RDMA_TAG_M			(0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
341 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING	0x10
342 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING	0x1A
343 	u8 rdma_reserved[2];
344 	u8 mng_vlan_prot_id;
345 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER	0x10
346 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER	0x11
347 	u8 prot_id_reserved[30];
348 };
349 
350 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
351 struct ice_aqc_get_vlan_mode {
352 	u8 vlan_mode;
353 #define ICE_AQ_VLAN_MODE_DVM_ENA	BIT(0)
354 	u8 l2tag_prio_tagging;
355 	u8 reserved[98];
356 };
357 
358 /* Add VSI (indirect 0x0210)
359  * Update VSI (indirect 0x0211)
360  * Get VSI (indirect 0x0212)
361  * Free VSI (indirect 0x0213)
362  */
363 struct ice_aqc_add_get_update_free_vsi {
364 	__le16 vsi_num;
365 #define ICE_AQ_VSI_NUM_S	0
366 #define ICE_AQ_VSI_NUM_M	(0x03FF << ICE_AQ_VSI_NUM_S)
367 #define ICE_AQ_VSI_IS_VALID	BIT(15)
368 	__le16 cmd_flags;
369 #define ICE_AQ_VSI_KEEP_ALLOC	0x1
370 	u8 vf_id;
371 	u8 reserved;
372 	__le16 vsi_flags;
373 #define ICE_AQ_VSI_TYPE_S	0
374 #define ICE_AQ_VSI_TYPE_M	(0x3 << ICE_AQ_VSI_TYPE_S)
375 #define ICE_AQ_VSI_TYPE_VF	0x0
376 #define ICE_AQ_VSI_TYPE_VMDQ2	0x1
377 #define ICE_AQ_VSI_TYPE_PF	0x2
378 #define ICE_AQ_VSI_TYPE_EMP_MNG	0x3
379 	__le32 addr_high;
380 	__le32 addr_low;
381 };
382 
383 /* Response descriptor for:
384  * Add VSI (indirect 0x0210)
385  * Update VSI (indirect 0x0211)
386  * Free VSI (indirect 0x0213)
387  */
388 struct ice_aqc_add_update_free_vsi_resp {
389 	__le16 vsi_num;
390 	__le16 ext_status;
391 	__le16 vsi_used;
392 	__le16 vsi_free;
393 	__le32 addr_high;
394 	__le32 addr_low;
395 };
396 
397 struct ice_aqc_vsi_props {
398 	__le16 valid_sections;
399 #define ICE_AQ_VSI_PROP_SW_VALID		BIT(0)
400 #define ICE_AQ_VSI_PROP_SECURITY_VALID		BIT(1)
401 #define ICE_AQ_VSI_PROP_VLAN_VALID		BIT(2)
402 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID		BIT(3)
403 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID	BIT(4)
404 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID		BIT(5)
405 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID		BIT(6)
406 #define ICE_AQ_VSI_PROP_Q_OPT_VALID		BIT(7)
407 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID		BIT(8)
408 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID		BIT(11)
409 #define ICE_AQ_VSI_PROP_PASID_VALID		BIT(12)
410 	/* switch section */
411 	u8 sw_id;
412 	u8 sw_flags;
413 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB		BIT(5)
414 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB		BIT(6)
415 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)
416 	u8 sw_flags2;
417 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0
418 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
419 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)
420 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)
421 	u8 veb_stat_id;
422 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0
423 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M		(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
424 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID		BIT(5)
425 	/* security section */
426 	u8 sec_flags;
427 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	BIT(0)
428 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF	BIT(2)
429 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S		4
430 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M		(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
431 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)
432 	u8 sec_reserved;
433 	/* VLAN section */
434 	__le16 port_based_inner_vlan; /* VLANS include priority bits */
435 	u8 inner_vlan_reserved[2];
436 	u8 inner_vlan_flags;
437 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S		0
438 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
439 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1
440 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED	0x2
441 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL	0x3
442 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID	BIT(2)
443 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S		3
444 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
445 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH	0x0U
446 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP	0x1U
447 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR		0x2U
448 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING	0x3U
449 	u8 inner_vlan_reserved2[3];
450 	/* ingress egress up sections */
451 	__le32 ingress_table; /* bitmap, 3 bits per up */
452 #define ICE_AQ_VSI_UP_TABLE_UP0_S		0
453 #define ICE_AQ_VSI_UP_TABLE_UP0_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
454 #define ICE_AQ_VSI_UP_TABLE_UP1_S		3
455 #define ICE_AQ_VSI_UP_TABLE_UP1_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
456 #define ICE_AQ_VSI_UP_TABLE_UP2_S		6
457 #define ICE_AQ_VSI_UP_TABLE_UP2_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
458 #define ICE_AQ_VSI_UP_TABLE_UP3_S		9
459 #define ICE_AQ_VSI_UP_TABLE_UP3_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
460 #define ICE_AQ_VSI_UP_TABLE_UP4_S		12
461 #define ICE_AQ_VSI_UP_TABLE_UP4_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
462 #define ICE_AQ_VSI_UP_TABLE_UP5_S		15
463 #define ICE_AQ_VSI_UP_TABLE_UP5_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
464 #define ICE_AQ_VSI_UP_TABLE_UP6_S		18
465 #define ICE_AQ_VSI_UP_TABLE_UP6_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
466 #define ICE_AQ_VSI_UP_TABLE_UP7_S		21
467 #define ICE_AQ_VSI_UP_TABLE_UP7_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
468 	__le32 egress_table;   /* same defines as for ingress table */
469 	/* outer tags section */
470 	__le16 port_based_outer_vlan;
471 	u8 outer_vlan_flags;
472 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S		0
473 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
474 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH	0x0
475 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP	0x1
476 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW	0x2
477 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING	0x3
478 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S		2
479 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M		(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
480 #define ICE_AQ_VSI_OUTER_TAG_NONE		0x0
481 #define ICE_AQ_VSI_OUTER_TAG_STAG		0x1
482 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100		0x2
483 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100		0x3
484 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT		BIT(4)
485 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S			5
486 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M			(0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
487 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1
488 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED	0x2
489 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL		0x3
490 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC		BIT(7)
491 	u8 outer_vlan_reserved;
492 	/* queue mapping section */
493 	__le16 mapping_flags;
494 #define ICE_AQ_VSI_Q_MAP_CONTIG			0x0
495 #define ICE_AQ_VSI_Q_MAP_NONCONTIG		BIT(0)
496 	__le16 q_mapping[16];
497 #define ICE_AQ_VSI_Q_S				0
498 #define ICE_AQ_VSI_Q_M				(0x7FF << ICE_AQ_VSI_Q_S)
499 	__le16 tc_mapping[8];
500 #define ICE_AQ_VSI_TC_Q_OFFSET_S		0
501 #define ICE_AQ_VSI_TC_Q_OFFSET_M		(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
502 #define ICE_AQ_VSI_TC_Q_NUM_S			11
503 #define ICE_AQ_VSI_TC_Q_NUM_M			(0xF << ICE_AQ_VSI_TC_Q_NUM_S)
504 	/* queueing option section */
505 	u8 q_opt_rss;
506 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S		0
507 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M		(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
508 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI		0x0
509 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF		0x2
510 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL		0x3
511 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S		2
512 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M		(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
513 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S		6
514 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M		GENMASK(7, 6)
515 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ		0x0U
516 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ	0x1U
517 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR		0x2U
518 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH		0x3U
519 	u8 q_opt_tc;
520 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S		0
521 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M		(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
522 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR		BIT(7)
523 	u8 q_opt_flags;
524 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN		BIT(0)
525 	u8 q_opt_reserved[3];
526 	/* outer up section */
527 	__le32 outer_up_table; /* same structure and defines as ingress tbl */
528 	/* section 10 */
529 	__le16 sect_10_reserved;
530 	/* flow director section */
531 	__le16 fd_options;
532 #define ICE_AQ_VSI_FD_ENABLE			BIT(0)
533 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE		BIT(1)
534 #define ICE_AQ_VSI_FD_PROG_ENABLE		BIT(3)
535 	__le16 max_fd_fltr_dedicated;
536 	__le16 max_fd_fltr_shared;
537 	__le16 fd_def_q;
538 #define ICE_AQ_VSI_FD_DEF_Q_S			0
539 #define ICE_AQ_VSI_FD_DEF_Q_M			(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
540 #define ICE_AQ_VSI_FD_DEF_GRP_S			12
541 #define ICE_AQ_VSI_FD_DEF_GRP_M			(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
542 	__le16 fd_report_opt;
543 #define ICE_AQ_VSI_FD_REPORT_Q_S		0
544 #define ICE_AQ_VSI_FD_REPORT_Q_M		(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
545 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S		12
546 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M		(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
547 #define ICE_AQ_VSI_FD_DEF_DROP			BIT(15)
548 	/* PASID section */
549 	__le32 pasid_id;
550 #define ICE_AQ_VSI_PASID_ID_S			0
551 #define ICE_AQ_VSI_PASID_ID_M			(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
552 #define ICE_AQ_VSI_PASID_ID_VALID		BIT(31)
553 	u8 reserved[24];
554 };
555 
556 #define ICE_MAX_NUM_RECIPES 64
557 
558 /* Add/Get Recipe (indirect 0x0290/0x0292) */
559 struct ice_aqc_add_get_recipe {
560 	__le16 num_sub_recipes;	/* Input in Add cmd, Output in Get cmd */
561 	__le16 return_index;	/* Input, used for Get cmd only */
562 	u8 reserved[4];
563 	__le32 addr_high;
564 	__le32 addr_low;
565 };
566 
567 struct ice_aqc_recipe_content {
568 	u8 rid;
569 #define ICE_AQ_RECIPE_ID_S		0
570 #define ICE_AQ_RECIPE_ID_M		(0x3F << ICE_AQ_RECIPE_ID_S)
571 #define ICE_AQ_RECIPE_ID_IS_ROOT	BIT(7)
572 #define ICE_AQ_SW_ID_LKUP_IDX		0
573 	u8 lkup_indx[5];
574 #define ICE_AQ_RECIPE_LKUP_DATA_S	0
575 #define ICE_AQ_RECIPE_LKUP_DATA_M	(0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
576 #define ICE_AQ_RECIPE_LKUP_IGNORE	BIT(7)
577 #define ICE_AQ_SW_ID_LKUP_MASK		0x00FF
578 	__le16 mask[5];
579 	u8 result_indx;
580 #define ICE_AQ_RECIPE_RESULT_DATA_S	0
581 #define ICE_AQ_RECIPE_RESULT_DATA_M	(0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
582 #define ICE_AQ_RECIPE_RESULT_EN		BIT(7)
583 	u8 rsvd0[3];
584 	u8 act_ctrl_join_priority;
585 	u8 act_ctrl_fwd_priority;
586 #define ICE_AQ_RECIPE_FWD_PRIORITY_S	0
587 #define ICE_AQ_RECIPE_FWD_PRIORITY_M	(0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
588 	u8 act_ctrl;
589 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2	BIT(0)
590 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2	BIT(1)
591 #define ICE_AQ_RECIPE_ACT_INV_ACT	BIT(2)
592 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S	4
593 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M	(0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
594 	u8 rsvd1;
595 	__le32 dflt_act;
596 #define ICE_AQ_RECIPE_DFLT_ACT_S	0
597 #define ICE_AQ_RECIPE_DFLT_ACT_M	(0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
598 #define ICE_AQ_RECIPE_DFLT_ACT_VALID	BIT(31)
599 };
600 
601 struct ice_aqc_recipe_data_elem {
602 	u8 recipe_indx;
603 	u8 resp_bits;
604 #define ICE_AQ_RECIPE_WAS_UPDATED	BIT(0)
605 	u8 rsvd0[2];
606 	u8 recipe_bitmap[8];
607 	u8 rsvd1[4];
608 	struct ice_aqc_recipe_content content;
609 	u8 rsvd2[20];
610 };
611 
612 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
613 struct ice_aqc_recipe_to_profile {
614 	__le16 profile_id;
615 	u8 rsvd[6];
616 	__le64 recipe_assoc;
617 };
618 static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16);
619 
620 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
621  */
622 struct ice_aqc_sw_rules {
623 	/* ops: add switch rules, referring the number of rules.
624 	 * ops: update switch rules, referring the number of filters
625 	 * ops: remove switch rules, referring the entry index.
626 	 * ops: get switch rules, referring to the number of filters.
627 	 */
628 	__le16 num_rules_fltr_entry_index;
629 	u8 reserved[6];
630 	__le32 addr_high;
631 	__le32 addr_low;
632 };
633 
634 /* Add switch rule response:
635  * Content of return buffer is same as the input buffer. The status field and
636  * LUT index are updated as part of the response
637  */
638 struct ice_aqc_sw_rules_elem_hdr {
639 	__le16 type; /* Switch rule type, one of T_... */
640 #define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
641 #define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
642 #define ICE_AQC_SW_RULES_T_LG_ACT		0x2
643 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
644 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
645 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
646 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
647 	__le16 status;
648 } __packed __aligned(sizeof(__le16));
649 
650 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
651  * This structures describes the lookup rules and associated actions. "index"
652  * is returned as part of a response to a successful Add command, and can be
653  * used to identify the rule for Update/Get/Remove commands.
654  */
655 struct ice_sw_rule_lkup_rx_tx {
656 	struct ice_aqc_sw_rules_elem_hdr hdr;
657 
658 	__le16 recipe_id;
659 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD		10
660 	/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
661 	__le16 src;
662 	__le32 act;
663 
664 	/* Bit 0:1 - Action type */
665 #define ICE_SINGLE_ACT_TYPE_S	0x00
666 #define ICE_SINGLE_ACT_TYPE_M	(0x3 << ICE_SINGLE_ACT_TYPE_S)
667 
668 	/* Bit 2 - Loop back enable
669 	 * Bit 3 - LAN enable
670 	 */
671 #define ICE_SINGLE_ACT_LB_ENABLE	BIT(2)
672 #define ICE_SINGLE_ACT_LAN_ENABLE	BIT(3)
673 
674 	/* Action type = 0 - Forward to VSI or VSI list */
675 #define ICE_SINGLE_ACT_VSI_FORWARDING	0x0
676 
677 #define ICE_SINGLE_ACT_VSI_ID_S		4
678 #define ICE_SINGLE_ACT_VSI_ID_M		(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
679 #define ICE_SINGLE_ACT_VSI_LIST_ID_S	4
680 #define ICE_SINGLE_ACT_VSI_LIST_ID_M	(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
681 	/* This bit needs to be set if action is forward to VSI list */
682 #define ICE_SINGLE_ACT_VSI_LIST		BIT(14)
683 #define ICE_SINGLE_ACT_VALID_BIT	BIT(17)
684 #define ICE_SINGLE_ACT_DROP		BIT(18)
685 
686 	/* Action type = 1 - Forward to Queue of Queue group */
687 #define ICE_SINGLE_ACT_TO_Q		0x1
688 #define ICE_SINGLE_ACT_Q_INDEX_S	4
689 #define ICE_SINGLE_ACT_Q_INDEX_M	(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
690 #define ICE_SINGLE_ACT_Q_REGION_S	15
691 #define ICE_SINGLE_ACT_Q_REGION_M	(0x7 << ICE_SINGLE_ACT_Q_REGION_S)
692 #define ICE_SINGLE_ACT_Q_PRIORITY	BIT(18)
693 
694 	/* Action type = 2 - Prune */
695 #define ICE_SINGLE_ACT_PRUNE		0x2
696 #define ICE_SINGLE_ACT_EGRESS		BIT(15)
697 #define ICE_SINGLE_ACT_INGRESS		BIT(16)
698 #define ICE_SINGLE_ACT_PRUNET		BIT(17)
699 	/* Bit 18 should be set to 0 for this action */
700 
701 	/* Action type = 2 - Pointer */
702 #define ICE_SINGLE_ACT_PTR		0x2
703 #define ICE_SINGLE_ACT_PTR_VAL_S	4
704 #define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
705 	/* Bit 18 should be set to 1 */
706 #define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
707 
708 	/* Action type = 3 - Other actions. Last two bits
709 	 * are other action identifier
710 	 */
711 #define ICE_SINGLE_ACT_OTHER_ACTS		0x3
712 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S	17
713 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M	\
714 				(0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
715 
716 	/* Bit 17:18 - Defines other actions */
717 	/* Other action = 0 - Mirror VSI */
718 #define ICE_SINGLE_OTHER_ACT_MIRROR		0
719 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S	4
720 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M	\
721 				(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
722 
723 	/* Other action = 3 - Set Stat count */
724 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT		3
725 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S	4
726 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M	\
727 				(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
728 
729 	__le16 index; /* The index of the rule in the lookup table */
730 	/* Length and values of the header to be matched per recipe or
731 	 * lookup-type
732 	 */
733 	__le16 hdr_len;
734 	u8 hdr_data[];
735 } __packed __aligned(sizeof(__le16));
736 
737 /* Add/Update/Remove large action command/response entry
738  * "index" is returned as part of a response to a successful Add command, and
739  * can be used to identify the action for Update/Get/Remove commands.
740  */
741 struct ice_sw_rule_lg_act {
742 	struct ice_aqc_sw_rules_elem_hdr hdr;
743 
744 	__le16 index; /* Index in large action table */
745 	__le16 size;
746 	/* Max number of large actions */
747 #define ICE_MAX_LG_ACT	4
748 	/* Bit 0:1 - Action type */
749 #define ICE_LG_ACT_TYPE_S	0
750 #define ICE_LG_ACT_TYPE_M	(0x7 << ICE_LG_ACT_TYPE_S)
751 
752 	/* Action type = 0 - Forward to VSI or VSI list */
753 #define ICE_LG_ACT_VSI_FORWARDING	0
754 #define ICE_LG_ACT_VSI_ID_S		3
755 #define ICE_LG_ACT_VSI_ID_M		(0x3FF << ICE_LG_ACT_VSI_ID_S)
756 #define ICE_LG_ACT_VSI_LIST_ID_S	3
757 #define ICE_LG_ACT_VSI_LIST_ID_M	(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
758 	/* This bit needs to be set if action is forward to VSI list */
759 #define ICE_LG_ACT_VSI_LIST		BIT(13)
760 
761 #define ICE_LG_ACT_VALID_BIT		BIT(16)
762 
763 	/* Action type = 1 - Forward to Queue of Queue group */
764 #define ICE_LG_ACT_TO_Q			0x1
765 #define ICE_LG_ACT_Q_INDEX_S		3
766 #define ICE_LG_ACT_Q_INDEX_M		(0x7FF << ICE_LG_ACT_Q_INDEX_S)
767 #define ICE_LG_ACT_Q_REGION_S		14
768 #define ICE_LG_ACT_Q_REGION_M		(0x7 << ICE_LG_ACT_Q_REGION_S)
769 #define ICE_LG_ACT_Q_PRIORITY_SET	BIT(17)
770 
771 	/* Action type = 2 - Prune */
772 #define ICE_LG_ACT_PRUNE		0x2
773 #define ICE_LG_ACT_EGRESS		BIT(14)
774 #define ICE_LG_ACT_INGRESS		BIT(15)
775 #define ICE_LG_ACT_PRUNET		BIT(16)
776 
777 	/* Action type = 3 - Mirror VSI */
778 #define ICE_LG_OTHER_ACT_MIRROR		0x3
779 #define ICE_LG_ACT_MIRROR_VSI_ID_S	3
780 #define ICE_LG_ACT_MIRROR_VSI_ID_M	(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
781 
782 	/* Action type = 5 - Generic Value */
783 #define ICE_LG_ACT_GENERIC		0x5
784 #define ICE_LG_ACT_GENERIC_VALUE_S	3
785 #define ICE_LG_ACT_GENERIC_VALUE_M	(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
786 #define ICE_LG_ACT_GENERIC_OFFSET_S	19
787 #define ICE_LG_ACT_GENERIC_OFFSET_M	(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
788 #define ICE_LG_ACT_GENERIC_PRIORITY_S	22
789 #define ICE_LG_ACT_GENERIC_PRIORITY_M	(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
790 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX	7
791 
792 	/* Action = 7 - Set Stat count */
793 #define ICE_LG_ACT_STAT_COUNT		0x7
794 #define ICE_LG_ACT_STAT_COUNT_S		3
795 #define ICE_LG_ACT_STAT_COUNT_M		(0x7F << ICE_LG_ACT_STAT_COUNT_S)
796 	__le32 act[]; /* array of size for actions */
797 } __packed __aligned(sizeof(__le16));
798 
799 /* Add/Update/Remove VSI list command/response entry
800  * "index" is returned as part of a response to a successful Add command, and
801  * can be used to identify the VSI list for Update/Get/Remove commands.
802  */
803 struct ice_sw_rule_vsi_list {
804 	struct ice_aqc_sw_rules_elem_hdr hdr;
805 
806 	__le16 index; /* Index of VSI/Prune list */
807 	__le16 number_vsi;
808 	__le16 vsi[]; /* Array of number_vsi VSI numbers */
809 } __packed __aligned(sizeof(__le16));
810 
811 /* Query PFC Mode (direct 0x0302)
812  * Set PFC Mode (direct 0x0303)
813  */
814 struct ice_aqc_set_query_pfc_mode {
815 	u8	pfc_mode;
816 /* For Query Command response, reserved in all other cases */
817 #define ICE_AQC_PFC_VLAN_BASED_PFC	1
818 #define ICE_AQC_PFC_DSCP_BASED_PFC	2
819 	u8	rsvd[15];
820 };
821 /* Get Default Topology (indirect 0x0400) */
822 struct ice_aqc_get_topo {
823 	u8 port_num;
824 	u8 num_branches;
825 	__le16 reserved1;
826 	__le32 reserved2;
827 	__le32 addr_high;
828 	__le32 addr_low;
829 };
830 
831 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */
832 struct ice_aqc_get_set_tx_topo {
833 	u8 set_flags;
834 #define ICE_AQC_TX_TOPO_FLAGS_CORRER		BIT(0)
835 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM		BIT(1)
836 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW		BIT(4)
837 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED		BIT(5)
838 
839 	u8 get_flags;
840 #define ICE_AQC_TX_TOPO_GET_RAM		2
841 
842 	__le16 reserved1;
843 	__le32 reserved2;
844 	__le32 addr_high;
845 	__le32 addr_low;
846 };
847 
848 /* Update TSE (indirect 0x0403)
849  * Get TSE (indirect 0x0404)
850  * Add TSE (indirect 0x0401)
851  * Delete TSE (indirect 0x040F)
852  * Move TSE (indirect 0x0408)
853  * Suspend Nodes (indirect 0x0409)
854  * Resume Nodes (indirect 0x040A)
855  */
856 struct ice_aqc_sched_elem_cmd {
857 	__le16 num_elem_req;	/* Used by commands */
858 	__le16 num_elem_resp;	/* Used by responses */
859 	__le32 reserved;
860 	__le32 addr_high;
861 	__le32 addr_low;
862 };
863 
864 struct ice_aqc_txsched_move_grp_info_hdr {
865 	__le32 src_parent_teid;
866 	__le32 dest_parent_teid;
867 	__le16 num_elems;
868 	u8 mode;
869 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF		0x0
870 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN		0x1
871 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN		0x2
872 	u8 reserved;
873 };
874 
875 struct ice_aqc_move_elem {
876 	struct ice_aqc_txsched_move_grp_info_hdr hdr;
877 	__le32 teid[];
878 };
879 
880 struct ice_aqc_elem_info_bw {
881 	__le16 bw_profile_idx;
882 	__le16 bw_alloc;
883 };
884 
885 struct ice_aqc_txsched_elem {
886 	u8 elem_type; /* Special field, reserved for some aq calls */
887 #define ICE_AQC_ELEM_TYPE_UNDEFINED		0x0
888 #define ICE_AQC_ELEM_TYPE_ROOT_PORT		0x1
889 #define ICE_AQC_ELEM_TYPE_TC			0x2
890 #define ICE_AQC_ELEM_TYPE_SE_GENERIC		0x3
891 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT		0x4
892 #define ICE_AQC_ELEM_TYPE_LEAF			0x5
893 #define ICE_AQC_ELEM_TYPE_SE_PADDED		0x6
894 	u8 valid_sections;
895 #define ICE_AQC_ELEM_VALID_GENERIC		BIT(0)
896 #define ICE_AQC_ELEM_VALID_CIR			BIT(1)
897 #define ICE_AQC_ELEM_VALID_EIR			BIT(2)
898 #define ICE_AQC_ELEM_VALID_SHARED		BIT(3)
899 	u8 generic;
900 #define ICE_AQC_ELEM_GENERIC_MODE_M		0x1
901 #define ICE_AQC_ELEM_GENERIC_PRIO_S		0x1
902 #define ICE_AQC_ELEM_GENERIC_PRIO_M	        GENMASK(3, 1)
903 #define ICE_AQC_ELEM_GENERIC_SP_S		0x4
904 #define ICE_AQC_ELEM_GENERIC_SP_M	        GENMASK(4, 4)
905 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S	0x5
906 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M	\
907 	(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
908 	u8 flags; /* Special field, reserved for some aq calls */
909 #define ICE_AQC_ELEM_FLAG_SUSPEND_M		0x1
910 	struct ice_aqc_elem_info_bw cir_bw;
911 	struct ice_aqc_elem_info_bw eir_bw;
912 	__le16 srl_id;
913 	__le16 reserved2;
914 };
915 
916 struct ice_aqc_txsched_elem_data {
917 	__le32 parent_teid;
918 	__le32 node_teid;
919 	struct ice_aqc_txsched_elem data;
920 };
921 
922 struct ice_aqc_txsched_topo_grp_info_hdr {
923 	__le32 parent_teid;
924 	__le16 num_elems;
925 	__le16 reserved2;
926 };
927 
928 struct ice_aqc_add_elem {
929 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
930 	struct ice_aqc_txsched_elem_data generic[];
931 };
932 
933 struct ice_aqc_get_topo_elem {
934 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
935 	struct ice_aqc_txsched_elem_data
936 		generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
937 };
938 
939 struct ice_aqc_delete_elem {
940 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
941 	__le32 teid[];
942 };
943 
944 /* Query Port ETS (indirect 0x040E)
945  *
946  * This indirect command is used to query port TC node configuration.
947  */
948 struct ice_aqc_query_port_ets {
949 	__le32 port_teid;
950 	__le32 reserved;
951 	__le32 addr_high;
952 	__le32 addr_low;
953 };
954 
955 struct ice_aqc_port_ets_elem {
956 	u8 tc_valid_bits;
957 	u8 reserved[3];
958 	/* 3 bits for UP per TC 0-7, 4th byte reserved */
959 	__le32 up2tc;
960 	u8 tc_bw_share[8];
961 	__le32 port_eir_prof_id;
962 	__le32 port_cir_prof_id;
963 	/* 3 bits per Node priority to TC 0-7, 4th byte reserved */
964 	__le32 tc_node_prio;
965 #define ICE_TC_NODE_PRIO_S	0x4
966 	u8 reserved1[4];
967 	__le32 tc_node_teid[8]; /* Used for response, reserved in command */
968 };
969 
970 /* Rate limiting profile for
971  * Add RL profile (indirect 0x0410)
972  * Query RL profile (indirect 0x0411)
973  * Remove RL profile (indirect 0x0415)
974  * These indirect commands acts on single or multiple
975  * RL profiles with specified data.
976  */
977 struct ice_aqc_rl_profile {
978 	__le16 num_profiles;
979 	__le16 num_processed; /* Only for response. Reserved in Command. */
980 	u8 reserved[4];
981 	__le32 addr_high;
982 	__le32 addr_low;
983 };
984 
985 struct ice_aqc_rl_profile_elem {
986 	u8 level;
987 	u8 flags;
988 #define ICE_AQC_RL_PROFILE_TYPE_S	0x0
989 #define ICE_AQC_RL_PROFILE_TYPE_M	(0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
990 #define ICE_AQC_RL_PROFILE_TYPE_CIR	0
991 #define ICE_AQC_RL_PROFILE_TYPE_EIR	1
992 #define ICE_AQC_RL_PROFILE_TYPE_SRL	2
993 /* The following flag is used for Query RL Profile Data */
994 #define ICE_AQC_RL_PROFILE_INVAL_S	0x7
995 #define ICE_AQC_RL_PROFILE_INVAL_M	(0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
996 
997 	__le16 profile_id;
998 	__le16 max_burst_size;
999 	__le16 rl_multiply;
1000 	__le16 wake_up_calc;
1001 	__le16 rl_encode;
1002 };
1003 
1004 /* Query Scheduler Resource Allocation (indirect 0x0412)
1005  * This indirect command retrieves the scheduler resources allocated by
1006  * EMP Firmware to the given PF.
1007  */
1008 struct ice_aqc_query_txsched_res {
1009 	u8 reserved[8];
1010 	__le32 addr_high;
1011 	__le32 addr_low;
1012 };
1013 
1014 struct ice_aqc_generic_sched_props {
1015 	__le16 phys_levels;
1016 	__le16 logical_levels;
1017 	u8 flattening_bitmap;
1018 	u8 max_device_cgds;
1019 	u8 max_pf_cgds;
1020 	u8 rsvd0;
1021 	__le16 rdma_qsets;
1022 	u8 rsvd1[22];
1023 };
1024 
1025 struct ice_aqc_layer_props {
1026 	u8 logical_layer;
1027 	u8 chunk_size;
1028 	__le16 max_device_nodes;
1029 	__le16 max_pf_nodes;
1030 	u8 rsvd0[4];
1031 	__le16 max_sibl_grp_sz;
1032 	__le16 max_cir_rl_profiles;
1033 	__le16 max_eir_rl_profiles;
1034 	__le16 max_srl_profiles;
1035 	u8 rsvd1[14];
1036 };
1037 
1038 struct ice_aqc_query_txsched_res_resp {
1039 	struct ice_aqc_generic_sched_props sched_props;
1040 	struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1041 };
1042 
1043 /* Get PHY capabilities (indirect 0x0600) */
1044 struct ice_aqc_get_phy_caps {
1045 	u8 lport_num;
1046 	u8 reserved;
1047 	__le16 param0;
1048 	/* 18.0 - Report qualified modules */
1049 #define ICE_AQC_GET_PHY_RQM		BIT(0)
1050 	/* 18.1 - 18.3 : Report mode
1051 	 * 000b - Report NVM capabilities
1052 	 * 001b - Report topology capabilities
1053 	 * 010b - Report SW configured
1054 	 * 100b - Report default capabilities
1055 	 */
1056 #define ICE_AQC_REPORT_MODE_S			1
1057 #define ICE_AQC_REPORT_MODE_M			(7 << ICE_AQC_REPORT_MODE_S)
1058 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA	0
1059 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA		BIT(1)
1060 #define ICE_AQC_REPORT_ACTIVE_CFG		BIT(2)
1061 #define ICE_AQC_REPORT_DFLT_CFG		BIT(3)
1062 	__le32 reserved1;
1063 	__le32 addr_high;
1064 	__le32 addr_low;
1065 };
1066 
1067 /* This is #define of PHY type (Extended):
1068  * The first set of defines is for phy_type_low.
1069  */
1070 #define ICE_PHY_TYPE_LOW_100BASE_TX		BIT_ULL(0)
1071 #define ICE_PHY_TYPE_LOW_100M_SGMII		BIT_ULL(1)
1072 #define ICE_PHY_TYPE_LOW_1000BASE_T		BIT_ULL(2)
1073 #define ICE_PHY_TYPE_LOW_1000BASE_SX		BIT_ULL(3)
1074 #define ICE_PHY_TYPE_LOW_1000BASE_LX		BIT_ULL(4)
1075 #define ICE_PHY_TYPE_LOW_1000BASE_KX		BIT_ULL(5)
1076 #define ICE_PHY_TYPE_LOW_1G_SGMII		BIT_ULL(6)
1077 #define ICE_PHY_TYPE_LOW_2500BASE_T		BIT_ULL(7)
1078 #define ICE_PHY_TYPE_LOW_2500BASE_X		BIT_ULL(8)
1079 #define ICE_PHY_TYPE_LOW_2500BASE_KX		BIT_ULL(9)
1080 #define ICE_PHY_TYPE_LOW_5GBASE_T		BIT_ULL(10)
1081 #define ICE_PHY_TYPE_LOW_5GBASE_KR		BIT_ULL(11)
1082 #define ICE_PHY_TYPE_LOW_10GBASE_T		BIT_ULL(12)
1083 #define ICE_PHY_TYPE_LOW_10G_SFI_DA		BIT_ULL(13)
1084 #define ICE_PHY_TYPE_LOW_10GBASE_SR		BIT_ULL(14)
1085 #define ICE_PHY_TYPE_LOW_10GBASE_LR		BIT_ULL(15)
1086 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1		BIT_ULL(16)
1087 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC	BIT_ULL(17)
1088 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C		BIT_ULL(18)
1089 #define ICE_PHY_TYPE_LOW_25GBASE_T		BIT_ULL(19)
1090 #define ICE_PHY_TYPE_LOW_25GBASE_CR		BIT_ULL(20)
1091 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S		BIT_ULL(21)
1092 #define ICE_PHY_TYPE_LOW_25GBASE_CR1		BIT_ULL(22)
1093 #define ICE_PHY_TYPE_LOW_25GBASE_SR		BIT_ULL(23)
1094 #define ICE_PHY_TYPE_LOW_25GBASE_LR		BIT_ULL(24)
1095 #define ICE_PHY_TYPE_LOW_25GBASE_KR		BIT_ULL(25)
1096 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S		BIT_ULL(26)
1097 #define ICE_PHY_TYPE_LOW_25GBASE_KR1		BIT_ULL(27)
1098 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC	BIT_ULL(28)
1099 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C		BIT_ULL(29)
1100 #define ICE_PHY_TYPE_LOW_40GBASE_CR4		BIT_ULL(30)
1101 #define ICE_PHY_TYPE_LOW_40GBASE_SR4		BIT_ULL(31)
1102 #define ICE_PHY_TYPE_LOW_40GBASE_LR4		BIT_ULL(32)
1103 #define ICE_PHY_TYPE_LOW_40GBASE_KR4		BIT_ULL(33)
1104 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC	BIT_ULL(34)
1105 #define ICE_PHY_TYPE_LOW_40G_XLAUI		BIT_ULL(35)
1106 #define ICE_PHY_TYPE_LOW_50GBASE_CR2		BIT_ULL(36)
1107 #define ICE_PHY_TYPE_LOW_50GBASE_SR2		BIT_ULL(37)
1108 #define ICE_PHY_TYPE_LOW_50GBASE_LR2		BIT_ULL(38)
1109 #define ICE_PHY_TYPE_LOW_50GBASE_KR2		BIT_ULL(39)
1110 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC	BIT_ULL(40)
1111 #define ICE_PHY_TYPE_LOW_50G_LAUI2		BIT_ULL(41)
1112 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC	BIT_ULL(42)
1113 #define ICE_PHY_TYPE_LOW_50G_AUI2		BIT_ULL(43)
1114 #define ICE_PHY_TYPE_LOW_50GBASE_CP		BIT_ULL(44)
1115 #define ICE_PHY_TYPE_LOW_50GBASE_SR		BIT_ULL(45)
1116 #define ICE_PHY_TYPE_LOW_50GBASE_FR		BIT_ULL(46)
1117 #define ICE_PHY_TYPE_LOW_50GBASE_LR		BIT_ULL(47)
1118 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4	BIT_ULL(48)
1119 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC	BIT_ULL(49)
1120 #define ICE_PHY_TYPE_LOW_50G_AUI1		BIT_ULL(50)
1121 #define ICE_PHY_TYPE_LOW_100GBASE_CR4		BIT_ULL(51)
1122 #define ICE_PHY_TYPE_LOW_100GBASE_SR4		BIT_ULL(52)
1123 #define ICE_PHY_TYPE_LOW_100GBASE_LR4		BIT_ULL(53)
1124 #define ICE_PHY_TYPE_LOW_100GBASE_KR4		BIT_ULL(54)
1125 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC	BIT_ULL(55)
1126 #define ICE_PHY_TYPE_LOW_100G_CAUI4		BIT_ULL(56)
1127 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC	BIT_ULL(57)
1128 #define ICE_PHY_TYPE_LOW_100G_AUI4		BIT_ULL(58)
1129 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4	BIT_ULL(59)
1130 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4	BIT_ULL(60)
1131 #define ICE_PHY_TYPE_LOW_100GBASE_CP2		BIT_ULL(61)
1132 #define ICE_PHY_TYPE_LOW_100GBASE_SR2		BIT_ULL(62)
1133 #define ICE_PHY_TYPE_LOW_100GBASE_DR		BIT_ULL(63)
1134 #define ICE_PHY_TYPE_LOW_MAX_INDEX		63
1135 /* The second set of defines is for phy_type_high. */
1136 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4	BIT_ULL(0)
1137 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC	BIT_ULL(1)
1138 #define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)
1139 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)
1140 #define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)
1141 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4		BIT_ULL(5)
1142 #define ICE_PHY_TYPE_HIGH_200G_SR4		BIT_ULL(6)
1143 #define ICE_PHY_TYPE_HIGH_200G_FR4		BIT_ULL(7)
1144 #define ICE_PHY_TYPE_HIGH_200G_LR4		BIT_ULL(8)
1145 #define ICE_PHY_TYPE_HIGH_200G_DR4		BIT_ULL(9)
1146 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4		BIT_ULL(10)
1147 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC	BIT_ULL(11)
1148 #define ICE_PHY_TYPE_HIGH_200G_AUI4		BIT_ULL(12)
1149 #define ICE_PHY_TYPE_HIGH_MAX_INDEX		12
1150 
1151 struct ice_aqc_get_phy_caps_data {
1152 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1153 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1154 	u8 caps;
1155 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE			BIT(0)
1156 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE			BIT(1)
1157 #define ICE_AQC_PHY_LOW_POWER_MODE			BIT(2)
1158 #define ICE_AQC_PHY_EN_LINK				BIT(3)
1159 #define ICE_AQC_PHY_AN_MODE				BIT(4)
1160 #define ICE_AQC_GET_PHY_EN_MOD_QUAL			BIT(5)
1161 #define ICE_AQC_PHY_EN_AUTO_FEC				BIT(7)
1162 #define ICE_AQC_PHY_CAPS_MASK				ICE_M(0xff, 0)
1163 	u8 low_power_ctrl_an;
1164 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG		BIT(0)
1165 #define ICE_AQC_PHY_AN_EN_CLAUSE28			BIT(1)
1166 #define ICE_AQC_PHY_AN_EN_CLAUSE73			BIT(2)
1167 #define ICE_AQC_PHY_AN_EN_CLAUSE37			BIT(3)
1168 	__le16 eee_cap;
1169 #define ICE_AQC_PHY_EEE_EN_100BASE_TX			BIT(0)
1170 #define ICE_AQC_PHY_EEE_EN_1000BASE_T			BIT(1)
1171 #define ICE_AQC_PHY_EEE_EN_10GBASE_T			BIT(2)
1172 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX			BIT(3)
1173 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR			BIT(4)
1174 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR			BIT(5)
1175 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4			BIT(6)
1176 	__le16 eeer_value;
1177 	u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1178 	u8 phy_fw_ver[8];
1179 	u8 link_fec_options;
1180 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN		BIT(0)
1181 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ		BIT(1)
1182 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ			BIT(2)
1183 #define ICE_AQC_PHY_FEC_25G_KR_REQ			BIT(3)
1184 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ			BIT(4)
1185 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN		BIT(6)
1186 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN		BIT(7)
1187 #define ICE_AQC_PHY_FEC_MASK				ICE_M(0xdf, 0)
1188 	u8 module_compliance_enforcement;
1189 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE			BIT(0)
1190 	u8 extended_compliance_code;
1191 #define ICE_MODULE_TYPE_TOTAL_BYTE			3
1192 	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1193 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS			0xA0
1194 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS		0x80
1195 #define ICE_AQC_MOD_TYPE_IDENT				1
1196 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE	BIT(0)
1197 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE	BIT(1)
1198 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR		BIT(4)
1199 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR		BIT(5)
1200 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM		BIT(6)
1201 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER		BIT(7)
1202 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS			0xA0
1203 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS		0x86
1204 	u8 qualified_module_count;
1205 	u8 rsvd2[7];	/* Bytes 47:41 reserved */
1206 #define ICE_AQC_QUAL_MOD_COUNT_MAX			16
1207 	struct {
1208 		u8 v_oui[3];
1209 		u8 rsvd3;
1210 		u8 v_part[16];
1211 		__le32 v_rev;
1212 		__le64 rsvd4;
1213 	} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1214 };
1215 
1216 /* Set PHY capabilities (direct 0x0601)
1217  * NOTE: This command must be followed by setup link and restart auto-neg
1218  */
1219 struct ice_aqc_set_phy_cfg {
1220 	u8 lport_num;
1221 	u8 reserved[7];
1222 	__le32 addr_high;
1223 	__le32 addr_low;
1224 };
1225 
1226 /* Set PHY config command data structure */
1227 struct ice_aqc_set_phy_cfg_data {
1228 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1229 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1230 	u8 caps;
1231 #define ICE_AQ_PHY_ENA_VALID_MASK	ICE_M(0xef, 0)
1232 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY	BIT(0)
1233 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY	BIT(1)
1234 #define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)
1235 #define ICE_AQ_PHY_ENA_LINK		BIT(3)
1236 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT	BIT(5)
1237 #define ICE_AQ_PHY_ENA_LESM		BIT(6)
1238 #define ICE_AQ_PHY_ENA_AUTO_FEC		BIT(7)
1239 	u8 low_power_ctrl_an;
1240 	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1241 	__le16 eeer_value;
1242 	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1243 	u8 module_compliance_enforcement;
1244 };
1245 
1246 /* Set MAC Config command data structure (direct 0x0603) */
1247 struct ice_aqc_set_mac_cfg {
1248 	__le16 max_frame_size;
1249 	u8 params;
1250 #define ICE_AQ_SET_MAC_PACE_S		3
1251 #define ICE_AQ_SET_MAC_PACE_M		(0xF << ICE_AQ_SET_MAC_PACE_S)
1252 #define ICE_AQ_SET_MAC_PACE_TYPE_M	BIT(7)
1253 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE	0
1254 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED	ICE_AQ_SET_MAC_PACE_TYPE_M
1255 	u8 tx_tmr_priority;
1256 	__le16 tx_tmr_value;
1257 	__le16 fc_refresh_threshold;
1258 	u8 drop_opts;
1259 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK		BIT(0)
1260 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE		0
1261 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS	BIT(0)
1262 	u8 reserved[7];
1263 };
1264 
1265 /* Restart AN command data structure (direct 0x0605)
1266  * Also used for response, with only the lport_num field present.
1267  */
1268 struct ice_aqc_restart_an {
1269 	u8 lport_num;
1270 	u8 reserved;
1271 	u8 cmd_flags;
1272 #define ICE_AQC_RESTART_AN_LINK_RESTART	BIT(1)
1273 #define ICE_AQC_RESTART_AN_LINK_ENABLE	BIT(2)
1274 	u8 reserved2[13];
1275 };
1276 
1277 /* Get link status (indirect 0x0607), also used for Link Status Event */
1278 struct ice_aqc_get_link_status {
1279 	u8 lport_num;
1280 	u8 reserved;
1281 	__le16 cmd_flags;
1282 #define ICE_AQ_LSE_M			0x3
1283 #define ICE_AQ_LSE_NOP			0x0
1284 #define ICE_AQ_LSE_DIS			0x2
1285 #define ICE_AQ_LSE_ENA			0x3
1286 	/* only response uses this flag */
1287 #define ICE_AQ_LSE_IS_ENABLED		0x1
1288 	__le32 reserved2;
1289 	__le32 addr_high;
1290 	__le32 addr_low;
1291 };
1292 
1293 /* Get link status response data structure, also used for Link Status Event */
1294 struct ice_aqc_get_link_status_data {
1295 	u8 topo_media_conflict;
1296 #define ICE_AQ_LINK_TOPO_CONFLICT	BIT(0)
1297 #define ICE_AQ_LINK_MEDIA_CONFLICT	BIT(1)
1298 #define ICE_AQ_LINK_TOPO_CORRUPT	BIT(2)
1299 #define ICE_AQ_LINK_TOPO_UNREACH_PRT	BIT(4)
1300 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT	BIT(5)
1301 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA	BIT(6)
1302 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA	BIT(7)
1303 	u8 link_cfg_err;
1304 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED	BIT(5)
1305 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE	BIT(6)
1306 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT	BIT(7)
1307 	u8 link_info;
1308 #define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
1309 #define ICE_AQ_LINK_FAULT		BIT(1)
1310 #define ICE_AQ_LINK_FAULT_TX		BIT(2)
1311 #define ICE_AQ_LINK_FAULT_RX		BIT(3)
1312 #define ICE_AQ_LINK_FAULT_REMOTE	BIT(4)
1313 #define ICE_AQ_LINK_UP_PORT		BIT(5)	/* External Port Link Status */
1314 #define ICE_AQ_MEDIA_AVAILABLE		BIT(6)
1315 #define ICE_AQ_SIGNAL_DETECT		BIT(7)
1316 	u8 an_info;
1317 #define ICE_AQ_AN_COMPLETED		BIT(0)
1318 #define ICE_AQ_LP_AN_ABILITY		BIT(1)
1319 #define ICE_AQ_PD_FAULT			BIT(2)	/* Parallel Detection Fault */
1320 #define ICE_AQ_FEC_EN			BIT(3)
1321 #define ICE_AQ_PHY_LOW_POWER		BIT(4)	/* Low Power State */
1322 #define ICE_AQ_LINK_PAUSE_TX		BIT(5)
1323 #define ICE_AQ_LINK_PAUSE_RX		BIT(6)
1324 #define ICE_AQ_QUALIFIED_MODULE		BIT(7)
1325 	u8 ext_info;
1326 #define ICE_AQ_LINK_PHY_TEMP_ALARM	BIT(0)
1327 #define ICE_AQ_LINK_EXCESSIVE_ERRORS	BIT(1)	/* Excessive Link Errors */
1328 	/* Port Tx Suspended */
1329 #define ICE_AQ_LINK_TX_S		2
1330 #define ICE_AQ_LINK_TX_M		(0x03 << ICE_AQ_LINK_TX_S)
1331 #define ICE_AQ_LINK_TX_ACTIVE		0
1332 #define ICE_AQ_LINK_TX_DRAINED		1
1333 #define ICE_AQ_LINK_TX_FLUSHED		3
1334 	u8 reserved2;
1335 	__le16 max_frame_size;
1336 	u8 cfg;
1337 #define ICE_AQ_LINK_25G_KR_FEC_EN	BIT(0)
1338 #define ICE_AQ_LINK_25G_RS_528_FEC_EN	BIT(1)
1339 #define ICE_AQ_LINK_25G_RS_544_FEC_EN	BIT(2)
1340 #define ICE_AQ_FEC_MASK			ICE_M(0x7, 0)
1341 	/* Pacing Config */
1342 #define ICE_AQ_CFG_PACING_S		3
1343 #define ICE_AQ_CFG_PACING_M		(0xF << ICE_AQ_CFG_PACING_S)
1344 #define ICE_AQ_CFG_PACING_TYPE_M	BIT(7)
1345 #define ICE_AQ_CFG_PACING_TYPE_AVG	0
1346 #define ICE_AQ_CFG_PACING_TYPE_FIXED	ICE_AQ_CFG_PACING_TYPE_M
1347 	/* External Device Power Ability */
1348 	u8 power_desc;
1349 #define ICE_AQ_PWR_CLASS_M		0x3F
1350 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH	0
1351 #define ICE_AQ_LINK_PWR_BASET_HIGH	1
1352 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1	0
1353 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2	1
1354 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3	2
1355 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4	3
1356 	__le16 link_speed;
1357 #define ICE_AQ_LINK_SPEED_M		0x7FF
1358 #define ICE_AQ_LINK_SPEED_10MB		BIT(0)
1359 #define ICE_AQ_LINK_SPEED_100MB		BIT(1)
1360 #define ICE_AQ_LINK_SPEED_1000MB	BIT(2)
1361 #define ICE_AQ_LINK_SPEED_2500MB	BIT(3)
1362 #define ICE_AQ_LINK_SPEED_5GB		BIT(4)
1363 #define ICE_AQ_LINK_SPEED_10GB		BIT(5)
1364 #define ICE_AQ_LINK_SPEED_20GB		BIT(6)
1365 #define ICE_AQ_LINK_SPEED_25GB		BIT(7)
1366 #define ICE_AQ_LINK_SPEED_40GB		BIT(8)
1367 #define ICE_AQ_LINK_SPEED_50GB		BIT(9)
1368 #define ICE_AQ_LINK_SPEED_100GB		BIT(10)
1369 #define ICE_AQ_LINK_SPEED_200GB		BIT(11)
1370 #define ICE_AQ_LINK_SPEED_UNKNOWN	BIT(15)
1371 	/* Aligns next field to 8-byte boundary */
1372 	__le16 reserved3;
1373 	u8 ext_fec_status;
1374 	/* RS 272 FEC enabled */
1375 #define ICE_AQ_LINK_RS_272_FEC_EN      BIT(0)
1376 	u8 reserved4;
1377 	/* Use values from ICE_PHY_TYPE_LOW_* */
1378 	__le64 phy_type_low;
1379 	/* Use values from ICE_PHY_TYPE_HIGH_* */
1380 	__le64 phy_type_high;
1381 #define ICE_AQC_LS_DATA_SIZE_V1 \
1382 	offsetofend(struct ice_aqc_get_link_status_data, phy_type_high)
1383 	/* Get link status v2 link partner data */
1384 	__le64 lp_phy_type_low;
1385 	__le64 lp_phy_type_high;
1386 	u8 lp_fec_adv;
1387 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP  BIT(0)
1388 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP  BIT(1)
1389 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP  BIT(2)
1390 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3)
1391 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4)
1392 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5)
1393 	u8 lp_fec_req;
1394 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ  BIT(0)
1395 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ  BIT(1)
1396 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ  BIT(2)
1397 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ  BIT(3)
1398 	u8 lp_flowcontrol;
1399 #define ICE_AQ_LINK_LP_PAUSE_ADV       BIT(0)
1400 #define ICE_AQ_LINK_LP_ASM_DIR_ADV     BIT(1)
1401 	u8 reserved5[5];
1402 #define ICE_AQC_LS_DATA_SIZE_V2 \
1403 	offsetofend(struct ice_aqc_get_link_status_data, reserved5)
1404 } __packed;
1405 
1406 /* Set event mask command (direct 0x0613) */
1407 struct ice_aqc_set_event_mask {
1408 	u8	lport_num;
1409 	u8	reserved[7];
1410 	__le16	event_mask;
1411 #define ICE_AQ_LINK_EVENT_UPDOWN		BIT(1)
1412 #define ICE_AQ_LINK_EVENT_MEDIA_NA		BIT(2)
1413 #define ICE_AQ_LINK_EVENT_LINK_FAULT		BIT(3)
1414 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM	BIT(4)
1415 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS	BIT(5)
1416 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT		BIT(6)
1417 #define ICE_AQ_LINK_EVENT_AN_COMPLETED		BIT(7)
1418 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL	BIT(8)
1419 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED	BIT(9)
1420 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL	BIT(12)
1421 	u8	reserved1[6];
1422 };
1423 
1424 /* Set MAC Loopback command (direct 0x0620) */
1425 struct ice_aqc_set_mac_lb {
1426 	u8 lb_mode;
1427 #define ICE_AQ_MAC_LB_EN		BIT(0)
1428 #define ICE_AQ_MAC_LB_OSC_CLK		BIT(1)
1429 	u8 reserved[15];
1430 };
1431 
1432 /* Set PHY recovered clock output (direct 0x0630) */
1433 struct ice_aqc_set_phy_rec_clk_out {
1434 	u8 phy_output;
1435 	u8 port_num;
1436 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT	0xFF
1437 	u8 flags;
1438 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN	BIT(0)
1439 	u8 rsvd;
1440 	__le32 freq;
1441 	u8 rsvd2[6];
1442 	__le16 node_handle;
1443 };
1444 
1445 /* Get PHY recovered clock output (direct 0x0631) */
1446 struct ice_aqc_get_phy_rec_clk_out {
1447 	u8 phy_output;
1448 	u8 port_num;
1449 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT	0xFF
1450 	u8 flags;
1451 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN	BIT(0)
1452 	u8 rsvd[11];
1453 	__le16 node_handle;
1454 };
1455 
1456 /* Get sensor reading (direct 0x0632) */
1457 struct ice_aqc_get_sensor_reading {
1458 	u8 sensor;
1459 	u8 format;
1460 	u8 reserved[6];
1461 	__le32 addr_high;
1462 	__le32 addr_low;
1463 };
1464 
1465 /* Get sensor reading response (direct 0x0632) */
1466 struct ice_aqc_get_sensor_reading_resp {
1467 	union {
1468 		u8 raw[8];
1469 		/* Output data for sensor 0x00, format 0x00 */
1470 		struct _packed {
1471 			s8 temp;
1472 			u8 temp_warning_threshold;
1473 			u8 temp_critical_threshold;
1474 			u8 temp_fatal_threshold;
1475 			u8 reserved[4];
1476 		} s0f0;
1477 	} data;
1478 };
1479 
1480 /* DNL call command (indirect 0x0682)
1481  * Struct is used for both command and response
1482  */
1483 struct ice_aqc_dnl_call_command {
1484 	u8 ctx; /* Used in command, reserved in response */
1485 	u8 reserved;
1486 	__le16 activity_id;
1487 #define ICE_AQC_ACT_ID_DNL 0x1129
1488 	__le32 reserved1;
1489 	__le32 addr_high;
1490 	__le32 addr_low;
1491 };
1492 
1493 struct ice_aqc_dnl_equa_param {
1494 	__le16 data_in;
1495 #define ICE_AQC_RX_EQU_SHIFT 8
1496 #define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT)
1497 #define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT)
1498 #define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT)
1499 #define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT)
1500 #define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT)
1501 #define ICE_AQC_RX_EQU_CTLE_GAINHF (0x20 << ICE_AQC_RX_EQU_SHIFT)
1502 #define ICE_AQC_RX_EQU_CTLE_GAINLF (0x21 << ICE_AQC_RX_EQU_SHIFT)
1503 #define ICE_AQC_RX_EQU_CTLE_GAINDC (0x22 << ICE_AQC_RX_EQU_SHIFT)
1504 #define ICE_AQC_RX_EQU_CTLE_BW (0x23 << ICE_AQC_RX_EQU_SHIFT)
1505 #define ICE_AQC_RX_EQU_DFE_GAIN (0x30 << ICE_AQC_RX_EQU_SHIFT)
1506 #define ICE_AQC_RX_EQU_DFE_GAIN2 (0x31 << ICE_AQC_RX_EQU_SHIFT)
1507 #define ICE_AQC_RX_EQU_DFE_2 (0x32 << ICE_AQC_RX_EQU_SHIFT)
1508 #define ICE_AQC_RX_EQU_DFE_3 (0x33 << ICE_AQC_RX_EQU_SHIFT)
1509 #define ICE_AQC_RX_EQU_DFE_4 (0x34 << ICE_AQC_RX_EQU_SHIFT)
1510 #define ICE_AQC_RX_EQU_DFE_5 (0x35 << ICE_AQC_RX_EQU_SHIFT)
1511 #define ICE_AQC_RX_EQU_DFE_6 (0x36 << ICE_AQC_RX_EQU_SHIFT)
1512 #define ICE_AQC_RX_EQU_DFE_7 (0x37 << ICE_AQC_RX_EQU_SHIFT)
1513 #define ICE_AQC_RX_EQU_DFE_8 (0x38 << ICE_AQC_RX_EQU_SHIFT)
1514 #define ICE_AQC_RX_EQU_DFE_9 (0x39 << ICE_AQC_RX_EQU_SHIFT)
1515 #define ICE_AQC_RX_EQU_DFE_10 (0x3A << ICE_AQC_RX_EQU_SHIFT)
1516 #define ICE_AQC_RX_EQU_DFE_11 (0x3B << ICE_AQC_RX_EQU_SHIFT)
1517 #define ICE_AQC_RX_EQU_DFE_12 (0x3C << ICE_AQC_RX_EQU_SHIFT)
1518 #define ICE_AQC_TX_EQU_PRE1 0x0
1519 #define ICE_AQC_TX_EQU_PRE3 0x3
1520 #define ICE_AQC_TX_EQU_ATTEN 0x4
1521 #define ICE_AQC_TX_EQU_POST1 0x8
1522 #define ICE_AQC_TX_EQU_PRE2 0xC
1523 	__le16 op_code_serdes_sel;
1524 #define ICE_AQC_OP_CODE_SHIFT 4
1525 #define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT)
1526 #define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT)
1527 	__le32 reserved[3];
1528 };
1529 
1530 struct ice_aqc_dnl_equa_respon {
1531 	/* Equalization value can be negative */
1532 	int val;
1533 	__le32 reserved[3];
1534 };
1535 
1536 /* DNL call command/response buffer (indirect 0x0682) */
1537 struct ice_aqc_dnl_call {
1538 	union {
1539 		struct ice_aqc_dnl_equa_param txrx_equa_reqs;
1540 		__le32 stores[4];
1541 		struct ice_aqc_dnl_equa_respon txrx_equa_resp;
1542 	} sto;
1543 };
1544 
1545 struct ice_aqc_link_topo_params {
1546 	u8 lport_num;
1547 	u8 lport_num_valid;
1548 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID	BIT(0)
1549 	u8 node_type_ctx;
1550 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S		0
1551 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M	(0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1552 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY		0
1553 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL	1
1554 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL	2
1555 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL	3
1556 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED		4
1557 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL	5
1558 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE	6
1559 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ	7
1560 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM	8
1561 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL	9
1562 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX	10
1563 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS		11
1564 #define ICE_AQC_LINK_TOPO_NODE_CTX_S		4
1565 #define ICE_AQC_LINK_TOPO_NODE_CTX_M		\
1566 				(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1567 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL	0
1568 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD	1
1569 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT		2
1570 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE		3
1571 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED	4
1572 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE	5
1573 	u8 index;
1574 };
1575 
1576 struct ice_aqc_link_topo_addr {
1577 	struct ice_aqc_link_topo_params topo_params;
1578 	__le16 handle;
1579 #define ICE_AQC_LINK_TOPO_HANDLE_S	0
1580 #define ICE_AQC_LINK_TOPO_HANDLE_M	(0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1581 /* Used to decode the handle field */
1582 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M	BIT(9)
1583 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM	BIT(9)
1584 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ	0
1585 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S		0
1586 /* In case of a Mezzanine type */
1587 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M	\
1588 				(0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1589 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S	6
1590 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M	(0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1591 /* In case of a LOM type */
1592 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M	\
1593 				(0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1594 };
1595 
1596 /* Get Link Topology Handle (direct, 0x06E0) */
1597 struct ice_aqc_get_link_topo {
1598 	struct ice_aqc_link_topo_addr addr;
1599 	u8 node_part_num;
1600 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575		0x21
1601 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032	0x24
1602 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384	0x25
1603 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY		0x30
1604 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827		0x31
1605 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX	0x47
1606 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS		0x48
1607 	u8 rsvd[9];
1608 };
1609 
1610 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
1611 struct ice_aqc_i2c {
1612 	struct ice_aqc_link_topo_addr topo_addr;
1613 	__le16 i2c_addr;
1614 	u8 i2c_params;
1615 #define ICE_AQC_I2C_DATA_SIZE_M		GENMASK(3, 0)
1616 #define ICE_AQC_I2C_USE_REPEATED_START	BIT(7)
1617 
1618 	u8 rsvd;
1619 	__le16 i2c_bus_addr;
1620 	u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1621 };
1622 
1623 /* Read I2C Response (direct, 0x06E2) */
1624 struct ice_aqc_read_i2c_resp {
1625 	u8 i2c_data[16];
1626 };
1627 
1628 /* Set Port Identification LED (direct, 0x06E9) */
1629 struct ice_aqc_set_port_id_led {
1630 	u8 lport_num;
1631 	u8 lport_num_valid;
1632 	u8 ident_mode;
1633 #define ICE_AQC_PORT_IDENT_LED_BLINK	BIT(0)
1634 #define ICE_AQC_PORT_IDENT_LED_ORIG	0
1635 	u8 rsvd[13];
1636 };
1637 
1638 /* Get Port Options (indirect, 0x06EA) */
1639 struct ice_aqc_get_port_options {
1640 	u8 lport_num;
1641 	u8 lport_num_valid;
1642 	u8 port_options_count;
1643 #define ICE_AQC_PORT_OPT_COUNT_M	GENMASK(3, 0)
1644 #define ICE_AQC_PORT_OPT_MAX		16
1645 
1646 	u8 innermost_phy_index;
1647 	u8 port_options;
1648 #define ICE_AQC_PORT_OPT_ACTIVE_M	GENMASK(3, 0)
1649 #define ICE_AQC_PORT_OPT_VALID		BIT(7)
1650 
1651 	u8 pending_port_option_status;
1652 #define ICE_AQC_PENDING_PORT_OPT_IDX_M	GENMASK(3, 0)
1653 #define ICE_AQC_PENDING_PORT_OPT_VALID	BIT(7)
1654 
1655 	u8 rsvd[2];
1656 	__le32 addr_high;
1657 	__le32 addr_low;
1658 };
1659 
1660 struct ice_aqc_get_port_options_elem {
1661 	u8 pmd;
1662 #define ICE_AQC_PORT_OPT_PMD_COUNT_M	GENMASK(3, 0)
1663 
1664 	u8 max_lane_speed;
1665 #define ICE_AQC_PORT_OPT_MAX_LANE_M	GENMASK(3, 0)
1666 #define ICE_AQC_PORT_OPT_MAX_LANE_100M	0
1667 #define ICE_AQC_PORT_OPT_MAX_LANE_1G	1
1668 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M	2
1669 #define ICE_AQC_PORT_OPT_MAX_LANE_5G	3
1670 #define ICE_AQC_PORT_OPT_MAX_LANE_10G	4
1671 #define ICE_AQC_PORT_OPT_MAX_LANE_25G	5
1672 #define ICE_AQC_PORT_OPT_MAX_LANE_50G	6
1673 #define ICE_AQC_PORT_OPT_MAX_LANE_100G	7
1674 #define ICE_AQC_PORT_OPT_MAX_LANE_200G	8
1675 
1676 	u8 global_scid[2];
1677 	u8 phy_scid[2];
1678 	u8 pf2port_cid[2];
1679 };
1680 
1681 /* Set Port Option (direct, 0x06EB) */
1682 struct ice_aqc_set_port_option {
1683 	u8 lport_num;
1684 	u8 lport_num_valid;
1685 	u8 selected_port_option;
1686 	u8 rsvd[13];
1687 };
1688 
1689 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1690 struct ice_aqc_gpio {
1691 	__le16 gpio_ctrl_handle;
1692 #define ICE_AQC_GPIO_HANDLE_S	0
1693 #define ICE_AQC_GPIO_HANDLE_M	(0x3FF << ICE_AQC_GPIO_HANDLE_S)
1694 	u8 gpio_num;
1695 	u8 gpio_val;
1696 	u8 rsvd[12];
1697 };
1698 
1699 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1700 struct ice_aqc_sff_eeprom {
1701 	u8 lport_num;
1702 	u8 lport_num_valid;
1703 #define ICE_AQC_SFF_PORT_NUM_VALID	BIT(0)
1704 	__le16 i2c_bus_addr;
1705 #define ICE_AQC_SFF_I2CBUS_7BIT_M	0x7F
1706 #define ICE_AQC_SFF_I2CBUS_10BIT_M	0x3FF
1707 #define ICE_AQC_SFF_I2CBUS_TYPE_M	BIT(10)
1708 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT	0
1709 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT	ICE_AQC_SFF_I2CBUS_TYPE_M
1710 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S	11
1711 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M	(0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1712 #define ICE_AQC_SFF_NO_PAGE_CHANGE	0
1713 #define ICE_AQC_SFF_SET_23_ON_MISMATCH	1
1714 #define ICE_AQC_SFF_SET_22_ON_MISMATCH	2
1715 #define ICE_AQC_SFF_IS_WRITE		BIT(15)
1716 	__le16 i2c_mem_addr;
1717 	__le16 eeprom_page;
1718 #define  ICE_AQC_SFF_EEPROM_BANK_S 0
1719 #define  ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1720 #define  ICE_AQC_SFF_EEPROM_PAGE_S 8
1721 #define  ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1722 	__le32 addr_high;
1723 	__le32 addr_low;
1724 };
1725 
1726 /* NVM Read command (indirect 0x0701)
1727  * NVM Erase commands (direct 0x0702)
1728  * NVM Update commands (indirect 0x0703)
1729  */
1730 struct ice_aqc_nvm {
1731 #define ICE_AQC_NVM_MAX_OFFSET		0xFFFFFF
1732 	__le16 offset_low;
1733 	u8 offset_high;
1734 	u8 cmd_flags;
1735 #define ICE_AQC_NVM_LAST_CMD		BIT(0)
1736 #define ICE_AQC_NVM_PCIR_REQ		BIT(0)	/* Used by NVM Update reply */
1737 #define ICE_AQC_NVM_PRESERVATION_S	1
1738 #define ICE_AQC_NVM_PRESERVATION_M	(3 << ICE_AQC_NVM_PRESERVATION_S)
1739 #define ICE_AQC_NVM_NO_PRESERVATION	(0 << ICE_AQC_NVM_PRESERVATION_S)
1740 #define ICE_AQC_NVM_PRESERVE_ALL	BIT(1)
1741 #define ICE_AQC_NVM_FACTORY_DEFAULT	(2 << ICE_AQC_NVM_PRESERVATION_S)
1742 #define ICE_AQC_NVM_PRESERVE_SELECTED	(3 << ICE_AQC_NVM_PRESERVATION_S)
1743 #define ICE_AQC_NVM_ACTIV_SEL_NVM	BIT(3) /* Write Activate/SR Dump only */
1744 #define ICE_AQC_NVM_ACTIV_SEL_OROM	BIT(4)
1745 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST	BIT(5)
1746 #define ICE_AQC_NVM_SPECIAL_UPDATE	BIT(6)
1747 #define ICE_AQC_NVM_REVERT_LAST_ACTIV	BIT(6) /* Write Activate only */
1748 #define ICE_AQC_NVM_ACTIV_SEL_MASK	ICE_M(0x7, 3)
1749 #define ICE_AQC_NVM_FLASH_ONLY		BIT(7)
1750 #define ICE_AQC_NVM_RESET_LVL_M		ICE_M(0x3, 0) /* Write reply only */
1751 #define ICE_AQC_NVM_POR_FLAG		0
1752 #define ICE_AQC_NVM_PERST_FLAG		1
1753 #define ICE_AQC_NVM_EMPR_FLAG		2
1754 #define ICE_AQC_NVM_EMPR_ENA		BIT(0) /* Write Activate reply only */
1755 	/* For Write Activate, several flags are sent as part of a separate
1756 	 * flags2 field using a separate byte. For simplicity of the software
1757 	 * interface, we pass the flags as a 16 bit value so these flags are
1758 	 * all offset by 8 bits
1759 	 */
1760 #define ICE_AQC_NVM_ACTIV_REQ_EMPR	BIT(8) /* NVM Write Activate only */
1761 	__le16 module_typeid;
1762 	__le16 length;
1763 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF
1764 	__le32 addr_high;
1765 	__le32 addr_low;
1766 };
1767 
1768 #define ICE_AQC_NVM_START_POINT			0
1769 #define ICE_AQC_NVM_SECTOR_UNIT			4096
1770 #define ICE_AQC_NVM_SDP_AC_PTR_OFFSET		0xD8
1771 #define ICE_AQC_NVM_SDP_AC_PTR_M		GENMASK(14, 0)
1772 #define ICE_AQC_NVM_SDP_AC_PTR_INVAL		0x7FFF
1773 #define ICE_AQC_NVM_SDP_AC_PTR_TYPE_M		BIT(15)
1774 #define ICE_AQC_NVM_SDP_AC_SDP_NUM_M		GENMASK(2, 0)
1775 #define ICE_AQC_NVM_SDP_AC_DIR_M		BIT(3)
1776 #define ICE_AQC_NVM_SDP_AC_PIN_M		GENMASK(15, 6)
1777 #define ICE_AQC_NVM_SDP_AC_MAX_SIZE		7
1778 
1779 #define ICE_AQC_NVM_TX_TOPO_MOD_ID		0x14B
1780 
1781 struct ice_aqc_nvm_tx_topo_user_sel {
1782 	__le16 length;
1783 	u8 data;
1784 #define ICE_AQC_NVM_TX_TOPO_USER_SEL	BIT(4)
1785 	u8 reserved;
1786 };
1787 
1788 /* NVM Checksum Command (direct, 0x0706) */
1789 struct ice_aqc_nvm_checksum {
1790 	u8 flags;
1791 #define ICE_AQC_NVM_CHECKSUM_VERIFY	BIT(0)
1792 #define ICE_AQC_NVM_CHECKSUM_RECALC	BIT(1)
1793 	u8 rsvd;
1794 	__le16 checksum; /* Used only by response */
1795 #define ICE_AQC_NVM_CHECKSUM_CORRECT	0xBABA
1796 	u8 rsvd2[12];
1797 };
1798 
1799 /* Used for NVM Set Package Data command - 0x070A */
1800 struct ice_aqc_nvm_pkg_data {
1801 	u8 reserved[3];
1802 	u8 cmd_flags;
1803 #define ICE_AQC_NVM_PKG_DELETE		BIT(0) /* used for command call */
1804 #define ICE_AQC_NVM_PKG_SKIPPED		BIT(0) /* used for command response */
1805 
1806 	u32 reserved1;
1807 	__le32 addr_high;
1808 	__le32 addr_low;
1809 };
1810 
1811 /* Used for Pass Component Table command - 0x070B */
1812 struct ice_aqc_nvm_pass_comp_tbl {
1813 	u8 component_response; /* Response only */
1814 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED		0x0
1815 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE	0x1
1816 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED		0x2
1817 #define ICE_AQ_NVM_PASS_COMP_PARTIAL_CHECK		0x3
1818 	u8 component_response_code; /* Response only */
1819 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE	0x0
1820 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE	0x1
1821 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER		0x2
1822 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE		0x3
1823 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE		0x4
1824 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE	0x5
1825 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE		0x6
1826 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE	0x7
1827 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE	0x8
1828 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE	0xA
1829 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE		0xB
1830 	u8 reserved;
1831 	u8 transfer_flag;
1832 #define ICE_AQ_NVM_PASS_COMP_TBL_START			0x1
1833 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE			0x2
1834 #define ICE_AQ_NVM_PASS_COMP_TBL_END			0x4
1835 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END		0x5
1836 	__le32 reserved1;
1837 	__le32 addr_high;
1838 	__le32 addr_low;
1839 };
1840 
1841 struct ice_aqc_nvm_comp_tbl {
1842 	__le16 comp_class;
1843 #define NVM_COMP_CLASS_ALL_FW	0x000A
1844 
1845 	__le16 comp_id;
1846 #define NVM_COMP_ID_OROM	0x5
1847 #define NVM_COMP_ID_NVM		0x6
1848 #define NVM_COMP_ID_NETLIST	0x8
1849 
1850 	u8 comp_class_idx;
1851 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1852 
1853 	__le32 comp_cmp_stamp;
1854 	u8 cvs_type;
1855 #define NVM_CVS_TYPE_ASCII	0x1
1856 
1857 	u8 cvs_len;
1858 	u8 cvs[]; /* Component Version String */
1859 } __packed;
1860 
1861 /* Send to PF command (indirect 0x0801) ID is only used by PF
1862  *
1863  * Send to VF command (indirect 0x0802) ID is only used by PF
1864  *
1865  */
1866 struct ice_aqc_pf_vf_msg {
1867 	__le32 id;
1868 	u32 reserved;
1869 	__le32 addr_high;
1870 	__le32 addr_low;
1871 };
1872 
1873 /* Get LLDP MIB (indirect 0x0A00)
1874  * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1875  * as the format is the same.
1876  */
1877 struct ice_aqc_lldp_get_mib {
1878 	u8 type;
1879 #define ICE_AQ_LLDP_MIB_TYPE_S			0
1880 #define ICE_AQ_LLDP_MIB_TYPE_M			(0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1881 #define ICE_AQ_LLDP_MIB_LOCAL			0
1882 #define ICE_AQ_LLDP_MIB_REMOTE			1
1883 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE	2
1884 #define ICE_AQ_LLDP_BRID_TYPE_S			2
1885 #define ICE_AQ_LLDP_BRID_TYPE_M			(0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1886 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID	0
1887 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR		1
1888 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1889 #define ICE_AQ_LLDP_TX_S			0x4
1890 #define ICE_AQ_LLDP_TX_M			(0x03 << ICE_AQ_LLDP_TX_S)
1891 #define ICE_AQ_LLDP_TX_ACTIVE			0
1892 #define ICE_AQ_LLDP_TX_SUSPENDED		1
1893 #define ICE_AQ_LLDP_TX_FLUSHED			3
1894 /* DCBX mode */
1895 #define ICE_AQ_LLDP_DCBX_M			GENMASK(7, 6)
1896 #define ICE_AQ_LLDP_DCBX_NA			0
1897 #define ICE_AQ_LLDP_DCBX_CEE			1
1898 #define ICE_AQ_LLDP_DCBX_IEEE			2
1899 
1900 	u8 state;
1901 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M		BIT(0)
1902 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED		0
1903 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING		1
1904 
1905 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1906  * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1907  * Get LLDP MIB (0x0A00) response only.
1908  */
1909 	__le16 local_len;
1910 	__le16 remote_len;
1911 	u8 reserved[2];
1912 	__le32 addr_high;
1913 	__le32 addr_low;
1914 };
1915 
1916 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1917 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1918 struct ice_aqc_lldp_set_mib_change {
1919 	u8 command;
1920 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE		0x0
1921 #define ICE_AQ_LLDP_MIB_UPDATE_DIS		0x1
1922 #define ICE_AQ_LLDP_MIB_PENDING_M		BIT(1)
1923 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE		0
1924 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE		1
1925 	u8 reserved[15];
1926 };
1927 
1928 /* Stop LLDP (direct 0x0A05) */
1929 struct ice_aqc_lldp_stop {
1930 	u8 command;
1931 #define ICE_AQ_LLDP_AGENT_STATE_MASK	BIT(0)
1932 #define ICE_AQ_LLDP_AGENT_STOP		0x0
1933 #define ICE_AQ_LLDP_AGENT_SHUTDOWN	ICE_AQ_LLDP_AGENT_STATE_MASK
1934 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS	BIT(1)
1935 	u8 reserved[15];
1936 };
1937 
1938 /* Start LLDP (direct 0x0A06) */
1939 struct ice_aqc_lldp_start {
1940 	u8 command;
1941 #define ICE_AQ_LLDP_AGENT_START		BIT(0)
1942 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA	BIT(1)
1943 	u8 reserved[15];
1944 };
1945 
1946 /* Get CEE DCBX Oper Config (0x0A07)
1947  * The command uses the generic descriptor struct and
1948  * returns the struct below as an indirect response.
1949  */
1950 struct ice_aqc_get_cee_dcb_cfg_resp {
1951 	u8 oper_num_tc;
1952 	u8 oper_prio_tc[4];
1953 	u8 oper_tc_bw[8];
1954 	u8 oper_pfc_en;
1955 	__le16 oper_app_prio;
1956 #define ICE_AQC_CEE_APP_FCOE_S		0
1957 #define ICE_AQC_CEE_APP_FCOE_M		(0x7 << ICE_AQC_CEE_APP_FCOE_S)
1958 #define ICE_AQC_CEE_APP_ISCSI_S		3
1959 #define ICE_AQC_CEE_APP_ISCSI_M		(0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1960 #define ICE_AQC_CEE_APP_FIP_S		8
1961 #define ICE_AQC_CEE_APP_FIP_M		(0x7 << ICE_AQC_CEE_APP_FIP_S)
1962 	__le32 tlv_status;
1963 #define ICE_AQC_CEE_PG_STATUS_S		0
1964 #define ICE_AQC_CEE_PG_STATUS_M		(0x7 << ICE_AQC_CEE_PG_STATUS_S)
1965 #define ICE_AQC_CEE_PFC_STATUS_S	3
1966 #define ICE_AQC_CEE_PFC_STATUS_M	(0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1967 #define ICE_AQC_CEE_FCOE_STATUS_S	8
1968 #define ICE_AQC_CEE_FCOE_STATUS_M	(0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1969 #define ICE_AQC_CEE_ISCSI_STATUS_S	11
1970 #define ICE_AQC_CEE_ISCSI_STATUS_M	(0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1971 #define ICE_AQC_CEE_FIP_STATUS_S	16
1972 #define ICE_AQC_CEE_FIP_STATUS_M	(0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1973 	u8 reserved[12];
1974 };
1975 
1976 /* Set Local LLDP MIB (indirect 0x0A08)
1977  * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1978  */
1979 struct ice_aqc_lldp_set_local_mib {
1980 	u8 type;
1981 #define SET_LOCAL_MIB_TYPE_DCBX_M		BIT(0)
1982 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB		0
1983 #define SET_LOCAL_MIB_TYPE_CEE_M		BIT(1)
1984 #define SET_LOCAL_MIB_TYPE_CEE_WILLING		0
1985 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING	SET_LOCAL_MIB_TYPE_CEE_M
1986 	u8 reserved0;
1987 	__le16 length;
1988 	u8 reserved1[4];
1989 	__le32 addr_high;
1990 	__le32 addr_low;
1991 };
1992 
1993 /* Stop/Start LLDP Agent (direct 0x0A09)
1994  * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1995  * The same structure is used for the response, with the command field
1996  * being used as the status field.
1997  */
1998 struct ice_aqc_lldp_stop_start_specific_agent {
1999 	u8 command;
2000 #define ICE_AQC_START_STOP_AGENT_M		BIT(0)
2001 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX	0
2002 #define ICE_AQC_START_STOP_AGENT_START_DCBX	ICE_AQC_START_STOP_AGENT_M
2003 	u8 reserved[15];
2004 };
2005 
2006 /* LLDP Filter Control (direct 0x0A0A) */
2007 struct ice_aqc_lldp_filter_ctrl {
2008 	u8 cmd_flags;
2009 #define ICE_AQC_LLDP_FILTER_ACTION_ADD		0x0
2010 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE	0x1
2011 	u8 reserved1;
2012 	__le16 vsi_num;
2013 	u8 reserved2[12];
2014 };
2015 
2016 #define ICE_AQC_RSS_VSI_VALID BIT(15)
2017 
2018 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
2019 struct ice_aqc_get_set_rss_key {
2020 	__le16 vsi_id;
2021 	u8 reserved[6];
2022 	__le32 addr_high;
2023 	__le32 addr_low;
2024 };
2025 
2026 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE	0x28
2027 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE	0xC
2028 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
2029 				(ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
2030 				 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
2031 
2032 struct ice_aqc_get_set_rss_keys {
2033 	u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
2034 	u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
2035 };
2036 
2037 enum ice_lut_type {
2038 	ICE_LUT_VSI = 0,
2039 	ICE_LUT_PF = 1,
2040 	ICE_LUT_GLOBAL = 2,
2041 };
2042 
2043 enum ice_lut_size {
2044 	ICE_LUT_VSI_SIZE = 64,
2045 	ICE_LUT_GLOBAL_SIZE = 512,
2046 	ICE_LUT_PF_SIZE = 2048,
2047 };
2048 
2049 /* enum ice_aqc_lut_flags combines constants used to fill
2050  * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID,
2051  * LUT size and LUT type, last of which does not need neither shift nor mask.
2052  */
2053 enum ice_aqc_lut_flags {
2054 	ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */
2055 	ICE_AQC_LUT_SIZE_512 = BIT(2),
2056 	ICE_AQC_LUT_SIZE_2K = BIT(3),
2057 
2058 	ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4),
2059 };
2060 
2061 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
2062 struct ice_aqc_get_set_rss_lut {
2063 	__le16 vsi_id;
2064 	__le16 flags;
2065 	__le32 reserved;
2066 	__le32 addr_high;
2067 	__le32 addr_low;
2068 };
2069 
2070 /* Sideband Control Interface Commands */
2071 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */
2072 struct ice_aqc_neigh_dev_req {
2073 	__le16 sb_data_len;
2074 	u8 reserved[6];
2075 	__le32 addr_high;
2076 	__le32 addr_low;
2077 };
2078 
2079 /* Add Tx LAN Queues (indirect 0x0C30) */
2080 struct ice_aqc_add_txqs {
2081 	u8 num_qgrps;
2082 	u8 reserved[3];
2083 	__le32 reserved1;
2084 	__le32 addr_high;
2085 	__le32 addr_low;
2086 };
2087 
2088 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2089  * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2090  */
2091 struct ice_aqc_add_txqs_perq {
2092 	__le16 txq_id;
2093 	u8 rsvd[2];
2094 	__le32 q_teid;
2095 	ice_txq_ctx_buf_t txq_ctx;
2096 	u8 rsvd2[2];
2097 	struct ice_aqc_txsched_elem info;
2098 } __packed;
2099 
2100 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2101  * is an array of the following structs. Please note that the length of
2102  * each struct ice_aqc_add_tx_qgrp is variable due
2103  * to the variable number of queues in each group!
2104  */
2105 struct ice_aqc_add_tx_qgrp {
2106 	__le32 parent_teid;
2107 	u8 num_txqs;
2108 	u8 rsvd[3];
2109 	struct ice_aqc_add_txqs_perq txqs[];
2110 };
2111 
2112 /* Disable Tx LAN Queues (indirect 0x0C31) */
2113 struct ice_aqc_dis_txqs {
2114 	u8 cmd_type;
2115 #define ICE_AQC_Q_DIS_CMD_S		0
2116 #define ICE_AQC_Q_DIS_CMD_M		(0x3 << ICE_AQC_Q_DIS_CMD_S)
2117 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET	(0 << ICE_AQC_Q_DIS_CMD_S)
2118 #define ICE_AQC_Q_DIS_CMD_VM_RESET	BIT(ICE_AQC_Q_DIS_CMD_S)
2119 #define ICE_AQC_Q_DIS_CMD_VF_RESET	(2 << ICE_AQC_Q_DIS_CMD_S)
2120 #define ICE_AQC_Q_DIS_CMD_PF_RESET	(3 << ICE_AQC_Q_DIS_CMD_S)
2121 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL	BIT(2)
2122 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE	BIT(3)
2123 	u8 num_entries;
2124 	__le16 vmvf_and_timeout;
2125 #define ICE_AQC_Q_DIS_VMVF_NUM_S	0
2126 #define ICE_AQC_Q_DIS_VMVF_NUM_M	(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2127 #define ICE_AQC_Q_DIS_TIMEOUT_S		10
2128 #define ICE_AQC_Q_DIS_TIMEOUT_M		(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2129 	__le32 blocked_cgds;
2130 	__le32 addr_high;
2131 	__le32 addr_low;
2132 };
2133 
2134 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2135  * contains the following structures, arrayed one after the
2136  * other.
2137  * Note: Since the q_id is 16 bits wide, if the
2138  * number of queues is even, then 2 bytes of alignment MUST be
2139  * added before the start of the next group, to allow correct
2140  * alignment of the parent_teid field.
2141  */
2142 struct ice_aqc_dis_txq_item {
2143 	__le32 parent_teid;
2144 	u8 num_qs;
2145 	u8 rsvd;
2146 	/* The length of the q_id array varies according to num_qs */
2147 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S		15
2148 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q	\
2149 			(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2150 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET	\
2151 			(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2152 	__le16 q_id[];
2153 } __packed;
2154 
2155 /* Move/Reconfigure Tx queue (indirect 0x0C32) */
2156 struct ice_aqc_cfg_txqs {
2157 	u8 cmd_type;
2158 #define ICE_AQC_Q_CFG_MOVE_NODE		0x1
2159 #define ICE_AQC_Q_CFG_TC_CHNG		0x2
2160 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG	0x3
2161 #define ICE_AQC_Q_CFG_SUBSEQ_CALL	BIT(2)
2162 #define ICE_AQC_Q_CFG_FLUSH		BIT(3)
2163 	u8 num_qs;
2164 	u8 port_num_chng;
2165 #define ICE_AQC_Q_CFG_SRC_PRT_M		0x7
2166 #define ICE_AQC_Q_CFG_DST_PRT_S		3
2167 #define ICE_AQC_Q_CFG_DST_PRT_M		(0x7 << ICE_AQC_Q_CFG_DST_PRT_S)
2168 	u8 time_out;
2169 #define ICE_AQC_Q_CFG_TIMEOUT_S		2
2170 #define ICE_AQC_Q_CFG_TIMEOUT_M		(0x1F << ICE_AQC_Q_CFG_TIMEOUT_S)
2171 	__le32 blocked_cgds;
2172 	__le32 addr_high;
2173 	__le32 addr_low;
2174 };
2175 
2176 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */
2177 struct ice_aqc_cfg_txq_perq {
2178 	__le16 q_handle;
2179 	u8 tc;
2180 	u8 rsvd;
2181 	__le32 q_teid;
2182 };
2183 
2184 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */
2185 struct ice_aqc_cfg_txqs_buf {
2186 	__le32 src_parent_teid;
2187 	__le32 dst_parent_teid;
2188 	struct ice_aqc_cfg_txq_perq queue_info[];
2189 };
2190 
2191 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
2192 struct ice_aqc_add_rdma_qset {
2193 	u8 num_qset_grps;
2194 	u8 reserved[7];
2195 	__le32 addr_high;
2196 	__le32 addr_low;
2197 };
2198 
2199 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set
2200  * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
2201  */
2202 struct ice_aqc_add_tx_rdma_qset_entry {
2203 	__le16 tx_qset_id;
2204 	u8 rsvd[2];
2205 	__le32 qset_teid;
2206 	struct ice_aqc_txsched_elem info;
2207 };
2208 
2209 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
2210  * is an array of the following structs. Please note that the length of
2211  * each struct ice_aqc_add_rdma_qset is variable due to the variable
2212  * number of queues in each group!
2213  */
2214 struct ice_aqc_add_rdma_qset_data {
2215 	__le32 parent_teid;
2216 	__le16 num_qsets;
2217 	u8 rsvd[2];
2218 	struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
2219 };
2220 
2221 /* Download Package (indirect 0x0C40) */
2222 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
2223 struct ice_aqc_download_pkg {
2224 	u8 flags;
2225 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF	0x01
2226 	u8 reserved[3];
2227 	__le32 reserved1;
2228 	__le32 addr_high;
2229 	__le32 addr_low;
2230 };
2231 
2232 struct ice_aqc_download_pkg_resp {
2233 	__le32 error_offset;
2234 	__le32 error_info;
2235 	__le32 addr_high;
2236 	__le32 addr_low;
2237 };
2238 
2239 /* Get Package Info List (indirect 0x0C43) */
2240 struct ice_aqc_get_pkg_info_list {
2241 	__le32 reserved1;
2242 	__le32 reserved2;
2243 	__le32 addr_high;
2244 	__le32 addr_low;
2245 };
2246 
2247 /* Version format for packages */
2248 struct ice_pkg_ver {
2249 	u8 major;
2250 	u8 minor;
2251 	u8 update;
2252 	u8 draft;
2253 };
2254 
2255 #define ICE_PKG_NAME_SIZE	32
2256 #define ICE_SEG_ID_SIZE		28
2257 #define ICE_SEG_NAME_SIZE	28
2258 
2259 struct ice_aqc_get_pkg_info {
2260 	struct ice_pkg_ver ver;
2261 	char name[ICE_SEG_NAME_SIZE];
2262 	__le32 track_id;
2263 	u8 is_in_nvm;
2264 	u8 is_active;
2265 	u8 is_active_at_boot;
2266 	u8 is_modified;
2267 };
2268 
2269 /* Get Package Info List response buffer format (0x0C43) */
2270 struct ice_aqc_get_pkg_info_resp {
2271 	__le32 count;
2272 	struct ice_aqc_get_pkg_info pkg_info[];
2273 };
2274 
2275 #define ICE_AQC_GET_CGU_MAX_PHASE_ADJ	GENMASK(30, 0)
2276 
2277 /* Get CGU abilities command response data structure (indirect 0x0C61) */
2278 struct ice_aqc_get_cgu_abilities {
2279 	u8 num_inputs;
2280 	u8 num_outputs;
2281 	u8 pps_dpll_idx;
2282 	u8 eec_dpll_idx;
2283 	__le32 max_in_freq;
2284 	__le32 max_in_phase_adj;
2285 	__le32 max_out_freq;
2286 	__le32 max_out_phase_adj;
2287 	u8 cgu_part_num;
2288 	u8 rsvd[3];
2289 };
2290 
2291 /* Set CGU input config (direct 0x0C62) */
2292 struct ice_aqc_set_cgu_input_config {
2293 	u8 input_idx;
2294 	u8 flags1;
2295 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ		BIT(6)
2296 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY	BIT(7)
2297 	u8 flags2;
2298 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN		BIT(5)
2299 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN		BIT(6)
2300 	u8 rsvd;
2301 	__le32 freq;
2302 	__le32 phase_delay;
2303 	u8 rsvd2[2];
2304 	__le16 node_handle;
2305 };
2306 
2307 /* Get CGU input config response descriptor structure (direct 0x0C63) */
2308 struct ice_aqc_get_cgu_input_config {
2309 	u8 input_idx;
2310 	u8 status;
2311 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS		BIT(0)
2312 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL		BIT(1)
2313 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL		BIT(2)
2314 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL		BIT(3)
2315 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL		BIT(4)
2316 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL	BIT(6)
2317 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP		BIT(7)
2318 	u8 type;
2319 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY		BIT(0)
2320 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS			BIT(4)
2321 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL		BIT(5)
2322 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY			BIT(6)
2323 	u8 flags1;
2324 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP	BIT(0)
2325 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP		BIT(2)
2326 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP		BIT(3)
2327 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ		BIT(7)
2328 	__le32 freq;
2329 	__le32 phase_delay;
2330 	u8 flags2;
2331 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN		BIT(5)
2332 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN		BIT(6)
2333 	u8 rsvd[1];
2334 	__le16 node_handle;
2335 };
2336 
2337 /* Set CGU output config (direct 0x0C64) */
2338 struct ice_aqc_set_cgu_output_config {
2339 	u8 output_idx;
2340 	u8 flags;
2341 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN		BIT(0)
2342 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN	BIT(1)
2343 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ     BIT(2)
2344 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE    BIT(3)
2345 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL  BIT(4)
2346 	u8 src_sel;
2347 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL    ICE_M(0x1F, 0)
2348 	u8 rsvd;
2349 	__le32 freq;
2350 	__le32 phase_delay;
2351 	u8 rsvd2[2];
2352 	__le16 node_handle;
2353 };
2354 
2355 /* Get CGU output config (direct 0x0C65) */
2356 struct ice_aqc_get_cgu_output_config {
2357 	u8 output_idx;
2358 	u8 flags;
2359 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN		BIT(0)
2360 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN	BIT(1)
2361 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY	BIT(2)
2362 	u8 src_sel;
2363 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT	0
2364 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \
2365 	ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)
2366 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT		5
2367 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \
2368 	ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
2369 	u8 rsvd;
2370 	__le32 freq;
2371 	__le32 src_freq;
2372 	u8 rsvd2[2];
2373 	__le16 node_handle;
2374 };
2375 
2376 /* Get CGU DPLL status (direct 0x0C66) */
2377 struct ice_aqc_get_cgu_dpll_status {
2378 	u8 dpll_num;
2379 	u8 ref_state;
2380 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS		BIT(0)
2381 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM		BIT(1)
2382 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM		BIT(2)
2383 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST		BIT(3)
2384 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM		BIT(4)
2385 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN	BIT(5)
2386 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC	BIT(6)
2387 	u8 dpll_state;
2388 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK		BIT(0)
2389 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO		BIT(1)
2390 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY	BIT(2)
2391 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT		BIT(5)
2392 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT	BIT(7)
2393 	u8 config;
2394 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL		ICE_M(0x1F, 0)
2395 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT		5
2396 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE		\
2397 	ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2398 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN	0
2399 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC	\
2400 	ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2401 	__le32 phase_offset_h;
2402 	__le32 phase_offset_l;
2403 	u8 eec_mode;
2404 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1		0xA
2405 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2		0xB
2406 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN	0xF
2407 	u8 rsvd[1];
2408 	__le16 node_handle;
2409 };
2410 
2411 /* Set CGU DPLL config (direct 0x0C67) */
2412 struct ice_aqc_set_cgu_dpll_config {
2413 	u8 dpll_num;
2414 	u8 ref_state;
2415 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS		BIT(0)
2416 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM		BIT(1)
2417 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM		BIT(2)
2418 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST		BIT(3)
2419 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM		BIT(4)
2420 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN	BIT(5)
2421 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC	BIT(6)
2422 	u8 rsvd;
2423 	u8 config;
2424 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL		ICE_M(0x1F, 0)
2425 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT		5
2426 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE		\
2427 	ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
2428 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN	0
2429 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC	\
2430 	ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
2431 	u8 rsvd2[8];
2432 	u8 eec_mode;
2433 	u8 rsvd3[1];
2434 	__le16 node_handle;
2435 };
2436 
2437 /* Set CGU reference priority (direct 0x0C68) */
2438 struct ice_aqc_set_cgu_ref_prio {
2439 	u8 dpll_num;
2440 	u8 ref_idx;
2441 	u8 ref_priority;
2442 	u8 rsvd[11];
2443 	__le16 node_handle;
2444 };
2445 
2446 /* Get CGU reference priority (direct 0x0C69) */
2447 struct ice_aqc_get_cgu_ref_prio {
2448 	u8 dpll_num;
2449 	u8 ref_idx;
2450 	u8 ref_priority; /* Valid only in response */
2451 	u8 rsvd[13];
2452 };
2453 
2454 /* Get CGU info (direct 0x0C6A) */
2455 struct ice_aqc_get_cgu_info {
2456 	__le32 cgu_id;
2457 	__le32 cgu_cfg_ver;
2458 	__le32 cgu_fw_ver;
2459 	u8 node_part_num;
2460 	u8 dev_rev;
2461 	__le16 node_handle;
2462 };
2463 
2464 /* Driver Shared Parameters (direct, 0x0C90) */
2465 struct ice_aqc_driver_shared_params {
2466 	u8 set_or_get_op;
2467 #define ICE_AQC_DRIVER_PARAM_OP_MASK		BIT(0)
2468 #define ICE_AQC_DRIVER_PARAM_SET		0
2469 #define ICE_AQC_DRIVER_PARAM_GET		1
2470 	u8 param_indx;
2471 #define ICE_AQC_DRIVER_PARAM_MAX_IDX		15
2472 	u8 rsvd[2];
2473 	__le32 param_val;
2474 	__le32 addr_high;
2475 	__le32 addr_low;
2476 };
2477 
2478 /* Lan Queue Overflow Event (direct, 0x1001) */
2479 struct ice_aqc_event_lan_overflow {
2480 	__le32 prtdcb_ruptq;
2481 	__le32 qtx_ctl;
2482 	u8 reserved[8];
2483 };
2484 
2485 enum ice_aqc_fw_logging_mod {
2486 	ICE_AQC_FW_LOG_ID_GENERAL = 0,
2487 	ICE_AQC_FW_LOG_ID_CTRL,
2488 	ICE_AQC_FW_LOG_ID_LINK,
2489 	ICE_AQC_FW_LOG_ID_LINK_TOPO,
2490 	ICE_AQC_FW_LOG_ID_DNL,
2491 	ICE_AQC_FW_LOG_ID_I2C,
2492 	ICE_AQC_FW_LOG_ID_SDP,
2493 	ICE_AQC_FW_LOG_ID_MDIO,
2494 	ICE_AQC_FW_LOG_ID_ADMINQ,
2495 	ICE_AQC_FW_LOG_ID_HDMA,
2496 	ICE_AQC_FW_LOG_ID_LLDP,
2497 	ICE_AQC_FW_LOG_ID_DCBX,
2498 	ICE_AQC_FW_LOG_ID_DCB,
2499 	ICE_AQC_FW_LOG_ID_XLR,
2500 	ICE_AQC_FW_LOG_ID_NVM,
2501 	ICE_AQC_FW_LOG_ID_AUTH,
2502 	ICE_AQC_FW_LOG_ID_VPD,
2503 	ICE_AQC_FW_LOG_ID_IOSF,
2504 	ICE_AQC_FW_LOG_ID_PARSER,
2505 	ICE_AQC_FW_LOG_ID_SW,
2506 	ICE_AQC_FW_LOG_ID_SCHEDULER,
2507 	ICE_AQC_FW_LOG_ID_TXQ,
2508 	ICE_AQC_FW_LOG_ID_RSVD,
2509 	ICE_AQC_FW_LOG_ID_POST,
2510 	ICE_AQC_FW_LOG_ID_WATCHDOG,
2511 	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2512 	ICE_AQC_FW_LOG_ID_MNG,
2513 	ICE_AQC_FW_LOG_ID_SYNCE,
2514 	ICE_AQC_FW_LOG_ID_HEALTH,
2515 	ICE_AQC_FW_LOG_ID_TSDRV,
2516 	ICE_AQC_FW_LOG_ID_PFREG,
2517 	ICE_AQC_FW_LOG_ID_MDLVER,
2518 	ICE_AQC_FW_LOG_ID_MAX,
2519 };
2520 
2521 enum ice_aqc_health_status_mask {
2522 	ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK = BIT(0),
2523 	ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK      = BIT(1),
2524 	ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK      = BIT(2),
2525 };
2526 
2527 /* Set Health Status (direct 0xFF20) */
2528 struct ice_aqc_set_health_status_cfg {
2529 	u8 event_source;
2530 	u8 reserved[15];
2531 };
2532 
2533 enum ice_aqc_health_status {
2534 	ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT		= 0x101,
2535 	ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE			= 0x102,
2536 	ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL			= 0x103,
2537 	ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM			= 0x104,
2538 	ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT			= 0x105,
2539 	ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT		= 0x106,
2540 	ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED		= 0x107,
2541 	ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT		= 0x108,
2542 	ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE	= 0x109,
2543 	ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG		= 0x10B,
2544 	ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS			= 0x10C,
2545 	ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE		= 0x10D,
2546 	ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED	= 0x10F,
2547 	ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT		= 0x110,
2548 	ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED	= 0x111,
2549 	ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO			= 0x112,
2550 	ICE_AQC_HEALTH_STATUS_ERR_NETLIST			= 0x113,
2551 	ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT			= 0x114,
2552 	ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS		= 0x115,
2553 	ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME			= 0x116,
2554 	ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT			= 0x117,
2555 	ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG			= 0x120,
2556 	ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD			= 0x121,
2557 	ICE_AQC_HEALTH_STATUS_INFO_RECOVERY			= 0x500,
2558 	ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS			= 0x501,
2559 	ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH			= 0x502,
2560 	ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH			= 0x503,
2561 	ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH			= 0x504,
2562 	ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT			= 0x505,
2563 	ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT			= 0x506,
2564 	ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION		= 0x507,
2565 	ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION		= 0x508,
2566 	ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB			= 0x509,
2567 	ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT			= 0x50A,
2568 	ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET			= 0x50B,
2569 	ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL			= 0x50C,
2570 	ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL		= 0x50D,
2571 	ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP			= 0x1000,
2572 	ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL			= 0x1001,
2573 	ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ			= 0x1002,
2574 };
2575 
2576 /* Get Health Status (indirect 0xFF22) */
2577 struct ice_aqc_get_health_status {
2578 	__le16 health_status_count;
2579 	u8 reserved[6];
2580 	__le32 addr_high;
2581 	__le32 addr_low;
2582 };
2583 
2584 enum ice_aqc_health_status_scope {
2585 	ICE_AQC_HEALTH_STATUS_PF	= 0x1,
2586 	ICE_AQC_HEALTH_STATUS_PORT	= 0x2,
2587 	ICE_AQC_HEALTH_STATUS_GLOBAL	= 0x3,
2588 };
2589 
2590 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA	0xDEADBEEF
2591 
2592 /* Get Health Status event buffer entry (0xFF22),
2593  * repeated per reported health status.
2594  */
2595 struct ice_aqc_health_status_elem {
2596 	__le16 health_status_code;
2597 	__le16 event_source;
2598 	__le32 internal_data1;
2599 	__le32 internal_data2;
2600 };
2601 
2602 /* Set FW Logging configuration (indirect 0xFF30)
2603  * Register for FW Logging (indirect 0xFF31)
2604  * Query FW Logging (indirect 0xFF32)
2605  * FW Log Event (indirect 0xFF33)
2606  */
2607 struct ice_aqc_fw_log {
2608 	u8 cmd_flags;
2609 #define ICE_AQC_FW_LOG_CONF_UART_EN	BIT(0)
2610 #define ICE_AQC_FW_LOG_CONF_AQ_EN	BIT(1)
2611 #define ICE_AQC_FW_LOG_QUERY_REGISTERED	BIT(2)
2612 #define ICE_AQC_FW_LOG_CONF_SET_VALID	BIT(3)
2613 #define ICE_AQC_FW_LOG_AQ_REGISTER	BIT(0)
2614 #define ICE_AQC_FW_LOG_AQ_QUERY		BIT(2)
2615 
2616 	u8 rsp_flag;
2617 	__le16 fw_rt_msb;
2618 	union {
2619 		struct {
2620 			__le32 fw_rt_lsb;
2621 		} sync;
2622 		struct {
2623 			__le16 log_resolution;
2624 #define ICE_AQC_FW_LOG_MIN_RESOLUTION		(1)
2625 #define ICE_AQC_FW_LOG_MAX_RESOLUTION		(128)
2626 
2627 			__le16 mdl_cnt;
2628 		} cfg;
2629 	} ops;
2630 	__le32 addr_high;
2631 	__le32 addr_low;
2632 };
2633 
2634 /* Response Buffer for:
2635  *    Set Firmware Logging Configuration (0xFF30)
2636  *    Query FW Logging (0xFF32)
2637  */
2638 struct ice_aqc_fw_log_cfg_resp {
2639 	__le16 module_identifier;
2640 	u8 log_level;
2641 	u8 rsvd0;
2642 };
2643 
2644 /**
2645  * struct ice_aq_desc - Admin Queue (AQ) descriptor
2646  * @flags: ICE_AQ_FLAG_* flags
2647  * @opcode: AQ command opcode
2648  * @datalen: length in bytes of indirect/external data buffer
2649  * @retval: return value from firmware
2650  * @cookie_high: opaque data high-half
2651  * @cookie_low: opaque data low-half
2652  * @params: command-specific parameters
2653  *
2654  * Descriptor format for commands the driver posts on the Admin Transmit Queue
2655  * (ATQ). The firmware writes back onto the command descriptor and returns
2656  * the result of the command. Asynchronous events that are not an immediate
2657  * result of the command are written to the Admin Receive Queue (ARQ) using
2658  * the same descriptor format. Descriptors are in little-endian notation with
2659  * 32-bit words.
2660  */
2661 struct ice_aq_desc {
2662 	__le16 flags;
2663 	__le16 opcode;
2664 	__le16 datalen;
2665 	__le16 retval;
2666 	__le32 cookie_high;
2667 	__le32 cookie_low;
2668 	union {
2669 		u8 raw[16];
2670 		struct ice_aqc_generic generic;
2671 		struct ice_aqc_get_ver get_ver;
2672 		struct ice_aqc_driver_ver driver_ver;
2673 		struct ice_aqc_q_shutdown q_shutdown;
2674 		struct ice_aqc_req_res res_owner;
2675 		struct ice_aqc_manage_mac_read mac_read;
2676 		struct ice_aqc_manage_mac_write mac_write;
2677 		struct ice_aqc_clear_pxe clear_pxe;
2678 		struct ice_aqc_list_caps get_cap;
2679 		struct ice_aqc_get_phy_caps get_phy;
2680 		struct ice_aqc_set_phy_cfg set_phy;
2681 		struct ice_aqc_restart_an restart_an;
2682 		struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out;
2683 		struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out;
2684 		struct ice_aqc_get_sensor_reading get_sensor_reading;
2685 		struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;
2686 		struct ice_aqc_gpio read_write_gpio;
2687 		struct ice_aqc_sff_eeprom read_write_sff_param;
2688 		struct ice_aqc_set_port_id_led set_port_id_led;
2689 		struct ice_aqc_get_port_options get_port_options;
2690 		struct ice_aqc_set_port_option set_port_option;
2691 		struct ice_aqc_get_sw_cfg get_sw_conf;
2692 		struct ice_aqc_set_port_params set_port_params;
2693 		struct ice_aqc_sw_rules sw_rules;
2694 		struct ice_aqc_add_get_recipe add_get_recipe;
2695 		struct ice_aqc_recipe_to_profile recipe_to_profile;
2696 		struct ice_aqc_get_topo get_topo;
2697 		struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2698 		struct ice_aqc_query_txsched_res query_sched_res;
2699 		struct ice_aqc_query_port_ets port_ets;
2700 		struct ice_aqc_rl_profile rl_profile;
2701 		struct ice_aqc_nvm nvm;
2702 		struct ice_aqc_nvm_checksum nvm_checksum;
2703 		struct ice_aqc_nvm_pkg_data pkg_data;
2704 		struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
2705 		struct ice_aqc_pf_vf_msg virt;
2706 		struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2707 		struct ice_aqc_lldp_get_mib lldp_get_mib;
2708 		struct ice_aqc_lldp_set_mib_change lldp_set_event;
2709 		struct ice_aqc_lldp_stop lldp_stop;
2710 		struct ice_aqc_lldp_start lldp_start;
2711 		struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2712 		struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2713 		struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2714 		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2715 		struct ice_aqc_get_set_rss_key get_set_rss_key;
2716 		struct ice_aqc_neigh_dev_req neigh_dev;
2717 		struct ice_aqc_add_txqs add_txqs;
2718 		struct ice_aqc_dis_txqs dis_txqs;
2719 		struct ice_aqc_cfg_txqs cfg_txqs;
2720 		struct ice_aqc_add_rdma_qset add_rdma_qset;
2721 		struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2722 		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2723 		struct ice_aqc_download_pkg download_pkg;
2724 		struct ice_aqc_set_cgu_input_config set_cgu_input_config;
2725 		struct ice_aqc_get_cgu_input_config get_cgu_input_config;
2726 		struct ice_aqc_set_cgu_output_config set_cgu_output_config;
2727 		struct ice_aqc_get_cgu_output_config get_cgu_output_config;
2728 		struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status;
2729 		struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config;
2730 		struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio;
2731 		struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio;
2732 		struct ice_aqc_get_cgu_info get_cgu_info;
2733 		struct ice_aqc_driver_shared_params drv_shared_params;
2734 		struct ice_aqc_fw_log fw_log;
2735 		struct ice_aqc_set_mac_lb set_mac_lb;
2736 		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2737 		struct ice_aqc_set_mac_cfg set_mac_cfg;
2738 		struct ice_aqc_set_event_mask set_event_mask;
2739 		struct ice_aqc_get_link_status get_link_status;
2740 		struct ice_aqc_event_lan_overflow lan_overflow;
2741 		struct ice_aqc_get_link_topo get_link_topo;
2742 		struct ice_aqc_set_health_status_cfg set_health_status_cfg;
2743 		struct ice_aqc_get_health_status get_health_status;
2744 		struct ice_aqc_dnl_call_command dnl_call;
2745 		struct ice_aqc_i2c read_write_i2c;
2746 		struct ice_aqc_read_i2c_resp read_i2c_resp;
2747 		struct ice_aqc_get_set_tx_topo get_set_tx_topo;
2748 	} params;
2749 };
2750 
2751 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2752 #define ICE_AQ_LG_BUF	512
2753 
2754 #define ICE_AQ_FLAG_DD_S	0
2755 #define ICE_AQ_FLAG_CMP_S	1
2756 #define ICE_AQ_FLAG_ERR_S	2
2757 #define ICE_AQ_FLAG_LB_S	9
2758 #define ICE_AQ_FLAG_RD_S	10
2759 #define ICE_AQ_FLAG_BUF_S	12
2760 #define ICE_AQ_FLAG_SI_S	13
2761 
2762 #define ICE_AQ_FLAG_DD		BIT(ICE_AQ_FLAG_DD_S)  /* 0x1    */
2763 #define ICE_AQ_FLAG_CMP		BIT(ICE_AQ_FLAG_CMP_S) /* 0x2    */
2764 #define ICE_AQ_FLAG_ERR		BIT(ICE_AQ_FLAG_ERR_S) /* 0x4    */
2765 #define ICE_AQ_FLAG_LB		BIT(ICE_AQ_FLAG_LB_S)  /* 0x200  */
2766 #define ICE_AQ_FLAG_RD		BIT(ICE_AQ_FLAG_RD_S)  /* 0x400  */
2767 #define ICE_AQ_FLAG_BUF		BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2768 #define ICE_AQ_FLAG_SI		BIT(ICE_AQ_FLAG_SI_S)  /* 0x2000 */
2769 
2770 /* error codes */
2771 enum ice_aq_err {
2772 	ICE_AQ_RC_OK		= 0,  /* Success */
2773 	ICE_AQ_RC_EPERM		= 1,  /* Operation not permitted */
2774 	ICE_AQ_RC_ENOENT	= 2,  /* No such element */
2775 	ICE_AQ_RC_ENOMEM	= 9,  /* Out of memory */
2776 	ICE_AQ_RC_EBUSY		= 12, /* Device or resource busy */
2777 	ICE_AQ_RC_EEXIST	= 13, /* Object already exists */
2778 	ICE_AQ_RC_EINVAL	= 14, /* Invalid argument */
2779 	ICE_AQ_RC_ENOSPC	= 16, /* No space left or allocation failure */
2780 	ICE_AQ_RC_ENOSYS	= 17, /* Function not implemented */
2781 	ICE_AQ_RC_EMODE		= 21, /* Op not allowed in current dev mode */
2782 	ICE_AQ_RC_ENOSEC	= 24, /* Missing security manifest */
2783 	ICE_AQ_RC_EBADSIG	= 25, /* Bad RSA signature */
2784 	ICE_AQ_RC_ESVN		= 26, /* SVN number prohibits this package */
2785 	ICE_AQ_RC_EBADMAN	= 27, /* Manifest hash mismatch */
2786 	ICE_AQ_RC_EBADBUF	= 28, /* Buffer hash mismatches manifest */
2787 };
2788 
2789 /* Admin Queue command opcodes */
2790 enum ice_adminq_opc {
2791 	/* AQ commands */
2792 	ice_aqc_opc_get_ver				= 0x0001,
2793 	ice_aqc_opc_driver_ver				= 0x0002,
2794 	ice_aqc_opc_q_shutdown				= 0x0003,
2795 
2796 	/* resource ownership */
2797 	ice_aqc_opc_req_res				= 0x0008,
2798 	ice_aqc_opc_release_res				= 0x0009,
2799 
2800 	/* device/function capabilities */
2801 	ice_aqc_opc_list_func_caps			= 0x000A,
2802 	ice_aqc_opc_list_dev_caps			= 0x000B,
2803 
2804 	/* manage MAC address */
2805 	ice_aqc_opc_manage_mac_read			= 0x0107,
2806 	ice_aqc_opc_manage_mac_write			= 0x0108,
2807 
2808 	/* PXE */
2809 	ice_aqc_opc_clear_pxe_mode			= 0x0110,
2810 
2811 	/* internal switch commands */
2812 	ice_aqc_opc_get_sw_cfg				= 0x0200,
2813 	ice_aqc_opc_set_port_params			= 0x0203,
2814 
2815 	/* Alloc/Free/Get Resources */
2816 	ice_aqc_opc_alloc_res				= 0x0208,
2817 	ice_aqc_opc_free_res				= 0x0209,
2818 	ice_aqc_opc_share_res				= 0x020B,
2819 	ice_aqc_opc_set_vlan_mode_parameters		= 0x020C,
2820 	ice_aqc_opc_get_vlan_mode_parameters		= 0x020D,
2821 
2822 	/* VSI commands */
2823 	ice_aqc_opc_add_vsi				= 0x0210,
2824 	ice_aqc_opc_update_vsi				= 0x0211,
2825 	ice_aqc_opc_free_vsi				= 0x0213,
2826 
2827 	/* recipe commands */
2828 	ice_aqc_opc_add_recipe				= 0x0290,
2829 	ice_aqc_opc_recipe_to_profile			= 0x0291,
2830 	ice_aqc_opc_get_recipe				= 0x0292,
2831 	ice_aqc_opc_get_recipe_to_profile		= 0x0293,
2832 
2833 	/* switch rules population commands */
2834 	ice_aqc_opc_add_sw_rules			= 0x02A0,
2835 	ice_aqc_opc_update_sw_rules			= 0x02A1,
2836 	ice_aqc_opc_remove_sw_rules			= 0x02A2,
2837 
2838 	ice_aqc_opc_clear_pf_cfg			= 0x02A4,
2839 
2840 	/* DCB commands */
2841 	ice_aqc_opc_query_pfc_mode			= 0x0302,
2842 	ice_aqc_opc_set_pfc_mode			= 0x0303,
2843 
2844 	/* transmit scheduler commands */
2845 	ice_aqc_opc_get_dflt_topo			= 0x0400,
2846 	ice_aqc_opc_add_sched_elems			= 0x0401,
2847 	ice_aqc_opc_cfg_sched_elems			= 0x0403,
2848 	ice_aqc_opc_get_sched_elems			= 0x0404,
2849 	ice_aqc_opc_move_sched_elems			= 0x0408,
2850 	ice_aqc_opc_suspend_sched_elems			= 0x0409,
2851 	ice_aqc_opc_resume_sched_elems			= 0x040A,
2852 	ice_aqc_opc_query_port_ets			= 0x040E,
2853 	ice_aqc_opc_delete_sched_elems			= 0x040F,
2854 	ice_aqc_opc_add_rl_profiles			= 0x0410,
2855 	ice_aqc_opc_query_sched_res			= 0x0412,
2856 	ice_aqc_opc_remove_rl_profiles			= 0x0415,
2857 
2858 	/* tx topology commands */
2859 	ice_aqc_opc_set_tx_topo				= 0x0417,
2860 	ice_aqc_opc_get_tx_topo				= 0x0418,
2861 
2862 	/* PHY commands */
2863 	ice_aqc_opc_get_phy_caps			= 0x0600,
2864 	ice_aqc_opc_set_phy_cfg				= 0x0601,
2865 	ice_aqc_opc_set_mac_cfg				= 0x0603,
2866 	ice_aqc_opc_restart_an				= 0x0605,
2867 	ice_aqc_opc_get_link_status			= 0x0607,
2868 	ice_aqc_opc_set_event_mask			= 0x0613,
2869 	ice_aqc_opc_set_mac_lb				= 0x0620,
2870 	ice_aqc_opc_set_phy_rec_clk_out			= 0x0630,
2871 	ice_aqc_opc_get_phy_rec_clk_out			= 0x0631,
2872 	ice_aqc_opc_get_sensor_reading			= 0x0632,
2873 	ice_aqc_opc_dnl_call                            = 0x0682,
2874 	ice_aqc_opc_get_link_topo			= 0x06E0,
2875 	ice_aqc_opc_read_i2c				= 0x06E2,
2876 	ice_aqc_opc_write_i2c				= 0x06E3,
2877 	ice_aqc_opc_set_port_id_led			= 0x06E9,
2878 	ice_aqc_opc_get_port_options			= 0x06EA,
2879 	ice_aqc_opc_set_port_option			= 0x06EB,
2880 	ice_aqc_opc_set_gpio				= 0x06EC,
2881 	ice_aqc_opc_get_gpio				= 0x06ED,
2882 	ice_aqc_opc_sff_eeprom				= 0x06EE,
2883 
2884 	/* NVM commands */
2885 	ice_aqc_opc_nvm_read				= 0x0701,
2886 	ice_aqc_opc_nvm_erase				= 0x0702,
2887 	ice_aqc_opc_nvm_write				= 0x0703,
2888 	ice_aqc_opc_nvm_checksum			= 0x0706,
2889 	ice_aqc_opc_nvm_write_activate			= 0x0707,
2890 	ice_aqc_opc_nvm_update_empr			= 0x0709,
2891 	ice_aqc_opc_nvm_pkg_data			= 0x070A,
2892 	ice_aqc_opc_nvm_pass_component_tbl		= 0x070B,
2893 
2894 	/* PF/VF mailbox commands */
2895 	ice_mbx_opc_send_msg_to_pf			= 0x0801,
2896 	ice_mbx_opc_send_msg_to_vf			= 0x0802,
2897 	/* LLDP commands */
2898 	ice_aqc_opc_lldp_get_mib			= 0x0A00,
2899 	ice_aqc_opc_lldp_set_mib_change			= 0x0A01,
2900 	ice_aqc_opc_lldp_stop				= 0x0A05,
2901 	ice_aqc_opc_lldp_start				= 0x0A06,
2902 	ice_aqc_opc_get_cee_dcb_cfg			= 0x0A07,
2903 	ice_aqc_opc_lldp_set_local_mib			= 0x0A08,
2904 	ice_aqc_opc_lldp_stop_start_specific_agent	= 0x0A09,
2905 	ice_aqc_opc_lldp_filter_ctrl			= 0x0A0A,
2906 	ice_aqc_opc_lldp_execute_pending_mib		= 0x0A0B,
2907 
2908 	/* RSS commands */
2909 	ice_aqc_opc_set_rss_key				= 0x0B02,
2910 	ice_aqc_opc_set_rss_lut				= 0x0B03,
2911 	ice_aqc_opc_get_rss_key				= 0x0B04,
2912 	ice_aqc_opc_get_rss_lut				= 0x0B05,
2913 
2914 	/* Sideband Control Interface commands */
2915 	ice_aqc_opc_neighbour_device_request		= 0x0C00,
2916 
2917 	/* Tx queue handling commands/events */
2918 	ice_aqc_opc_add_txqs				= 0x0C30,
2919 	ice_aqc_opc_dis_txqs				= 0x0C31,
2920 	ice_aqc_opc_cfg_txqs				= 0x0C32,
2921 	ice_aqc_opc_add_rdma_qset			= 0x0C33,
2922 
2923 	/* package commands */
2924 	ice_aqc_opc_download_pkg			= 0x0C40,
2925 	ice_aqc_opc_upload_section			= 0x0C41,
2926 	ice_aqc_opc_update_pkg				= 0x0C42,
2927 	ice_aqc_opc_get_pkg_info_list			= 0x0C43,
2928 
2929 	/* 1588/SyncE commands/events */
2930 	ice_aqc_opc_get_cgu_abilities			= 0x0C61,
2931 	ice_aqc_opc_set_cgu_input_config		= 0x0C62,
2932 	ice_aqc_opc_get_cgu_input_config		= 0x0C63,
2933 	ice_aqc_opc_set_cgu_output_config		= 0x0C64,
2934 	ice_aqc_opc_get_cgu_output_config		= 0x0C65,
2935 	ice_aqc_opc_get_cgu_dpll_status			= 0x0C66,
2936 	ice_aqc_opc_set_cgu_dpll_config			= 0x0C67,
2937 	ice_aqc_opc_set_cgu_ref_prio			= 0x0C68,
2938 	ice_aqc_opc_get_cgu_ref_prio			= 0x0C69,
2939 	ice_aqc_opc_get_cgu_info			= 0x0C6A,
2940 
2941 	ice_aqc_opc_driver_shared_params		= 0x0C90,
2942 
2943 	/* Standalone Commands/Events */
2944 	ice_aqc_opc_event_lan_overflow			= 0x1001,
2945 
2946 	/* System Diagnostic commands */
2947 	ice_aqc_opc_set_health_status_cfg		= 0xFF20,
2948 	ice_aqc_opc_get_health_status			= 0xFF22,
2949 
2950 	/* FW Logging Commands */
2951 	ice_aqc_opc_fw_logs_config			= 0xFF30,
2952 	ice_aqc_opc_fw_logs_register			= 0xFF31,
2953 	ice_aqc_opc_fw_logs_query			= 0xFF32,
2954 	ice_aqc_opc_fw_logs_event			= 0xFF33,
2955 };
2956 
2957 #endif /* _ICE_ADMINQ_CMD_H_ */
2958