1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/sys_soc.h>
19 #include <linux/units.h>
20
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mc.h>
25 #include <media/v4l2-subdev.h>
26
27 /* LINK registers */
28 /* Module Configuration Register */
29 #define CSI2nMCG 0x0
30 #define CSI2nMCG_SDLN GENMASK(11, 8)
31
32 /* Module Control Register 0 */
33 #define CSI2nMCT0 0x10
34 #define CSI2nMCT0_VDLN(x) ((x) << 0)
35
36 /* Module Control Register 2 */
37 #define CSI2nMCT2 0x18
38 #define CSI2nMCT2_FRRSKW(x) ((x) << 16)
39 #define CSI2nMCT2_FRRCLK(x) ((x) << 0)
40
41 /* Module Control Register 3 */
42 #define CSI2nMCT3 0x1c
43 #define CSI2nMCT3_RXEN BIT(0)
44
45 /* Reset Control Register */
46 #define CSI2nRTCT 0x28
47 #define CSI2nRTCT_VSRST BIT(0)
48
49 /* Reset Status Register */
50 #define CSI2nRTST 0x2c
51 #define CSI2nRTST_VSRSTS BIT(0)
52
53 /* Receive Data Type Enable Low Register */
54 #define CSI2nDTEL 0x60
55
56 /* Receive Data Type Enable High Register */
57 #define CSI2nDTEH 0x64
58
59 /* DPHY registers */
60 /* D-PHY Control Register 0 */
61 #define CSIDPHYCTRL0 0x400
62 #define CSIDPHYCTRL0_EN_LDO1200 BIT(1)
63 #define CSIDPHYCTRL0_EN_BGR BIT(0)
64
65 /* D-PHY Timing Register 0 */
66 #define CSIDPHYTIM0 0x404
67 #define CSIDPHYTIM0_TCLK_MISS(x) ((x) << 24)
68 #define CSIDPHYTIM0_T_INIT(x) ((x) << 0)
69
70 /* D-PHY Timing Register 1 */
71 #define CSIDPHYTIM1 0x408
72 #define CSIDPHYTIM1_THS_PREPARE(x) ((x) << 24)
73 #define CSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16)
74 #define CSIDPHYTIM1_THS_SETTLE(x) ((x) << 8)
75 #define CSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0)
76
77 /* D-PHY Skew Adjustment Function */
78 #define CSIDPHYSKW0 0x460
79 #define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x) ((x) & 0x3)
80 #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) (((x) & 0x3) << 4)
81 #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) (((x) & 0x3) << 8)
82 #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) (((x) & 0x3) << 12)
83 #define CSIDPHYSKW0_DEFAULT_SKW (CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \
84 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \
85 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \
86 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1))
87
88 #define VSRSTS_RETRIES 20
89
90 #define RZG2L_CSI2_MIN_WIDTH 320
91 #define RZG2L_CSI2_MIN_HEIGHT 240
92 #define RZG2L_CSI2_MAX_WIDTH 2800
93 #define RZG2L_CSI2_MAX_HEIGHT 4095
94
95 #define RZG2L_CSI2_DEFAULT_WIDTH RZG2L_CSI2_MIN_WIDTH
96 #define RZG2L_CSI2_DEFAULT_HEIGHT RZG2L_CSI2_MIN_HEIGHT
97 #define RZG2L_CSI2_DEFAULT_FMT MEDIA_BUS_FMT_UYVY8_1X16
98
99 enum rzg2l_csi2_pads {
100 RZG2L_CSI2_SINK = 0,
101 RZG2L_CSI2_SOURCE,
102 NR_OF_RZG2L_CSI2_PAD,
103 };
104
105 struct rzg2l_csi2 {
106 struct device *dev;
107 void __iomem *base;
108 struct reset_control *presetn;
109 struct reset_control *cmn_rstb;
110 struct clk *sysclk;
111 struct clk *vclk;
112 unsigned long vclk_rate;
113
114 struct v4l2_subdev subdev;
115 struct media_pad pads[NR_OF_RZG2L_CSI2_PAD];
116
117 struct v4l2_async_notifier notifier;
118 struct v4l2_subdev *remote_source;
119
120 unsigned short lanes;
121 unsigned long hsfreq;
122
123 bool dphy_enabled;
124 };
125
126 struct rzg2l_csi2_timings {
127 u32 t_init;
128 u32 tclk_miss;
129 u32 tclk_settle;
130 u32 ths_settle;
131 u32 tclk_prepare;
132 u32 ths_prepare;
133 u32 max_hsfreq;
134 };
135
136 static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = {
137 {
138 .max_hsfreq = 80,
139 .t_init = 79801,
140 .tclk_miss = 4,
141 .tclk_settle = 23,
142 .ths_settle = 31,
143 .tclk_prepare = 10,
144 .ths_prepare = 19,
145 },
146 {
147 .max_hsfreq = 125,
148 .t_init = 79801,
149 .tclk_miss = 4,
150 .tclk_settle = 23,
151 .ths_settle = 28,
152 .tclk_prepare = 10,
153 .ths_prepare = 19,
154 },
155 {
156 .max_hsfreq = 250,
157 .t_init = 79801,
158 .tclk_miss = 4,
159 .tclk_settle = 23,
160 .ths_settle = 22,
161 .tclk_prepare = 10,
162 .ths_prepare = 16,
163 },
164 {
165 .max_hsfreq = 360,
166 .t_init = 79801,
167 .tclk_miss = 4,
168 .tclk_settle = 18,
169 .ths_settle = 19,
170 .tclk_prepare = 10,
171 .ths_prepare = 10,
172 },
173 {
174 .max_hsfreq = 1500,
175 .t_init = 79801,
176 .tclk_miss = 4,
177 .tclk_settle = 18,
178 .ths_settle = 18,
179 .tclk_prepare = 10,
180 .ths_prepare = 10,
181 },
182 };
183
184 struct rzg2l_csi2_format {
185 u32 code;
186 unsigned int bpp;
187 };
188
189 static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {
190 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16 },
191 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, },
192 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, },
193 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, },
194 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, },
195 };
196
sd_to_csi2(struct v4l2_subdev * sd)197 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
198 {
199 return container_of(sd, struct rzg2l_csi2, subdev);
200 }
201
rzg2l_csi2_code_to_fmt(unsigned int code)202 static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code)
203 {
204 unsigned int i;
205
206 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++)
207 if (rzg2l_csi2_formats[i].code == code)
208 return &rzg2l_csi2_formats[i];
209
210 return NULL;
211 }
212
notifier_to_csi2(struct v4l2_async_notifier * n)213 static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
214 {
215 return container_of(n, struct rzg2l_csi2, notifier);
216 }
217
rzg2l_csi2_read(struct rzg2l_csi2 * csi2,unsigned int reg)218 static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg)
219 {
220 return ioread32(csi2->base + reg);
221 }
222
rzg2l_csi2_write(struct rzg2l_csi2 * csi2,unsigned int reg,u32 data)223 static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg,
224 u32 data)
225 {
226 iowrite32(data, csi2->base + reg);
227 }
228
rzg2l_csi2_set(struct rzg2l_csi2 * csi2,unsigned int reg,u32 set)229 static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set)
230 {
231 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set);
232 }
233
rzg2l_csi2_clr(struct rzg2l_csi2 * csi2,unsigned int reg,u32 clr)234 static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr)
235 {
236 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr);
237 }
238
rzg2l_csi2_calc_mbps(struct rzg2l_csi2 * csi2)239 static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2)
240 {
241 struct v4l2_subdev *source = csi2->remote_source;
242 const struct rzg2l_csi2_format *format;
243 const struct v4l2_mbus_framefmt *fmt;
244 struct v4l2_subdev_state *state;
245 struct v4l2_ctrl *ctrl;
246 u64 mbps;
247
248 /* Read the pixel rate control from remote. */
249 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
250 if (!ctrl) {
251 dev_err(csi2->dev, "no pixel rate control in subdev %s\n",
252 source->name);
253 return -EINVAL;
254 }
255
256 state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev);
257 fmt = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);
258 format = rzg2l_csi2_code_to_fmt(fmt->code);
259 v4l2_subdev_unlock_state(state);
260
261 /*
262 * Calculate hsfreq in Mbps
263 * hsfreq = (pixel_rate * bits_per_sample) / number_of_lanes
264 */
265 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * format->bpp;
266 do_div(mbps, csi2->lanes * 1000000);
267
268 return mbps;
269 }
270
271 /* -----------------------------------------------------------------------------
272 * DPHY setting
273 */
274
rzg2l_csi2_dphy_disable(struct rzg2l_csi2 * csi2)275 static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2)
276 {
277 int ret;
278
279 /* Reset the CRU (D-PHY) */
280 ret = reset_control_assert(csi2->cmn_rstb);
281 if (ret)
282 return ret;
283
284 /* Stop the D-PHY clock */
285 clk_disable_unprepare(csi2->sysclk);
286
287 /* Cancel the EN_LDO1200 register setting */
288 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);
289
290 /* Cancel the EN_BGR register setting */
291 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);
292
293 csi2->dphy_enabled = false;
294
295 return 0;
296 }
297
rzg2l_csi2_dphy_enable(struct rzg2l_csi2 * csi2)298 static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2)
299 {
300 const struct rzg2l_csi2_timings *dphy_timing;
301 u32 dphytim0, dphytim1;
302 unsigned int i;
303 int mbps;
304 int ret;
305
306 mbps = rzg2l_csi2_calc_mbps(csi2);
307 if (mbps < 0)
308 return mbps;
309
310 csi2->hsfreq = mbps;
311
312 /* Set DPHY timing parameters */
313 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) {
314 dphy_timing = &rzg2l_csi2_global_timings[i];
315
316 if (csi2->hsfreq <= dphy_timing->max_hsfreq)
317 break;
318 }
319
320 if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings))
321 return -EINVAL;
322
323 /* Set D-PHY timing parameters */
324 dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) |
325 CSIDPHYTIM0_T_INIT(dphy_timing->t_init);
326 dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) |
327 CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) |
328 CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) |
329 CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle);
330 rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0);
331 rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1);
332
333 /* Enable D-PHY power control 0 */
334 rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW);
335
336 /* Set the EN_BGR bit */
337 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);
338
339 /* Delay 20us to be stable */
340 usleep_range(20, 40);
341
342 /* Enable D-PHY power control 1 */
343 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);
344
345 /* Delay 10us to be stable */
346 usleep_range(10, 20);
347
348 /* Start supplying the internal clock for the D-PHY block */
349 ret = clk_prepare_enable(csi2->sysclk);
350 if (ret)
351 rzg2l_csi2_dphy_disable(csi2);
352
353 csi2->dphy_enabled = true;
354
355 return ret;
356 }
357
rzg2l_csi2_dphy_setting(struct v4l2_subdev * sd,bool on)358 static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on)
359 {
360 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
361
362 if (on)
363 return rzg2l_csi2_dphy_enable(csi2);
364
365 return rzg2l_csi2_dphy_disable(csi2);
366 }
367
rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 * csi2)368 static int rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2)
369 {
370 unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ;
371 u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff;
372
373 /* Select data lanes */
374 rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes));
375
376 frrskw_coeff = 3 * vclk_rate * 8;
377 frrclk_coeff = frrskw_coeff / 2;
378 frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq);
379 frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq);
380 rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) |
381 CSI2nMCT2_FRRCLK(frrclk));
382
383 /*
384 * Select data type.
385 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8,
386 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit,
387 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit
388 * data types 1 to 8
389 */
390 rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f);
391 rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f);
392
393 clk_disable_unprepare(csi2->vclk);
394
395 /* Enable LINK reception */
396 rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);
397
398 return clk_prepare_enable(csi2->vclk);
399 }
400
rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 * csi2)401 static int rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2)
402 {
403 unsigned int timeout = VSRSTS_RETRIES;
404
405 /* Stop LINK reception */
406 rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);
407
408 /* Request a software reset of the LINK Video Pixel Interface */
409 rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST);
410
411 /* Make sure CSI2nRTST.VSRSTS bit is cleared */
412 while (--timeout) {
413 if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS))
414 break;
415 usleep_range(100, 200);
416 }
417
418 if (!timeout)
419 dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n");
420
421 return 0;
422 }
423
rzg2l_csi2_mipi_link_setting(struct v4l2_subdev * sd,bool on)424 static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on)
425 {
426 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
427 int ret;
428
429 if (on)
430 ret = rzg2l_csi2_mipi_link_enable(csi2);
431 else
432 ret = rzg2l_csi2_mipi_link_disable(csi2);
433
434 return ret;
435 }
436
rzg2l_csi2_s_stream(struct v4l2_subdev * sd,int enable)437 static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable)
438 {
439 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
440 int s_stream_ret = 0;
441 int ret;
442
443 if (enable) {
444 ret = pm_runtime_resume_and_get(csi2->dev);
445 if (ret)
446 return ret;
447
448 ret = rzg2l_csi2_mipi_link_setting(sd, 1);
449 if (ret)
450 goto err_pm_put;
451
452 ret = reset_control_deassert(csi2->cmn_rstb);
453 if (ret)
454 goto err_mipi_link_disable;
455 }
456
457 ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable);
458 if (ret)
459 s_stream_ret = ret;
460
461 if (enable && ret)
462 goto err_assert_rstb;
463
464 if (!enable) {
465 ret = rzg2l_csi2_dphy_setting(sd, 0);
466 if (ret && !s_stream_ret)
467 s_stream_ret = ret;
468 ret = rzg2l_csi2_mipi_link_setting(sd, 0);
469 if (ret && !s_stream_ret)
470 s_stream_ret = ret;
471
472 pm_runtime_put_sync(csi2->dev);
473 }
474
475 return s_stream_ret;
476
477 err_assert_rstb:
478 reset_control_assert(csi2->cmn_rstb);
479 err_mipi_link_disable:
480 rzg2l_csi2_mipi_link_setting(sd, 0);
481 err_pm_put:
482 pm_runtime_put_sync(csi2->dev);
483 return ret;
484 }
485
rzg2l_csi2_pre_streamon(struct v4l2_subdev * sd,u32 flags)486 static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags)
487 {
488 return rzg2l_csi2_dphy_setting(sd, 1);
489 }
490
rzg2l_csi2_post_streamoff(struct v4l2_subdev * sd)491 static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd)
492 {
493 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
494
495 /*
496 * In ideal case D-PHY will be disabled in s_stream(0) callback
497 * as mentioned in the HW manual. The below will only happen when
498 * pre_streamon succeeds and further down the line s_stream(1)
499 * fails so we need to undo things in post_streamoff.
500 */
501 if (csi2->dphy_enabled)
502 return rzg2l_csi2_dphy_setting(sd, 0);
503
504 return 0;
505 }
506
rzg2l_csi2_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * fmt)507 static int rzg2l_csi2_set_format(struct v4l2_subdev *sd,
508 struct v4l2_subdev_state *state,
509 struct v4l2_subdev_format *fmt)
510 {
511 struct v4l2_mbus_framefmt *src_format;
512 struct v4l2_mbus_framefmt *sink_format;
513
514 src_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SOURCE);
515 if (fmt->pad == RZG2L_CSI2_SOURCE) {
516 fmt->format = *src_format;
517 return 0;
518 }
519
520 sink_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);
521
522 if (!rzg2l_csi2_code_to_fmt(fmt->format.code))
523 sink_format->code = rzg2l_csi2_formats[0].code;
524 else
525 sink_format->code = fmt->format.code;
526
527 sink_format->field = V4L2_FIELD_NONE;
528 sink_format->colorspace = fmt->format.colorspace;
529 sink_format->xfer_func = fmt->format.xfer_func;
530 sink_format->ycbcr_enc = fmt->format.ycbcr_enc;
531 sink_format->quantization = fmt->format.quantization;
532 sink_format->width = clamp_t(u32, fmt->format.width,
533 RZG2L_CSI2_MIN_WIDTH, RZG2L_CSI2_MAX_WIDTH);
534 sink_format->height = clamp_t(u32, fmt->format.height,
535 RZG2L_CSI2_MIN_HEIGHT, RZG2L_CSI2_MAX_HEIGHT);
536 fmt->format = *sink_format;
537
538 /* propagate format to source pad */
539 *src_format = *sink_format;
540
541 return 0;
542 }
543
rzg2l_csi2_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)544 static int rzg2l_csi2_init_state(struct v4l2_subdev *sd,
545 struct v4l2_subdev_state *sd_state)
546 {
547 struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, };
548
549 fmt.format.width = RZG2L_CSI2_DEFAULT_WIDTH;
550 fmt.format.height = RZG2L_CSI2_DEFAULT_HEIGHT;
551 fmt.format.field = V4L2_FIELD_NONE;
552 fmt.format.code = RZG2L_CSI2_DEFAULT_FMT;
553 fmt.format.colorspace = V4L2_COLORSPACE_SRGB;
554 fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
555 fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT;
556 fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT;
557
558 return rzg2l_csi2_set_format(sd, sd_state, &fmt);
559 }
560
rzg2l_csi2_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)561 static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd,
562 struct v4l2_subdev_state *sd_state,
563 struct v4l2_subdev_mbus_code_enum *code)
564 {
565 if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats))
566 return -EINVAL;
567
568 code->code = rzg2l_csi2_formats[code->index].code;
569
570 return 0;
571 }
572
rzg2l_csi2_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)573 static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd,
574 struct v4l2_subdev_state *sd_state,
575 struct v4l2_subdev_frame_size_enum *fse)
576 {
577 if (fse->index != 0)
578 return -EINVAL;
579
580 if (!rzg2l_csi2_code_to_fmt(fse->code))
581 return -EINVAL;
582
583 fse->min_width = RZG2L_CSI2_MIN_WIDTH;
584 fse->min_height = RZG2L_CSI2_MIN_HEIGHT;
585 fse->max_width = RZG2L_CSI2_MAX_WIDTH;
586 fse->max_height = RZG2L_CSI2_MAX_HEIGHT;
587
588 return 0;
589 }
590
rzg2l_csi2_get_frame_desc(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_frame_desc * fd)591 static int rzg2l_csi2_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
592 struct v4l2_mbus_frame_desc *fd)
593 {
594 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
595 struct media_pad *remote_pad;
596
597 if (!csi2->remote_source)
598 return -ENODEV;
599
600 remote_pad = media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]);
601 if (IS_ERR(remote_pad)) {
602 dev_err(csi2->dev, "can't get source pad of %s (%ld)\n",
603 csi2->remote_source->name, PTR_ERR(remote_pad));
604 return PTR_ERR(remote_pad);
605 }
606 return v4l2_subdev_call(csi2->remote_source, pad, get_frame_desc,
607 remote_pad->index, fd);
608 }
609
610 static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = {
611 .s_stream = rzg2l_csi2_s_stream,
612 .pre_streamon = rzg2l_csi2_pre_streamon,
613 .post_streamoff = rzg2l_csi2_post_streamoff,
614 };
615
616 static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = {
617 .enum_mbus_code = rzg2l_csi2_enum_mbus_code,
618 .enum_frame_size = rzg2l_csi2_enum_frame_size,
619 .set_fmt = rzg2l_csi2_set_format,
620 .get_fmt = v4l2_subdev_get_fmt,
621 .get_frame_desc = rzg2l_csi2_get_frame_desc,
622 };
623
624 static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = {
625 .video = &rzg2l_csi2_video_ops,
626 .pad = &rzg2l_csi2_pad_ops,
627 };
628
629 static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = {
630 .init_state = rzg2l_csi2_init_state,
631 };
632
633 /* -----------------------------------------------------------------------------
634 * Async handling and registration of subdevices and links.
635 */
636
rzg2l_csi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)637 static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier,
638 struct v4l2_subdev *subdev,
639 struct v4l2_async_connection *asd)
640 {
641 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);
642
643 csi2->remote_source = subdev;
644
645 dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name);
646
647 return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK,
648 &csi2->subdev.entity, 0,
649 MEDIA_LNK_FL_ENABLED |
650 MEDIA_LNK_FL_IMMUTABLE);
651 }
652
rzg2l_csi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)653 static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier,
654 struct v4l2_subdev *subdev,
655 struct v4l2_async_connection *asd)
656 {
657 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);
658
659 csi2->remote_source = NULL;
660
661 dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name);
662 }
663
664 static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = {
665 .bound = rzg2l_csi2_notify_bound,
666 .unbind = rzg2l_csi2_notify_unbind,
667 };
668
rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 * csi2,struct v4l2_fwnode_endpoint * vep)669 static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2,
670 struct v4l2_fwnode_endpoint *vep)
671 {
672 /* Only port 0 endpoint 0 is valid. */
673 if (vep->base.port || vep->base.id)
674 return -ENOTCONN;
675
676 csi2->lanes = vep->bus.mipi_csi2.num_data_lanes;
677
678 return 0;
679 }
680
rzg2l_csi2_parse_dt(struct rzg2l_csi2 * csi2)681 static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2)
682 {
683 struct v4l2_fwnode_endpoint v4l2_ep = {
684 .bus_type = V4L2_MBUS_CSI2_DPHY
685 };
686 struct v4l2_async_connection *asd;
687 struct fwnode_handle *fwnode;
688 struct fwnode_handle *ep;
689 int ret;
690
691 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0);
692 if (!ep) {
693 dev_err(csi2->dev, "Not connected to subdevice\n");
694 return -EINVAL;
695 }
696
697 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
698 if (ret) {
699 dev_err(csi2->dev, "Could not parse v4l2 endpoint\n");
700 fwnode_handle_put(ep);
701 return -EINVAL;
702 }
703
704 ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep);
705 if (ret) {
706 fwnode_handle_put(ep);
707 return ret;
708 }
709
710 fwnode = fwnode_graph_get_remote_endpoint(ep);
711 fwnode_handle_put(ep);
712
713 v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->subdev);
714 csi2->notifier.ops = &rzg2l_csi2_notify_ops;
715
716 asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode,
717 struct v4l2_async_connection);
718 fwnode_handle_put(fwnode);
719 if (IS_ERR(asd))
720 return PTR_ERR(asd);
721
722 ret = v4l2_async_nf_register(&csi2->notifier);
723 if (ret)
724 v4l2_async_nf_cleanup(&csi2->notifier);
725
726 return ret;
727 }
728
rzg2l_validate_csi2_lanes(struct rzg2l_csi2 * csi2)729 static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2)
730 {
731 int lanes;
732 int ret;
733
734 if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) {
735 dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n",
736 csi2->lanes);
737 return -EINVAL;
738 }
739
740 ret = pm_runtime_resume_and_get(csi2->dev);
741 if (ret)
742 return ret;
743
744 /* Checking the maximum lanes support for CSI-2 module */
745 lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8;
746 if (lanes < csi2->lanes) {
747 dev_err(csi2->dev,
748 "Failed to support %d data lanes\n", csi2->lanes);
749 ret = -EINVAL;
750 }
751
752 pm_runtime_put_sync(csi2->dev);
753
754 return ret;
755 }
756
757 /* -----------------------------------------------------------------------------
758 * Platform Device Driver.
759 */
760
761 static const struct media_entity_operations rzg2l_csi2_entity_ops = {
762 .link_validate = v4l2_subdev_link_validate,
763 };
764
rzg2l_csi2_probe(struct platform_device * pdev)765 static int rzg2l_csi2_probe(struct platform_device *pdev)
766 {
767 struct rzg2l_csi2 *csi2;
768 int ret;
769
770 csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);
771 if (!csi2)
772 return -ENOMEM;
773
774 csi2->base = devm_platform_ioremap_resource(pdev, 0);
775 if (IS_ERR(csi2->base))
776 return PTR_ERR(csi2->base);
777
778 csi2->cmn_rstb = devm_reset_control_get_exclusive(&pdev->dev, "cmn-rstb");
779 if (IS_ERR(csi2->cmn_rstb))
780 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->cmn_rstb),
781 "Failed to get cpg cmn-rstb\n");
782
783 csi2->presetn = devm_reset_control_get_shared(&pdev->dev, "presetn");
784 if (IS_ERR(csi2->presetn))
785 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->presetn),
786 "Failed to get cpg presetn\n");
787
788 csi2->sysclk = devm_clk_get(&pdev->dev, "system");
789 if (IS_ERR(csi2->sysclk))
790 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->sysclk),
791 "Failed to get system clk\n");
792
793 csi2->vclk = devm_clk_get(&pdev->dev, "video");
794 if (IS_ERR(csi2->vclk))
795 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->vclk),
796 "Failed to get video clock\n");
797 csi2->vclk_rate = clk_get_rate(csi2->vclk);
798
799 csi2->dev = &pdev->dev;
800
801 platform_set_drvdata(pdev, csi2);
802
803 ret = rzg2l_csi2_parse_dt(csi2);
804 if (ret)
805 return ret;
806
807 pm_runtime_enable(&pdev->dev);
808
809 ret = rzg2l_validate_csi2_lanes(csi2);
810 if (ret)
811 goto error_pm;
812
813 csi2->subdev.dev = &pdev->dev;
814 v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops);
815 csi2->subdev.internal_ops = &rzg2l_csi2_internal_ops;
816 v4l2_set_subdevdata(&csi2->subdev, &pdev->dev);
817 snprintf(csi2->subdev.name, sizeof(csi2->subdev.name),
818 "csi-%s", dev_name(&pdev->dev));
819 csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
820
821 csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
822 csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops;
823
824 csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK |
825 MEDIA_PAD_FL_MUST_CONNECT;
826 /*
827 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual
828 * channels should be implemented by streams API which is under
829 * development lets hardcode to VC0 for now.
830 */
831 csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE |
832 MEDIA_PAD_FL_MUST_CONNECT;
833 ret = media_entity_pads_init(&csi2->subdev.entity, ARRAY_SIZE(csi2->pads),
834 csi2->pads);
835 if (ret)
836 goto error_pm;
837
838 ret = v4l2_subdev_init_finalize(&csi2->subdev);
839 if (ret < 0)
840 goto error_async;
841
842 ret = v4l2_async_register_subdev(&csi2->subdev);
843 if (ret < 0)
844 goto error_subdev;
845
846 return 0;
847
848 error_subdev:
849 v4l2_subdev_cleanup(&csi2->subdev);
850 error_async:
851 v4l2_async_nf_unregister(&csi2->notifier);
852 v4l2_async_nf_cleanup(&csi2->notifier);
853 media_entity_cleanup(&csi2->subdev.entity);
854 error_pm:
855 pm_runtime_disable(&pdev->dev);
856
857 return ret;
858 }
859
rzg2l_csi2_remove(struct platform_device * pdev)860 static void rzg2l_csi2_remove(struct platform_device *pdev)
861 {
862 struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev);
863
864 v4l2_async_nf_unregister(&csi2->notifier);
865 v4l2_async_nf_cleanup(&csi2->notifier);
866 v4l2_async_unregister_subdev(&csi2->subdev);
867 v4l2_subdev_cleanup(&csi2->subdev);
868 media_entity_cleanup(&csi2->subdev.entity);
869 pm_runtime_disable(&pdev->dev);
870 }
871
rzg2l_csi2_pm_runtime_suspend(struct device * dev)872 static int rzg2l_csi2_pm_runtime_suspend(struct device *dev)
873 {
874 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);
875
876 reset_control_assert(csi2->presetn);
877
878 return 0;
879 }
880
rzg2l_csi2_pm_runtime_resume(struct device * dev)881 static int rzg2l_csi2_pm_runtime_resume(struct device *dev)
882 {
883 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);
884
885 return reset_control_deassert(csi2->presetn);
886 }
887
888 static const struct dev_pm_ops rzg2l_csi2_pm_ops = {
889 RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend,
890 rzg2l_csi2_pm_runtime_resume, NULL)
891 };
892
893 static const struct of_device_id rzg2l_csi2_of_table[] = {
894 { .compatible = "renesas,rzg2l-csi2", },
895 { /* sentinel */ }
896 };
897 MODULE_DEVICE_TABLE(of, rzg2l_csi2_of_table);
898
899 static struct platform_driver rzg2l_csi2_pdrv = {
900 .remove = rzg2l_csi2_remove,
901 .probe = rzg2l_csi2_probe,
902 .driver = {
903 .name = "rzg2l-csi2",
904 .of_match_table = rzg2l_csi2_of_table,
905 .pm = pm_ptr(&rzg2l_csi2_pm_ops),
906 },
907 };
908
909 module_platform_driver(rzg2l_csi2_pdrv);
910
911 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
912 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver");
913 MODULE_LICENSE("GPL");
914