1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <linux/soc/mediatek/mtk_wed.h> 18 #if defined(__FreeBSD__) 19 #include <linux/wait.h> 20 #include <linux/bitfield.h> 21 #include <linux/debugfs.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #endif 25 #include <net/mac80211.h> 26 #include <net/page_pool/helpers.h> 27 #include "util.h" 28 #include "testmode.h" 29 30 #define MT_MCU_RING_SIZE 32 31 #define MT_RX_BUF_SIZE 2048 32 #define MT_SKB_HEAD_LEN 256 33 34 #define MT_MAX_NON_AQL_PKT 16 35 #define MT_TXQ_FREE_THR 32 36 37 #define MT76_TOKEN_FREE_THR 64 38 39 #define MT_QFLAG_WED_RING GENMASK(1, 0) 40 #define MT_QFLAG_WED_TYPE GENMASK(4, 2) 41 #define MT_QFLAG_WED BIT(5) 42 #define MT_QFLAG_WED_RRO BIT(6) 43 #define MT_QFLAG_WED_RRO_EN BIT(7) 44 #define MT_QFLAG_EMI_EN BIT(8) 45 #define MT_QFLAG_NPU BIT(9) 46 47 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 48 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 49 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 50 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n)) 51 52 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 53 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 54 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 55 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 56 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 57 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 58 #define MT_WED_RRO_Q_RXDMAD_C __MT_WED_RRO_Q(MT76_WED_RRO_Q_RXDMAD_C, 0) 59 60 #define __MT_NPU_Q(_type, _n) (MT_QFLAG_NPU | \ 61 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 62 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 63 #define MT_NPU_Q_TX(_n) __MT_NPU_Q(MT76_WED_Q_TX, _n) 64 #define MT_NPU_Q_RX(_n) __MT_NPU_Q(MT76_WED_Q_RX, _n) 65 66 struct mt76_dev; 67 struct mt76_phy; 68 struct mt76_wcid; 69 struct mt76s_intr; 70 struct mt76_chanctx; 71 struct mt76_vif_link; 72 73 struct mt76_reg_pair { 74 u32 reg; 75 u32 value; 76 }; 77 78 enum mt76_bus_type { 79 MT76_BUS_MMIO, 80 MT76_BUS_USB, 81 MT76_BUS_SDIO, 82 }; 83 84 enum mt76_wed_type { 85 MT76_WED_Q_TX, 86 MT76_WED_Q_TXFREE, 87 MT76_WED_Q_RX, 88 MT76_WED_RRO_Q_DATA, 89 MT76_WED_RRO_Q_MSDU_PG, 90 MT76_WED_RRO_Q_IND, 91 MT76_WED_RRO_Q_RXDMAD_C, 92 }; 93 94 enum mt76_hwrro_mode { 95 MT76_HWRRO_OFF, 96 MT76_HWRRO_V3, 97 MT76_HWRRO_V3_1, 98 }; 99 100 struct mt76_bus_ops { 101 u32 (*rr)(struct mt76_dev *dev, u32 offset); 102 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 103 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 104 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 105 int len); 106 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 107 int len); 108 int (*wr_rp)(struct mt76_dev *dev, u32 base, 109 const struct mt76_reg_pair *rp, int len); 110 int (*rd_rp)(struct mt76_dev *dev, u32 base, 111 struct mt76_reg_pair *rp, int len); 112 enum mt76_bus_type type; 113 }; 114 115 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 116 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 117 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 118 119 enum mt76_txq_id { 120 MT_TXQ_VO = IEEE80211_AC_VO, 121 MT_TXQ_VI = IEEE80211_AC_VI, 122 MT_TXQ_BE = IEEE80211_AC_BE, 123 MT_TXQ_BK = IEEE80211_AC_BK, 124 MT_TXQ_PSD, 125 MT_TXQ_BEACON, 126 MT_TXQ_CAB, 127 __MT_TXQ_MAX 128 }; 129 130 enum mt76_mcuq_id { 131 MT_MCUQ_WM, 132 MT_MCUQ_WA, 133 MT_MCUQ_FWDL, 134 __MT_MCUQ_MAX 135 }; 136 137 enum mt76_rxq_id { 138 MT_RXQ_MAIN, 139 MT_RXQ_MCU, 140 MT_RXQ_MCU_WA, 141 MT_RXQ_BAND1, 142 MT_RXQ_BAND1_WA, 143 MT_RXQ_MAIN_WA, 144 MT_RXQ_BAND2, 145 MT_RXQ_BAND2_WA, 146 MT_RXQ_RRO_BAND0, 147 MT_RXQ_RRO_BAND1, 148 MT_RXQ_RRO_BAND2, 149 MT_RXQ_MSDU_PAGE_BAND0, 150 MT_RXQ_MSDU_PAGE_BAND1, 151 MT_RXQ_MSDU_PAGE_BAND2, 152 MT_RXQ_TXFREE_BAND0, 153 MT_RXQ_TXFREE_BAND1, 154 MT_RXQ_TXFREE_BAND2, 155 MT_RXQ_RRO_IND, 156 MT_RXQ_RRO_RXDMAD_C, 157 MT_RXQ_NPU0, 158 MT_RXQ_NPU1, 159 __MT_RXQ_MAX 160 }; 161 162 enum mt76_band_id { 163 MT_BAND0, 164 MT_BAND1, 165 MT_BAND2, 166 __MT_MAX_BAND 167 }; 168 169 enum mt76_cipher_type { 170 MT_CIPHER_NONE, 171 MT_CIPHER_WEP40, 172 MT_CIPHER_TKIP, 173 MT_CIPHER_TKIP_NO_MIC, 174 MT_CIPHER_AES_CCMP, 175 MT_CIPHER_WEP104, 176 MT_CIPHER_BIP_CMAC_128, 177 MT_CIPHER_WEP128, 178 MT_CIPHER_WAPI, 179 MT_CIPHER_CCMP_CCX, 180 MT_CIPHER_CCMP_256, 181 MT_CIPHER_GCMP, 182 MT_CIPHER_GCMP_256, 183 }; 184 185 enum mt76_dfs_state { 186 MT_DFS_STATE_UNKNOWN, 187 MT_DFS_STATE_DISABLED, 188 MT_DFS_STATE_CAC, 189 MT_DFS_STATE_ACTIVE, 190 }; 191 192 #define MT76_RNR_SCAN_MAX_BSSIDS 16 193 struct mt76_scan_rnr_param { 194 u8 bssid[MT76_RNR_SCAN_MAX_BSSIDS][ETH_ALEN]; 195 u8 channel[MT76_RNR_SCAN_MAX_BSSIDS]; 196 u8 random_mac[ETH_ALEN]; 197 u8 seq_num; 198 u8 bssid_num; 199 u32 sreq_flag; 200 }; 201 202 struct mt76_queue_buf { 203 dma_addr_t addr; 204 u16 len:15, 205 skip_unmap:1; 206 }; 207 208 struct mt76_tx_info { 209 struct mt76_queue_buf buf[32]; 210 struct sk_buff *skb; 211 int nbuf; 212 u32 info; 213 }; 214 215 struct mt76_queue_entry { 216 union { 217 void *buf; 218 struct sk_buff *skb; 219 }; 220 union { 221 struct mt76_txwi_cache *txwi; 222 struct urb *urb; 223 int buf_sz; 224 }; 225 dma_addr_t dma_addr[2]; 226 u16 dma_len[2]; 227 u16 wcid; 228 bool skip_buf0:1; 229 bool skip_buf1:1; 230 bool done:1; 231 }; 232 233 struct mt76_queue_regs { 234 u32 desc_base; 235 u32 ring_size; 236 u32 cpu_idx; 237 u32 dma_idx; 238 } __packed __aligned(4); 239 240 struct mt76_queue { 241 struct mt76_queue_regs __iomem *regs; 242 243 spinlock_t lock; 244 spinlock_t cleanup_lock; 245 struct mt76_queue_entry *entry; 246 struct mt76_rro_desc *rro_desc; 247 struct mt76_desc *desc; 248 249 u16 first; 250 u16 head; 251 u16 tail; 252 u8 hw_idx; 253 u8 ep; 254 int ndesc; 255 int queued; 256 int buf_size; 257 bool stopped; 258 bool blocked; 259 260 u8 buf_offset; 261 u16 flags; 262 u8 magic_cnt; 263 264 __le16 *emi_cpu_idx; 265 266 struct mtk_wed_device *wed; 267 struct mt76_dev *dev; 268 u32 wed_regs; 269 270 dma_addr_t desc_dma; 271 struct sk_buff *rx_head; 272 struct page_pool *page_pool; 273 }; 274 275 struct mt76_mcu_ops { 276 unsigned int max_retry; 277 u32 headroom; 278 u32 tailroom; 279 280 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 281 int len, bool wait_resp); 282 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb, 283 int cmd, int *seq); 284 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 285 int cmd, int *seq); 286 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 287 struct sk_buff *skb, int seq); 288 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 289 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 290 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 291 const struct mt76_reg_pair *rp, int len); 292 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 293 struct mt76_reg_pair *rp, int len); 294 int (*mcu_restart)(struct mt76_dev *dev); 295 }; 296 297 struct mt76_queue_ops { 298 int (*init)(struct mt76_dev *dev, 299 int (*poll)(struct napi_struct *napi, int budget)); 300 301 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 302 int idx, int n_desc, int bufsize, 303 u32 ring_base); 304 305 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q, 306 enum mt76_txq_id qid, struct sk_buff *skb, 307 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 308 309 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 310 struct sk_buff *skb, u32 tx_info); 311 312 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 313 int *len, u32 *info, bool *more); 314 315 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 316 317 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 318 bool flush); 319 320 void (*rx_queue_init)(struct mt76_dev *dev, enum mt76_rxq_id qid, 321 int (*poll)(struct napi_struct *napi, int budget)); 322 323 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 324 325 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 326 327 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q, 328 bool reset_idx); 329 }; 330 331 enum mt76_phy_type { 332 MT_PHY_TYPE_CCK, 333 MT_PHY_TYPE_OFDM, 334 MT_PHY_TYPE_HT, 335 MT_PHY_TYPE_HT_GF, 336 MT_PHY_TYPE_VHT, 337 MT_PHY_TYPE_HE_SU = 8, 338 MT_PHY_TYPE_HE_EXT_SU, 339 MT_PHY_TYPE_HE_TB, 340 MT_PHY_TYPE_HE_MU, 341 MT_PHY_TYPE_EHT_SU = 13, 342 MT_PHY_TYPE_EHT_TRIG, 343 MT_PHY_TYPE_EHT_MU, 344 __MT_PHY_TYPE_MAX, 345 }; 346 347 struct mt76_sta_stats { 348 u64 tx_mode[__MT_PHY_TYPE_MAX]; 349 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 350 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 351 u64 tx_mcs[16]; /* mcs idx */ 352 u64 tx_bytes; 353 /* WED TX */ 354 u32 tx_packets; /* unit: MSDU */ 355 u32 tx_retries; 356 u32 tx_failed; 357 /* WED RX */ 358 u64 rx_bytes; 359 u32 rx_packets; 360 u32 rx_errors; 361 u32 rx_drops; 362 }; 363 364 enum mt76_wcid_flags { 365 MT_WCID_FLAG_CHECK_PS, 366 MT_WCID_FLAG_PS, 367 MT_WCID_FLAG_4ADDR, 368 MT_WCID_FLAG_HDR_TRANS, 369 }; 370 371 #define MT76_N_WCIDS 1088 372 373 /* stored in ieee80211_tx_info::hw_queue */ 374 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 375 376 DECLARE_EWMA(signal, 10, 8); 377 378 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 379 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 380 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 381 #define MT_WCID_TX_INFO_SET BIT(31) 382 383 struct mt76_wcid { 384 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 385 386 atomic_t non_aql_packets; 387 unsigned long flags; 388 389 struct ewma_signal rssi; 390 int inactive_count; 391 392 struct rate_info rate; 393 unsigned long ampdu_state; 394 395 u16 idx; 396 u8 hw_key_idx; 397 u8 hw_key_idx2; 398 399 u8 offchannel:1; 400 u8 sta:1; 401 u8 sta_disabled:1; 402 u8 amsdu:1; 403 u8 phy_idx:2; 404 u8 link_id:4; 405 bool link_valid; 406 407 u8 rx_check_pn; 408 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 409 u16 cipher; 410 411 u32 tx_info; 412 bool sw_iv; 413 414 struct list_head tx_list; 415 struct sk_buff_head tx_pending; 416 struct sk_buff_head tx_offchannel; 417 418 struct list_head list; 419 struct idr pktid; 420 421 struct mt76_sta_stats stats; 422 423 struct list_head poll_list; 424 425 struct mt76_wcid *def_wcid; 426 }; 427 428 struct mt76_txq { 429 u16 wcid; 430 431 u16 agg_ssn; 432 bool send_bar; 433 bool aggr; 434 }; 435 436 /* data0 */ 437 #define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28) 438 #define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16) 439 #define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0) 440 /* data1 */ 441 #define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29) 442 #define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0) 443 struct mt76_wed_rro_ind { 444 __le32 data0; 445 __le32 data1; 446 }; 447 448 struct mt76_txwi_cache { 449 struct list_head list; 450 dma_addr_t dma_addr; 451 452 union { 453 struct sk_buff *skb; 454 void *ptr; 455 }; 456 457 u8 qid; 458 }; 459 460 struct mt76_rx_tid { 461 struct rcu_head rcu_head; 462 463 struct mt76_dev *dev; 464 465 spinlock_t lock; 466 struct delayed_work reorder_work; 467 468 u16 id; 469 u16 head; 470 u16 size; 471 u16 nframes; 472 473 u8 num; 474 475 u8 started:1, stopped:1, timer_pending:1; 476 477 struct sk_buff *reorder_buf[] __counted_by(size); 478 }; 479 480 #define MT_TX_CB_DMA_DONE BIT(0) 481 #define MT_TX_CB_TXS_DONE BIT(1) 482 #define MT_TX_CB_TXS_FAILED BIT(2) 483 484 #define MT_PACKET_ID_MASK GENMASK(6, 0) 485 #define MT_PACKET_ID_NO_ACK 0 486 #define MT_PACKET_ID_NO_SKB 1 487 #define MT_PACKET_ID_WED 2 488 #define MT_PACKET_ID_FIRST 3 489 #define MT_PACKET_ID_HAS_RATE BIT(7) 490 /* This is timer for when to give up when waiting for TXS callback, 491 * with starting time being the time at which the DMA_DONE callback 492 * was seen (so, we know packet was processed then, it should not take 493 * long after that for firmware to send the TXS callback if it is going 494 * to do so.) 495 */ 496 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 497 498 struct mt76_tx_cb { 499 unsigned long jiffies; 500 u16 wcid; 501 u8 pktid; 502 u8 flags; 503 }; 504 505 enum { 506 MT76_STATE_INITIALIZED, 507 MT76_STATE_REGISTERED, 508 MT76_STATE_RUNNING, 509 MT76_STATE_MCU_RUNNING, 510 MT76_SCANNING, 511 MT76_HW_SCANNING, 512 MT76_HW_SCHED_SCANNING, 513 MT76_RESTART, 514 MT76_RESET, 515 MT76_MCU_RESET, 516 MT76_REMOVED, 517 MT76_READING_STATS, 518 MT76_STATE_POWER_OFF, 519 MT76_STATE_SUSPEND, 520 MT76_STATE_ROC, 521 MT76_STATE_PM, 522 MT76_STATE_WED_RESET, 523 }; 524 525 enum mt76_sta_event { 526 MT76_STA_EVENT_ASSOC, 527 MT76_STA_EVENT_AUTHORIZE, 528 MT76_STA_EVENT_DISASSOC, 529 }; 530 531 struct mt76_hw_cap { 532 bool has_2ghz; 533 bool has_5ghz; 534 bool has_6ghz; 535 }; 536 537 #define MT_DRV_TXWI_NO_FREE BIT(0) 538 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 539 #define MT_DRV_SW_RX_AIRTIME BIT(2) 540 #define MT_DRV_RX_DMA_HDR BIT(3) 541 #define MT_DRV_HW_MGMT_TXQ BIT(4) 542 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 543 #define MT_DRV_IGNORE_TXS_FAILED BIT(6) 544 545 struct mt76_driver_ops { 546 u32 drv_flags; 547 u32 survey_flags; 548 u16 txwi_size; 549 u16 token_size; 550 u8 mcs_rates; 551 552 unsigned int link_data_size; 553 554 void (*update_survey)(struct mt76_phy *phy); 555 int (*set_channel)(struct mt76_phy *phy); 556 557 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 558 enum mt76_txq_id qid, struct mt76_wcid *wcid, 559 struct ieee80211_sta *sta, 560 struct mt76_tx_info *tx_info); 561 562 void (*tx_complete_skb)(struct mt76_dev *dev, 563 struct mt76_queue_entry *e); 564 565 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 566 567 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 568 569 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 570 struct sk_buff *skb, u32 *info); 571 572 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 573 574 void (*rx_rro_ind_process)(struct mt76_dev *dev, void *data); 575 int (*rx_rro_add_msdu_page)(struct mt76_dev *dev, struct mt76_queue *q, 576 dma_addr_t p, void *data); 577 578 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 579 bool ps); 580 581 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 582 struct ieee80211_sta *sta); 583 584 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif, 585 struct ieee80211_sta *sta, enum mt76_sta_event ev); 586 587 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 588 struct ieee80211_sta *sta); 589 590 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif, 591 struct ieee80211_bss_conf *link_conf, 592 struct mt76_vif_link *mlink); 593 594 void (*vif_link_remove)(struct mt76_phy *phy, 595 struct ieee80211_vif *vif, 596 struct ieee80211_bss_conf *link_conf, 597 struct mt76_vif_link *mlink); 598 }; 599 600 struct mt76_channel_state { 601 u64 cc_active; 602 u64 cc_busy; 603 u64 cc_rx; 604 u64 cc_bss_rx; 605 u64 cc_tx; 606 607 s8 noise; 608 }; 609 610 struct mt76_sband { 611 struct ieee80211_supported_band sband; 612 struct mt76_channel_state *chan; 613 }; 614 615 /* addr req mask */ 616 #define MT_VEND_TYPE_EEPROM BIT(31) 617 #define MT_VEND_TYPE_CFG BIT(30) 618 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 619 620 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 621 enum mt_vendor_req { 622 MT_VEND_DEV_MODE = 0x1, 623 MT_VEND_WRITE = 0x2, 624 MT_VEND_POWER_ON = 0x4, 625 MT_VEND_MULTI_WRITE = 0x6, 626 MT_VEND_MULTI_READ = 0x7, 627 MT_VEND_READ_EEPROM = 0x9, 628 MT_VEND_WRITE_FCE = 0x42, 629 MT_VEND_WRITE_CFG = 0x46, 630 MT_VEND_READ_CFG = 0x47, 631 MT_VEND_READ_EXT = 0x63, 632 MT_VEND_WRITE_EXT = 0x66, 633 MT_VEND_FEATURE_SET = 0x91, 634 }; 635 636 enum mt76u_in_ep { 637 MT_EP_IN_PKT_RX, 638 MT_EP_IN_CMD_RESP, 639 __MT_EP_IN_MAX, 640 }; 641 642 enum mt76u_out_ep { 643 MT_EP_OUT_INBAND_CMD, 644 MT_EP_OUT_AC_BE, 645 MT_EP_OUT_AC_BK, 646 MT_EP_OUT_AC_VI, 647 MT_EP_OUT_AC_VO, 648 MT_EP_OUT_HCCA, 649 __MT_EP_OUT_MAX, 650 }; 651 652 struct mt76_mcu { 653 struct mutex mutex; 654 u32 msg_seq; 655 int timeout; 656 657 struct sk_buff_head res_q; 658 wait_queue_head_t wait; 659 }; 660 661 #define MT_TX_SG_MAX_SIZE 8 662 #define MT_RX_SG_MAX_SIZE 4 663 #define MT_NUM_TX_ENTRIES 256 664 #define MT_NUM_RX_ENTRIES 128 665 #define MCU_RESP_URB_SIZE 1024 666 struct mt76_usb { 667 struct mutex usb_ctrl_mtx; 668 u8 *data; 669 u16 data_len; 670 671 struct mt76_worker status_worker; 672 struct mt76_worker rx_worker; 673 674 struct work_struct stat_work; 675 676 u8 out_ep[__MT_EP_OUT_MAX]; 677 u8 in_ep[__MT_EP_IN_MAX]; 678 bool sg_en; 679 680 struct mt76u_mcu { 681 u8 *data; 682 /* multiple reads */ 683 struct mt76_reg_pair *rp; 684 int rp_len; 685 u32 base; 686 } mcu; 687 }; 688 689 #define MT76S_XMIT_BUF_SZ 0x3fe00 690 #define MT76S_NUM_TX_ENTRIES 256 691 #define MT76S_NUM_RX_ENTRIES 512 692 struct mt76_sdio { 693 struct mt76_worker txrx_worker; 694 struct mt76_worker status_worker; 695 struct mt76_worker net_worker; 696 struct mt76_worker stat_worker; 697 698 u8 *xmit_buf; 699 u32 xmit_buf_sz; 700 701 struct sdio_func *func; 702 void *intr_data; 703 u8 hw_ver; 704 wait_queue_head_t wait; 705 706 int pse_mcu_quota_max; 707 struct { 708 int pse_data_quota; 709 int ple_data_quota; 710 int pse_mcu_quota; 711 int pse_page_size; 712 int deficit; 713 } sched; 714 715 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 716 }; 717 718 struct mt76_mmio { 719 void __iomem *regs; 720 spinlock_t irq_lock; 721 u32 irqmask; 722 723 struct mtk_wed_device wed; 724 struct mtk_wed_device wed_hif2; 725 struct completion wed_reset; 726 struct completion wed_reset_complete; 727 728 struct airoha_ppe_dev __rcu *ppe_dev; 729 struct airoha_npu __rcu *npu; 730 phys_addr_t phy_addr; 731 int npu_type; 732 }; 733 734 struct mt76_rx_status { 735 union { 736 struct mt76_wcid *wcid; 737 u16 wcid_idx; 738 }; 739 740 u32 reorder_time; 741 742 u32 ampdu_ref; 743 u32 timestamp; 744 745 u8 iv[6]; 746 747 u8 phy_idx:2; 748 u8 aggr:1; 749 u8 qos_ctl; 750 u16 seqno; 751 752 u16 freq; 753 u32 flag; 754 u8 enc_flags; 755 u8 encoding:3, bw:4; 756 union { 757 struct { 758 u8 he_ru:3; 759 u8 he_gi:2; 760 u8 he_dcm:1; 761 }; 762 struct { 763 u8 ru:4; 764 u8 gi:2; 765 } eht; 766 }; 767 768 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 769 u8 rate_idx; 770 u8 nss:5, band:3; 771 s8 signal; 772 u8 chains; 773 s8 chain_signal[IEEE80211_MAX_CHAINS]; 774 }; 775 776 struct mt76_freq_range_power { 777 const struct cfg80211_sar_freq_ranges *range; 778 s8 power; 779 }; 780 781 struct mt76_testmode_ops { 782 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 783 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 784 enum mt76_testmode_state new_state); 785 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 786 }; 787 788 struct mt76_testmode_data { 789 enum mt76_testmode_state state; 790 791 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 792 struct sk_buff *tx_skb; 793 794 u32 tx_count; 795 u16 tx_mpdu_len; 796 797 u8 tx_rate_mode; 798 u8 tx_rate_idx; 799 u8 tx_rate_nss; 800 u8 tx_rate_sgi; 801 u8 tx_rate_ldpc; 802 u8 tx_rate_stbc; 803 u8 tx_ltf; 804 805 u8 tx_antenna_mask; 806 u8 tx_spe_idx; 807 808 u8 tx_duty_cycle; 809 u32 tx_time; 810 u32 tx_ipg; 811 812 u32 freq_offset; 813 814 u8 tx_power[4]; 815 u8 tx_power_control; 816 817 u8 addr[3][ETH_ALEN]; 818 819 u32 tx_pending; 820 u32 tx_queued; 821 u16 tx_queued_limit; 822 u32 tx_done; 823 struct { 824 u64 packets[__MT_RXQ_MAX]; 825 u64 fcs_error[__MT_RXQ_MAX]; 826 } rx_stats; 827 }; 828 829 struct mt76_vif_link { 830 u8 idx; 831 u8 link_idx; 832 u8 omac_idx; 833 u8 band_idx; 834 u8 wmm_idx; 835 u8 scan_seq_num; 836 u8 cipher; 837 u8 basic_rates_idx; 838 u8 mcast_rates_idx; 839 u8 beacon_rates_idx; 840 bool offchannel; 841 struct ieee80211_chanctx_conf *ctx; 842 struct mt76_wcid *wcid; 843 struct mt76_vif_data *mvif; 844 struct rcu_head rcu_head; 845 }; 846 847 struct mt76_vif_data { 848 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 849 struct mt76_vif_link __rcu *offchannel_link; 850 851 struct mt76_phy *roc_phy; 852 u16 valid_links; 853 u8 deflink_id; 854 }; 855 856 struct mt76_phy { 857 struct ieee80211_hw *hw; 858 struct mt76_dev *dev; 859 void *priv; 860 861 unsigned long state; 862 unsigned int num_sta; 863 u8 band_idx; 864 865 spinlock_t tx_lock; 866 struct list_head tx_list; 867 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 868 869 struct cfg80211_chan_def chandef; 870 struct cfg80211_chan_def main_chandef; 871 bool offchannel; 872 bool radar_enabled; 873 874 struct delayed_work roc_work; 875 struct ieee80211_vif *roc_vif; 876 struct mt76_vif_link *roc_link; 877 878 struct mt76_chanctx *chanctx; 879 880 struct mt76_channel_state *chan_state; 881 enum mt76_dfs_state dfs_state; 882 ktime_t survey_time; 883 884 u32 aggr_stats[32]; 885 886 struct mt76_hw_cap cap; 887 struct mt76_sband sband_2g; 888 struct mt76_sband sband_5g; 889 struct mt76_sband sband_6g; 890 891 u8 macaddr[ETH_ALEN]; 892 893 int txpower_cur; 894 u8 antenna_mask; 895 u16 chainmask; 896 897 #ifdef CONFIG_NL80211_TESTMODE 898 struct mt76_testmode_data test; 899 #endif 900 901 struct delayed_work mac_work; 902 u8 mac_work_count; 903 904 struct { 905 struct sk_buff *head; 906 struct sk_buff **tail; 907 u16 seqno; 908 } rx_amsdu[__MT_RXQ_MAX]; 909 910 struct mt76_freq_range_power *frp; 911 912 struct { 913 struct led_classdev cdev; 914 char name[32]; 915 bool al; 916 u8 pin; 917 } leds; 918 }; 919 920 struct mt76_dev { 921 struct mt76_phy phy; /* must be first */ 922 struct mt76_phy *phys[__MT_MAX_BAND]; 923 struct mt76_phy *band_phys[NUM_NL80211_BANDS]; 924 925 struct ieee80211_hw *hw; 926 927 spinlock_t wed_lock; 928 spinlock_t lock; 929 spinlock_t cc_lock; 930 931 u32 cur_cc_bss_rx; 932 933 struct mt76_rx_status rx_ampdu_status; 934 u32 rx_ampdu_len; 935 u32 rx_ampdu_ref; 936 937 struct mutex mutex; 938 939 const struct mt76_bus_ops *bus; 940 const struct mt76_driver_ops *drv; 941 const struct mt76_mcu_ops *mcu_ops; 942 struct device *dev; 943 struct device *dma_dev; 944 945 struct mt76_mcu mcu; 946 947 struct net_device *napi_dev; 948 struct net_device *tx_napi_dev; 949 spinlock_t rx_lock; 950 struct napi_struct napi[__MT_RXQ_MAX]; 951 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 952 struct tasklet_struct irq_tasklet; 953 954 struct list_head txwi_cache; 955 struct list_head rxwi_cache; 956 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 957 struct mt76_queue q_rx[__MT_RXQ_MAX]; 958 const struct mt76_queue_ops *queue_ops; 959 int tx_dma_idx[4]; 960 enum mt76_hwrro_mode hwrro_mode; 961 962 struct mt76_worker tx_worker; 963 struct napi_struct tx_napi; 964 965 spinlock_t token_lock; 966 struct idr token; 967 u16 wed_token_count; 968 u16 token_count; 969 u16 token_start; 970 u16 token_size; 971 972 spinlock_t rx_token_lock; 973 struct idr rx_token; 974 u16 rx_token_size; 975 976 wait_queue_head_t tx_wait; 977 /* spinclock used to protect wcid pktid linked list */ 978 spinlock_t status_lock; 979 980 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 981 982 u64 vif_mask; 983 984 struct mt76_wcid global_wcid; 985 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 986 struct list_head wcid_list; 987 988 struct list_head sta_poll_list; 989 spinlock_t sta_poll_lock; 990 991 u32 rev; 992 993 struct tasklet_struct pre_tbtt_tasklet; 994 int beacon_int; 995 u8 beacon_mask; 996 997 struct debugfs_blob_wrapper eeprom; 998 struct debugfs_blob_wrapper otp; 999 1000 char alpha2[3]; 1001 enum nl80211_dfs_regions region; 1002 1003 struct mt76_scan_rnr_param rnr; 1004 1005 u32 debugfs_reg; 1006 1007 u8 csa_complete; 1008 1009 u32 rxfilter; 1010 1011 struct delayed_work scan_work; 1012 struct { 1013 struct cfg80211_scan_request *req; 1014 struct ieee80211_channel *chan; 1015 struct ieee80211_vif *vif; 1016 struct mt76_vif_link *mlink; 1017 struct mt76_phy *phy; 1018 int chan_idx; 1019 } scan; 1020 1021 #ifdef CONFIG_NL80211_TESTMODE 1022 const struct mt76_testmode_ops *test_ops; 1023 struct { 1024 const char *name; 1025 u32 offset; 1026 } test_mtd; 1027 #endif 1028 struct workqueue_struct *wq; 1029 #if defined(__FreeBSD__) 1030 struct completion drv_start_complete; 1031 #endif 1032 1033 union { 1034 struct mt76_mmio mmio; 1035 struct mt76_usb usb; 1036 struct mt76_sdio sdio; 1037 }; 1038 1039 atomic_t bus_hung; 1040 }; 1041 1042 /* per-phy stats. */ 1043 struct mt76_mib_stats { 1044 u32 ack_fail_cnt; 1045 u32 fcs_err_cnt; 1046 u32 rts_cnt; 1047 u32 rts_retries_cnt; 1048 u32 ba_miss_cnt; 1049 u32 tx_bf_cnt; 1050 u32 tx_mu_bf_cnt; 1051 u32 tx_mu_mpdu_cnt; 1052 u32 tx_mu_acked_mpdu_cnt; 1053 u32 tx_su_acked_mpdu_cnt; 1054 u32 tx_bf_ibf_ppdu_cnt; 1055 u32 tx_bf_ebf_ppdu_cnt; 1056 1057 u32 tx_bf_rx_fb_all_cnt; 1058 u32 tx_bf_rx_fb_eht_cnt; 1059 u32 tx_bf_rx_fb_he_cnt; 1060 u32 tx_bf_rx_fb_vht_cnt; 1061 u32 tx_bf_rx_fb_ht_cnt; 1062 1063 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 1064 u32 tx_bf_rx_fb_nc_cnt; 1065 u32 tx_bf_rx_fb_nr_cnt; 1066 u32 tx_bf_fb_cpl_cnt; 1067 u32 tx_bf_fb_trig_cnt; 1068 1069 u32 tx_ampdu_cnt; 1070 u32 tx_stop_q_empty_cnt; 1071 u32 tx_mpdu_attempts_cnt; 1072 u32 tx_mpdu_success_cnt; 1073 u32 tx_pkt_ebf_cnt; 1074 u32 tx_pkt_ibf_cnt; 1075 1076 u32 tx_rwp_fail_cnt; 1077 u32 tx_rwp_need_cnt; 1078 1079 /* rx stats */ 1080 u32 rx_fifo_full_cnt; 1081 u32 channel_idle_cnt; 1082 u32 primary_cca_busy_time; 1083 u32 secondary_cca_busy_time; 1084 u32 primary_energy_detect_time; 1085 u32 cck_mdrdy_time; 1086 u32 ofdm_mdrdy_time; 1087 u32 green_mdrdy_time; 1088 u32 rx_vector_mismatch_cnt; 1089 u32 rx_delimiter_fail_cnt; 1090 u32 rx_mrdy_cnt; 1091 u32 rx_len_mismatch_cnt; 1092 u32 rx_mpdu_cnt; 1093 u32 rx_ampdu_cnt; 1094 u32 rx_ampdu_bytes_cnt; 1095 u32 rx_ampdu_valid_subframe_cnt; 1096 u32 rx_ampdu_valid_subframe_bytes_cnt; 1097 u32 rx_pfdrop_cnt; 1098 u32 rx_vec_queue_overflow_drop_cnt; 1099 u32 rx_ba_cnt; 1100 1101 u32 tx_amsdu[8]; 1102 u32 tx_amsdu_cnt; 1103 1104 /* mcu_muru_stats */ 1105 u32 dl_cck_cnt; 1106 u32 dl_ofdm_cnt; 1107 u32 dl_htmix_cnt; 1108 u32 dl_htgf_cnt; 1109 u32 dl_vht_su_cnt; 1110 u32 dl_vht_2mu_cnt; 1111 u32 dl_vht_3mu_cnt; 1112 u32 dl_vht_4mu_cnt; 1113 u32 dl_he_su_cnt; 1114 u32 dl_he_ext_su_cnt; 1115 u32 dl_he_2ru_cnt; 1116 u32 dl_he_2mu_cnt; 1117 u32 dl_he_3ru_cnt; 1118 u32 dl_he_3mu_cnt; 1119 u32 dl_he_4ru_cnt; 1120 u32 dl_he_4mu_cnt; 1121 u32 dl_he_5to8ru_cnt; 1122 u32 dl_he_9to16ru_cnt; 1123 u32 dl_he_gtr16ru_cnt; 1124 1125 u32 ul_hetrig_su_cnt; 1126 u32 ul_hetrig_2ru_cnt; 1127 u32 ul_hetrig_3ru_cnt; 1128 u32 ul_hetrig_4ru_cnt; 1129 u32 ul_hetrig_5to8ru_cnt; 1130 u32 ul_hetrig_9to16ru_cnt; 1131 u32 ul_hetrig_gtr16ru_cnt; 1132 u32 ul_hetrig_2mu_cnt; 1133 u32 ul_hetrig_3mu_cnt; 1134 u32 ul_hetrig_4mu_cnt; 1135 }; 1136 1137 struct mt76_power_limits { 1138 s8 cck[4]; 1139 s8 ofdm[8]; 1140 s8 mcs[4][10]; 1141 s8 ru[7][12]; 1142 s8 eht[16][16]; 1143 1144 struct { 1145 s8 cck[4]; 1146 s8 ofdm[4]; 1147 s8 ofdm_bf[4]; 1148 s8 ru[7][10]; 1149 s8 ru_bf[7][10]; 1150 } path; 1151 }; 1152 1153 struct mt76_ethtool_worker_info { 1154 u64 *data; 1155 int idx; 1156 int initial_stat_idx; 1157 int worker_stat_count; 1158 int sta_count; 1159 }; 1160 1161 struct mt76_chanctx { 1162 struct mt76_phy *phy; 1163 }; 1164 1165 #define CCK_RATE(_idx, _rate) { \ 1166 .bitrate = _rate, \ 1167 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 1168 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 1169 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 1170 } 1171 1172 #define OFDM_RATE(_idx, _rate) { \ 1173 .bitrate = _rate, \ 1174 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1175 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1176 } 1177 1178 extern struct ieee80211_rate mt76_rates[12]; 1179 1180 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1181 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1182 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1183 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1184 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1185 1186 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1187 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1188 1189 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1190 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1191 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1192 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1193 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1194 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1195 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1196 1197 1198 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1199 1200 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1201 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1202 1203 #define mt76_get_field(_dev, _reg, _field) \ 1204 FIELD_GET(_field, mt76_rr(dev, _reg)) 1205 1206 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1207 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1208 1209 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1210 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1211 1212 #define mt76_hw(dev) (dev)->mphy.hw 1213 1214 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1215 int timeout); 1216 1217 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1218 1219 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1220 int timeout, int kick); 1221 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1222 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1223 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1224 1225 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1226 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1227 bool mt76_pci_aspm_supported(struct pci_dev *pdev); 1228 1229 static inline u16 mt76_chip(struct mt76_dev *dev) 1230 { 1231 return dev->rev >> 16; 1232 } 1233 1234 static inline u16 mt76_rev(struct mt76_dev *dev) 1235 { 1236 return dev->rev & 0xffff; 1237 } 1238 1239 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed); 1240 void mt76_wed_offload_disable(struct mtk_wed_device *wed); 1241 void mt76_wed_reset_complete(struct mtk_wed_device *wed); 1242 void mt76_wed_dma_reset(struct mt76_dev *dev); 1243 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1244 struct net_device *netdev, enum tc_setup_type type, 1245 void *type_data); 1246 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1247 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size); 1248 int mt76_wed_offload_enable(struct mtk_wed_device *wed); 1249 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); 1250 #else 1251 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size) 1252 { 1253 return 0; 1254 } 1255 1256 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed) 1257 { 1258 return 0; 1259 } 1260 1261 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, 1262 bool reset) 1263 { 1264 return 0; 1265 } 1266 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1267 1268 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1269 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1270 1271 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1272 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1273 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1274 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1275 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1276 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1277 #define mt76_queue_rx_init(dev, ...) (dev)->mt76.queue_ops->rx_queue_init(&((dev)->mt76), __VA_ARGS__) 1278 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1279 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1280 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1281 1282 #define mt76_for_each_q_rx(dev, i) \ 1283 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1284 if ((dev)->q_rx[i].ndesc) 1285 1286 1287 #define mt76_dereference(p, dev) \ 1288 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex)) 1289 1290 static inline struct mt76_dev *mt76_wed_to_dev(struct mtk_wed_device *wed) 1291 { 1292 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1293 if (wed->wlan.hif2) 1294 return container_of(wed, struct mt76_dev, mmio.wed_hif2); 1295 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1296 return container_of(wed, struct mt76_dev, mmio.wed); 1297 } 1298 1299 static inline struct mt76_wcid * 1300 __mt76_wcid_ptr(struct mt76_dev *dev, u16 idx) 1301 { 1302 if (idx >= ARRAY_SIZE(dev->wcid)) 1303 return NULL; 1304 return rcu_dereference(dev->wcid[idx]); 1305 } 1306 1307 #define mt76_wcid_ptr(dev, idx) __mt76_wcid_ptr(&(dev)->mt76, idx) 1308 1309 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1310 const struct ieee80211_ops *ops, 1311 const struct mt76_driver_ops *drv_ops); 1312 int mt76_register_device(struct mt76_dev *dev, bool vht, 1313 struct ieee80211_rate *rates, int n_rates); 1314 void mt76_unregister_device(struct mt76_dev *dev); 1315 void mt76_free_device(struct mt76_dev *dev); 1316 void mt76_reset_device(struct mt76_dev *dev); 1317 void mt76_unregister_phy(struct mt76_phy *phy); 1318 1319 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size, 1320 u8 band_idx); 1321 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1322 const struct ieee80211_ops *ops, 1323 u8 band_idx); 1324 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1325 struct ieee80211_rate *rates, int n_rates); 1326 struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw, 1327 struct ieee80211_vif *vif); 1328 1329 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1330 const struct file_operations *ops); 1331 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1332 { 1333 return mt76_register_debugfs_fops(&dev->phy, NULL); 1334 } 1335 1336 int mt76_queues_read(struct seq_file *s, void *data); 1337 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1338 s8 *val, int len); 1339 1340 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1341 int mt76_eeprom_override(struct mt76_phy *phy); 1342 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1343 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1344 const char *cell_name, int len); 1345 1346 struct mt76_queue * 1347 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1348 int ring_base, void *wed, u32 flags); 1349 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1350 int n_desc, int ring_base, void *wed, 1351 u32 flags) 1352 { 1353 struct mt76_queue *q; 1354 1355 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags); 1356 if (IS_ERR(q)) 1357 return PTR_ERR(q); 1358 1359 phy->q_tx[qid] = q; 1360 1361 return 0; 1362 } 1363 1364 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1365 int n_desc, int ring_base) 1366 { 1367 struct mt76_queue *q; 1368 1369 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0); 1370 if (IS_ERR(q)) 1371 return PTR_ERR(q); 1372 1373 dev->q_mcu[qid] = q; 1374 1375 return 0; 1376 } 1377 1378 static inline struct mt76_phy * 1379 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1380 { 1381 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1382 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1383 return dev->phys[phy_idx]; 1384 1385 return &dev->phy; 1386 } 1387 1388 static inline struct ieee80211_hw * 1389 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1390 { 1391 return mt76_dev_phy(dev, phy_idx)->hw; 1392 } 1393 1394 static inline u8 * 1395 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1396 { 1397 return (u8 *)t - dev->drv->txwi_size; 1398 } 1399 1400 /* increment with wrap-around */ 1401 static inline int mt76_incr(int val, int size) 1402 { 1403 return (val + 1) & (size - 1); 1404 } 1405 1406 /* decrement with wrap-around */ 1407 static inline int mt76_decr(int val, int size) 1408 { 1409 return (val - 1) & (size - 1); 1410 } 1411 1412 u8 mt76_ac_to_hwq(u8 ac); 1413 1414 static inline struct ieee80211_txq * 1415 mtxq_to_txq(struct mt76_txq *mtxq) 1416 { 1417 void *ptr = mtxq; 1418 1419 return container_of(ptr, struct ieee80211_txq, drv_priv); 1420 } 1421 1422 static inline struct ieee80211_sta * 1423 wcid_to_sta(struct mt76_wcid *wcid) 1424 { 1425 void *ptr = wcid; 1426 1427 if (!wcid || !wcid->sta) 1428 return NULL; 1429 1430 if (wcid->def_wcid) 1431 ptr = wcid->def_wcid; 1432 1433 return container_of(ptr, struct ieee80211_sta, drv_priv); 1434 } 1435 1436 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1437 { 1438 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1439 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1440 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1441 } 1442 1443 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1444 { 1445 struct mt76_rx_status mstat; 1446 u8 *data = skb->data; 1447 1448 /* Alignment concerns */ 1449 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1450 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1451 1452 mstat = *((struct mt76_rx_status *)skb->cb); 1453 1454 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1455 data += sizeof(struct ieee80211_radiotap_he); 1456 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1457 data += sizeof(struct ieee80211_radiotap_he_mu); 1458 1459 return data; 1460 } 1461 1462 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1463 { 1464 int len = ieee80211_get_hdrlen_from_skb(skb); 1465 1466 if (len % 4 == 0) 1467 return; 1468 1469 skb_push(skb, 2); 1470 memmove(skb->data, skb->data + 2, len); 1471 1472 skb->data[len] = 0; 1473 skb->data[len + 1] = 0; 1474 } 1475 1476 static inline bool mt76_is_skb_pktid(u8 pktid) 1477 { 1478 if (pktid & MT_PACKET_ID_HAS_RATE) 1479 return false; 1480 1481 return pktid >= MT_PACKET_ID_FIRST; 1482 } 1483 1484 static inline u8 mt76_tx_power_path_delta(u8 path) 1485 { 1486 static const u8 path_delta[5] = { 0, 6, 9, 12, 14 }; 1487 u8 idx = path - 1; 1488 1489 return (idx < ARRAY_SIZE(path_delta)) ? path_delta[idx] : 0; 1490 } 1491 1492 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1493 { 1494 #ifdef CONFIG_NL80211_TESTMODE 1495 return phy->test.state != MT76_TM_STATE_OFF; 1496 #else 1497 return false; 1498 #endif 1499 } 1500 1501 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1502 struct sk_buff *skb, 1503 struct ieee80211_hw **hw) 1504 { 1505 #ifdef CONFIG_NL80211_TESTMODE 1506 int i; 1507 1508 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1509 struct mt76_phy *phy = dev->phys[i]; 1510 1511 if (phy && skb == phy->test.tx_skb) { 1512 *hw = dev->phys[i]->hw; 1513 return true; 1514 } 1515 } 1516 return false; 1517 #else 1518 return false; 1519 #endif 1520 } 1521 1522 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1523 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1524 struct mt76_wcid *wcid, struct sk_buff *skb); 1525 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1526 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1527 bool send_bar); 1528 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1529 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1530 void mt76_txq_schedule_all(struct mt76_phy *phy); 1531 void mt76_tx_worker_run(struct mt76_dev *dev); 1532 void mt76_tx_worker(struct mt76_worker *w); 1533 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1534 struct ieee80211_sta *sta, 1535 u16 tids, int nframes, 1536 enum ieee80211_frame_release_type reason, 1537 bool more_data); 1538 bool mt76_has_tx_pending(struct mt76_phy *phy); 1539 int mt76_update_channel(struct mt76_phy *phy); 1540 void mt76_update_survey(struct mt76_phy *phy); 1541 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1542 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1543 struct survey_info *survey); 1544 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1545 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1546 1547 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1548 u16 ssn, u16 size); 1549 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1550 1551 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1552 struct ieee80211_key_conf *key); 1553 1554 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1555 __acquires(&dev->status_lock); 1556 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1557 __releases(&dev->status_lock); 1558 1559 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1560 struct sk_buff *skb); 1561 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1562 struct mt76_wcid *wcid, int pktid, 1563 struct sk_buff_head *list); 1564 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1565 struct sk_buff_head *list); 1566 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1567 struct list_head *free_list); 1568 static inline void 1569 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1570 { 1571 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1572 } 1573 1574 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1575 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1576 struct ieee80211_sta *sta, 1577 enum ieee80211_sta_state old_state, 1578 enum ieee80211_sta_state new_state); 1579 void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif, 1580 struct ieee80211_sta *sta); 1581 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1582 struct ieee80211_sta *sta); 1583 1584 int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx); 1585 1586 s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower); 1587 1588 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1589 unsigned int link_id, int *dbm); 1590 int mt76_init_sar_power(struct ieee80211_hw *hw, 1591 const struct cfg80211_sar_specs *sar); 1592 int mt76_get_sar_power(struct mt76_phy *phy, 1593 struct ieee80211_channel *chan, 1594 int power); 1595 1596 void mt76_csa_check(struct mt76_dev *dev); 1597 void mt76_csa_finish(struct mt76_dev *dev); 1598 1599 int mt76_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant, 1600 u32 *rx_ant); 1601 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1602 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1603 int mt76_get_rate(struct mt76_dev *dev, 1604 struct ieee80211_supported_band *sband, 1605 int idx, bool cck); 1606 int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1607 struct ieee80211_scan_request *hw_req); 1608 void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1609 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1610 const u8 *mac); 1611 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1612 struct ieee80211_vif *vif); 1613 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1614 int mt76_add_chanctx(struct ieee80211_hw *hw, 1615 struct ieee80211_chanctx_conf *conf); 1616 void mt76_remove_chanctx(struct ieee80211_hw *hw, 1617 struct ieee80211_chanctx_conf *conf); 1618 void mt76_change_chanctx(struct ieee80211_hw *hw, 1619 struct ieee80211_chanctx_conf *conf, 1620 u32 changed); 1621 int mt76_assign_vif_chanctx(struct ieee80211_hw *hw, 1622 struct ieee80211_vif *vif, 1623 struct ieee80211_bss_conf *link_conf, 1624 struct ieee80211_chanctx_conf *conf); 1625 void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw, 1626 struct ieee80211_vif *vif, 1627 struct ieee80211_bss_conf *link_conf, 1628 struct ieee80211_chanctx_conf *conf); 1629 int mt76_switch_vif_chanctx(struct ieee80211_hw *hw, 1630 struct ieee80211_vif_chanctx_switch *vifs, 1631 int n_vifs, 1632 enum ieee80211_chanctx_switch_mode mode); 1633 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1634 struct ieee80211_channel *chan, int duration, 1635 enum ieee80211_roc_type type); 1636 int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw, 1637 struct ieee80211_vif *vif); 1638 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1639 void *data, int len); 1640 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1641 struct netlink_callback *cb, void *data, int len); 1642 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1643 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1644 1645 #ifdef CONFIG_MT76_NPU 1646 void mt76_npu_check_ppe(struct mt76_dev *dev, struct sk_buff *skb, 1647 u32 info); 1648 int mt76_npu_dma_add_buf(struct mt76_phy *phy, struct mt76_queue *q, 1649 struct sk_buff *skb, struct mt76_queue_buf *buf, 1650 void *txwi_ptr); 1651 int mt76_npu_rx_queue_init(struct mt76_dev *dev, struct mt76_queue *q); 1652 int mt76_npu_fill_rx_queue(struct mt76_dev *dev, struct mt76_queue *q); 1653 void mt76_npu_queue_cleanup(struct mt76_dev *dev, struct mt76_queue *q); 1654 void mt76_npu_disable_irqs(struct mt76_dev *dev); 1655 int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr, int type); 1656 void mt76_npu_deinit(struct mt76_dev *dev); 1657 void mt76_npu_queue_setup(struct mt76_dev *dev, struct mt76_queue *q); 1658 void mt76_npu_txdesc_cleanup(struct mt76_queue *q, int index); 1659 int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1660 struct net_device *dev, enum tc_setup_type type, 1661 void *type_data); 1662 #else 1663 static inline void mt76_npu_check_ppe(struct mt76_dev *dev, 1664 struct sk_buff *skb, u32 info) 1665 { 1666 } 1667 1668 static inline int mt76_npu_dma_add_buf(struct mt76_phy *phy, 1669 struct mt76_queue *q, 1670 struct sk_buff *skb, 1671 struct mt76_queue_buf *buf, 1672 void *txwi_ptr) 1673 { 1674 return -EOPNOTSUPP; 1675 } 1676 1677 static inline int mt76_npu_fill_rx_queue(struct mt76_dev *dev, 1678 struct mt76_queue *q) 1679 { 1680 return 0; 1681 } 1682 1683 static inline void mt76_npu_queue_cleanup(struct mt76_dev *dev, 1684 struct mt76_queue *q) 1685 { 1686 } 1687 1688 static inline void mt76_npu_disable_irqs(struct mt76_dev *dev) 1689 { 1690 } 1691 1692 static inline int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr, 1693 int type) 1694 { 1695 return 0; 1696 } 1697 1698 static inline void mt76_npu_deinit(struct mt76_dev *dev) 1699 { 1700 } 1701 1702 static inline void mt76_npu_queue_setup(struct mt76_dev *dev, 1703 struct mt76_queue *q) 1704 { 1705 } 1706 1707 static inline void mt76_npu_txdesc_cleanup(struct mt76_queue *q, 1708 int index) 1709 { 1710 } 1711 1712 static inline int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, 1713 struct ieee80211_vif *vif, 1714 struct net_device *dev, 1715 enum tc_setup_type type, 1716 void *type_data) 1717 { 1718 return -EOPNOTSUPP; 1719 } 1720 #endif /* CONFIG_MT76_NPU */ 1721 1722 static inline bool mt76_npu_device_active(struct mt76_dev *dev) 1723 { 1724 return !!rcu_access_pointer(dev->mmio.npu); 1725 } 1726 1727 static inline bool mt76_ppe_device_active(struct mt76_dev *dev) 1728 { 1729 return !!rcu_access_pointer(dev->mmio.ppe_dev); 1730 } 1731 1732 static inline int mt76_npu_send_msg(struct airoha_npu *npu, int ifindex, 1733 enum airoha_npu_wlan_set_cmd cmd, 1734 u32 val, gfp_t gfp) 1735 { 1736 return airoha_npu_wlan_send_msg(npu, ifindex, cmd, &val, sizeof(val), 1737 gfp); 1738 } 1739 1740 static inline int mt76_npu_get_msg(struct airoha_npu *npu, int ifindex, 1741 enum airoha_npu_wlan_get_cmd cmd, 1742 u32 *val, gfp_t gfp) 1743 { 1744 return airoha_npu_wlan_get_msg(npu, ifindex, cmd, val, sizeof(*val), 1745 gfp); 1746 } 1747 1748 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1749 { 1750 #ifdef CONFIG_NL80211_TESTMODE 1751 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1752 1753 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1754 state = MT76_TM_STATE_OFF; 1755 1756 mt76_testmode_set_state(phy, state); 1757 #endif 1758 } 1759 1760 1761 /* internal */ 1762 static inline struct ieee80211_hw * 1763 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1764 { 1765 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1766 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1767 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1768 1769 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1770 1771 return hw; 1772 } 1773 1774 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1775 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1776 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1777 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1778 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1779 struct napi_struct *napi); 1780 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1781 struct napi_struct *napi); 1782 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1783 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1784 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1785 struct mt76_queue_entry *e); 1786 int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1787 bool offchannel); 1788 int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1789 bool offchannel); 1790 void mt76_scan_work(struct work_struct *work); 1791 void mt76_abort_scan(struct mt76_dev *dev); 1792 void mt76_roc_complete_work(struct work_struct *work); 1793 void mt76_roc_complete(struct mt76_phy *phy); 1794 void mt76_abort_roc(struct mt76_phy *phy); 1795 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy, 1796 struct ieee80211_vif *vif); 1797 void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif, 1798 struct mt76_vif_link *mlink); 1799 1800 /* usb */ 1801 static inline bool mt76u_urb_error(struct urb *urb) 1802 { 1803 return urb->status && 1804 urb->status != -ECONNRESET && 1805 urb->status != -ESHUTDOWN && 1806 urb->status != -ENOENT; 1807 } 1808 1809 static inline int 1810 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1811 int timeout, int ep) 1812 { 1813 #if defined(__FreeBSD__) && !defined(CONFIG_USB) 1814 return (0); 1815 #else 1816 struct usb_interface *uintf = to_usb_interface(dev->dev); 1817 struct usb_device *udev = interface_to_usbdev(uintf); 1818 struct mt76_usb *usb = &dev->usb; 1819 unsigned int pipe; 1820 1821 if (actual_len) 1822 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1823 else 1824 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1825 1826 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1827 #endif 1828 } 1829 1830 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1831 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1832 struct mt76_sta_stats *stats, bool eht); 1833 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1834 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1835 u16 val, u16 offset, void *buf, size_t len); 1836 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1837 u8 req_type, u16 val, u16 offset, 1838 void *buf, size_t len); 1839 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1840 const u16 offset, const u32 val); 1841 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1842 void *data, int len); 1843 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1844 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1845 u32 addr, u32 val); 1846 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1847 struct mt76_bus_ops *ops); 1848 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1849 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1850 int mt76u_alloc_queues(struct mt76_dev *dev); 1851 void mt76u_stop_tx(struct mt76_dev *dev); 1852 void mt76u_stop_rx(struct mt76_dev *dev); 1853 int mt76u_resume_rx(struct mt76_dev *dev); 1854 void mt76u_queues_deinit(struct mt76_dev *dev); 1855 1856 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1857 const struct mt76_bus_ops *bus_ops); 1858 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1859 int mt76s_alloc_tx(struct mt76_dev *dev); 1860 void mt76s_deinit(struct mt76_dev *dev); 1861 void mt76s_sdio_irq(struct sdio_func *func); 1862 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1863 bool mt76s_txqs_empty(struct mt76_dev *dev); 1864 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1865 int hw_ver); 1866 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1867 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1868 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1869 u32 mt76s_read_pcr(struct mt76_dev *dev); 1870 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1871 const void *data, int len); 1872 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1873 void *data, int len); 1874 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1875 const struct mt76_reg_pair *data, 1876 int len); 1877 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1878 struct mt76_reg_pair *data, int len); 1879 1880 struct sk_buff * 1881 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1882 int len, int data_len, gfp_t gfp); 1883 static inline struct sk_buff * 1884 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1885 int data_len) 1886 { 1887 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1888 } 1889 1890 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1891 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1892 unsigned long expires); 1893 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1894 int len, bool wait_resp, struct sk_buff **ret); 1895 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1896 int cmd, bool wait_resp, struct sk_buff **ret); 1897 #if defined(__linux__) 1898 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1899 #elif defined(__FreeBSD__) 1900 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const u8 *data, 1901 #endif 1902 int len, int max_len); 1903 static inline int 1904 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1905 int len) 1906 { 1907 int max_len = 4096 - dev->mcu_ops->headroom; 1908 1909 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1910 } 1911 1912 static inline int 1913 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1914 bool wait_resp) 1915 { 1916 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1917 } 1918 1919 static inline int 1920 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1921 bool wait_resp) 1922 { 1923 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1924 } 1925 1926 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1927 1928 struct device_node * 1929 mt76_find_power_limits_node(struct mt76_dev *dev); 1930 struct device_node * 1931 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1932 1933 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1934 struct ieee80211_channel *chan, 1935 struct mt76_power_limits *dest, 1936 s8 target_power); 1937 1938 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q) 1939 { 1940 int i; 1941 1942 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 1943 if (q == &dev->q_rx[i]) 1944 return true; 1945 } 1946 1947 return false; 1948 } 1949 1950 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q) 1951 { 1952 return (q->flags & MT_QFLAG_WED) && 1953 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 1954 } 1955 1956 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q) 1957 { 1958 return q->flags & MT_QFLAG_WED_RRO; 1959 } 1960 1961 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q) 1962 { 1963 return mt76_queue_is_wed_rro(q) && 1964 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1965 } 1966 1967 static inline bool mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue *q) 1968 { 1969 return mt76_queue_is_wed_rro(q) && 1970 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_RXDMAD_C; 1971 } 1972 1973 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1974 { 1975 return mt76_queue_is_wed_rro(q) && 1976 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA; 1977 } 1978 1979 static inline bool mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue *q) 1980 { 1981 return mt76_queue_is_wed_rro(q) && 1982 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == 1983 MT76_WED_RRO_Q_MSDU_PG; 1984 } 1985 1986 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1987 { 1988 return (q->flags & MT_QFLAG_WED) && 1989 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1990 } 1991 1992 static inline bool mt76_queue_is_emi(struct mt76_queue *q) 1993 { 1994 return q->flags & MT_QFLAG_EMI_EN; 1995 } 1996 1997 static inline bool mt76_queue_is_npu(struct mt76_queue *q) 1998 { 1999 return q->flags & MT_QFLAG_NPU; 2000 } 2001 2002 static inline bool mt76_queue_is_npu_tx(struct mt76_queue *q) 2003 { 2004 return mt76_queue_is_npu(q) && 2005 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TX; 2006 } 2007 2008 static inline bool mt76_queue_is_npu_rx(struct mt76_queue *q) 2009 { 2010 return mt76_queue_is_npu(q) && 2011 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 2012 } 2013 2014 struct mt76_txwi_cache * 2015 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 2016 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 2017 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 2018 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 2019 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 2020 struct mt76_txwi_cache *r, dma_addr_t phys); 2021 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 2022 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 2023 { 2024 struct page *page = virt_to_head_page(buf); 2025 2026 page_pool_put_full_page(pp_page_to_nmdesc(page)->pp, page, 2027 allow_direct); 2028 } 2029 2030 static inline void * 2031 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 2032 { 2033 struct page *page; 2034 2035 page = page_pool_alloc_frag(q->page_pool, offset, size, 2036 GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32); 2037 if (!page) 2038 return NULL; 2039 2040 #if defined(__linux__) 2041 return page_address(page) + *offset; 2042 #elif defined(__FreeBSD__) 2043 return (void *)((uintptr_t)page_address(page) + *offset); 2044 #endif 2045 } 2046 2047 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 2048 { 2049 spin_lock_bh(&dev->token_lock); 2050 __mt76_set_tx_blocked(dev, blocked); 2051 spin_unlock_bh(&dev->token_lock); 2052 } 2053 2054 static inline int 2055 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 2056 { 2057 int token; 2058 2059 spin_lock_bh(&dev->token_lock); 2060 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 2061 spin_unlock_bh(&dev->token_lock); 2062 2063 return token; 2064 } 2065 2066 static inline struct mt76_txwi_cache * 2067 mt76_token_put(struct mt76_dev *dev, int token) 2068 { 2069 struct mt76_txwi_cache *txwi; 2070 2071 spin_lock_bh(&dev->token_lock); 2072 txwi = idr_remove(&dev->token, token); 2073 spin_unlock_bh(&dev->token_lock); 2074 2075 return txwi; 2076 } 2077 2078 void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx); 2079 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 2080 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid); 2081 2082 static inline void 2083 mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif) 2084 { 2085 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 2086 2087 mlink->mvif = mvif; 2088 rcu_assign_pointer(mvif->link[0], mlink); 2089 } 2090 2091 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif); 2092 u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links); 2093 2094 static inline struct mt76_vif_link * 2095 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id) 2096 { 2097 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 2098 struct mt76_vif_data *mvif = mlink->mvif; 2099 2100 if (!link_id) 2101 return mlink; 2102 2103 return mt76_dereference(mvif->link[link_id], dev); 2104 } 2105 2106 static inline struct mt76_vif_link * 2107 mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif, 2108 struct ieee80211_bss_conf *link_conf) 2109 { 2110 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 2111 struct mt76_vif_data *mvif = mlink->mvif; 2112 2113 if (link_conf == &vif->bss_conf || !link_conf->link_id) 2114 return mlink; 2115 2116 return mt76_dereference(mvif->link[link_conf->link_id], dev); 2117 } 2118 2119 static inline struct mt76_phy * 2120 mt76_vif_link_phy(struct mt76_vif_link *mlink) 2121 { 2122 struct mt76_chanctx *ctx; 2123 2124 if (!mlink->ctx) 2125 return NULL; 2126 2127 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv; 2128 2129 return ctx->phy; 2130 } 2131 2132 #endif 2133