1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011, 2025 Chelsio Communications.
5 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 #ifndef __T4_ADAPTER_H__
31 #define __T4_ADAPTER_H__
32
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/counter.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
41 #include <sys/seqc.h>
42 #include <sys/sx.h>
43 #include <sys/vmem.h>
44 #include <vm/uma.h>
45
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <machine/bus.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <sys/taskqueue.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_var.h>
55 #include <net/if_media.h>
56 #include <net/pfil.h>
57 #include <netinet/in.h>
58 #include <netinet/tcp_lro.h>
59
60 #include "offload.h"
61 #include "t4_ioctl.h"
62 #include "common/t4_msg.h"
63 #include "firmware/t4fw_interface.h"
64
65 #define KTR_CXGBE KTR_SPARE3
66 MALLOC_DECLARE(M_CXGBE);
67 #define CXGBE_UNIMPLEMENTED(s) \
68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
69
70 /*
71 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's
72 * LIST_HEAD when building iw_cxgbe.
73 */
74 #define CXGBE_LIST_HEAD(name, type) \
75 struct name { \
76 struct type *lh_first; /* first element */ \
77 }
78
79 #ifndef SYSCTL_ADD_UQUAD
80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
81 #define sysctl_handle_64 sysctl_handle_quad
82 #define CTLTYPE_U64 CTLTYPE_QUAD
83 #endif
84
85 SYSCTL_DECL(_hw_cxgbe);
86
87 struct adapter;
88 typedef struct adapter adapter_t;
89
90 enum {
91 /*
92 * All ingress queues use this entry size. Note that the firmware event
93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
94 * be at least 64.
95 */
96 IQ_ESIZE = 64,
97
98 /* Default queue sizes for all kinds of ingress queues */
99 FW_IQ_QSIZE = 256,
100 RX_IQ_QSIZE = 1024,
101
102 /* All egress queues use this entry size */
103 EQ_ESIZE = 64,
104
105 /* Default queue sizes for all kinds of egress queues */
106 CTRL_EQ_QSIZE = 1024,
107 TX_EQ_QSIZE = 1024,
108
109 #if MJUMPAGESIZE != MCLBYTES
110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
111 #else
112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
113 #endif
114 CL_METADATA_SIZE = CACHE_LINE_SIZE,
115
116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
117 TX_SGL_SEGS = 39,
118 TX_SGL_SEGS_TSO = 38,
119 TX_SGL_SEGS_VM = 38,
120 TX_SGL_SEGS_VM_TSO = 37,
121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
122 TX_SGL_SEGS_VXLAN_TSO = 37,
123 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
124 };
125
126 enum {
127 /* adapter intr_type */
128 INTR_INTX = (1 << 0),
129 INTR_MSI = (1 << 1),
130 INTR_MSIX = (1 << 2)
131 };
132
133 enum {
134 XGMAC_MTU = (1 << 0),
135 XGMAC_PROMISC = (1 << 1),
136 XGMAC_ALLMULTI = (1 << 2),
137 XGMAC_VLANEX = (1 << 3),
138 XGMAC_UCADDR = (1 << 4),
139 XGMAC_MCADDRS = (1 << 5),
140
141 XGMAC_ALL = 0xffff
142 };
143
144 enum {
145 /* flags understood by begin_synchronized_op */
146 HOLD_LOCK = (1 << 0),
147 SLEEP_OK = (1 << 1),
148 INTR_OK = (1 << 2),
149
150 /* flags understood by end_synchronized_op */
151 LOCK_HELD = HOLD_LOCK,
152 };
153
154 enum {
155 /* adapter flags. synch_op or adapter_lock. */
156 FULL_INIT_DONE = (1 << 0),
157 FW_OK = (1 << 1),
158 CHK_MBOX_ACCESS = (1 << 2),
159 MASTER_PF = (1 << 3),
160 BUF_PACKING_OK = (1 << 6),
161 IS_VF = (1 << 7),
162 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */
163 CXGBE_BUSY = (1 << 9),
164
165 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */
166 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */
167 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */
168 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */
169 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */
170
171 /* port flags */
172 HAS_TRACEQ = (1 << 3),
173 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
174
175 /* VI flags */
176 VI_DETACHING = (1 << 0),
177 VI_INIT_DONE = (1 << 1),
178 /* 1 << 2 is unused, was VI_SYSCTL_CTX */
179 TX_USES_VM_WR = (1 << 3),
180 VI_SKIP_STATS = (1 << 4),
181
182 /* adapter debug_flags */
183 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
184 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
185 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
186 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
187 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
188 };
189
190 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING)
191 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0)
192 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0)
193 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
194 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
195 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
196
197 struct vi_info {
198 device_t dev;
199 struct port_info *pi;
200 struct adapter *adapter;
201
202 if_t ifp;
203 struct pfil_head *pfil;
204
205 unsigned long flags;
206 int if_flags;
207
208 uint16_t *rss, *nm_rss;
209 uint16_t viid; /* opaque VI identifier */
210 uint16_t smt_idx;
211 uint16_t vin;
212 uint8_t vfvld;
213 int16_t xact_addr_filt;/* index of exact MAC address filter */
214 uint16_t rss_size; /* size of VI's RSS table slice */
215 uint16_t rss_base; /* start of VI's RSS table slice */
216 int hashen;
217
218 int nintr;
219 int first_intr;
220
221 /* These need to be int as they are used in sysctl */
222 int ntxq; /* # of tx queues */
223 int first_txq; /* index of first tx queue */
224 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
225 int nrxq; /* # of rx queues */
226 int first_rxq; /* index of first rx queue */
227 int nofldtxq; /* # of offload tx queues */
228 int first_ofld_txq; /* index of first offload tx queue */
229 int nofldrxq; /* # of offload rx queues */
230 int first_ofld_rxq; /* index of first offload rx queue */
231 int nnmtxq;
232 int first_nm_txq;
233 int nnmrxq;
234 int first_nm_rxq;
235 int tmr_idx;
236 int ofld_tmr_idx;
237 int pktc_idx;
238 int ofld_pktc_idx;
239 int qsize_rxq;
240 int qsize_txq;
241
242 struct timeval last_refreshed;
243 struct fw_vi_stats_vf stats;
244 struct mtx tick_mtx;
245 struct callout tick;
246
247 struct sysctl_ctx_list ctx;
248 struct sysctl_oid *rxq_oid;
249 struct sysctl_oid *txq_oid;
250 struct sysctl_oid *nm_rxq_oid;
251 struct sysctl_oid *nm_txq_oid;
252 struct sysctl_oid *ofld_rxq_oid;
253 struct sysctl_oid *ofld_txq_oid;
254
255 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
256 u_int txq_rr;
257 u_int rxq_rr;
258 };
259
260 struct tx_ch_rl_params {
261 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
262 uint32_t maxrate;
263 };
264
265 /* CLRL state */
266 enum clrl_state {
267 CS_UNINITIALIZED = 0,
268 CS_PARAMS_SET, /* sw parameters have been set. */
269 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */
270 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */
271 CS_HW_CONFIGURED /* configured in the hardware. */
272 };
273
274 /* CLRL flags */
275 enum {
276 CF_USER = (1 << 0), /* was configured by driver ioctl. */
277 };
278
279 struct tx_cl_rl_params {
280 enum clrl_state state;
281 int refcount;
282 uint8_t flags;
283 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
284 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
285 enum fw_sched_params_mode mode; /* aggr or per-flow */
286 uint32_t maxrate;
287 uint16_t pktsize;
288 uint16_t burstsize;
289 };
290
291 /* Tx scheduler parameters for a channel/port */
292 struct tx_sched_params {
293 /* Channel Rate Limiter */
294 struct tx_ch_rl_params ch_rl;
295
296 /* Class WRR */
297 /* XXX */
298
299 /* Class Rate Limiter (including the default pktsize and burstsize). */
300 int pktsize;
301 int burstsize;
302 struct tx_cl_rl_params cl_rl[];
303 };
304
305 struct port_info {
306 device_t dev;
307 struct adapter *adapter;
308
309 struct vi_info *vi;
310 int nvi;
311 int up_vis;
312 int uld_vis;
313 bool vxlan_tcam_entry;
314
315 struct tx_sched_params *sched_params;
316
317 struct mtx pi_lock;
318 char lockname[16];
319 unsigned long flags;
320
321 uint8_t hw_port; /* associated hardware port idx */
322 int8_t mdio_addr;
323 uint8_t port_type;
324 uint8_t mod_type;
325 uint8_t port_id;
326 uint8_t tx_chan; /* tx TP c-channel */
327 uint8_t rx_chan; /* rx TP c-channel */
328 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
329 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
330
331 struct link_config link_cfg;
332 struct ifmedia media;
333
334 struct port_stats stats;
335 u_int tnl_cong_drops;
336 u_int tx_parse_error;
337 int fcs_reg;
338 uint64_t fcs_base;
339
340 struct sysctl_ctx_list ctx;
341 };
342
343 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
344
345 struct cluster_metadata {
346 uma_zone_t zone;
347 caddr_t cl;
348 u_int refcount;
349 };
350
351 struct fl_sdesc {
352 caddr_t cl;
353 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
354 int16_t moff; /* offset of metadata from cl */
355 uint8_t zidx;
356 };
357
358 struct tx_desc {
359 __be64 flit[8];
360 };
361
362 struct tx_sdesc {
363 struct mbuf *m; /* m_nextpkt linked chain of frames */
364 uint8_t desc_used; /* # of hardware descriptors used by the WR */
365 };
366
367
368 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
369 struct iq_desc {
370 struct rss_header rss;
371 uint8_t cpl[IQ_PAD];
372 struct rsp_ctrl rsp;
373 };
374 #undef IQ_PAD
375 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
376
377 enum {
378 /* iq type */
379 IQ_OTHER = FW_IQ_IQTYPE_OTHER,
380 IQ_ETH = FW_IQ_IQTYPE_NIC,
381 IQ_OFLD = FW_IQ_IQTYPE_OFLD,
382
383 /* iq flags */
384 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
385 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
386 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
387 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
388 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
389 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */
390
391 /* iq state */
392 IQS_DISABLED = 0,
393 IQS_BUSY = 1,
394 IQS_IDLE = 2,
395
396 /* netmap related flags */
397 NM_OFF = 0,
398 NM_ON = 1,
399 NM_BUSY = 2,
400 };
401
402 enum {
403 CPL_COOKIE_RESERVED = 0,
404 CPL_COOKIE_FILTER,
405 CPL_COOKIE_DDP0,
406 CPL_COOKIE_DDP1,
407 CPL_COOKIE_TOM,
408 CPL_COOKIE_HASHFILTER,
409 CPL_COOKIE_ETHOFLD,
410 CPL_COOKIE_KERN_TLS,
411
412 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
413 };
414
415 /*
416 * Crypto replies use the low bit in the 64-bit cookie of CPL_FW6_PLD as a
417 * CPL cookie to identify the sender/receiver.
418 */
419 enum {
420 CPL_FW6_COOKIE_CCR = 0,
421 CPL_FW6_COOKIE_KTLS,
422
423 NUM_CPL_FW6_COOKIES = 2 /* Low bits of cookie value. */
424 };
425
426 _Static_assert(powerof2(NUM_CPL_FW6_COOKIES),
427 "NUM_CPL_FW6_COOKIES must be a power of 2");
428
429 #define CPL_FW6_COOKIE_MASK (NUM_CPL_FW6_COOKIES - 1)
430
431 #define CPL_FW6_PLD_COOKIE(cpl) (be64toh((cpl)->data[1]) & ~CPL_FW6_COOKIE_MASK)
432
433 struct sge_iq;
434 struct rss_header;
435 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
436 struct mbuf *);
437 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
438 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
439
440 /*
441 * Ingress Queue: T4 is producer, driver is consumer.
442 */
443 struct sge_iq {
444 uint16_t flags;
445 uint8_t qtype;
446 volatile int state;
447 struct adapter *adapter;
448 struct iq_desc *desc; /* KVA of descriptor ring */
449 int8_t intr_pktc_idx; /* packet count threshold index */
450 uint8_t gen; /* generation bit */
451 uint8_t intr_params; /* interrupt holdoff parameters */
452 int8_t cong_drop; /* congestion drop settings for the queue */
453 uint16_t qsize; /* size (# of entries) of the queue */
454 uint16_t sidx; /* index of the entry with the status page */
455 uint16_t cidx; /* consumer index */
456 uint16_t cntxt_id; /* SGE context id for the iq */
457 uint16_t abs_id; /* absolute SGE id for the iq */
458 int16_t intr_idx; /* interrupt used by the queue */
459
460 STAILQ_ENTRY(sge_iq) link;
461
462 bus_dma_tag_t desc_tag;
463 bus_dmamap_t desc_map;
464 bus_addr_t ba; /* bus address of descriptor ring */
465 };
466
467 enum {
468 /* eq type */
469 EQ_CTRL = 1,
470 EQ_ETH = 2,
471 EQ_OFLD = 3,
472
473 /* eq flags */
474 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
475 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */
476 EQ_ENABLED = (1 << 3), /* open for business */
477 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
478 };
479
480 /* Listed in order of preference. Update t4_sysctls too if you change these */
481 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
482
483 /*
484 * Egress Queue: driver is producer, T4 is consumer.
485 *
486 * Note: A free list is an egress queue (driver produces the buffers and T4
487 * consumes them) but it's special enough to have its own struct (see sge_fl).
488 */
489 struct sge_eq {
490 unsigned int flags; /* MUST be first */
491 unsigned int cntxt_id; /* SGE context id for the eq */
492 unsigned int abs_id; /* absolute SGE id for the eq */
493 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */
494 uint8_t doorbells;
495 uint8_t port_id; /* port_id of the port associated with the eq */
496 uint8_t tx_chan; /* tx channel used by the eq */
497 uint8_t hw_port; /* hw port used by the eq */
498 struct mtx eq_lock;
499
500 struct tx_desc *desc; /* KVA of descriptor ring */
501 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
502 u_int udb_qid; /* relative qid within the doorbell page */
503 uint16_t sidx; /* index of the entry with the status page */
504 uint16_t cidx; /* consumer idx (desc idx) */
505 uint16_t pidx; /* producer idx (desc idx) */
506 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
507 uint16_t dbidx; /* pidx of the most recent doorbell */
508 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */
509 volatile u_int equiq; /* EQUIQ outstanding */
510 struct sge_iq *iq; /* iq that receives egr_update for the eq */
511
512 bus_dma_tag_t desc_tag;
513 bus_dmamap_t desc_map;
514 bus_addr_t ba; /* bus address of descriptor ring */
515 char lockname[16];
516 };
517
518 struct rx_buf_info {
519 uma_zone_t zone; /* zone that this cluster comes from */
520 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K.
521 * hwsize[hwidx1] = size1. No spare. */
522 uint16_t size2; /* hwsize[hwidx2] = size2.
523 * spare in cluster = size1 - size2. */
524 int8_t hwidx1; /* SGE bufsize idx for size1 */
525 int8_t hwidx2; /* SGE bufsize idx for size2 */
526 uint8_t type; /* EXT_xxx type of the cluster */
527 };
528
529 enum {
530 NUM_MEMWIN = 3,
531
532 MEMWIN0_APERTURE = 2048,
533 MEMWIN0_BASE = 0x1b800,
534
535 MEMWIN1_APERTURE = 32768,
536 MEMWIN1_BASE = 0x28000,
537
538 MEMWIN2_APERTURE_T4 = 65536,
539 MEMWIN2_BASE_T4 = 0x30000,
540
541 MEMWIN2_APERTURE_T5 = 128 * 1024,
542 MEMWIN2_BASE_T5 = 0x60000,
543 };
544
545 struct memwin {
546 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
547 uint32_t mw_base; /* constant after setup_memwin */
548 uint32_t mw_aperture; /* ditto */
549 uint32_t mw_curpos; /* protected by mw_lock */
550 };
551
552 enum {
553 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
554 FL_DOOMED = (1 << 1), /* about to be destroyed */
555 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
556 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
557 };
558
559 #define FL_RUNNING_LOW(fl) \
560 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
561 #define FL_NOT_RUNNING_LOW(fl) \
562 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
563
564 struct sge_fl {
565 struct mtx fl_lock;
566 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
567 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
568 uint16_t zidx; /* refill zone idx */
569 uint16_t safe_zidx;
570 uint16_t lowat; /* # of buffers <= this means fl needs help */
571 int flags;
572 uint16_t buf_boundary;
573
574 /* The 16b idx all deal with hw descriptors */
575 uint16_t dbidx; /* hw pidx after last doorbell */
576 uint16_t sidx; /* index of status page */
577 volatile uint16_t hw_cidx;
578
579 /* The 32b idx are all buffer idx, not hardware descriptor idx */
580 uint32_t cidx; /* consumer index */
581 uint32_t pidx; /* producer index */
582
583 uint32_t dbval;
584 u_int rx_offset; /* offset in fl buf (when buffer packing) */
585 volatile uint32_t *udb;
586
587 uint64_t cl_allocated; /* # of clusters allocated */
588 uint64_t cl_recycled; /* # of clusters recycled */
589 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
590
591 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
592 struct mbuf *m0;
593 struct mbuf **pnext;
594 u_int remaining;
595
596 uint16_t qsize; /* # of hw descriptors (status page included) */
597 uint16_t cntxt_id; /* SGE context id for the freelist */
598 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
599 bus_dma_tag_t desc_tag;
600 bus_dmamap_t desc_map;
601 char lockname[16];
602 bus_addr_t ba; /* bus address of descriptor ring */
603 };
604
605 struct mp_ring;
606
607 struct txpkts {
608 uint8_t wr_type; /* type 0 or type 1 */
609 uint8_t npkt; /* # of packets in this work request */
610 uint8_t len16; /* # of 16B pieces used by this work request */
611 uint8_t score;
612 uint8_t max_npkt; /* maximum number of packets allowed */
613 uint16_t plen; /* total payload (sum of all packets) */
614
615 /* straight from fw_eth_tx_pkts_vm_wr. */
616 __u8 ethmacdst[6];
617 __u8 ethmacsrc[6];
618 __be16 ethtype;
619 __be16 vlantci;
620
621 struct mbuf *mb[15];
622 };
623
624 /* txq: SGE egress queue + what's needed for Ethernet NIC */
625 struct sge_txq {
626 struct sge_eq eq; /* MUST be first */
627
628 if_t ifp; /* the interface this txq belongs to */
629 struct mp_ring *r; /* tx software ring */
630 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
631 struct sglist *gl;
632 __be32 cpl_ctrl0; /* for convenience */
633 int tc_idx; /* traffic class */
634 uint64_t last_tx; /* cycle count when eth_tx was last called */
635 struct txpkts txp;
636
637 struct task tx_reclaim_task;
638 /* stats for common events first */
639
640 uint64_t txcsum; /* # of times hardware assisted with checksum */
641 uint64_t tso_wrs; /* # of TSO work requests */
642 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
643 uint64_t imm_wrs; /* # of work requests with immediate data */
644 uint64_t sgl_wrs; /* # of work requests with direct SGL */
645 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
646 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
647 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
648 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
649 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
650 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */
651 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
652 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */
653 uint64_t vxlan_txcsum;
654
655 uint64_t kern_tls_records;
656 uint64_t kern_tls_short;
657 uint64_t kern_tls_partial;
658 uint64_t kern_tls_full;
659 uint64_t kern_tls_octets;
660 uint64_t kern_tls_waste;
661 uint64_t kern_tls_header;
662 uint64_t kern_tls_fin_short;
663 uint64_t kern_tls_cbc;
664 uint64_t kern_tls_gcm;
665 union {
666 struct {
667 /* T6 only. */
668 uint64_t kern_tls_options;
669 uint64_t kern_tls_fin;
670 };
671 struct {
672 /* T7 only. */
673 uint64_t kern_tls_ghash_received;
674 uint64_t kern_tls_ghash_requested;
675 uint64_t kern_tls_lso;
676 uint64_t kern_tls_partial_ghash;
677 uint64_t kern_tls_splitmode;
678 uint64_t kern_tls_trailer;
679 };
680 };
681
682 /* stats for not-that-common events */
683
684 /* Optional scratch space for constructing work requests. */
685 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
686 } __aligned(CACHE_LINE_SIZE);
687
688 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
689 struct sge_rxq {
690 struct sge_iq iq; /* MUST be first */
691 struct sge_fl fl; /* MUST follow iq */
692
693 if_t ifp; /* the interface this rxq belongs to */
694 struct lro_ctrl lro; /* LRO state */
695
696 /* stats for common events first */
697
698 uint64_t rxcsum; /* # of times hardware assisted with checksum */
699 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
700 uint64_t vxlan_rxcsum;
701
702 /* stats for not-that-common events */
703
704 } __aligned(CACHE_LINE_SIZE);
705
706 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)707 iq_to_rxq(struct sge_iq *iq)
708 {
709
710 return (__containerof(iq, struct sge_rxq, iq));
711 }
712
713 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
714 struct sge_ofld_rxq {
715 struct sge_iq iq; /* MUST be first */
716 struct sge_fl fl; /* MUST follow iq */
717 counter_u64_t rx_iscsi_ddp_setup_ok;
718 counter_u64_t rx_iscsi_ddp_setup_error;
719 uint64_t rx_iscsi_ddp_pdus;
720 uint64_t rx_iscsi_ddp_octets;
721 uint64_t rx_iscsi_fl_pdus;
722 uint64_t rx_iscsi_fl_octets;
723 uint64_t rx_iscsi_padding_errors;
724 uint64_t rx_iscsi_header_digest_errors;
725 uint64_t rx_iscsi_data_digest_errors;
726 counter_u64_t rx_nvme_ddp_setup_ok;
727 counter_u64_t rx_nvme_ddp_setup_no_stag;
728 counter_u64_t rx_nvme_ddp_setup_error;
729 counter_u64_t rx_nvme_ddp_pdus;
730 counter_u64_t rx_nvme_ddp_octets;
731 counter_u64_t rx_nvme_fl_pdus;
732 counter_u64_t rx_nvme_fl_octets;
733 counter_u64_t rx_nvme_invalid_headers;
734 counter_u64_t rx_nvme_header_digest_errors;
735 counter_u64_t rx_nvme_data_digest_errors;
736 uint64_t rx_aio_ddp_jobs;
737 uint64_t rx_aio_ddp_octets;
738 u_long rx_toe_tls_records;
739 u_long rx_toe_tls_octets;
740 u_long rx_toe_ddp_octets;
741 counter_u64_t ddp_buffer_alloc;
742 counter_u64_t ddp_buffer_reuse;
743 counter_u64_t ddp_buffer_free;
744 } __aligned(CACHE_LINE_SIZE);
745
746 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)747 iq_to_ofld_rxq(struct sge_iq *iq)
748 {
749
750 return (__containerof(iq, struct sge_ofld_rxq, iq));
751 }
752
753 struct wrqe {
754 STAILQ_ENTRY(wrqe) link;
755 struct sge_wrq *wrq;
756 int wr_len;
757 char wr[] __aligned(16);
758 };
759
760 struct wrq_cookie {
761 TAILQ_ENTRY(wrq_cookie) link;
762 int ndesc;
763 int pidx;
764 };
765
766 /*
767 * wrq: SGE egress queue that is given prebuilt work requests. Control queues
768 * are of this type.
769 */
770 struct sge_wrq {
771 struct sge_eq eq; /* MUST be first */
772
773 struct adapter *adapter;
774 struct task wrq_tx_task;
775
776 /* Tx desc reserved but WR not "committed" yet. */
777 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
778
779 /* List of WRs ready to go out as soon as descriptors are available. */
780 STAILQ_HEAD(, wrqe) wr_list;
781 u_int nwr_pending;
782 u_int ndesc_needed;
783
784 /* stats for common events first */
785
786 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
787 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
788 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
789
790 /* stats for not-that-common events */
791
792 /*
793 * Scratch space for work requests that wrap around after reaching the
794 * status page, and some information about the last WR that used it.
795 */
796 uint16_t ss_pidx;
797 uint16_t ss_len;
798 uint8_t ss[SGE_MAX_WR_LEN];
799
800 } __aligned(CACHE_LINE_SIZE);
801
802 /* ofld_txq: SGE egress queue + miscellaneous items */
803 struct sge_ofld_txq {
804 struct sge_wrq wrq;
805 counter_u64_t tx_iscsi_pdus;
806 counter_u64_t tx_iscsi_octets;
807 counter_u64_t tx_iscsi_iso_wrs;
808 counter_u64_t tx_nvme_pdus;
809 counter_u64_t tx_nvme_octets;
810 counter_u64_t tx_nvme_iso_wrs;
811 counter_u64_t tx_aio_jobs;
812 counter_u64_t tx_aio_octets;
813 counter_u64_t tx_toe_tls_records;
814 counter_u64_t tx_toe_tls_octets;
815 } __aligned(CACHE_LINE_SIZE);
816
817 static inline int
ofld_txq_group(int val,int mask)818 ofld_txq_group(int val, int mask)
819 {
820 const uint32_t ngroup = 1 << bitcount32(mask);
821 const int mshift = ffs(mask) - 1;
822 const uint32_t gmask = ngroup - 1;
823
824 return (val >> mshift & gmask);
825 }
826
827 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
828 struct sge_nm_rxq {
829 /* Items used by the driver rx ithread are in this cacheline. */
830 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */
831 u_int nid; /* netmap ring # for this queue */
832 struct vi_info *vi;
833
834 struct iq_desc *iq_desc;
835 uint16_t iq_abs_id;
836 uint16_t iq_cntxt_id;
837 uint16_t iq_cidx;
838 uint16_t iq_sidx;
839 uint8_t iq_gen;
840 uint32_t fl_sidx;
841
842 /* Items used by netmap rxsync are in this cacheline. */
843 __be64 *fl_desc __aligned(CACHE_LINE_SIZE);
844 uint16_t fl_cntxt_id;
845 uint32_t fl_pidx;
846 uint32_t fl_sidx2; /* copy of fl_sidx */
847 uint32_t fl_db_val;
848 u_int fl_db_saved;
849 u_int fl_db_threshold; /* in descriptors */
850 u_int fl_hwidx:4;
851
852 /*
853 * fl_cidx is used by both the ithread and rxsync, the rest are not used
854 * in the rx fast path.
855 */
856 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
857
858 bus_dma_tag_t iq_desc_tag;
859 bus_dmamap_t iq_desc_map;
860 bus_addr_t iq_ba;
861 int intr_idx;
862
863 bus_dma_tag_t fl_desc_tag;
864 bus_dmamap_t fl_desc_map;
865 bus_addr_t fl_ba;
866 };
867
868 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
869 struct sge_nm_txq {
870 struct tx_desc *desc;
871 uint16_t cidx;
872 uint16_t pidx;
873 uint16_t sidx;
874 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
875 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
876 uint16_t dbidx; /* pidx of the most recent doorbell */
877 uint8_t doorbells;
878 volatile uint32_t *udb;
879 u_int udb_qid;
880 u_int cntxt_id;
881 __be32 cpl_ctrl0; /* for convenience */
882 __be32 op_pkd; /* ditto */
883 u_int nid; /* netmap ring # for this queue */
884
885 /* infrequently used items after this */
886
887 bus_dma_tag_t desc_tag;
888 bus_dmamap_t desc_map;
889 bus_addr_t ba;
890 int iqidx;
891 } __aligned(CACHE_LINE_SIZE);
892
893 struct sge {
894 int nctrlq; /* total # of control queues */
895 int nrxq; /* total # of Ethernet rx queues */
896 int ntxq; /* total # of Ethernet tx queues */
897 int nofldrxq; /* total # of TOE rx queues */
898 int nofldtxq; /* total # of TOE tx queues */
899 int nnmrxq; /* total # of netmap rx queues */
900 int nnmtxq; /* total # of netmap tx queues */
901 int niq; /* total # of ingress queues */
902 int neq; /* total # of egress queues */
903
904 struct sge_iq fwq; /* Firmware event queue */
905 struct sge_wrq *ctrlq; /* Control queues */
906 struct sge_txq *txq; /* NIC tx queues */
907 struct sge_rxq *rxq; /* NIC rx queues */
908 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */
909 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
910 struct sge_nm_txq *nm_txq; /* netmap tx queues */
911 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
912
913 uint16_t iq_start; /* first cntxt_id */
914 uint16_t iq_base; /* first abs_id */
915 int eq_start; /* first cntxt_id */
916 int eq_base; /* first abs_id */
917 int iqmap_sz;
918 int eqmap_sz;
919 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
920 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
921
922 int8_t safe_zidx;
923 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
924 };
925
926 struct devnames {
927 const char *nexus_name;
928 const char *ifnet_name;
929 const char *vi_ifnet_name;
930 const char *pf03_drv_name;
931 const char *vf_nexus_name;
932 const char *vf_ifnet_name;
933 };
934
935 struct clip_entry;
936
937 #define CNT_CAL_INFO 3
938 struct clock_sync {
939 uint64_t hw_cur;
940 uint64_t hw_prev;
941 sbintime_t sbt_cur;
942 sbintime_t sbt_prev;
943 seqc_t gen;
944 };
945
946 struct adapter {
947 SLIST_ENTRY(adapter) link;
948 device_t dev;
949 struct cdev *cdev;
950 const struct devnames *names;
951
952 /* PCIe register resources */
953 int regs_rid;
954 struct resource *regs_res;
955 int msix_rid;
956 struct resource *msix_res;
957 bus_space_handle_t bh;
958 bus_space_tag_t bt;
959 bus_size_t mmio_len;
960 int udbs_rid;
961 struct resource *udbs_res;
962 volatile uint8_t *udbs_base;
963
964 unsigned int pf;
965 unsigned int mbox;
966 unsigned int vpd_busy;
967 unsigned int vpd_flag;
968
969 /* Interrupt information */
970 int intr_type;
971 int intr_count;
972 struct irq {
973 struct resource *res;
974 int rid;
975 void *tag;
976 struct sge_rxq *rxq;
977 struct sge_nm_rxq *nm_rxq;
978 } __aligned(CACHE_LINE_SIZE) *irq;
979 int sge_gts_reg;
980 int sge_kdoorbell_reg;
981
982 bus_dma_tag_t dmat; /* Parent DMA tag */
983
984 struct sge sge;
985 int lro_timeout;
986 int sc_do_rxcopy;
987
988 int vxlan_port;
989 u_int vxlan_refcount;
990 int rawf_base;
991 int nrawf;
992 u_int vlan_id;
993
994 struct taskqueue *tq[MAX_NPORTS]; /* General purpose taskqueues */
995 struct port_info *port[MAX_NPORTS];
996 uint8_t chan_map[MAX_NCHAN]; /* tx_chan -> port_id */
997 uint8_t port_map[MAX_NPORTS]; /* hw_port -> port_id */
998
999 CXGBE_LIST_HEAD(, clip_entry) *clip_table;
1000 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */
1001 u_long clip_mask;
1002 int clip_gen;
1003 struct timeout_task clip_task;
1004
1005 void *tom_softc; /* (struct tom_data *) */
1006 struct tom_tunables tt;
1007 struct t4_offload_policy *policy;
1008 struct rwlock policy_lock;
1009
1010 void *iwarp_softc; /* (struct c4iw_dev *) */
1011 struct iw_tunables iwt;
1012 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
1013 void *nvme_ulp_softc; /* (struct nvmf_che_adapter *) */
1014 struct l2t_data *l2t; /* L2 table */
1015 struct smt_data *smt; /* Source MAC Table */
1016 struct tid_info tids;
1017 vmem_t *key_map;
1018 struct tls_tunables tlst;
1019
1020 vmem_t *pbl_arena;
1021 vmem_t *stag_arena;
1022
1023 uint8_t doorbells;
1024 int offload_map; /* port_id's with IFCAP_TOE enabled */
1025 int bt_map; /* hw_port's that are BASE-T */
1026 int active_ulds; /* ULDs activated on this adapter */
1027 int flags;
1028 int debug_flags;
1029 int error_flags; /* Used by error handler and live reset. */
1030
1031 char ifp_lockname[16];
1032 struct mtx ifp_lock;
1033 if_t ifp; /* tracer ifp */
1034 struct ifmedia media;
1035 int traceq; /* iq used by all tracers, -1 if none */
1036 int tracer_valid; /* bitmap of valid tracers */
1037 int tracer_enabled; /* bitmap of enabled tracers */
1038
1039 char fw_version[16];
1040 char tp_version[16];
1041 char er_version[16];
1042 char bs_version[16];
1043 char cfg_file[32];
1044 u_int cfcsum;
1045 struct adapter_params params;
1046 const struct chip_params *chip_params;
1047 struct t4_virt_res vres;
1048
1049 uint16_t nbmcaps;
1050 uint16_t linkcaps;
1051 uint16_t switchcaps;
1052 uint16_t nvmecaps;
1053 uint16_t niccaps;
1054 uint16_t toecaps;
1055 uint16_t rdmacaps;
1056 uint16_t cryptocaps;
1057 uint16_t iscsicaps;
1058 uint16_t fcoecaps;
1059
1060 struct sysctl_ctx_list ctx;
1061 struct sysctl_oid *ctrlq_oid;
1062 struct sysctl_oid *fwq_oid;
1063
1064 struct mtx sc_lock;
1065 char lockname[16];
1066
1067 /* Starving free lists */
1068 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
1069 TAILQ_HEAD(, sge_fl) sfl;
1070 struct callout sfl_callout;
1071 struct callout cal_callout;
1072 struct clock_sync cal_info[CNT_CAL_INFO];
1073 int cal_current;
1074 int cal_count;
1075 uint32_t cal_gen;
1076
1077 /*
1078 * Driver code that can run when the adapter is suspended must use this
1079 * lock or a synchronized_op and check for HW_OFF_LIMITS before
1080 * accessing hardware.
1081 *
1082 * XXX: could be changed to rwlock. wlock in suspend/resume and for
1083 * indirect register access, rlock everywhere else.
1084 */
1085 struct mtx reg_lock;
1086
1087 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
1088
1089 struct mtx tc_lock;
1090 struct task tc_task;
1091
1092 struct task fatal_error_task;
1093 struct task reset_task;
1094 const void *reset_thread;
1095 int num_resets;
1096 int incarnation;
1097
1098 const char *last_op;
1099 const void *last_op_thr;
1100 int last_op_flags;
1101
1102 int swintr;
1103 int sensor_resets;
1104
1105 struct callout ktls_tick;
1106 };
1107
1108 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
1109 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
1110 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
1111 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
1112
1113 #define ASSERT_SYNCHRONIZED_OP(sc) \
1114 KASSERT(IS_BUSY(sc) && \
1115 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
1116 ("%s: operation not synchronized.", __func__))
1117
1118 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
1119 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
1120 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
1121 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
1122
1123 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
1124 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
1125 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
1126 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
1127 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
1128
1129 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
1130 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
1131 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
1132 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
1133
1134 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
1135 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
1136 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
1137 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
1138 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
1139
1140 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
1141 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
1142 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
1143 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
1144 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
1145
1146 #define for_each_txq(vi, iter, q) \
1147 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
1148 iter < vi->ntxq; ++iter, ++q)
1149 #define for_each_rxq(vi, iter, q) \
1150 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
1151 iter < vi->nrxq; ++iter, ++q)
1152 #define for_each_ofld_txq(vi, iter, q) \
1153 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
1154 iter < vi->nofldtxq; ++iter, ++q)
1155 #define for_each_ofld_rxq(vi, iter, q) \
1156 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
1157 iter < vi->nofldrxq; ++iter, ++q)
1158 #define for_each_nm_txq(vi, iter, q) \
1159 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
1160 iter < vi->nnmtxq; ++iter, ++q)
1161 #define for_each_nm_rxq(vi, iter, q) \
1162 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
1163 iter < vi->nnmrxq; ++iter, ++q)
1164 #define for_each_vi(_pi, _iter, _vi) \
1165 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
1166 ++(_iter), ++(_vi))
1167
1168 #define IDXINCR(idx, incr, wrap) do { \
1169 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
1170 } while (0)
1171 #define IDXDIFF(head, tail, wrap) \
1172 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1173
1174 /* One for errors, one for firmware events */
1175 #define T4_EXTRA_INTR 2
1176
1177 /* One for firmware events */
1178 #define T4VF_EXTRA_INTR 1
1179
1180 static inline int
forwarding_intr_to_fwq(struct adapter * sc)1181 forwarding_intr_to_fwq(struct adapter *sc)
1182 {
1183
1184 return (sc->intr_count == 1);
1185 }
1186
1187 /* Works reliably inside a synch_op or with reg_lock held. */
1188 static inline bool
hw_off_limits(struct adapter * sc)1189 hw_off_limits(struct adapter *sc)
1190 {
1191 const int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS;
1192
1193 return (__predict_false(off_limits != 0));
1194 }
1195
1196 /* Works reliably inside a synch_op or with reg_lock held. */
1197 static inline bool
hw_all_ok(struct adapter * sc)1198 hw_all_ok(struct adapter *sc)
1199 {
1200 const int not_ok = atomic_load_int(&sc->error_flags) &
1201 (ADAP_STOPPED | HW_OFF_LIMITS);
1202
1203 return (__predict_true(not_ok == 0));
1204 }
1205
1206 static inline int
mbuf_nsegs(struct mbuf * m)1207 mbuf_nsegs(struct mbuf *m)
1208 {
1209 M_ASSERTPKTHDR(m);
1210 KASSERT(m->m_pkthdr.inner_l5hlen > 0,
1211 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1212
1213 return (m->m_pkthdr.inner_l5hlen);
1214 }
1215
1216 static inline void
set_mbuf_nsegs(struct mbuf * m,uint8_t nsegs)1217 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1218 {
1219 M_ASSERTPKTHDR(m);
1220 m->m_pkthdr.inner_l5hlen = nsegs;
1221 }
1222
1223 /* Internal mbuf flags stored in PH_loc.eight[1]. */
1224 #define MC_NOMAP 0x01
1225 #define MC_RAW_WR 0x02
1226 #define MC_TLS 0x04
1227
1228 static inline int
mbuf_cflags(struct mbuf * m)1229 mbuf_cflags(struct mbuf *m)
1230 {
1231 M_ASSERTPKTHDR(m);
1232 return (m->m_pkthdr.PH_loc.eight[4]);
1233 }
1234
1235 static inline void
set_mbuf_cflags(struct mbuf * m,uint8_t flags)1236 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
1237 {
1238 M_ASSERTPKTHDR(m);
1239 m->m_pkthdr.PH_loc.eight[4] = flags;
1240 }
1241
1242 static inline int
mbuf_len16(struct mbuf * m)1243 mbuf_len16(struct mbuf *m)
1244 {
1245 int n;
1246
1247 M_ASSERTPKTHDR(m);
1248 n = m->m_pkthdr.PH_loc.eight[0];
1249 if (!(mbuf_cflags(m) & MC_TLS))
1250 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1251
1252 return (n);
1253 }
1254
1255 static inline void
set_mbuf_len16(struct mbuf * m,uint8_t len16)1256 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1257 {
1258 M_ASSERTPKTHDR(m);
1259 if (!(mbuf_cflags(m) & MC_TLS))
1260 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
1261 m->m_pkthdr.PH_loc.eight[0] = len16;
1262 }
1263
1264 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)1265 t4_read_reg(struct adapter *sc, uint32_t reg)
1266 {
1267 if (hw_off_limits(sc))
1268 MPASS(curthread == sc->reset_thread);
1269 return bus_space_read_4(sc->bt, sc->bh, reg);
1270 }
1271
1272 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)1273 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1274 {
1275 if (hw_off_limits(sc))
1276 MPASS(curthread == sc->reset_thread);
1277 bus_space_write_4(sc->bt, sc->bh, reg, val);
1278 }
1279
1280 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)1281 t4_read_reg64(struct adapter *sc, uint32_t reg)
1282 {
1283 if (hw_off_limits(sc))
1284 MPASS(curthread == sc->reset_thread);
1285 #ifdef __LP64__
1286 return bus_space_read_8(sc->bt, sc->bh, reg);
1287 #else
1288 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1289 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1290
1291 #endif
1292 }
1293
1294 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)1295 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1296 {
1297 if (hw_off_limits(sc))
1298 MPASS(curthread == sc->reset_thread);
1299 #ifdef __LP64__
1300 bus_space_write_8(sc->bt, sc->bh, reg, val);
1301 #else
1302 bus_space_write_4(sc->bt, sc->bh, reg, val);
1303 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1304 #endif
1305 }
1306
1307 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)1308 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1309 {
1310 if (hw_off_limits(sc))
1311 MPASS(curthread == sc->reset_thread);
1312 *val = pci_read_config(sc->dev, reg, 1);
1313 }
1314
1315 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)1316 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1317 {
1318 if (hw_off_limits(sc))
1319 MPASS(curthread == sc->reset_thread);
1320 pci_write_config(sc->dev, reg, val, 1);
1321 }
1322
1323 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)1324 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1325 {
1326
1327 if (hw_off_limits(sc))
1328 MPASS(curthread == sc->reset_thread);
1329 *val = pci_read_config(sc->dev, reg, 2);
1330 }
1331
1332 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)1333 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1334 {
1335 if (hw_off_limits(sc))
1336 MPASS(curthread == sc->reset_thread);
1337 pci_write_config(sc->dev, reg, val, 2);
1338 }
1339
1340 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)1341 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1342 {
1343 if (hw_off_limits(sc))
1344 MPASS(curthread == sc->reset_thread);
1345 *val = pci_read_config(sc->dev, reg, 4);
1346 }
1347
1348 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)1349 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1350 {
1351 if (hw_off_limits(sc))
1352 MPASS(curthread == sc->reset_thread);
1353 pci_write_config(sc->dev, reg, val, 4);
1354 }
1355
1356 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)1357 adap2pinfo(struct adapter *sc, int idx)
1358 {
1359
1360 return (sc->port[idx]);
1361 }
1362
1363 static inline void
t4_os_set_hw_addr(struct port_info * pi,uint8_t hw_addr[])1364 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1365 {
1366
1367 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1368 }
1369
1370 static inline int
tx_resume_threshold(struct sge_eq * eq)1371 tx_resume_threshold(struct sge_eq *eq)
1372 {
1373
1374 /* not quite the same as qsize / 4, but this will do. */
1375 return (eq->sidx / 4);
1376 }
1377
1378 static inline int
t4_use_ldst(struct adapter * sc)1379 t4_use_ldst(struct adapter *sc)
1380 {
1381
1382 #ifdef notyet
1383 return (sc->flags & FW_OK || !sc->use_bd);
1384 #else
1385 return (0);
1386 #endif
1387 }
1388
1389 static inline void
CH_DUMP_MBOX(struct adapter * sc,int mbox,const int reg,const char * msg,const __be64 * const p,const bool err)1390 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1391 const char *msg, const __be64 *const p, const bool err)
1392 {
1393
1394 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1395 return;
1396 if (p != NULL) {
1397 log(err ? LOG_ERR : LOG_DEBUG,
1398 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1399 "%016llx %016llx %016llx %016llx\n",
1400 device_get_nameunit(sc->dev), mbox, msg,
1401 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1402 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1403 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1404 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1405 } else {
1406 log(err ? LOG_ERR : LOG_DEBUG,
1407 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1408 "%016llx %016llx %016llx %016llx\n",
1409 device_get_nameunit(sc->dev), mbox, msg,
1410 (long long)t4_read_reg64(sc, reg),
1411 (long long)t4_read_reg64(sc, reg + 8),
1412 (long long)t4_read_reg64(sc, reg + 16),
1413 (long long)t4_read_reg64(sc, reg + 24),
1414 (long long)t4_read_reg64(sc, reg + 32),
1415 (long long)t4_read_reg64(sc, reg + 40),
1416 (long long)t4_read_reg64(sc, reg + 48),
1417 (long long)t4_read_reg64(sc, reg + 56));
1418 }
1419 }
1420
1421 /* t4_main.c */
1422 extern int t4_ntxq;
1423 extern int t4_nrxq;
1424 extern int t4_intr_types;
1425 extern int t4_tmr_idx;
1426 extern int t4_pktc_idx;
1427 extern unsigned int t4_qsize_rxq;
1428 extern unsigned int t4_qsize_txq;
1429 extern int t4_ddp_rcvbuf_len;
1430 extern unsigned int t4_ddp_rcvbuf_cache;
1431 extern device_method_t cxgbe_methods[];
1432
1433 int t4_os_find_pci_capability(struct adapter *, int);
1434 void t4_os_portmod_changed(struct port_info *);
1435 void t4_os_link_changed(struct port_info *);
1436 void t4_iterate(void (*)(struct adapter *, void *), void *);
1437 void t4_init_devnames(struct adapter *);
1438 void t4_add_adapter(struct adapter *);
1439 int t4_detach_common(device_t);
1440 int t4_map_bars_0_and_4(struct adapter *);
1441 int t4_map_bar_2(struct adapter *);
1442 int t4_adj_doorbells(struct adapter *);
1443 int t4_setup_intr_handlers(struct adapter *);
1444 void t4_sysctls(struct adapter *);
1445 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1446 void end_synchronized_op(struct adapter *, int);
1447 void begin_vi_detach(struct adapter *, struct vi_info *);
1448 void end_vi_detach(struct adapter *, struct vi_info *);
1449 int update_mac_settings(if_t, int);
1450 int adapter_init(struct adapter *);
1451 int vi_init(struct vi_info *);
1452 void vi_sysctls(struct vi_info *);
1453 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1454 int alloc_atid(struct adapter *, void *);
1455 void *lookup_atid(struct adapter *, int);
1456 void free_atid(struct adapter *, int);
1457 void release_tid(struct adapter *, int, struct sge_wrq *);
1458 int cxgbe_media_change(if_t);
1459 void cxgbe_media_status(if_t, struct ifmediareq *);
1460 void t4_os_cim_err(struct adapter *);
1461 int suspend_adapter(struct adapter *);
1462 int resume_adapter(struct adapter *);
1463 int toe_capability(struct vi_info *, bool);
1464
1465 #ifdef KERN_TLS
1466 /* t6_kern_tls.c */
1467 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *,
1468 struct m_snd_tag **);
1469 void t6_ktls_modload(void);
1470 void t6_ktls_modunload(void);
1471 int t6_ktls_try(if_t, struct socket *, struct ktls_session *);
1472 int t6_ktls_parse_pkt(struct mbuf *);
1473 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int);
1474
1475 /* t7_kern_tls.c */
1476 int t7_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1477 struct m_snd_tag **);
1478 void t7_ktls_modload(void);
1479 void t7_ktls_modunload(void);
1480 int t7_ktls_parse_pkt(struct mbuf *);
1481 int t7_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int);
1482 #endif
1483
1484 /* t4_keyctx.c */
1485 struct auth_hash;
1486 union authctx;
1487 #ifdef KERN_TLS
1488 struct ktls_session;
1489 struct tls_key_req;
1490 struct tls_keyctx;
1491 #endif
1492
1493 void t4_aes_getdeckey(void *, const void *, unsigned int);
1494 void t4_copy_partial_hash(int, union authctx *, void *);
1495 void t4_init_gmac_hash(const char *, int, char *);
1496 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int,
1497 char *);
1498 #ifdef KERN_TLS
1499 u_int t4_tls_key_info_size(const struct ktls_session *);
1500 int t4_tls_proto_ver(const struct ktls_session *);
1501 int t4_tls_cipher_mode(const struct ktls_session *);
1502 int t4_tls_auth_mode(const struct ktls_session *);
1503 int t4_tls_hmac_ctrl(const struct ktls_session *);
1504 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *);
1505 int t4_alloc_tls_keyid(struct adapter *);
1506 void t4_free_tls_keyid(struct adapter *, int);
1507 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int,
1508 struct tls_key_req *);
1509 #endif
1510
1511 #ifdef DEV_NETMAP
1512 /* t4_netmap.c */
1513 struct sge_nm_rxq;
1514 void cxgbe_nm_attach(struct vi_info *);
1515 void cxgbe_nm_detach(struct vi_info *);
1516 void service_nm_rxq(struct sge_nm_rxq *);
1517 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int);
1518 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
1519 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int);
1520 int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
1521 #endif
1522
1523 /* t4_sge.c */
1524 void t4_sge_modload(void);
1525 void t4_sge_modunload(void);
1526 uint64_t t4_sge_extfree_refs(void);
1527 void t4_tweak_chip_settings(struct adapter *);
1528 int t4_verify_chip_settings(struct adapter *);
1529 void t4_init_rx_buf_info(struct adapter *);
1530 int t4_create_dma_tag(struct adapter *);
1531 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1532 struct sysctl_oid_list *);
1533 int t4_destroy_dma_tag(struct adapter *);
1534 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
1535 bus_addr_t *, void **);
1536 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1537 void *);
1538 void free_fl_buffers(struct adapter *, struct sge_fl *);
1539 int t4_setup_adapter_queues(struct adapter *);
1540 int t4_teardown_adapter_queues(struct adapter *);
1541 int t4_setup_vi_queues(struct vi_info *);
1542 int t4_teardown_vi_queues(struct vi_info *);
1543 void t4_intr_all(void *);
1544 void t4_intr(void *);
1545 #ifdef DEV_NETMAP
1546 void t4_nm_intr(void *);
1547 void t4_vi_intr(void *);
1548 #endif
1549 void t4_intr_err(void *);
1550 void t4_intr_evt(void *);
1551 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1552 void t4_update_fl_bufsize(if_t);
1553 struct mbuf *alloc_wr_mbuf(int, int);
1554 int parse_pkt(struct mbuf **, bool);
1555 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1556 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1557 int t4_sge_set_conm_context(struct adapter *, int, int, int);
1558 void t4_register_an_handler(an_handler_t);
1559 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1560 void t4_register_cpl_handler(int, cpl_handler_t);
1561 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1562 #ifdef RATELIMIT
1563 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1564 #endif
1565
1566 /* t4_tracer.c */
1567 struct t4_tracer;
1568 void t4_tracer_modload(void);
1569 void t4_tracer_modunload(void);
1570 void t4_tracer_port_detach(struct adapter *);
1571 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1572 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1573 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1574 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1575
1576 /* t4_sched.c */
1577 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1578 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1579 int t4_init_tx_sched(struct adapter *);
1580 int t4_free_tx_sched(struct adapter *);
1581 void t4_update_tx_sched(struct adapter *);
1582 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1583 void t4_release_cl_rl(struct adapter *, int, int);
1584 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1585 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1586 #ifdef RATELIMIT
1587 void t4_init_etid_table(struct adapter *);
1588 void t4_free_etid_table(struct adapter *);
1589 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1590 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *,
1591 struct m_snd_tag **);
1592 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1593 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *);
1594 #endif
1595
1596 /* t4_filter.c */
1597 int get_filter_mode(struct adapter *, uint32_t *);
1598 int set_filter_mode(struct adapter *, uint32_t);
1599 int set_filter_mask(struct adapter *, uint32_t);
1600 int get_filter(struct adapter *, struct t4_filter *);
1601 int set_filter(struct adapter *, struct t4_filter *);
1602 int del_filter(struct adapter *, struct t4_filter *);
1603 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1604 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1605 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1606 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1607 void free_hftid_hash(struct tid_info *);
1608
1609 /* t4_tpt.c */
1610 #define T4_STAG_UNSET 0xffffffff
1611 #define T4_WRITE_MEM_DMA_LEN \
1612 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_sgl), 16)
1613 #define T4_ULPTX_MIN_IO 32
1614 #define T4_MAX_INLINE_SIZE 96
1615 #define T4_WRITE_MEM_INLINE_LEN(len) \
1616 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_idata) + \
1617 roundup((len), T4_ULPTX_MIN_IO), 16)
1618
1619 uint32_t t4_pblpool_alloc(struct adapter *, int);
1620 void t4_pblpool_free(struct adapter *, uint32_t, int);
1621 uint32_t t4_stag_alloc(struct adapter *, int);
1622 void t4_stag_free(struct adapter *, uint32_t, int);
1623 void t4_init_tpt(struct adapter *);
1624 void t4_free_tpt(struct adapter *);
1625 void t4_write_mem_dma_wr(struct adapter *, void *, int, int, uint32_t,
1626 uint32_t, vm_paddr_t, uint64_t);
1627 void t4_write_mem_inline_wr(struct adapter *, void *, int, int, uint32_t,
1628 uint32_t, void *, uint64_t);
1629
1630 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1631 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1632 {
1633 int len = offsetof(struct wrqe, wr) + wr_len;
1634 struct wrqe *wr;
1635
1636 wr = malloc(len, M_CXGBE, M_NOWAIT);
1637 if (__predict_false(wr == NULL))
1638 return (NULL);
1639 wr->wr_len = wr_len;
1640 wr->wrq = wrq;
1641 return (wr);
1642 }
1643
1644 static inline void *
wrtod(struct wrqe * wr)1645 wrtod(struct wrqe *wr)
1646 {
1647 return (&wr->wr[0]);
1648 }
1649
1650 static inline void
free_wrqe(struct wrqe * wr)1651 free_wrqe(struct wrqe *wr)
1652 {
1653 free(wr, M_CXGBE);
1654 }
1655
1656 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1657 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1658 {
1659 struct sge_wrq *wrq = wr->wrq;
1660
1661 TXQ_LOCK(wrq);
1662 if (__predict_true(wrq->eq.flags & EQ_HW_ALLOCATED))
1663 t4_wrq_tx_locked(sc, wrq, wr);
1664 else
1665 free(wr, M_CXGBE);
1666 TXQ_UNLOCK(wrq);
1667 }
1668
1669 static inline int
read_via_memwin(struct adapter * sc,int idx,uint32_t addr,uint32_t * val,int len)1670 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1671 int len)
1672 {
1673
1674 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1675 }
1676
1677 static inline int
write_via_memwin(struct adapter * sc,int idx,uint32_t addr,const uint32_t * val,int len)1678 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1679 const uint32_t *val, int len)
1680 {
1681
1682 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1683 }
1684
1685 /* Number of len16 -> number of descriptors */
1686 static inline int
tx_len16_to_desc(int len16)1687 tx_len16_to_desc(int len16)
1688 {
1689
1690 return (howmany(len16, EQ_ESIZE / 16));
1691 }
1692 #endif
1693