1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #include "dp_htt.h" 11 12 #define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) 13 #define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 14 #define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 15 #define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 16 #define ATH12K_HTT_STATS_SUBTYPE_MAX 16 17 #define ATH12K_HTT_MAX_STRING_LEN 256 18 19 #define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f) 20 #define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f) 21 #define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \ 22 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx)) 23 #define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \ 24 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx)) 25 26 void ath12k_debugfs_htt_stats_register(struct ath12k *ar); 27 28 #ifdef CONFIG_ATH12K_DEBUGFS 29 void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 30 struct sk_buff *skb); 31 #else /* CONFIG_ATH12K_DEBUGFS */ 32 static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 33 struct sk_buff *skb) 34 { 35 } 36 #endif 37 38 /** 39 * DOC: target -> host extended statistics upload 40 * 41 * The following field definitions describe the format of the HTT 42 * target to host stats upload confirmation message. 43 * The message contains a cookie echoed from the HTT host->target stats 44 * upload request, which identifies which request the confirmation is 45 * for, and a single stats can span over multiple HTT stats indication 46 * due to the HTT message size limitation so every HTT ext stats 47 * indication will have tag-length-value stats information elements. 48 * The tag-length header for each HTT stats IND message also includes a 49 * status field, to indicate whether the request for the stat type in 50 * question was fully met, partially met, unable to be met, or invalid 51 * (if the stat type in question is disabled in the target). 52 * A Done bit 1's indicate the end of the of stats info elements. 53 * 54 * 55 * |31 16|15 12|11|10 8|7 5|4 0| 56 * |--------------------------------------------------------------| 57 * | reserved | msg type | 58 * |--------------------------------------------------------------| 59 * | cookie LSBs | 60 * |--------------------------------------------------------------| 61 * | cookie MSBs | 62 * |--------------------------------------------------------------| 63 * | stats entry length | rsvd | D| S | stat type | 64 * |--------------------------------------------------------------| 65 * | type-specific stats info | 66 * | (see debugfs_htt_stats.h) | 67 * |--------------------------------------------------------------| 68 * Header fields: 69 * - MSG_TYPE 70 * Bits 7:0 71 * Purpose: Identifies this is a extended statistics upload confirmation 72 * message. 73 * Value: 0x1c 74 * - COOKIE_LSBS 75 * Bits 31:0 76 * Purpose: Provide a mechanism to match a target->host stats confirmation 77 * message with its preceding host->target stats request message. 78 * Value: MSBs of the opaque cookie specified by the host-side requestor 79 * - COOKIE_MSBS 80 * Bits 31:0 81 * Purpose: Provide a mechanism to match a target->host stats confirmation 82 * message with its preceding host->target stats request message. 83 * Value: MSBs of the opaque cookie specified by the host-side requestor 84 * 85 * Stats Information Element tag-length header fields: 86 * - STAT_TYPE 87 * Bits 7:0 88 * Purpose: identifies the type of statistics info held in the 89 * following information element 90 * Value: ath12k_dbg_htt_ext_stats_type 91 * - STATUS 92 * Bits 10:8 93 * Purpose: indicate whether the requested stats are present 94 * Value: 95 * 0 -> The requested stats have been delivered in full 96 * 1 -> The requested stats have been delivered in part 97 * 2 -> The requested stats could not be delivered (error case) 98 * 3 -> The requested stat type is either not recognized (invalid) 99 * - DONE 100 * Bits 11 101 * Purpose: 102 * Indicates the completion of the stats entry, this will be the last 103 * stats conf HTT segment for the requested stats type. 104 * Value: 105 * 0 -> the stats retrieval is ongoing 106 * 1 -> the stats retrieval is complete 107 * - LENGTH 108 * Bits 31:16 109 * Purpose: indicate the stats information size 110 * Value: This field specifies the number of bytes of stats information 111 * that follows the element tag-length header. 112 * It is expected but not required that this length is a multiple of 113 * 4 bytes. 114 */ 115 116 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 117 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 118 119 struct ath12k_htt_extd_stats_msg { 120 __le32 info0; 121 __le64 cookie; 122 __le32 info1; 123 u8 data[]; 124 } __packed; 125 126 /* htt_dbg_ext_stats_type */ 127 enum ath12k_dbg_htt_ext_stats_type { 128 ATH12K_DBG_HTT_EXT_STATS_RESET = 0, 129 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, 130 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX = 2, 131 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_HWQ = 3, 132 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, 133 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, 134 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, 135 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8, 136 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9, 137 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10, 138 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12, 139 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15, 140 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16, 141 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17, 142 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19, 143 ATH12K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22, 144 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 145 ATH12K_DBG_HTT_EXT_STATS_LATENCY_PROF_STATS = 25, 146 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_TRIG_STATS = 26, 147 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, 148 ATH12K_DBG_HTT_EXT_STATS_FSE_RX = 28, 149 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE_EXT = 30, 150 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE_TXBF = 31, 151 ATH12K_DBG_HTT_EXT_STATS_TXBF_OFDMA = 32, 152 ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36, 153 ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 154 ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38, 155 ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40, 156 ATH12K_DBG_HTT_EXT_AST_ENTRIES = 41, 157 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45, 158 ATH12K_DBG_HTT_DBG_PDEV_PUNCTURE_STATS = 46, 159 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49, 160 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51, 161 ATH12K_DGB_HTT_EXT_STATS_PDEV_MBSSID_CTRL_FRAME = 54, 162 ATH12K_DBG_HTT_PDEV_TDMA_STATS = 57, 163 ATH12K_DBG_HTT_MLO_SCHED_STATS = 63, 164 ATH12K_DBG_HTT_PDEV_MLO_IPC_STATS = 64, 165 ATH12K_DBG_HTT_EXT_PDEV_RTT_RESP_STATS = 65, 166 ATH12K_DBG_HTT_EXT_PDEV_RTT_INITIATOR_STATS = 66, 167 168 /* keep this last */ 169 ATH12K_DBG_HTT_NUM_EXT_STATS, 170 }; 171 172 enum ath12k_dbg_htt_tlv_tag { 173 HTT_STATS_TX_PDEV_CMN_TAG = 0, 174 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 175 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 176 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 177 HTT_STATS_STRING_TAG = 5, 178 HTT_STATS_TX_HWQ_CMN_TAG = 6, 179 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 180 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 181 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 182 HTT_STATS_TX_TQM_CMN_TAG = 14, 183 HTT_STATS_TX_TQM_PDEV_TAG = 15, 184 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 185 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 186 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 187 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 188 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 189 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 190 HTT_STATS_TX_DE_CMN_TAG = 23, 191 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 192 HTT_STATS_SFM_CMN_TAG = 26, 193 HTT_STATS_SRING_STATS_TAG = 27, 194 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, 195 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 196 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 197 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 198 HTT_STATS_TX_SCHED_CMN_TAG = 37, 199 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 200 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 201 HTT_STATS_SFM_CLIENT_TAG = 42, 202 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 203 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 204 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 205 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 206 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 207 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 208 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 209 HTT_STATS_HW_INTR_MISC_TAG = 54, 210 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 211 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 212 HTT_STATS_WHAL_TX_TAG = 66, 213 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 214 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 215 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 216 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 217 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 218 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 219 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 220 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 221 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 222 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 223 HTT_STATS_HW_WAR_TAG = 89, 224 HTT_STATS_LATENCY_PROF_STATS_TAG = 91, 225 HTT_STATS_LATENCY_CTX_TAG = 92, 226 HTT_STATS_LATENCY_CNT_TAG = 93, 227 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, 228 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, 229 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, 230 HTT_STATS_RX_FSE_STATS_TAG = 98, 231 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, 232 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, 233 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, 234 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 235 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, 236 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, 237 HTT_STATS_DLPAGER_STATS_TAG = 120, 238 HTT_STATS_PHY_COUNTERS_TAG = 121, 239 HTT_STATS_PHY_STATS_TAG = 122, 240 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, 241 HTT_STATS_PHY_RESET_STATS_TAG = 124, 242 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, 243 HTT_STATS_PER_RATE_STATS_TAG = 128, 244 HTT_STATS_MU_PPDU_DIST_TAG = 129, 245 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, 246 HTT_STATS_AST_ENTRY_TAG = 132, 247 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, 248 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, 249 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, 250 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, 251 HTT_STATS_TX_PDEV_HISTOGRAM_STATS_TAG = 144, 252 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, 253 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, 254 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, 255 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, 256 HTT_STATS_DMAC_RESET_STATS_TAG = 155, 257 HTT_STATS_PHY_TPC_STATS_TAG = 157, 258 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, 259 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, 260 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, 261 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, 262 HTT_STATS_PDEV_TDMA_TAG = 187, 263 HTT_STATS_MLO_SCHED_STATS_TAG = 190, 264 HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, 265 HTT_STATS_PDEV_RTT_RESP_STATS_TAG = 194, 266 HTT_STATS_PDEV_RTT_INIT_STATS_TAG = 195, 267 HTT_STATS_PDEV_RTT_HW_STATS_TAG = 196, 268 HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG = 197, 269 HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG = 198, 270 271 HTT_STATS_MAX_TAG, 272 }; 273 274 #define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0) 275 276 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 277 #define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 278 279 /* MU MIMO distribution stats is a 2-dimensional array 280 * with dimension one denoting stats for nr4[0] or nr8[1] 281 */ 282 #define ATH12K_HTT_STATS_NUM_NR_BINS 2 283 #define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 284 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 285 #define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9 286 #define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \ 287 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS) 288 #define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \ 289 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 290 291 enum ath12k_htt_tx_pdev_underrun_enum { 292 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 293 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 294 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 295 HTT_TX_PDEV_MAX_URRN_STATS = 3, 296 }; 297 298 enum ath12k_htt_stats_reset_cfg_param_alloc_pos { 299 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1, 300 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES, 301 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES, 302 }; 303 304 struct debug_htt_stats_req { 305 bool done; 306 bool override_cfg_param; 307 u8 pdev_id; 308 enum ath12k_dbg_htt_ext_stats_type type; 309 u32 cfg_param[4]; 310 u8 peer_addr[ETH_ALEN]; 311 struct completion htt_stats_rcvd; 312 u32 buf_len; 313 u8 buf[]; 314 }; 315 316 struct ath12k_htt_tx_pdev_stats_cmn_tlv { 317 __le32 mac_id__word; 318 __le32 hw_queued; 319 __le32 hw_reaped; 320 __le32 underrun; 321 __le32 hw_paused; 322 __le32 hw_flush; 323 __le32 hw_filt; 324 __le32 tx_abort; 325 __le32 mpdu_requed; 326 __le32 tx_xretry; 327 __le32 data_rc; 328 __le32 mpdu_dropped_xretry; 329 __le32 illgl_rate_phy_err; 330 __le32 cont_xretry; 331 __le32 tx_timeout; 332 __le32 pdev_resets; 333 __le32 phy_underrun; 334 __le32 txop_ovf; 335 __le32 seq_posted; 336 __le32 seq_failed_queueing; 337 __le32 seq_completed; 338 __le32 seq_restarted; 339 __le32 mu_seq_posted; 340 __le32 seq_switch_hw_paused; 341 __le32 next_seq_posted_dsr; 342 __le32 seq_posted_isr; 343 __le32 seq_ctrl_cached; 344 __le32 mpdu_count_tqm; 345 __le32 msdu_count_tqm; 346 __le32 mpdu_removed_tqm; 347 __le32 msdu_removed_tqm; 348 __le32 mpdus_sw_flush; 349 __le32 mpdus_hw_filter; 350 __le32 mpdus_truncated; 351 __le32 mpdus_ack_failed; 352 __le32 mpdus_expired; 353 __le32 mpdus_seq_hw_retry; 354 __le32 ack_tlv_proc; 355 __le32 coex_abort_mpdu_cnt_valid; 356 __le32 coex_abort_mpdu_cnt; 357 __le32 num_total_ppdus_tried_ota; 358 __le32 num_data_ppdus_tried_ota; 359 __le32 local_ctrl_mgmt_enqued; 360 __le32 local_ctrl_mgmt_freed; 361 __le32 local_data_enqued; 362 __le32 local_data_freed; 363 __le32 mpdu_tried; 364 __le32 isr_wait_seq_posted; 365 366 __le32 tx_active_dur_us_low; 367 __le32 tx_active_dur_us_high; 368 __le32 remove_mpdus_max_retries; 369 __le32 comp_delivered; 370 __le32 ppdu_ok; 371 __le32 self_triggers; 372 __le32 tx_time_dur_data; 373 __le32 seq_qdepth_repost_stop; 374 __le32 mu_seq_min_msdu_repost_stop; 375 __le32 seq_min_msdu_repost_stop; 376 __le32 seq_txop_repost_stop; 377 __le32 next_seq_cancel; 378 __le32 fes_offsets_err_cnt; 379 __le32 num_mu_peer_blacklisted; 380 __le32 mu_ofdma_seq_posted; 381 __le32 ul_mumimo_seq_posted; 382 __le32 ul_ofdma_seq_posted; 383 384 __le32 thermal_suspend_cnt; 385 __le32 dfs_suspend_cnt; 386 __le32 tx_abort_suspend_cnt; 387 __le32 tgt_specific_opaque_txq_suspend_info; 388 __le32 last_suspend_reason; 389 } __packed; 390 391 struct ath12k_htt_tx_pdev_stats_urrn_tlv { 392 DECLARE_FLEX_ARRAY(__le32, urrn_stats); 393 } __packed; 394 395 struct ath12k_htt_tx_pdev_stats_flush_tlv { 396 DECLARE_FLEX_ARRAY(__le32, flush_errs); 397 } __packed; 398 399 struct ath12k_htt_tx_pdev_stats_phy_err_tlv { 400 DECLARE_FLEX_ARRAY(__le32, phy_errs); 401 } __packed; 402 403 struct ath12k_htt_tx_pdev_stats_sifs_tlv { 404 DECLARE_FLEX_ARRAY(__le32, sifs_status); 405 } __packed; 406 407 struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv { 408 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 409 } __packed; 410 411 struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv { 412 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status); 413 } __packed; 414 415 enum ath12k_htt_stats_hw_mode { 416 ATH12K_HTT_STATS_HWMODE_AC = 0, 417 ATH12K_HTT_STATS_HWMODE_AX = 1, 418 ATH12K_HTT_STATS_HWMODE_BE = 2, 419 }; 420 421 struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv { 422 __le32 hw_mode; 423 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS]; 424 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 425 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS]; 426 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 427 } __packed; 428 429 #define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 430 #define ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 431 #define ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 432 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 433 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 434 #define ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES 7 435 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 436 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 437 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LTF 4 438 #define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 439 #define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 440 #define ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 441 #define ATH12K_HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 442 443 #define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ 444 (ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ 445 ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ 446 ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) 447 448 struct ath12k_htt_tx_pdev_rate_stats_tlv { 449 __le32 mac_id_word; 450 __le32 tx_ldpc; 451 __le32 rts_cnt; 452 __le32 ack_rssi; 453 __le32 tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 454 __le32 tx_su_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 455 __le32 tx_mu_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 456 __le32 tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 457 __le32 tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 458 __le32 tx_stbc[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 459 __le32 tx_pream[ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 460 __le32 tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 461 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 462 __le32 tx_dcm[ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 463 __le32 rts_success; 464 __le32 tx_legacy_cck_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 465 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 466 __le32 ac_mu_mimo_tx_ldpc; 467 __le32 ax_mu_mimo_tx_ldpc; 468 __le32 ofdma_tx_ldpc; 469 __le32 tx_he_ltf[ATH12K_HTT_TX_PDEV_STATS_NUM_LTF]; 470 __le32 ac_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 471 __le32 ax_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 472 __le32 ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 473 __le32 ac_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 474 __le32 ax_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 475 __le32 ofdma_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 476 __le32 ac_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 477 __le32 ax_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 478 __le32 ofdma_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 479 __le32 ac_mu_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 480 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 481 __le32 ax_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 482 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 483 __le32 ofdma_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 484 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 485 __le32 trigger_type_11ax[ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; 486 __le32 tx_11ax_su_ext; 487 __le32 tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 488 __le32 tx_stbc_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 489 __le32 tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 490 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 491 __le32 ax_mu_mimo_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 492 __le32 ofdma_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 493 __le32 ax_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 494 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 495 __le32 ofd_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 496 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 497 __le32 tx_mcs_ext_2[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 498 __le32 tx_bw_320mhz; 499 } __packed; 500 501 struct ath12k_htt_tx_histogram_stats_tlv { 502 __le32 rate_retry_mcs_drop_cnt; 503 __le32 mcs_drop_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; 504 __le32 per_histogram_cnt[ATH12K_HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; 505 __le32 low_latency_rate_cnt; 506 __le32 su_burst_rate_drop_cnt; 507 __le32 su_burst_rate_drop_fail_cnt; 508 } __packed; 509 510 #define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 511 #define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 512 #define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 513 #define ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 514 #define ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 515 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 516 #define ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 517 #define ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES 7 518 #define ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 519 #define ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS 16 520 #define ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 521 #define ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 522 #define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 523 524 struct ath12k_htt_rx_pdev_rate_stats_tlv { 525 __le32 mac_id_word; 526 __le32 nsts; 527 __le32 rx_ldpc; 528 __le32 rts_cnt; 529 __le32 rssi_mgmt; 530 __le32 rssi_data; 531 __le32 rssi_comb; 532 __le32 rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 533 __le32 rx_nss[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 534 __le32 rx_dcm[ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 535 __le32 rx_stbc[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 536 __le32 rx_bw[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 537 __le32 rx_pream[ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 538 u8 rssi_chain_in_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 539 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 540 __le32 rx_gi[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 541 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 542 __le32 rssi_in_dbm; 543 __le32 rx_11ax_su_ext; 544 __le32 rx_11ac_mumimo; 545 __le32 rx_11ax_mumimo; 546 __le32 rx_11ax_ofdma; 547 __le32 txbf; 548 __le32 rx_legacy_cck_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 549 __le32 rx_legacy_ofdm_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 550 __le32 rx_active_dur_us_low; 551 __le32 rx_active_dur_us_high; 552 __le32 rx_11ax_ul_ofdma; 553 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 554 __le32 ul_ofdma_rx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 555 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 556 __le32 ul_ofdma_rx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 557 __le32 ul_ofdma_rx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 558 __le32 ul_ofdma_rx_stbc; 559 __le32 ul_ofdma_rx_ldpc; 560 __le32 rx_ulofdma_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 561 __le32 rx_ulofdma_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 562 __le32 rx_ulofdma_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 563 __le32 rx_ulofdma_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 564 __le32 nss_count; 565 __le32 pilot_count; 566 __le32 rx_pil_evm_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 567 [ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS]; 568 __le32 rx_pilot_evm_db_mean[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 569 s8 rx_ul_fd_rssi[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 570 [ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 571 __le32 per_chain_rssi_pkt_type; 572 s8 rx_per_chain_rssi_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 573 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 574 __le32 rx_su_ndpa; 575 __le32 rx_11ax_su_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 576 __le32 rx_mu_ndpa; 577 __le32 rx_11ax_mu_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 578 __le32 rx_br_poll; 579 __le32 rx_11ax_dl_ofdma_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 580 __le32 rx_11ax_dl_ofdma_ru[ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 581 __le32 rx_ulmumimo_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 582 __le32 rx_ulmumimo_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 583 __le32 rx_ulmumimo_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 584 __le32 rx_ulmumimo_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 585 __le32 rx_ulofdma_non_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 586 __le32 rx_ulofdma_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 587 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 588 } __packed; 589 590 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 591 #define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 592 #define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 593 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5 594 #define ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS 5 595 596 struct ath12k_htt_rx_pdev_rate_ext_stats_tlv { 597 u8 rssi_chain_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 598 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 599 s8 rx_per_chain_rssi_ext_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 600 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 601 __le32 rssi_mcast_in_dbm; 602 __le32 rssi_mgmt_in_dbm; 603 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 604 __le32 rx_stbc_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 605 __le32 rx_gi_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 606 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 607 __le32 ul_ofdma_rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 608 __le32 ul_ofdma_rx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 609 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 610 __le32 rx_11ax_su_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 611 __le32 rx_11ax_mu_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 612 __le32 rx_11ax_dl_ofdma_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 613 __le32 rx_mcs_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 614 __le32 rx_bw_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS]; 615 __le32 rx_gi_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 616 [ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 617 __le32 rx_su_punctured_mode[ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 618 } __packed; 619 620 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 621 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 622 623 #define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 624 625 struct ath12k_htt_stats_tx_sched_cmn_tlv { 626 __le32 mac_id__word; 627 __le32 current_timestamp; 628 } __packed; 629 630 struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv { 631 __le32 mac_id__word; 632 __le32 sched_policy; 633 __le32 last_sched_cmd_posted_timestamp; 634 __le32 last_sched_cmd_compl_timestamp; 635 __le32 sched_2_tac_lwm_count; 636 __le32 sched_2_tac_ring_full; 637 __le32 sched_cmd_post_failure; 638 __le32 num_active_tids; 639 __le32 num_ps_schedules; 640 __le32 sched_cmds_pending; 641 __le32 num_tid_register; 642 __le32 num_tid_unregister; 643 __le32 num_qstats_queried; 644 __le32 qstats_update_pending; 645 __le32 last_qstats_query_timestamp; 646 __le32 num_tqm_cmdq_full; 647 __le32 num_de_sched_algo_trigger; 648 __le32 num_rt_sched_algo_trigger; 649 __le32 num_tqm_sched_algo_trigger; 650 __le32 notify_sched; 651 __le32 dur_based_sendn_term; 652 __le32 su_notify2_sched; 653 __le32 su_optimal_queued_msdus_sched; 654 __le32 su_delay_timeout_sched; 655 __le32 su_min_txtime_sched_delay; 656 __le32 su_no_delay; 657 __le32 num_supercycles; 658 __le32 num_subcycles_with_sort; 659 __le32 num_subcycles_no_sort; 660 } __packed; 661 662 struct ath12k_htt_sched_txq_cmd_posted_tlv { 663 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted); 664 } __packed; 665 666 struct ath12k_htt_sched_txq_cmd_reaped_tlv { 667 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped); 668 } __packed; 669 670 struct ath12k_htt_sched_txq_sched_order_su_tlv { 671 DECLARE_FLEX_ARRAY(__le32, sched_order_su); 672 } __packed; 673 674 struct ath12k_htt_sched_txq_sched_ineligibility_tlv { 675 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility); 676 } __packed; 677 678 enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum { 679 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, 680 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, 681 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, 682 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, 683 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, 684 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, 685 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, 686 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 687 }; 688 689 struct ath12k_htt_sched_txq_supercycle_triggers_tlv { 690 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers); 691 } __packed; 692 693 struct ath12k_htt_hw_stats_pdev_errs_tlv { 694 __le32 mac_id__word; 695 __le32 tx_abort; 696 __le32 tx_abort_fail_count; 697 __le32 rx_abort; 698 __le32 rx_abort_fail_count; 699 __le32 warm_reset; 700 __le32 cold_reset; 701 __le32 tx_flush; 702 __le32 tx_glb_reset; 703 __le32 tx_txq_reset; 704 __le32 rx_timeout_reset; 705 __le32 mac_cold_reset_restore_cal; 706 __le32 mac_cold_reset; 707 __le32 mac_warm_reset; 708 __le32 mac_only_reset; 709 __le32 phy_warm_reset; 710 __le32 phy_warm_reset_ucode_trig; 711 __le32 mac_warm_reset_restore_cal; 712 __le32 mac_sfm_reset; 713 __le32 phy_warm_reset_m3_ssr; 714 __le32 phy_warm_reset_reason_phy_m3; 715 __le32 phy_warm_reset_reason_tx_hw_stuck; 716 __le32 phy_warm_reset_reason_num_rx_frame_stuck; 717 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy; 718 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng; 719 __le32 phy_warm_reset_reason_mac_conv_phy_reset; 720 __le32 wal_rx_recovery_rst_mac_hang_cnt; 721 __le32 wal_rx_recovery_rst_known_sig_cnt; 722 __le32 wal_rx_recovery_rst_no_rx_cnt; 723 __le32 wal_rx_recovery_rst_no_rx_consec_cnt; 724 __le32 wal_rx_recovery_rst_rx_busy_cnt; 725 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt; 726 __le32 rx_flush_cnt; 727 __le32 phy_warm_reset_reason_tx_exp_cca_stuck; 728 __le32 phy_warm_reset_reason_tx_consec_flsh_war; 729 __le32 phy_warm_reset_reason_tx_hwsch_reset_war; 730 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war; 731 __le32 fw_rx_rings_reset; 732 __le32 rx_dest_drain_rx_descs_leak_prevented; 733 __le32 rx_dest_drain_rx_descs_saved_cnt; 734 __le32 rx_dest_drain_rxdma2reo_leak_detected; 735 __le32 rx_dest_drain_rxdma2fw_leak_detected; 736 __le32 rx_dest_drain_rxdma2wbm_leak_detected; 737 __le32 rx_dest_drain_rxdma1_2sw_leak_detected; 738 __le32 rx_dest_drain_rx_drain_ok_mac_idle; 739 __le32 rx_dest_drain_ok_mac_not_idle; 740 __le32 rx_dest_drain_prerequisite_invld; 741 __le32 rx_dest_drain_skip_non_lmac_reset; 742 __le32 rx_dest_drain_hw_fifo_notempty_post_wait; 743 } __packed; 744 745 #define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8 746 struct ath12k_htt_hw_stats_intr_misc_tlv { 747 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN]; 748 __le32 mask; 749 __le32 count; 750 } __packed; 751 752 struct ath12k_htt_hw_stats_whal_tx_tlv { 753 __le32 mac_id__word; 754 __le32 last_unpause_ppdu_id; 755 __le32 hwsch_unpause_wait_tqm_write; 756 __le32 hwsch_dummy_tlv_skipped; 757 __le32 hwsch_misaligned_offset_received; 758 __le32 hwsch_reset_count; 759 __le32 hwsch_dev_reset_war; 760 __le32 hwsch_delayed_pause; 761 __le32 hwsch_long_delayed_pause; 762 __le32 sch_rx_ppdu_no_response; 763 __le32 sch_selfgen_response; 764 __le32 sch_rx_sifs_resp_trigger; 765 } __packed; 766 767 struct ath12k_htt_hw_war_stats_tlv { 768 __le32 mac_id__word; 769 DECLARE_FLEX_ARRAY(__le32, hw_wars); 770 } __packed; 771 772 struct ath12k_htt_tx_tqm_cmn_stats_tlv { 773 __le32 mac_id__word; 774 __le32 max_cmdq_id; 775 __le32 list_mpdu_cnt_hist_intvl; 776 __le32 add_msdu; 777 __le32 q_empty; 778 __le32 q_not_empty; 779 __le32 drop_notification; 780 __le32 desc_threshold; 781 __le32 hwsch_tqm_invalid_status; 782 __le32 missed_tqm_gen_mpdus; 783 __le32 tqm_active_tids; 784 __le32 tqm_inactive_tids; 785 __le32 tqm_active_msduq_flows; 786 __le32 msduq_timestamp_updates; 787 __le32 msduq_updates_mpdu_head_info_cmd; 788 __le32 msduq_updates_emp_to_nonemp_status; 789 __le32 get_mpdu_head_info_cmds_by_query; 790 __le32 get_mpdu_head_info_cmds_by_tac; 791 __le32 gen_mpdu_cmds_by_query; 792 __le32 high_prio_q_not_empty; 793 } __packed; 794 795 struct ath12k_htt_tx_tqm_error_stats_tlv { 796 __le32 q_empty_failure; 797 __le32 q_not_empty_failure; 798 __le32 add_msdu_failure; 799 __le32 tqm_cache_ctl_err; 800 __le32 tqm_soft_reset; 801 __le32 tqm_reset_num_in_use_link_descs; 802 __le32 tqm_reset_num_lost_link_descs; 803 __le32 tqm_reset_num_lost_host_tx_buf_cnt; 804 __le32 tqm_reset_num_in_use_internal_tqm; 805 __le32 tqm_reset_num_in_use_idle_link_rng; 806 __le32 tqm_reset_time_to_tqm_hang_delta_ms; 807 __le32 tqm_reset_recovery_time_ms; 808 __le32 tqm_reset_num_peers_hdl; 809 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt; 810 __le32 tqm_reset_cumm_dirty_hw_msduq_proc; 811 __le32 tqm_reset_flush_cache_cmd_su_cnt; 812 __le32 tqm_reset_flush_cache_cmd_other_cnt; 813 __le32 tqm_reset_flush_cache_cmd_trig_type; 814 __le32 tqm_reset_flush_cache_cmd_trig_cfg; 815 __le32 tqm_reset_flush_cmd_skp_status_null; 816 } __packed; 817 818 struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv { 819 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason); 820 } __packed; 821 822 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 823 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 824 825 struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv { 826 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason); 827 } __packed; 828 829 struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv { 830 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist); 831 } __packed; 832 833 struct ath12k_htt_tx_tqm_pdev_stats_tlv { 834 __le32 msdu_count; 835 __le32 mpdu_count; 836 __le32 remove_msdu; 837 __le32 remove_mpdu; 838 __le32 remove_msdu_ttl; 839 __le32 send_bar; 840 __le32 bar_sync; 841 __le32 notify_mpdu; 842 __le32 sync_cmd; 843 __le32 write_cmd; 844 __le32 hwsch_trigger; 845 __le32 ack_tlv_proc; 846 __le32 gen_mpdu_cmd; 847 __le32 gen_list_cmd; 848 __le32 remove_mpdu_cmd; 849 __le32 remove_mpdu_tried_cmd; 850 __le32 mpdu_queue_stats_cmd; 851 __le32 mpdu_head_info_cmd; 852 __le32 msdu_flow_stats_cmd; 853 __le32 remove_msdu_cmd; 854 __le32 remove_msdu_ttl_cmd; 855 __le32 flush_cache_cmd; 856 __le32 update_mpduq_cmd; 857 __le32 enqueue; 858 __le32 enqueue_notify; 859 __le32 notify_mpdu_at_head; 860 __le32 notify_mpdu_state_valid; 861 __le32 sched_udp_notify1; 862 __le32 sched_udp_notify2; 863 __le32 sched_nonudp_notify1; 864 __le32 sched_nonudp_notify2; 865 } __packed; 866 867 struct ath12k_htt_tx_de_cmn_stats_tlv { 868 __le32 mac_id__word; 869 __le32 tcl2fw_entry_count; 870 __le32 not_to_fw; 871 __le32 invalid_pdev_vdev_peer; 872 __le32 tcl_res_invalid_addrx; 873 __le32 wbm2fw_entry_count; 874 __le32 invalid_pdev; 875 __le32 tcl_res_addrx_timeout; 876 __le32 invalid_vdev; 877 __le32 invalid_tcl_exp_frame_desc; 878 __le32 vdev_id_mismatch_cnt; 879 } __packed; 880 881 struct ath12k_htt_tx_de_eapol_packets_stats_tlv { 882 __le32 m1_packets; 883 __le32 m2_packets; 884 __le32 m3_packets; 885 __le32 m4_packets; 886 __le32 g1_packets; 887 __le32 g2_packets; 888 __le32 rc4_packets; 889 __le32 eap_packets; 890 __le32 eapol_start_packets; 891 __le32 eapol_logoff_packets; 892 __le32 eapol_encap_asf_packets; 893 } __packed; 894 895 struct ath12k_htt_tx_de_classify_stats_tlv { 896 __le32 arp_packets; 897 __le32 igmp_packets; 898 __le32 dhcp_packets; 899 __le32 host_inspected; 900 __le32 htt_included; 901 __le32 htt_valid_mcs; 902 __le32 htt_valid_nss; 903 __le32 htt_valid_preamble_type; 904 __le32 htt_valid_chainmask; 905 __le32 htt_valid_guard_interval; 906 __le32 htt_valid_retries; 907 __le32 htt_valid_bw_info; 908 __le32 htt_valid_power; 909 __le32 htt_valid_key_flags; 910 __le32 htt_valid_no_encryption; 911 __le32 fse_entry_count; 912 __le32 fse_priority_be; 913 __le32 fse_priority_high; 914 __le32 fse_priority_low; 915 __le32 fse_traffic_ptrn_be; 916 __le32 fse_traffic_ptrn_over_sub; 917 __le32 fse_traffic_ptrn_bursty; 918 __le32 fse_traffic_ptrn_interactive; 919 __le32 fse_traffic_ptrn_periodic; 920 __le32 fse_hwqueue_alloc; 921 __le32 fse_hwqueue_created; 922 __le32 fse_hwqueue_send_to_host; 923 __le32 mcast_entry; 924 __le32 bcast_entry; 925 __le32 htt_update_peer_cache; 926 __le32 htt_learning_frame; 927 __le32 fse_invalid_peer; 928 __le32 mec_notify; 929 } __packed; 930 931 struct ath12k_htt_tx_de_classify_failed_stats_tlv { 932 __le32 ap_bss_peer_not_found; 933 __le32 ap_bcast_mcast_no_peer; 934 __le32 sta_delete_in_progress; 935 __le32 ibss_no_bss_peer; 936 __le32 invalid_vdev_type; 937 __le32 invalid_ast_peer_entry; 938 __le32 peer_entry_invalid; 939 __le32 ethertype_not_ip; 940 __le32 eapol_lookup_failed; 941 __le32 qpeer_not_allow_data; 942 __le32 fse_tid_override; 943 __le32 ipv6_jumbogram_zero_length; 944 __le32 qos_to_non_qos_in_prog; 945 __le32 ap_bcast_mcast_eapol; 946 __le32 unicast_on_ap_bss_peer; 947 __le32 ap_vdev_invalid; 948 __le32 incomplete_llc; 949 __le32 eapol_duplicate_m3; 950 __le32 eapol_duplicate_m4; 951 } __packed; 952 953 struct ath12k_htt_tx_de_classify_status_stats_tlv { 954 __le32 eok; 955 __le32 classify_done; 956 __le32 lookup_failed; 957 __le32 send_host_dhcp; 958 __le32 send_host_mcast; 959 __le32 send_host_unknown_dest; 960 __le32 send_host; 961 __le32 status_invalid; 962 } __packed; 963 964 struct ath12k_htt_tx_de_enqueue_packets_stats_tlv { 965 __le32 enqueued_pkts; 966 __le32 to_tqm; 967 __le32 to_tqm_bypass; 968 } __packed; 969 970 struct ath12k_htt_tx_de_enqueue_discard_stats_tlv { 971 __le32 discarded_pkts; 972 __le32 local_frames; 973 __le32 is_ext_msdu; 974 } __packed; 975 976 struct ath12k_htt_tx_de_compl_stats_tlv { 977 __le32 tcl_dummy_frame; 978 __le32 tqm_dummy_frame; 979 __le32 tqm_notify_frame; 980 __le32 fw2wbm_enq; 981 __le32 tqm_bypass_frame; 982 } __packed; 983 984 enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats { 985 ATH12K_HTT_TX_MUMIMO_GRP_VALID, 986 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 987 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 988 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 989 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 990 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 991 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 992 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 993 ATH12K_HTT_TX_MUMIMO_GRP_INVALID, 994 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 995 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 996 }; 997 998 #define ATH12K_HTT_NUM_AC_WMM 0x4 999 #define ATH12K_HTT_MAX_NUM_SBT_INTR 4 1000 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 1001 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 1002 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 1003 #define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7 1004 #define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74 1005 #define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8 1006 #define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8 1007 #define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 1008 1009 #define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \ 1010 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 1011 #define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 1012 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE) 1013 1014 struct ath12k_htt_tx_selfgen_cmn_stats_tlv { 1015 __le32 mac_id__word; 1016 __le32 su_bar; 1017 __le32 rts; 1018 __le32 cts2self; 1019 __le32 qos_null; 1020 __le32 delayed_bar_1; 1021 __le32 delayed_bar_2; 1022 __le32 delayed_bar_3; 1023 __le32 delayed_bar_4; 1024 __le32 delayed_bar_5; 1025 __le32 delayed_bar_6; 1026 __le32 delayed_bar_7; 1027 } __packed; 1028 1029 struct ath12k_htt_tx_selfgen_ac_stats_tlv { 1030 __le32 ac_su_ndpa; 1031 __le32 ac_su_ndp; 1032 __le32 ac_mu_mimo_ndpa; 1033 __le32 ac_mu_mimo_ndp; 1034 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1]; 1035 } __packed; 1036 1037 struct ath12k_htt_tx_selfgen_ax_stats_tlv { 1038 __le32 ax_su_ndpa; 1039 __le32 ax_su_ndp; 1040 __le32 ax_mu_mimo_ndpa; 1041 __le32 ax_mu_mimo_ndp; 1042 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 1043 __le32 ax_basic_trigger; 1044 __le32 ax_bsr_trigger; 1045 __le32 ax_mu_bar_trigger; 1046 __le32 ax_mu_rts_trigger; 1047 __le32 ax_ulmumimo_trigger; 1048 } __packed; 1049 1050 struct ath12k_htt_tx_selfgen_be_stats_tlv { 1051 __le32 be_su_ndpa; 1052 __le32 be_su_ndp; 1053 __le32 be_mu_mimo_ndpa; 1054 __le32 be_mu_mimo_ndp; 1055 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1056 __le32 be_basic_trigger; 1057 __le32 be_bsr_trigger; 1058 __le32 be_mu_bar_trigger; 1059 __le32 be_mu_rts_trigger; 1060 __le32 be_ulmumimo_trigger; 1061 __le32 be_su_ndpa_queued; 1062 __le32 be_su_ndp_queued; 1063 __le32 be_mu_mimo_ndpa_queued; 1064 __le32 be_mu_mimo_ndp_queued; 1065 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1066 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1067 } __packed; 1068 1069 struct ath12k_htt_tx_selfgen_ac_err_stats_tlv { 1070 __le32 ac_su_ndp_err; 1071 __le32 ac_su_ndpa_err; 1072 __le32 ac_mu_mimo_ndpa_err; 1073 __le32 ac_mu_mimo_ndp_err; 1074 __le32 ac_mu_mimo_brp1_err; 1075 __le32 ac_mu_mimo_brp2_err; 1076 __le32 ac_mu_mimo_brp3_err; 1077 } __packed; 1078 1079 struct ath12k_htt_tx_selfgen_ax_err_stats_tlv { 1080 __le32 ax_su_ndp_err; 1081 __le32 ax_su_ndpa_err; 1082 __le32 ax_mu_mimo_ndpa_err; 1083 __le32 ax_mu_mimo_ndp_err; 1084 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 1085 __le32 ax_basic_trigger_err; 1086 __le32 ax_bsr_trigger_err; 1087 __le32 ax_mu_bar_trigger_err; 1088 __le32 ax_mu_rts_trigger_err; 1089 __le32 ax_ulmumimo_trigger_err; 1090 } __packed; 1091 1092 struct ath12k_htt_tx_selfgen_be_err_stats_tlv { 1093 __le32 be_su_ndp_err; 1094 __le32 be_su_ndpa_err; 1095 __le32 be_mu_mimo_ndpa_err; 1096 __le32 be_mu_mimo_ndp_err; 1097 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1098 __le32 be_basic_trigger_err; 1099 __le32 be_bsr_trigger_err; 1100 __le32 be_mu_bar_trigger_err; 1101 __le32 be_mu_rts_trigger_err; 1102 __le32 be_ulmumimo_trigger_err; 1103 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1104 __le32 be_su_ndpa_flushed; 1105 __le32 be_su_ndp_flushed; 1106 __le32 be_mu_mimo_ndpa_flushed; 1107 __le32 be_mu_mimo_ndp_flushed; 1108 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1109 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1110 } __packed; 1111 1112 enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats { 1113 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 1114 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 1115 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 1116 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 1117 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 1118 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 1119 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 1120 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 1121 1122 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS 1123 }; 1124 1125 struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv { 1126 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1127 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1128 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1129 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1130 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1131 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1132 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1133 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1134 } __packed; 1135 1136 struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv { 1137 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1138 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1139 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1140 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1141 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1142 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1143 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1144 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1145 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1146 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1147 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1148 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1149 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1150 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1151 } __packed; 1152 1153 struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv { 1154 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1155 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1156 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1157 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1158 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1159 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1160 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1161 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1162 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1163 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1164 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1165 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1166 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1167 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1168 } __packed; 1169 1170 struct ath12k_htt_stats_string_tlv { 1171 DECLARE_FLEX_ARRAY(__le32, data); 1172 } __packed; 1173 1174 #define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 1175 #define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8) 1176 #define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16) 1177 #define ATH12K_HTT_SRING_STATS_EP BIT(24) 1178 #define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 1179 #define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 1180 #define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 1181 #define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 1182 #define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 1183 #define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 1184 #define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 1185 #define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 1186 1187 struct ath12k_htt_sring_stats_tlv { 1188 __le32 mac_id__ring_id__arena__ep; 1189 __le32 base_addr_lsb; 1190 __le32 base_addr_msb; 1191 __le32 ring_size; 1192 __le32 elem_size; 1193 __le32 num_avail_words__num_valid_words; 1194 __le32 head_ptr__tail_ptr; 1195 __le32 consumer_empty__producer_full; 1196 __le32 prefetch_count__internal_tail_ptr; 1197 } __packed; 1198 1199 struct ath12k_htt_sfm_cmn_tlv { 1200 __le32 mac_id__word; 1201 __le32 buf_total; 1202 __le32 mem_empty; 1203 __le32 deallocate_bufs; 1204 __le32 num_records; 1205 } __packed; 1206 1207 struct ath12k_htt_sfm_client_tlv { 1208 __le32 client_id; 1209 __le32 buf_min; 1210 __le32 buf_max; 1211 __le32 buf_busy; 1212 __le32 buf_alloc; 1213 __le32 buf_avail; 1214 __le32 num_users; 1215 } __packed; 1216 1217 struct ath12k_htt_sfm_client_user_tlv { 1218 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n); 1219 } __packed; 1220 1221 struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv { 1222 __le32 mu_mimo_sch_posted; 1223 __le32 mu_mimo_sch_failed; 1224 __le32 mu_mimo_ppdu_posted; 1225 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1226 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1227 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1228 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1229 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1230 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1231 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1232 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1233 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1234 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1235 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1236 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1237 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1238 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1239 } __packed; 1240 1241 struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv { 1242 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1243 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1244 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1245 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1246 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 1247 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1248 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1249 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1250 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1251 } __packed; 1252 1253 enum ath12k_htt_stats_tx_sched_modes { 1254 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0, 1255 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX, 1256 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX, 1257 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE, 1258 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 1259 }; 1260 1261 struct ath12k_htt_tx_pdev_mpdu_stats_tlv { 1262 __le32 mpdus_queued_usr; 1263 __le32 mpdus_tried_usr; 1264 __le32 mpdus_failed_usr; 1265 __le32 mpdus_requeued_usr; 1266 __le32 err_no_ba_usr; 1267 __le32 mpdu_underrun_usr; 1268 __le32 ampdu_underrun_usr; 1269 __le32 user_index; 1270 __le32 tx_sched_mode; 1271 } __packed; 1272 1273 struct ath12k_htt_pdev_stats_cca_counters_tlv { 1274 __le32 tx_frame_usec; 1275 __le32 rx_frame_usec; 1276 __le32 rx_clear_usec; 1277 __le32 my_rx_frame_usec; 1278 __le32 usec_cnt; 1279 __le32 med_rx_idle_usec; 1280 __le32 med_tx_idle_global_usec; 1281 __le32 cca_obss_usec; 1282 } __packed; 1283 1284 struct ath12k_htt_pdev_cca_stats_hist_v1_tlv { 1285 __le32 chan_num; 1286 __le32 num_records; 1287 __le32 valid_cca_counters_bitmap; 1288 __le32 collection_interval; 1289 } __packed; 1290 1291 #define ATH12K_HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 1292 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 1293 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 1294 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 1295 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1296 #define ATH12K_HTT_TX_NUM_MCS_CNTRS 12 1297 #define ATH12K_HTT_TX_NUM_EXTRA_MCS_CNTRS 2 1298 1299 #define ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1300 (ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1301 ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS) 1302 1303 enum ath12k_htt_txbf_sound_steer_modes { 1304 ATH12K_HTT_IMPL_STEER_STATS = 0, 1305 ATH12K_HTT_EXPL_SUSIFS_STEER_STATS = 1, 1306 ATH12K_HTT_EXPL_SURBO_STEER_STATS = 2, 1307 ATH12K_HTT_EXPL_MUSIFS_STEER_STATS = 3, 1308 ATH12K_HTT_EXPL_MURBO_STEER_STATS = 4, 1309 ATH12K_HTT_TXBF_MAX_NUM_OF_MODES = 5 1310 }; 1311 1312 enum ath12k_htt_stats_sounding_tx_mode { 1313 ATH12K_HTT_TX_AC_SOUNDING_MODE = 0, 1314 ATH12K_HTT_TX_AX_SOUNDING_MODE = 1, 1315 ATH12K_HTT_TX_BE_SOUNDING_MODE = 2, 1316 ATH12K_HTT_TX_CMN_SOUNDING_MODE = 3, 1317 }; 1318 1319 struct ath12k_htt_tx_sounding_stats_tlv { 1320 __le32 tx_sounding_mode; 1321 __le32 cbf_20[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1322 __le32 cbf_40[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1323 __le32 cbf_80[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1324 __le32 cbf_160[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1325 __le32 sounding[ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1326 __le32 cv_nc_mismatch_err; 1327 __le32 cv_fcs_err; 1328 __le32 cv_frag_idx_mismatch; 1329 __le32 cv_invalid_peer_id; 1330 __le32 cv_no_txbf_setup; 1331 __le32 cv_expiry_in_update; 1332 __le32 cv_pkt_bw_exceed; 1333 __le32 cv_dma_not_done_err; 1334 __le32 cv_update_failed; 1335 __le32 cv_total_query; 1336 __le32 cv_total_pattern_query; 1337 __le32 cv_total_bw_query; 1338 __le32 cv_invalid_bw_coding; 1339 __le32 cv_forced_sounding; 1340 __le32 cv_standalone_sounding; 1341 __le32 cv_nc_mismatch; 1342 __le32 cv_fb_type_mismatch; 1343 __le32 cv_ofdma_bw_mismatch; 1344 __le32 cv_bw_mismatch; 1345 __le32 cv_pattern_mismatch; 1346 __le32 cv_preamble_mismatch; 1347 __le32 cv_nr_mismatch; 1348 __le32 cv_in_use_cnt_exceeded; 1349 __le32 cv_found; 1350 __le32 cv_not_found; 1351 __le32 sounding_320[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1352 __le32 cbf_320[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1353 __le32 cv_ntbr_sounding; 1354 __le32 cv_found_upload_in_progress; 1355 __le32 cv_expired_during_query; 1356 __le32 cv_dma_timeout_error; 1357 __le32 cv_buf_ibf_uploads; 1358 __le32 cv_buf_ebf_uploads; 1359 __le32 cv_buf_received; 1360 __le32 cv_buf_fed_back; 1361 __le32 cv_total_query_ibf; 1362 __le32 cv_found_ibf; 1363 __le32 cv_not_found_ibf; 1364 __le32 cv_expired_during_query_ibf; 1365 } __packed; 1366 1367 struct ath12k_htt_pdev_obss_pd_stats_tlv { 1368 __le32 num_obss_tx_ppdu_success; 1369 __le32 num_obss_tx_ppdu_failure; 1370 __le32 num_sr_tx_transmissions; 1371 __le32 num_spatial_reuse_opportunities; 1372 __le32 num_non_srg_opportunities; 1373 __le32 num_non_srg_ppdu_tried; 1374 __le32 num_non_srg_ppdu_success; 1375 __le32 num_srg_opportunities; 1376 __le32 num_srg_ppdu_tried; 1377 __le32 num_srg_ppdu_success; 1378 __le32 num_psr_opportunities; 1379 __le32 num_psr_ppdu_tried; 1380 __le32 num_psr_ppdu_success; 1381 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1382 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM]; 1383 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1384 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1385 __le32 num_obss_min_dur_check_flush_cnt; 1386 __le32 num_sr_ppdu_abort_flush_cnt; 1387 } __packed; 1388 1389 #define ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 1390 #define ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST 3 1391 #define ATH12K_HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 1392 1393 struct ath12k_htt_latency_prof_stats_tlv { 1394 __le32 print_header; 1395 s8 latency_prof_name[ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 1396 __le32 cnt; 1397 __le32 min; 1398 __le32 max; 1399 __le32 last; 1400 __le32 tot; 1401 __le32 avg; 1402 __le32 hist_intvl; 1403 __le32 hist[ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST]; 1404 } __packed; 1405 1406 struct ath12k_htt_latency_prof_ctx_tlv { 1407 __le32 duration; 1408 __le32 tx_msdu_cnt; 1409 __le32 tx_mpdu_cnt; 1410 __le32 tx_ppdu_cnt; 1411 __le32 rx_msdu_cnt; 1412 __le32 rx_mpdu_cnt; 1413 } __packed; 1414 1415 struct ath12k_htt_latency_prof_cnt_tlv { 1416 __le32 prof_enable_cnt; 1417 } __packed; 1418 1419 #define ATH12K_HTT_RX_NUM_MCS_CNTRS 12 1420 #define ATH12K_HTT_RX_NUM_GI_CNTRS 4 1421 #define ATH12K_HTT_RX_NUM_SPATIAL_STREAMS 8 1422 #define ATH12K_HTT_RX_NUM_BW_CNTRS 4 1423 #define ATH12K_HTT_RX_NUM_RU_SIZE_CNTRS 6 1424 #define ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS 7 1425 #define ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 1426 #define ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES 2 1427 #define ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS 2 1428 1429 enum ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE { 1430 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_26, 1431 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_52, 1432 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_106, 1433 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_242, 1434 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_484, 1435 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996, 1436 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996x2, 1437 ATH12K_HTT_TX_RX_PDEV_STATS_NUM_AX_RU_SIZE_CNTRS, 1438 }; 1439 1440 struct ath12k_htt_rx_pdev_ul_ofdma_user_stats_tlv { 1441 __le32 user_index; 1442 __le32 rx_ulofdma_non_data_ppdu; 1443 __le32 rx_ulofdma_data_ppdu; 1444 __le32 rx_ulofdma_mpdu_ok; 1445 __le32 rx_ulofdma_mpdu_fail; 1446 __le32 rx_ulofdma_non_data_nusers; 1447 __le32 rx_ulofdma_data_nusers; 1448 } __packed; 1449 1450 struct ath12k_htt_rx_pdev_ul_trigger_stats_tlv { 1451 __le32 mac_id__word; 1452 __le32 rx_11ax_ul_ofdma; 1453 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1454 __le32 ul_ofdma_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1455 __le32 ul_ofdma_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1456 __le32 ul_ofdma_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS]; 1457 __le32 ul_ofdma_rx_stbc; 1458 __le32 ul_ofdma_rx_ldpc; 1459 __le32 data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS]; 1460 __le32 non_data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS]; 1461 __le32 uplink_sta_aid[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1462 __le32 uplink_sta_target_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1463 __le32 uplink_sta_fd_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1464 __le32 uplink_sta_power_headroom[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1465 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1466 __le32 ul_ofdma_bsc_trig_rx_qos_null_only; 1467 } __packed; 1468 1469 #define ATH12K_HTT_TX_UL_MUMIMO_USER_STATS 8 1470 1471 struct ath12k_htt_rx_ul_mumimo_trig_stats_tlv { 1472 __le32 mac_id__word; 1473 __le32 rx_11ax_ul_mumimo; 1474 __le32 ul_mumimo_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1475 __le32 ul_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1476 __le32 ul_mumimo_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1477 __le32 ul_mumimo_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS]; 1478 __le32 ul_mumimo_rx_stbc; 1479 __le32 ul_mumimo_rx_ldpc; 1480 __le32 ul_mumimo_rx_mcs_ext[ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS]; 1481 __le32 ul_gi_ext[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS]; 1482 s8 ul_rssi[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1483 s8 tgt_rssi[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1484 s8 fd[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1485 s8 db[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1486 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1487 __le32 mumimo_bsc_trig_rx_qos_null_only; 1488 } __packed; 1489 1490 #define ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX 10 1491 #define ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX 10 1492 #define ATH12K_HTT_RX_NUM_SQUARE_INDEX 6 1493 #define ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX 4 1494 #define ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX 4 1495 1496 struct ath12k_htt_rx_fse_stats_tlv { 1497 __le32 fse_enable_cnt; 1498 __le32 fse_disable_cnt; 1499 __le32 fse_cache_invalidate_entry_cnt; 1500 __le32 fse_full_cache_invalidate_cnt; 1501 __le32 fse_num_cache_hits_cnt; 1502 __le32 fse_num_searches_cnt; 1503 __le32 fse_cache_occupancy_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX]; 1504 __le32 fse_cache_occupancy_curr_cnt[ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX]; 1505 __le32 fse_search_stat_square_cnt[ATH12K_HTT_RX_NUM_SQUARE_INDEX]; 1506 __le32 fse_search_stat_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX]; 1507 __le32 fse_search_stat_pending_cnt[ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX]; 1508 } __packed; 1509 1510 #define ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS 14 1511 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1512 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1513 #define ATH12K_HTT_TXBF_NUM_BW_CNTRS 5 1514 #define ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES 2 1515 1516 struct ath12k_htt_pdev_txrate_txbf_stats_tlv { 1517 __le32 tx_su_txbf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1518 __le32 tx_su_ibf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1519 __le32 tx_su_ol_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1520 __le32 tx_su_txbf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1521 __le32 tx_su_ibf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1522 __le32 tx_su_ol_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1523 __le32 tx_su_txbf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1524 __le32 tx_su_ibf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1525 __le32 tx_su_ol_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1526 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1527 __le32 txbf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1528 __le32 ibf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1529 __le32 ol[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1530 __le32 txbf_flag_set_mu_mode; 1531 __le32 txbf_flag_set_final_status; 1532 __le32 txbf_flag_not_set_verified_txbf_mode; 1533 __le32 txbf_flag_not_set_disable_p2p_access; 1534 __le32 txbf_flag_not_set_max_nss_in_he160; 1535 __le32 txbf_flag_not_set_disable_uldlofdma; 1536 __le32 txbf_flag_not_set_mcs_threshold_val; 1537 __le32 txbf_flag_not_set_final_status; 1538 } __packed; 1539 1540 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t { 1541 __le32 ax_ofdma_ndpa_queued; 1542 __le32 ax_ofdma_ndpa_tried; 1543 __le32 ax_ofdma_ndpa_flush; 1544 __le32 ax_ofdma_ndpa_err; 1545 } __packed; 1546 1547 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_tlv { 1548 __le32 num_elems_ax_ndpa_arr; 1549 __le32 arr_elem_size_ax_ndpa; 1550 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa); 1551 } __packed; 1552 1553 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t { 1554 __le32 ax_ofdma_ndp_queued; 1555 __le32 ax_ofdma_ndp_tried; 1556 __le32 ax_ofdma_ndp_flush; 1557 __le32 ax_ofdma_ndp_err; 1558 } __packed; 1559 1560 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_tlv { 1561 __le32 num_elems_ax_ndp_arr; 1562 __le32 arr_elem_size_ax_ndp; 1563 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp); 1564 } __packed; 1565 1566 struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t { 1567 __le32 ax_ofdma_brp_queued; 1568 __le32 ax_ofdma_brp_tried; 1569 __le32 ax_ofdma_brp_flushed; 1570 __le32 ax_ofdma_brp_err; 1571 __le32 ax_ofdma_num_cbf_rcvd; 1572 } __packed; 1573 1574 struct ath12k_htt_txbf_ofdma_ax_brp_stats_tlv { 1575 __le32 num_elems_ax_brp_arr; 1576 __le32 arr_elem_size_ax_brp; 1577 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp); 1578 } __packed; 1579 1580 struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t { 1581 __le32 num_ppdu_steer; 1582 __le32 num_ppdu_ol; 1583 __le32 num_usr_prefetch; 1584 __le32 num_usr_sound; 1585 __le32 num_usr_force_sound; 1586 } __packed; 1587 1588 struct ath12k_htt_txbf_ofdma_ax_steer_stats_tlv { 1589 __le32 num_elems_ax_steer_arr; 1590 __le32 arr_elem_size_ax_steer; 1591 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer); 1592 } __packed; 1593 1594 struct ath12k_htt_txbf_ofdma_ax_steer_mpdu_stats_tlv { 1595 __le32 ax_ofdma_rbo_steer_mpdus_tried; 1596 __le32 ax_ofdma_rbo_steer_mpdus_failed; 1597 __le32 ax_ofdma_sifs_steer_mpdus_tried; 1598 __le32 ax_ofdma_sifs_steer_mpdus_failed; 1599 } __packed; 1600 1601 enum ath12k_htt_stats_page_lock_state { 1602 ATH12K_HTT_STATS_PAGE_LOCKED = 0, 1603 ATH12K_HTT_STATS_PAGE_UNLOCKED = 1, 1604 ATH12K_NUM_PG_LOCK_STATE 1605 }; 1606 1607 #define ATH12K_PAGER_MAX 10 1608 1609 #define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0) 1610 #define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8) 1611 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0) 1612 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16) 1613 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0) 1614 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16) 1615 1616 struct ath12k_htt_pgs_info { 1617 __le32 page_num; 1618 __le32 num_pgs; 1619 __le32 ts_lsb; 1620 __le32 ts_msb; 1621 } __packed; 1622 1623 struct ath12k_htt_dl_pager_stats_tlv { 1624 __le32 info0; 1625 __le32 info1; 1626 __le32 info2; 1627 struct ath12k_htt_pgs_info pgs_info[ATH12K_NUM_PG_LOCK_STATE][ATH12K_PAGER_MAX]; 1628 } __packed; 1629 1630 #define ATH12K_HTT_STATS_MAX_CHAINS 8 1631 #define ATH12K_HTT_MAX_RX_PKT_CNT 8 1632 #define ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1633 #define ATH12K_HTT_MAX_PER_BLK_ERR_CNT 20 1634 #define ATH12K_HTT_MAX_RX_OTA_ERR_CNT 14 1635 #define ATH12K_HTT_MAX_CH_PWR_INFO_SIZE 16 1636 1637 struct ath12k_htt_phy_stats_tlv { 1638 a_sle32 nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1639 __le32 false_radar_cnt; 1640 __le32 radar_cs_cnt; 1641 a_sle32 ani_level; 1642 __le32 fw_run_time; 1643 a_sle32 runtime_nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1644 } __packed; 1645 1646 struct ath12k_htt_phy_counters_tlv { 1647 __le32 rx_ofdma_timing_err_cnt; 1648 __le32 rx_cck_fail_cnt; 1649 __le32 mactx_abort_cnt; 1650 __le32 macrx_abort_cnt; 1651 __le32 phytx_abort_cnt; 1652 __le32 phyrx_abort_cnt; 1653 __le32 phyrx_defer_abort_cnt; 1654 __le32 rx_gain_adj_lstf_event_cnt; 1655 __le32 rx_gain_adj_non_legacy_cnt; 1656 __le32 rx_pkt_cnt[ATH12K_HTT_MAX_RX_PKT_CNT]; 1657 __le32 rx_pkt_crc_pass_cnt[ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1658 __le32 per_blk_err_cnt[ATH12K_HTT_MAX_PER_BLK_ERR_CNT]; 1659 __le32 rx_ota_err_cnt[ATH12K_HTT_MAX_RX_OTA_ERR_CNT]; 1660 } __packed; 1661 1662 struct ath12k_htt_phy_reset_stats_tlv { 1663 __le32 pdev_id; 1664 __le32 chan_mhz; 1665 __le32 chan_band_center_freq1; 1666 __le32 chan_band_center_freq2; 1667 __le32 chan_phy_mode; 1668 __le32 chan_flags; 1669 __le32 chan_num; 1670 __le32 reset_cause; 1671 __le32 prev_reset_cause; 1672 __le32 phy_warm_reset_src; 1673 __le32 rx_gain_tbl_mode; 1674 __le32 xbar_val; 1675 __le32 force_calibration; 1676 __le32 phyrf_mode; 1677 __le32 phy_homechan; 1678 __le32 phy_tx_ch_mask; 1679 __le32 phy_rx_ch_mask; 1680 __le32 phybb_ini_mask; 1681 __le32 phyrf_ini_mask; 1682 __le32 phy_dfs_en_mask; 1683 __le32 phy_sscan_en_mask; 1684 __le32 phy_synth_sel_mask; 1685 __le32 phy_adfs_freq; 1686 __le32 cck_fir_settings; 1687 __le32 phy_dyn_pri_chan; 1688 __le32 cca_thresh; 1689 __le32 dyn_cca_status; 1690 __le32 rxdesense_thresh_hw; 1691 __le32 rxdesense_thresh_sw; 1692 } __packed; 1693 1694 struct ath12k_htt_phy_reset_counters_tlv { 1695 __le32 pdev_id; 1696 __le32 cf_active_low_fail_cnt; 1697 __le32 cf_active_low_pass_cnt; 1698 __le32 phy_off_through_vreg_cnt; 1699 __le32 force_calibration_cnt; 1700 __le32 rf_mode_switch_phy_off_cnt; 1701 __le32 temperature_recal_cnt; 1702 } __packed; 1703 1704 struct ath12k_htt_phy_tpc_stats_tlv { 1705 __le32 pdev_id; 1706 __le32 tx_power_scale; 1707 __le32 tx_power_scale_db; 1708 __le32 min_negative_tx_power; 1709 __le32 reg_ctl_domain; 1710 __le32 max_reg_allowed_power[ATH12K_HTT_STATS_MAX_CHAINS]; 1711 __le32 max_reg_allowed_power_6ghz[ATH12K_HTT_STATS_MAX_CHAINS]; 1712 __le32 twice_max_rd_power; 1713 __le32 max_tx_power; 1714 __le32 home_max_tx_power; 1715 __le32 psd_power; 1716 __le32 eirp_power; 1717 __le32 power_type_6ghz; 1718 __le32 sub_band_cfreq[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1719 __le32 sub_band_txpower[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1720 } __packed; 1721 1722 struct ath12k_htt_t2h_soc_txrx_stats_common_tlv { 1723 __le32 inv_peers_msdu_drop_count_hi; 1724 __le32 inv_peers_msdu_drop_count_lo; 1725 } __packed; 1726 1727 #define ATH12K_HTT_AST_PDEV_ID_INFO GENMASK(1, 0) 1728 #define ATH12K_HTT_AST_VDEV_ID_INFO GENMASK(9, 2) 1729 #define ATH12K_HTT_AST_NEXT_HOP_INFO BIT(10) 1730 #define ATH12K_HTT_AST_MCAST_INFO BIT(11) 1731 #define ATH12K_HTT_AST_MONITOR_DIRECT_INFO BIT(12) 1732 #define ATH12K_HTT_AST_MESH_STA_INFO BIT(13) 1733 #define ATH12K_HTT_AST_MEC_INFO BIT(14) 1734 #define ATH12K_HTT_AST_INTRA_BSS_INFO BIT(15) 1735 1736 struct ath12k_htt_ast_entry_tlv { 1737 __le32 sw_peer_id; 1738 __le32 ast_index; 1739 struct htt_mac_addr mac_addr; 1740 __le32 info; 1741 } __packed; 1742 1743 enum ath12k_htt_stats_direction { 1744 ATH12K_HTT_STATS_DIRECTION_TX, 1745 ATH12K_HTT_STATS_DIRECTION_RX 1746 }; 1747 1748 enum ath12k_htt_stats_ppdu_type { 1749 ATH12K_HTT_STATS_PPDU_TYPE_MODE_SU, 1750 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_MIMO, 1751 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_MIMO, 1752 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, 1753 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_OFDMA 1754 }; 1755 1756 enum ath12k_htt_stats_param_type { 1757 ATH12K_HTT_STATS_PREAM_OFDM, 1758 ATH12K_HTT_STATS_PREAM_CCK, 1759 ATH12K_HTT_STATS_PREAM_HT, 1760 ATH12K_HTT_STATS_PREAM_VHT, 1761 ATH12K_HTT_STATS_PREAM_HE, 1762 ATH12K_HTT_STATS_PREAM_EHT, 1763 ATH12K_HTT_STATS_PREAM_RSVD1, 1764 ATH12K_HTT_STATS_PREAM_COUNT, 1765 }; 1766 1767 #define ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT 32 1768 1769 struct ath12k_htt_pdev_puncture_stats_tlv { 1770 __le32 mac_id__word; 1771 __le32 direction; 1772 __le32 preamble; 1773 __le32 ppdu_type; 1774 __le32 subband_cnt; 1775 __le32 last_used_pattern_mask; 1776 __le32 num_subbands_used_cnt[ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT]; 1777 } __packed; 1778 1779 struct ath12k_htt_dmac_reset_stats_tlv { 1780 __le32 reset_count; 1781 __le32 reset_time_lo_ms; 1782 __le32 reset_time_hi_ms; 1783 __le32 disengage_time_lo_ms; 1784 __le32 disengage_time_hi_ms; 1785 __le32 engage_time_lo_ms; 1786 __le32 engage_time_hi_ms; 1787 __le32 disengage_count; 1788 __le32 engage_count; 1789 __le32 drain_dest_ring_mask; 1790 } __packed; 1791 1792 struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv { 1793 __le32 mac_id__word; 1794 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1795 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1796 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM]; 1797 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1798 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1799 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1800 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1801 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM]; 1802 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM]; 1803 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM]; 1804 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM]; 1805 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM]; 1806 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM]; 1807 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM]; 1808 } __packed; 1809 1810 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS 4 1811 #define ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS 8 1812 #define ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS 14 1813 1814 enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE { 1815 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26, 1816 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52, 1817 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26, 1818 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106, 1819 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26, 1820 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242, 1821 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484, 1822 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242, 1823 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996, 1824 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484, 1825 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 1826 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2, 1827 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 1828 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3, 1829 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 1830 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4, 1831 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS, 1832 }; 1833 1834 enum ATH12K_HTT_RC_MODE { 1835 ATH12K_HTT_RC_MODE_SU_OL, 1836 ATH12K_HTT_RC_MODE_SU_BF, 1837 ATH12K_HTT_RC_MODE_MU1_INTF, 1838 ATH12K_HTT_RC_MODE_MU2_INTF, 1839 ATH12K_HTT_RC_MODE_MU3_INTF, 1840 ATH12K_HTT_RC_MODE_MU4_INTF, 1841 ATH12K_HTT_RC_MODE_MU5_INTF, 1842 ATH12K_HTT_RC_MODE_MU6_INTF, 1843 ATH12K_HTT_RC_MODE_MU7_INTF, 1844 ATH12K_HTT_RC_MODE_2D_COUNT 1845 }; 1846 1847 enum ath12k_htt_stats_rc_mode { 1848 ATH12K_HTT_STATS_RC_MODE_DLSU = 0, 1849 ATH12K_HTT_STATS_RC_MODE_DLMUMIMO = 1, 1850 ATH12K_HTT_STATS_RC_MODE_DLOFDMA = 2, 1851 ATH12K_HTT_STATS_RC_MODE_ULMUMIMO = 3, 1852 ATH12K_HTT_STATS_RC_MODE_ULOFDMA = 4, 1853 }; 1854 1855 enum ath12k_htt_stats_ru_type { 1856 ATH12K_HTT_STATS_RU_TYPE_INVALID, 1857 ATH12K_HTT_STATS_RU_TYPE_SINGLE_RU_ONLY, 1858 ATH12K_HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU, 1859 }; 1860 1861 struct ath12k_htt_tx_rate_stats { 1862 __le32 ppdus_tried; 1863 __le32 ppdus_ack_failed; 1864 __le32 mpdus_tried; 1865 __le32 mpdus_failed; 1866 } __packed; 1867 1868 struct ath12k_htt_tx_per_rate_stats_tlv { 1869 __le32 rc_mode; 1870 __le32 last_probed_mcs; 1871 __le32 last_probed_nss; 1872 __le32 last_probed_bw; 1873 struct ath12k_htt_tx_rate_stats per_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS]; 1874 struct ath12k_htt_tx_rate_stats per_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1875 struct ath12k_htt_tx_rate_stats per_mcs[ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS]; 1876 struct ath12k_htt_tx_rate_stats per_bw320; 1877 __le32 probe_cnt[ATH12K_HTT_RC_MODE_2D_COUNT]; 1878 __le32 ru_type; 1879 struct ath12k_htt_tx_rate_stats ru[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1880 } __packed; 1881 1882 #define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16 1883 #define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5 1884 #define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4 1885 #define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4 1886 1887 struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv { 1888 __le32 mac_id__word; 1889 __le32 be_ofdma_tx_ldpc; 1890 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1891 __le32 be_ofdma_tx_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1892 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS]; 1893 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1894 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1895 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS]; 1896 } __packed; 1897 1898 struct ath12k_htt_pdev_mbssid_ctrl_frame_tlv { 1899 __le32 mac_id__word; 1900 __le32 basic_trigger_across_bss; 1901 __le32 basic_trigger_within_bss; 1902 __le32 bsr_trigger_across_bss; 1903 __le32 bsr_trigger_within_bss; 1904 __le32 mu_rts_across_bss; 1905 __le32 mu_rts_within_bss; 1906 __le32 ul_mumimo_trigger_across_bss; 1907 __le32 ul_mumimo_trigger_within_bss; 1908 } __packed; 1909 1910 struct ath12k_htt_pdev_tdma_stats_tlv { 1911 __le32 mac_id__word; 1912 __le32 num_tdma_active_schedules; 1913 __le32 num_tdma_reserved_schedules; 1914 __le32 num_tdma_restricted_schedules; 1915 __le32 num_tdma_unconfigured_schedules; 1916 __le32 num_tdma_slot_switches; 1917 __le32 num_tdma_edca_switches; 1918 } __packed; 1919 1920 struct ath12k_htt_mlo_sched_stats_tlv { 1921 __le32 pref_link_num_sec_link_sched; 1922 __le32 pref_link_num_pref_link_timeout; 1923 __le32 pref_link_num_pref_link_sch_delay_ipc; 1924 __le32 pref_link_num_pref_link_timeout_ipc; 1925 } __packed; 1926 1927 #define ATH12K_HTT_HWMLO_MAX_LINKS 6 1928 #define ATH12K_HTT_MLO_MAX_IPC_RINGS 7 1929 1930 struct ath12k_htt_pdev_mlo_ipc_stats_tlv { 1931 __le32 mlo_ipc_ring_cnt[ATH12K_HTT_HWMLO_MAX_LINKS][ATH12K_HTT_MLO_MAX_IPC_RINGS]; 1932 } __packed; 1933 1934 struct ath12k_htt_stats_pdev_rtt_resp_stats_tlv { 1935 __le32 pdev_id; 1936 __le32 tx_11mc_ftm_suc; 1937 __le32 tx_11mc_ftm_suc_retry; 1938 __le32 tx_11mc_ftm_fail; 1939 __le32 rx_11mc_ftmr_cnt; 1940 __le32 rx_11mc_ftmr_dup_cnt; 1941 __le32 rx_11mc_iftmr_cnt; 1942 __le32 rx_11mc_iftmr_dup_cnt; 1943 __le32 ftmr_drop_11mc_resp_role_not_enabled_cnt; 1944 __le32 initiator_active_responder_rejected_cnt; 1945 __le32 responder_terminate_cnt; 1946 __le32 active_rsta_open; 1947 __le32 active_rsta_mac; 1948 __le32 active_rsta_mac_phy; 1949 __le32 num_assoc_ranging_peers; 1950 __le32 num_unassoc_ranging_peers; 1951 __le32 responder_alloc_cnt; 1952 __le32 responder_alloc_failure; 1953 __le32 pn_check_failure_cnt; 1954 __le32 pasn_m1_auth_recv_cnt; 1955 __le32 pasn_m1_auth_drop_cnt; 1956 __le32 pasn_m2_auth_recv_cnt; 1957 __le32 pasn_m2_auth_tx_fail_cnt; 1958 __le32 pasn_m3_auth_recv_cnt; 1959 __le32 pasn_m3_auth_drop_cnt; 1960 __le32 pasn_peer_create_request_cnt; 1961 __le32 pasn_peer_create_timeout_cnt; 1962 __le32 pasn_peer_created_cnt; 1963 __le32 sec_ranging_not_supported_mfp_not_setup; 1964 __le32 non_sec_ranging_discarded_for_assoc_peer; 1965 __le32 open_ranging_discarded_set_for_pasn_peer; 1966 __le32 unassoc_non_pasn_ranging_not_supported; 1967 __le32 num_req_bw_20_mhz; 1968 __le32 num_req_bw_40_mhz; 1969 __le32 num_req_bw_80_mhz; 1970 __le32 num_req_bw_160_mhz; 1971 __le32 tx_11az_ftm_successful; 1972 __le32 tx_11az_ftm_failed; 1973 __le32 rx_11az_ftmr_cnt; 1974 __le32 rx_11az_ftmr_dup_cnt; 1975 __le32 rx_11az_iftmr_dup_cnt; 1976 __le32 malformed_ftmr; 1977 __le32 ftmr_drop_ntb_resp_role_not_enabled_cnt; 1978 __le32 ftmr_drop_tb_resp_role_not_enabled_cnt; 1979 __le32 invalid_ftm_request_params; 1980 __le32 requested_bw_format_not_supported; 1981 __le32 ntb_unsec_unassoc_ranging_peer_alloc_failed; 1982 __le32 tb_unassoc_unsec_pasn_peer_creation_failed; 1983 __le32 num_ranging_sequences_processed; 1984 __le32 ntb_tx_ndp; 1985 __le32 ndp_rx_cnt; 1986 __le32 num_ntb_ranging_ndpas_recv; 1987 __le32 recv_lmr; 1988 __le32 invalid_ftmr_cnt; 1989 __le32 max_time_bw_meas_exp_cnt; 1990 } __packed; 1991 1992 #define ATH12K_HTT_MAX_SCH_CMD_RESULT 25 1993 #define ATH12K_HTT_SCH_CMD_STATUS_CNT 9 1994 1995 struct ath12k_htt_stats_pdev_rtt_init_stats_tlv { 1996 __le32 pdev_id; 1997 __le32 tx_11mc_ftmr_cnt; 1998 __le32 tx_11mc_ftmr_fail; 1999 __le32 tx_11mc_ftmr_suc_retry; 2000 __le32 rx_11mc_ftm_cnt; 2001 __le32 tx_meas_req_count; 2002 __le32 init_role_not_enabled; 2003 __le32 initiator_terminate_cnt; 2004 __le32 tx_11az_ftmr_fail; 2005 __le32 tx_11az_ftmr_start; 2006 __le32 tx_11az_ftmr_stop; 2007 __le32 rx_11az_ftm_cnt; 2008 __le32 active_ista; 2009 __le32 invalid_preamble; 2010 __le32 invalid_chan_bw_format; 2011 __le32 mgmt_buff_alloc_fail_cnt; 2012 __le32 ftm_parse_failure; 2013 __le32 ranging_negotiation_successful_cnt; 2014 __le32 incompatible_ftm_params; 2015 __le32 sec_ranging_req_in_open_mode; 2016 __le32 ftmr_tx_failed_null_11az_peer; 2017 __le32 ftmr_retry_timeout; 2018 __le32 max_time_bw_meas_exp_cnt; 2019 __le32 tb_meas_duration_expiry_cnt; 2020 __le32 num_tb_ranging_requests; 2021 __le32 ntbr_triggered_successfully; 2022 __le32 ntbr_trigger_failed; 2023 __le32 invalid_or_no_vreg_idx; 2024 __le32 set_vreg_params_failed; 2025 __le32 sac_mismatch; 2026 __le32 pasn_m1_auth_recv_cnt; 2027 __le32 pasn_m1_auth_tx_fail_cnt; 2028 __le32 pasn_m2_auth_recv_cnt; 2029 __le32 pasn_m2_auth_drop_cnt; 2030 __le32 pasn_m3_auth_recv_cnt; 2031 __le32 pasn_m3_auth_tx_fail_cnt; 2032 __le32 pasn_peer_create_request_cnt; 2033 __le32 pasn_peer_create_timeout_cnt; 2034 __le32 pasn_peer_created_cnt; 2035 __le32 ntbr_ndpa_failed; 2036 __le32 ntbr_sequence_successful; 2037 __le32 ntbr_ndp_failed; 2038 __le32 sch_cmd_status_cnts[ATH12K_HTT_SCH_CMD_STATUS_CNT]; 2039 __le32 lmr_timeout; 2040 __le32 lmr_recv; 2041 __le32 num_trigger_frames_received; 2042 __le32 num_tb_ranging_ndpas_recv; 2043 __le32 ndp_rx_cnt; 2044 } __packed; 2045 2046 struct ath12k_htt_stats_pdev_rtt_hw_stats_tlv { 2047 __le32 ista_ranging_ndpa_cnt; 2048 __le32 ista_ranging_ndp_cnt; 2049 __le32 ista_ranging_i2r_lmr_cnt; 2050 __le32 rtsa_ranging_resp_cnt; 2051 __le32 rtsa_ranging_ndp_cnt; 2052 __le32 rsta_ranging_lmr_cnt; 2053 __le32 tb_ranging_cts2s_rcvd_cnt; 2054 __le32 tb_ranging_ndp_rcvd_cnt; 2055 __le32 tb_ranging_lmr_rcvd_cnt; 2056 __le32 tb_ranging_tf_poll_resp_sent_cnt; 2057 __le32 tb_ranging_tf_sound_resp_sent_cnt; 2058 __le32 tb_ranging_tf_report_resp_sent_cnt; 2059 } __packed; 2060 2061 enum ath12k_htt_stats_txsend_ftype { 2062 ATH12K_HTT_FTYPE_TF_POLL, 2063 ATH12K_HTT_FTYPE_TF_SOUND, 2064 ATH12K_HTT_FTYPE_TBR_NDPA, 2065 ATH12K_HTT_FTYPE_TBR_NDP, 2066 ATH12K_HTT_FTYPE_TBR_LMR, 2067 ATH12K_HTT_FTYPE_TF_RPRT, 2068 ATH12K_HTT_FTYPE_MAX 2069 }; 2070 2071 struct ath12k_htt_stats_pdev_rtt_tbr_tlv { 2072 __le32 su_ftype[ATH12K_HTT_FTYPE_MAX]; 2073 __le32 mu_ftype[ATH12K_HTT_FTYPE_MAX]; 2074 } __packed; 2075 2076 struct ath12k_htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv { 2077 __le32 tbr_num_sch_cmd_result_buckets; 2078 __le32 su_res[ATH12K_HTT_FTYPE_MAX][ATH12K_HTT_MAX_SCH_CMD_RESULT]; 2079 __le32 mu_res[ATH12K_HTT_FTYPE_MAX][ATH12K_HTT_MAX_SCH_CMD_RESULT]; 2080 } __packed; 2081 2082 struct htt_rx_pdev_fw_stats_tlv { 2083 __le32 mac_id__word; 2084 __le32 ppdu_recvd; 2085 __le32 mpdu_cnt_fcs_ok; 2086 __le32 mpdu_cnt_fcs_err; 2087 __le32 tcp_msdu_cnt; 2088 __le32 tcp_ack_msdu_cnt; 2089 __le32 udp_msdu_cnt; 2090 __le32 other_msdu_cnt; 2091 __le32 fw_ring_mpdu_ind; 2092 __le32 fw_ring_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 2093 __le32 fw_ring_ctrl_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 2094 __le32 fw_ring_mcast_data_msdu; 2095 __le32 fw_ring_bcast_data_msdu; 2096 __le32 fw_ring_ucast_data_msdu; 2097 __le32 fw_ring_null_data_msdu; 2098 __le32 fw_ring_mpdu_drop; 2099 __le32 ofld_local_data_ind_cnt; 2100 __le32 ofld_local_data_buf_recycle_cnt; 2101 __le32 drx_local_data_ind_cnt; 2102 __le32 drx_local_data_buf_recycle_cnt; 2103 __le32 local_nondata_ind_cnt; 2104 __le32 local_nondata_buf_recycle_cnt; 2105 __le32 fw_status_buf_ring_refill_cnt; 2106 __le32 fw_status_buf_ring_empty_cnt; 2107 __le32 fw_pkt_buf_ring_refill_cnt; 2108 __le32 fw_pkt_buf_ring_empty_cnt; 2109 __le32 fw_link_buf_ring_refill_cnt; 2110 __le32 fw_link_buf_ring_empty_cnt; 2111 __le32 host_pkt_buf_ring_refill_cnt; 2112 __le32 host_pkt_buf_ring_empty_cnt; 2113 __le32 mon_pkt_buf_ring_refill_cnt; 2114 __le32 mon_pkt_buf_ring_empty_cnt; 2115 __le32 mon_status_buf_ring_refill_cnt; 2116 __le32 mon_status_buf_ring_empty_cnt; 2117 __le32 mon_desc_buf_ring_refill_cnt; 2118 __le32 mon_desc_buf_ring_empty_cnt; 2119 __le32 mon_dest_ring_update_cnt; 2120 __le32 mon_dest_ring_full_cnt; 2121 __le32 rx_suspend_cnt; 2122 __le32 rx_suspend_fail_cnt; 2123 __le32 rx_resume_cnt; 2124 __le32 rx_resume_fail_cnt; 2125 __le32 rx_ring_switch_cnt; 2126 __le32 rx_ring_restore_cnt; 2127 __le32 rx_flush_cnt; 2128 __le32 rx_recovery_reset_cnt; 2129 __le32 rx_lwm_prom_filter_dis; 2130 __le32 rx_hwm_prom_filter_en; 2131 __le32 bytes_received_low_32; 2132 __le32 bytes_received_high_32; 2133 } __packed; 2134 2135 struct htt_tx_hwq_stats_cmn_tlv { 2136 __le32 mac_id__hwq_id__word; 2137 __le32 xretry; 2138 __le32 underrun_cnt; 2139 __le32 flush_cnt; 2140 __le32 filt_cnt; 2141 __le32 null_mpdu_bmap; 2142 __le32 user_ack_failure; 2143 __le32 ack_tlv_proc; 2144 __le32 sched_id_proc; 2145 __le32 null_mpdu_tx_count; 2146 __le32 mpdu_bmap_not_recvd; 2147 __le32 num_bar; 2148 __le32 rts; 2149 __le32 cts2self; 2150 __le32 qos_null; 2151 __le32 mpdu_tried_cnt; 2152 __le32 mpdu_queued_cnt; 2153 __le32 mpdu_ack_fail_cnt; 2154 __le32 mpdu_filt_cnt; 2155 __le32 false_mpdu_ack_count; 2156 __le32 txq_timeout; 2157 } __packed; 2158 2159 #endif 2160