1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 #if defined(__FreeBSD__) 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/etherdevice.h> 21 #include <linux/rcupdate.h> 22 #include <linux/lockdep.h> 23 #include <linux/seq_file.h> 24 #include <linux/leds.h> 25 #endif 26 27 #include "util.h" 28 29 #define RTW_MAX_MAC_ID_NUM 32 30 #define RTW_MAX_SEC_CAM_NUM 32 31 #define MAX_PG_CAM_BACKUP_NUM 8 32 33 #define RTW_SCAN_MAX_SSIDS 4 34 35 #define RTW_MAX_PATTERN_NUM 12 36 #define RTW_MAX_PATTERN_MASK_SIZE 16 37 #define RTW_MAX_PATTERN_SIZE 128 38 39 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 40 41 #define RFREG_MASK 0xfffff 42 #define INV_RF_DATA 0xffffffff 43 #define TX_PAGE_SIZE_SHIFT 7 44 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT) 45 46 #define RTW_CHANNEL_WIDTH_MAX 3 47 #define RTW_RF_PATH_MAX 4 48 #define HW_FEATURE_LEN 13 49 50 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 51 52 extern bool rtw_bf_support; 53 extern bool rtw_disable_lps_deep_mode; 54 extern unsigned int rtw_debug_mask; 55 extern bool rtw_edcca_enabled; 56 extern const struct ieee80211_ops rtw_ops; 57 58 #define RTW_MAX_CHANNEL_NUM_2G 14 59 #define RTW_MAX_CHANNEL_NUM_5G 49 60 61 struct rtw_dev; 62 struct rtw_debugfs; 63 64 enum rtw_hci_type { 65 RTW_HCI_TYPE_PCIE, 66 RTW_HCI_TYPE_USB, 67 RTW_HCI_TYPE_SDIO, 68 69 RTW_HCI_TYPE_UNDEFINE, 70 }; 71 72 struct rtw_hci { 73 struct rtw_hci_ops *ops; 74 enum rtw_hci_type type; 75 76 u32 rpwm_addr; 77 u32 cpwm_addr; 78 79 u8 bulkout_num; 80 }; 81 82 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 83 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 84 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 85 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 86 87 #define IS_CH_5G_BAND_MID(channel) \ 88 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 89 90 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 91 #define IS_CH_5G_BAND(channel) \ 92 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 93 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 94 95 enum rtw_supported_band { 96 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 97 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 98 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 99 }; 100 101 /* now, support up to 80M bw */ 102 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 103 104 enum rtw_bandwidth { 105 RTW_CHANNEL_WIDTH_20 = 0, 106 RTW_CHANNEL_WIDTH_40 = 1, 107 RTW_CHANNEL_WIDTH_80 = 2, 108 RTW_CHANNEL_WIDTH_160 = 3, 109 RTW_CHANNEL_WIDTH_80_80 = 4, 110 RTW_CHANNEL_WIDTH_5 = 5, 111 RTW_CHANNEL_WIDTH_10 = 6, 112 }; 113 114 enum rtw_sc_offset { 115 RTW_SC_DONT_CARE = 0, 116 RTW_SC_20_UPPER = 1, 117 RTW_SC_20_LOWER = 2, 118 RTW_SC_20_UPMOST = 3, 119 RTW_SC_20_LOWEST = 4, 120 RTW_SC_40_UPPER = 9, 121 RTW_SC_40_LOWER = 10, 122 }; 123 124 enum rtw_net_type { 125 RTW_NET_NO_LINK = 0, 126 RTW_NET_AD_HOC = 1, 127 RTW_NET_MGD_LINKED = 2, 128 RTW_NET_AP_MODE = 3, 129 }; 130 131 enum rtw_rf_type { 132 RF_1T1R = 0, 133 RF_1T2R = 1, 134 RF_2T2R = 2, 135 RF_2T3R = 3, 136 RF_2T4R = 4, 137 RF_3T3R = 5, 138 RF_3T4R = 6, 139 RF_4T4R = 7, 140 RF_TYPE_MAX, 141 }; 142 143 enum rtw_rf_path { 144 RF_PATH_A = 0, 145 RF_PATH_B = 1, 146 RF_PATH_C = 2, 147 RF_PATH_D = 3, 148 }; 149 150 enum rtw_bb_path { 151 BB_PATH_A = BIT(0), 152 BB_PATH_B = BIT(1), 153 BB_PATH_C = BIT(2), 154 BB_PATH_D = BIT(3), 155 156 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 157 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 158 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 159 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 160 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 161 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 162 163 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 164 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 165 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 166 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 167 168 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 169 }; 170 171 enum rtw_rate_section { 172 RTW_RATE_SECTION_CCK = 0, 173 RTW_RATE_SECTION_OFDM, 174 RTW_RATE_SECTION_HT_1S, 175 RTW_RATE_SECTION_HT_2S, 176 RTW_RATE_SECTION_VHT_1S, 177 RTW_RATE_SECTION_VHT_2S, 178 179 /* keep last */ 180 RTW_RATE_SECTION_MAX, 181 }; 182 183 enum rtw_wireless_set { 184 WIRELESS_CCK = 0x00000001, 185 WIRELESS_OFDM = 0x00000002, 186 WIRELESS_HT = 0x00000004, 187 WIRELESS_VHT = 0x00000008, 188 }; 189 190 #define HT_STBC_EN BIT(0) 191 #define VHT_STBC_EN BIT(1) 192 #define HT_LDPC_EN BIT(0) 193 #define VHT_LDPC_EN BIT(1) 194 195 enum rtw_chip_type { 196 RTW_CHIP_TYPE_8822B, 197 RTW_CHIP_TYPE_8822C, 198 RTW_CHIP_TYPE_8723D, 199 RTW_CHIP_TYPE_8821C, 200 RTW_CHIP_TYPE_8703B, 201 RTW_CHIP_TYPE_8821A, 202 RTW_CHIP_TYPE_8812A, 203 }; 204 205 enum rtw_tx_queue_type { 206 /* the order of AC queues matters */ 207 RTW_TX_QUEUE_BK = 0x0, 208 RTW_TX_QUEUE_BE = 0x1, 209 RTW_TX_QUEUE_VI = 0x2, 210 RTW_TX_QUEUE_VO = 0x3, 211 212 RTW_TX_QUEUE_BCN = 0x4, 213 RTW_TX_QUEUE_MGMT = 0x5, 214 RTW_TX_QUEUE_HI0 = 0x6, 215 RTW_TX_QUEUE_H2C = 0x7, 216 /* keep it last */ 217 RTK_MAX_TX_QUEUE_NUM 218 }; 219 220 enum rtw_rx_queue_type { 221 RTW_RX_QUEUE_MPDU = 0x0, 222 RTW_RX_QUEUE_C2H = 0x1, 223 /* keep it last */ 224 RTK_MAX_RX_QUEUE_NUM 225 }; 226 227 enum rtw_fw_type { 228 RTW_NORMAL_FW = 0x0, 229 RTW_WOWLAN_FW = 0x1, 230 }; 231 232 enum rtw_rate_index { 233 RTW_RATEID_BGN_40M_2SS = 0, 234 RTW_RATEID_BGN_40M_1SS = 1, 235 RTW_RATEID_BGN_20M_2SS = 2, 236 RTW_RATEID_BGN_20M_1SS = 3, 237 RTW_RATEID_GN_N2SS = 4, 238 RTW_RATEID_GN_N1SS = 5, 239 RTW_RATEID_BG = 6, 240 RTW_RATEID_G = 7, 241 RTW_RATEID_B_20M = 8, 242 RTW_RATEID_ARFR0_AC_2SS = 9, 243 RTW_RATEID_ARFR1_AC_1SS = 10, 244 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 245 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 246 RTW_RATEID_ARFR4_AC_3SS = 13, 247 RTW_RATEID_ARFR5_N_3SS = 14, 248 RTW_RATEID_ARFR7_N_4SS = 15, 249 RTW_RATEID_ARFR6_AC_4SS = 16 250 }; 251 252 enum rtw_trx_desc_rate { 253 DESC_RATE1M = 0x00, 254 DESC_RATE2M = 0x01, 255 DESC_RATE5_5M = 0x02, 256 DESC_RATE11M = 0x03, 257 258 DESC_RATE6M = 0x04, 259 DESC_RATE9M = 0x05, 260 DESC_RATE12M = 0x06, 261 DESC_RATE18M = 0x07, 262 DESC_RATE24M = 0x08, 263 DESC_RATE36M = 0x09, 264 DESC_RATE48M = 0x0a, 265 DESC_RATE54M = 0x0b, 266 267 DESC_RATEMCS0 = 0x0c, 268 DESC_RATEMCS1 = 0x0d, 269 DESC_RATEMCS2 = 0x0e, 270 DESC_RATEMCS3 = 0x0f, 271 DESC_RATEMCS4 = 0x10, 272 DESC_RATEMCS5 = 0x11, 273 DESC_RATEMCS6 = 0x12, 274 DESC_RATEMCS7 = 0x13, 275 DESC_RATEMCS8 = 0x14, 276 DESC_RATEMCS9 = 0x15, 277 DESC_RATEMCS10 = 0x16, 278 DESC_RATEMCS11 = 0x17, 279 DESC_RATEMCS12 = 0x18, 280 DESC_RATEMCS13 = 0x19, 281 DESC_RATEMCS14 = 0x1a, 282 DESC_RATEMCS15 = 0x1b, 283 DESC_RATEMCS16 = 0x1c, 284 DESC_RATEMCS17 = 0x1d, 285 DESC_RATEMCS18 = 0x1e, 286 DESC_RATEMCS19 = 0x1f, 287 DESC_RATEMCS20 = 0x20, 288 DESC_RATEMCS21 = 0x21, 289 DESC_RATEMCS22 = 0x22, 290 DESC_RATEMCS23 = 0x23, 291 DESC_RATEMCS24 = 0x24, 292 DESC_RATEMCS25 = 0x25, 293 DESC_RATEMCS26 = 0x26, 294 DESC_RATEMCS27 = 0x27, 295 DESC_RATEMCS28 = 0x28, 296 DESC_RATEMCS29 = 0x29, 297 DESC_RATEMCS30 = 0x2a, 298 DESC_RATEMCS31 = 0x2b, 299 300 DESC_RATEVHT1SS_MCS0 = 0x2c, 301 DESC_RATEVHT1SS_MCS1 = 0x2d, 302 DESC_RATEVHT1SS_MCS2 = 0x2e, 303 DESC_RATEVHT1SS_MCS3 = 0x2f, 304 DESC_RATEVHT1SS_MCS4 = 0x30, 305 DESC_RATEVHT1SS_MCS5 = 0x31, 306 DESC_RATEVHT1SS_MCS6 = 0x32, 307 DESC_RATEVHT1SS_MCS7 = 0x33, 308 DESC_RATEVHT1SS_MCS8 = 0x34, 309 DESC_RATEVHT1SS_MCS9 = 0x35, 310 311 DESC_RATEVHT2SS_MCS0 = 0x36, 312 DESC_RATEVHT2SS_MCS1 = 0x37, 313 DESC_RATEVHT2SS_MCS2 = 0x38, 314 DESC_RATEVHT2SS_MCS3 = 0x39, 315 DESC_RATEVHT2SS_MCS4 = 0x3a, 316 DESC_RATEVHT2SS_MCS5 = 0x3b, 317 DESC_RATEVHT2SS_MCS6 = 0x3c, 318 DESC_RATEVHT2SS_MCS7 = 0x3d, 319 DESC_RATEVHT2SS_MCS8 = 0x3e, 320 DESC_RATEVHT2SS_MCS9 = 0x3f, 321 322 DESC_RATEVHT3SS_MCS0 = 0x40, 323 DESC_RATEVHT3SS_MCS1 = 0x41, 324 DESC_RATEVHT3SS_MCS2 = 0x42, 325 DESC_RATEVHT3SS_MCS3 = 0x43, 326 DESC_RATEVHT3SS_MCS4 = 0x44, 327 DESC_RATEVHT3SS_MCS5 = 0x45, 328 DESC_RATEVHT3SS_MCS6 = 0x46, 329 DESC_RATEVHT3SS_MCS7 = 0x47, 330 DESC_RATEVHT3SS_MCS8 = 0x48, 331 DESC_RATEVHT3SS_MCS9 = 0x49, 332 333 DESC_RATEVHT4SS_MCS0 = 0x4a, 334 DESC_RATEVHT4SS_MCS1 = 0x4b, 335 DESC_RATEVHT4SS_MCS2 = 0x4c, 336 DESC_RATEVHT4SS_MCS3 = 0x4d, 337 DESC_RATEVHT4SS_MCS4 = 0x4e, 338 DESC_RATEVHT4SS_MCS5 = 0x4f, 339 DESC_RATEVHT4SS_MCS6 = 0x50, 340 DESC_RATEVHT4SS_MCS7 = 0x51, 341 DESC_RATEVHT4SS_MCS8 = 0x52, 342 DESC_RATEVHT4SS_MCS9 = 0x53, 343 344 DESC_RATE_MAX, 345 }; 346 347 enum rtw_regulatory_domains { 348 RTW_REGD_FCC = 0, 349 RTW_REGD_MKK = 1, 350 RTW_REGD_ETSI = 2, 351 RTW_REGD_IC = 3, 352 RTW_REGD_KCC = 4, 353 RTW_REGD_ACMA = 5, 354 RTW_REGD_CHILE = 6, 355 RTW_REGD_UKRAINE = 7, 356 RTW_REGD_MEXICO = 8, 357 RTW_REGD_CN = 9, 358 RTW_REGD_QATAR = 10, 359 RTW_REGD_UK = 11, 360 361 RTW_REGD_WW, 362 RTW_REGD_MAX 363 }; 364 365 enum rtw_txq_flags { 366 RTW_TXQ_AMPDU, 367 RTW_TXQ_BLOCK_BA, 368 }; 369 370 enum rtw_flags { 371 RTW_FLAG_RUNNING, 372 RTW_FLAG_FW_RUNNING, 373 RTW_FLAG_SCANNING, 374 RTW_FLAG_POWERON, 375 RTW_FLAG_LEISURE_PS, 376 RTW_FLAG_LEISURE_PS_DEEP, 377 RTW_FLAG_DIG_DISABLE, 378 RTW_FLAG_BUSY_TRAFFIC, 379 RTW_FLAG_WOWLAN, 380 RTW_FLAG_RESTARTING, 381 RTW_FLAG_RESTART_TRIGGERING, 382 RTW_FLAG_FORCE_LOWEST_RATE, 383 384 NUM_OF_RTW_FLAGS, 385 }; 386 387 enum rtw_evm { 388 RTW_EVM_OFDM = 0, 389 RTW_EVM_1SS, 390 RTW_EVM_2SS_A, 391 RTW_EVM_2SS_B, 392 /* keep it last */ 393 RTW_EVM_NUM 394 }; 395 396 enum rtw_snr { 397 RTW_SNR_OFDM_A = 0, 398 RTW_SNR_OFDM_B, 399 RTW_SNR_OFDM_C, 400 RTW_SNR_OFDM_D, 401 RTW_SNR_1SS_A, 402 RTW_SNR_1SS_B, 403 RTW_SNR_1SS_C, 404 RTW_SNR_1SS_D, 405 RTW_SNR_2SS_A, 406 RTW_SNR_2SS_B, 407 RTW_SNR_2SS_C, 408 RTW_SNR_2SS_D, 409 /* keep it last */ 410 RTW_SNR_NUM 411 }; 412 413 enum rtw_port { 414 RTW_PORT_0 = 0, 415 RTW_PORT_1 = 1, 416 RTW_PORT_2 = 2, 417 RTW_PORT_3 = 3, 418 RTW_PORT_4 = 4, 419 RTW_PORT_NUM 420 }; 421 422 enum rtw_wow_flags { 423 RTW_WOW_FLAG_EN_MAGIC_PKT, 424 RTW_WOW_FLAG_EN_REKEY_PKT, 425 RTW_WOW_FLAG_EN_DISCONNECT, 426 427 /* keep it last */ 428 RTW_WOW_FLAG_MAX, 429 }; 430 431 /* the power index is represented by differences, which cck-1s & ht40-1s are 432 * the base values, so for 1s's differences, there are only ht20 & ofdm 433 */ 434 struct rtw_2g_1s_pwr_idx_diff { 435 #ifdef __LITTLE_ENDIAN 436 s8 ofdm:4; 437 s8 bw20:4; 438 #else 439 s8 bw20:4; 440 s8 ofdm:4; 441 #endif 442 } __packed; 443 444 struct rtw_2g_ns_pwr_idx_diff { 445 #ifdef __LITTLE_ENDIAN 446 s8 bw20:4; 447 s8 bw40:4; 448 s8 cck:4; 449 s8 ofdm:4; 450 #else 451 s8 ofdm:4; 452 s8 cck:4; 453 s8 bw40:4; 454 s8 bw20:4; 455 #endif 456 } __packed; 457 458 struct rtw_2g_txpwr_idx { 459 u8 cck_base[6]; 460 u8 bw40_base[5]; 461 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 462 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 463 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 464 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 465 }; 466 467 struct rtw_5g_ht_1s_pwr_idx_diff { 468 #ifdef __LITTLE_ENDIAN 469 s8 ofdm:4; 470 s8 bw20:4; 471 #else 472 s8 bw20:4; 473 s8 ofdm:4; 474 #endif 475 } __packed; 476 477 struct rtw_5g_ht_ns_pwr_idx_diff { 478 #ifdef __LITTLE_ENDIAN 479 s8 bw20:4; 480 s8 bw40:4; 481 #else 482 s8 bw40:4; 483 s8 bw20:4; 484 #endif 485 } __packed; 486 487 struct rtw_5g_ofdm_ns_pwr_idx_diff { 488 #ifdef __LITTLE_ENDIAN 489 s8 ofdm_3s:4; 490 s8 ofdm_2s:4; 491 s8 ofdm_4s:4; 492 s8 res:4; 493 #else 494 s8 res:4; 495 s8 ofdm_4s:4; 496 s8 ofdm_2s:4; 497 s8 ofdm_3s:4; 498 #endif 499 } __packed; 500 501 struct rtw_5g_vht_ns_pwr_idx_diff { 502 #ifdef __LITTLE_ENDIAN 503 s8 bw160:4; 504 s8 bw80:4; 505 #else 506 s8 bw80:4; 507 s8 bw160:4; 508 #endif 509 } __packed; 510 511 struct rtw_5g_txpwr_idx { 512 u8 bw40_base[14]; 513 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 514 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 515 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 516 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 517 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 518 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 519 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 520 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 521 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 522 } __packed; 523 524 struct rtw_txpwr_idx { 525 struct rtw_2g_txpwr_idx pwr_idx_2g; 526 struct rtw_5g_txpwr_idx pwr_idx_5g; 527 } __packed; 528 529 struct rtw_channel_params { 530 u8 center_chan; 531 u8 primary_chan; 532 u8 bandwidth; 533 }; 534 535 struct rtw_hw_reg { 536 u32 addr; 537 u32 mask; 538 }; 539 540 struct rtw_hw_reg_desc { 541 u32 addr; 542 u32 mask; 543 const char *desc; 544 }; 545 546 struct rtw_ltecoex_addr { 547 u32 ctrl; 548 u32 wdata; 549 u32 rdata; 550 }; 551 552 struct rtw_reg_domain { 553 u32 addr; 554 u32 mask; 555 #define RTW_REG_DOMAIN_MAC32 0 556 #define RTW_REG_DOMAIN_MAC16 1 557 #define RTW_REG_DOMAIN_MAC8 2 558 #define RTW_REG_DOMAIN_RF_A 3 559 #define RTW_REG_DOMAIN_RF_B 4 560 #define RTW_REG_DOMAIN_NL 0xFF 561 u8 domain; 562 }; 563 564 struct rtw_rf_sipi_addr { 565 u32 hssi_1; 566 u32 hssi_2; 567 u32 lssi_read; 568 u32 lssi_read_pi; 569 }; 570 571 struct rtw_hw_reg_offset { 572 struct rtw_hw_reg hw_reg; 573 u8 offset; 574 }; 575 576 struct rtw_backup_info { 577 u8 len; 578 u32 reg; 579 u32 val; 580 }; 581 582 enum rtw_vif_port_set { 583 PORT_SET_MAC_ADDR = BIT(0), 584 PORT_SET_BSSID = BIT(1), 585 PORT_SET_NET_TYPE = BIT(2), 586 PORT_SET_AID = BIT(3), 587 PORT_SET_BCN_CTRL = BIT(4), 588 }; 589 590 struct rtw_vif_port { 591 struct rtw_hw_reg mac_addr; 592 struct rtw_hw_reg bssid; 593 struct rtw_hw_reg net_type; 594 struct rtw_hw_reg aid; 595 struct rtw_hw_reg bcn_ctrl; 596 }; 597 598 struct rtw_tx_pkt_info { 599 u32 tx_pkt_size; 600 u8 offset; 601 u8 pkt_offset; 602 u8 tim_offset; 603 u8 mac_id; 604 u8 rate_id; 605 u8 rate; 606 u8 qsel; 607 u8 bw; 608 u8 sec_type; 609 u8 sn; 610 bool ampdu_en; 611 u8 ampdu_factor; 612 u8 ampdu_density; 613 u16 seq; 614 bool stbc; 615 bool ldpc; 616 bool dis_rate_fallback; 617 bool bmc; 618 bool use_rate; 619 bool ls; 620 bool fs; 621 bool short_gi; 622 bool report; 623 bool rts; 624 bool dis_qselseq; 625 bool en_hwseq; 626 u8 hw_ssn_sel; 627 bool nav_use_hdr; 628 bool bt_null; 629 }; 630 631 struct rtw_rx_pkt_stat { 632 bool phy_status; 633 bool icv_err; 634 bool crc_err; 635 bool decrypted; 636 bool is_c2h; 637 bool channel_invalid; 638 639 s32 signal_power; 640 u16 pkt_len; 641 u8 bw; 642 u8 drv_info_sz; 643 u8 shift; 644 u8 rate; 645 u8 mac_id; 646 u8 cam_id; 647 u8 ppdu_cnt; 648 u32 tsf_low; 649 s8 rx_power[RTW_RF_PATH_MAX]; 650 u8 rssi; 651 u8 rxsc; 652 s8 rx_snr[RTW_RF_PATH_MAX]; 653 u8 rx_evm[RTW_RF_PATH_MAX]; 654 s8 cfo_tail[RTW_RF_PATH_MAX]; 655 u16 freq; 656 u8 band; 657 658 struct rtw_sta_info *si; 659 struct ieee80211_vif *vif; 660 struct ieee80211_hdr *hdr; 661 }; 662 663 DECLARE_EWMA(tp, 10, 2); 664 665 struct rtw_traffic_stats { 666 /* units in bytes */ 667 u64 tx_unicast; 668 u64 rx_unicast; 669 670 /* count for packets */ 671 u64 tx_cnt; 672 u64 rx_cnt; 673 674 /* units in Mbps */ 675 u32 tx_throughput; 676 u32 rx_throughput; 677 struct ewma_tp tx_ewma_tp; 678 struct ewma_tp rx_ewma_tp; 679 }; 680 681 enum rtw_lps_mode { 682 RTW_MODE_ACTIVE = 0, 683 RTW_MODE_LPS = 1, 684 RTW_MODE_WMM_PS = 2, 685 }; 686 687 enum rtw_lps_deep_mode { 688 LPS_DEEP_MODE_NONE = 0, 689 LPS_DEEP_MODE_LCLK = 1, 690 LPS_DEEP_MODE_PG = 2, 691 }; 692 693 enum rtw_pwr_state { 694 RTW_RF_OFF = 0x0, 695 RTW_RF_ON = 0x4, 696 RTW_ALL_ON = 0xc, 697 }; 698 699 struct rtw_lps_conf { 700 enum rtw_lps_mode mode; 701 enum rtw_lps_deep_mode deep_mode; 702 enum rtw_lps_deep_mode wow_deep_mode; 703 enum rtw_pwr_state state; 704 u8 awake_interval; 705 u8 rlbm; 706 u8 smart_ps; 707 u8 port_id; 708 bool sec_cam_backup; 709 bool pattern_cam_backup; 710 }; 711 712 enum rtw_hw_key_type { 713 RTW_CAM_NONE = 0, 714 RTW_CAM_WEP40 = 1, 715 RTW_CAM_TKIP = 2, 716 RTW_CAM_AES = 4, 717 RTW_CAM_WEP104 = 5, 718 }; 719 720 struct rtw_cam_entry { 721 bool valid; 722 bool group; 723 u8 addr[ETH_ALEN]; 724 u8 hw_key_type; 725 struct ieee80211_key_conf *key; 726 }; 727 728 struct rtw_sec_desc { 729 /* search strategy */ 730 bool default_key_search; 731 732 u32 total_cam_num; 733 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 734 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 735 }; 736 737 struct rtw_tx_report { 738 /* protect the tx report queue */ 739 spinlock_t q_lock; 740 struct sk_buff_head queue; 741 atomic_t sn; 742 struct timer_list purge_timer; 743 }; 744 745 struct rtw_ra_report { 746 struct rate_info txrate; 747 u32 bit_rate; 748 u8 desc_rate; 749 }; 750 751 struct rtw_txq { 752 struct list_head list; 753 unsigned long flags; 754 }; 755 756 DECLARE_EWMA(rssi, 10, 16); 757 758 struct rtw_sta_info { 759 struct rtw_dev *rtwdev; 760 struct ieee80211_sta *sta; 761 struct ieee80211_vif *vif; 762 763 struct ewma_rssi avg_rssi; 764 u8 rssi_level; 765 766 u8 mac_id; 767 u8 rate_id; 768 enum rtw_bandwidth bw_mode; 769 u8 stbc_en:2; 770 u8 ldpc_en:2; 771 bool sgi_enable; 772 bool vht_enable; 773 u8 init_ra_lv; 774 u64 ra_mask; 775 776 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 777 778 struct rtw_ra_report ra_report; 779 780 bool use_cfg_mask; 781 struct cfg80211_bitrate_mask *mask; 782 783 struct work_struct rc_work; 784 }; 785 786 enum rtw_bfee_role { 787 RTW_BFEE_NONE, 788 RTW_BFEE_SU, 789 RTW_BFEE_MU 790 }; 791 792 struct rtw_bfee { 793 enum rtw_bfee_role role; 794 795 u16 p_aid; 796 u8 g_id; 797 u8 mac_addr[ETH_ALEN]; 798 u8 sound_dim; 799 800 /* SU-MIMO */ 801 u8 su_reg_index; 802 803 /* MU-MIMO */ 804 u16 aid; 805 }; 806 807 struct rtw_bf_info { 808 u8 bfer_mu_cnt; 809 u8 bfer_su_cnt; 810 DECLARE_BITMAP(bfer_su_reg_maping, 2); 811 u8 cur_csi_rpt_rate; 812 }; 813 814 struct rtw_vif { 815 enum rtw_net_type net_type; 816 u16 aid; 817 u8 mac_id; 818 u8 mac_addr[ETH_ALEN]; 819 u8 bssid[ETH_ALEN]; 820 u8 port; 821 u8 bcn_ctrl; 822 struct list_head rsvd_page_list; 823 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 824 const struct rtw_vif_port *conf; 825 struct cfg80211_scan_request *scan_req; 826 struct ieee80211_scan_ies *scan_ies; 827 828 struct rtw_traffic_stats stats; 829 830 struct rtw_bfee bfee; 831 }; 832 833 struct rtw_regulatory { 834 char alpha2[2]; 835 u8 txpwr_regd_2g; 836 u8 txpwr_regd_5g; 837 }; 838 839 enum rtw_regd_state { 840 RTW_REGD_STATE_WORLDWIDE, 841 RTW_REGD_STATE_PROGRAMMED, 842 RTW_REGD_STATE_SETTING, 843 844 RTW_REGD_STATE_NR, 845 }; 846 847 struct rtw_regd { 848 enum rtw_regd_state state; 849 const struct rtw_regulatory *regulatory; 850 enum nl80211_dfs_regions dfs_region; 851 }; 852 853 struct rtw_chip_ops { 854 int (*power_on)(struct rtw_dev *rtwdev); 855 void (*power_off)(struct rtw_dev *rtwdev); 856 int (*mac_init)(struct rtw_dev *rtwdev); 857 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 858 void (*shutdown)(struct rtw_dev *rtwdev); 859 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 860 void (*phy_set_param)(struct rtw_dev *rtwdev); 861 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 862 u8 bandwidth, u8 primary_chan_idx); 863 void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status, 864 struct rtw_rx_pkt_stat *pkt_stat); 865 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 866 u32 addr, u32 mask); 867 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 868 u32 addr, u32 mask, u32 data); 869 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 870 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 871 u32 size); 872 int (*set_antenna)(struct rtw_dev *rtwdev, 873 u32 antenna_tx, 874 u32 antenna_rx); 875 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 876 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 877 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 878 void (*phy_calibration)(struct rtw_dev *rtwdev); 879 void (*dpk_track)(struct rtw_dev *rtwdev); 880 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 881 void (*pwr_track)(struct rtw_dev *rtwdev); 882 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 883 struct rtw_bfee *bfee, bool enable); 884 void (*set_gid_table)(struct rtw_dev *rtwdev, 885 struct ieee80211_vif *vif, 886 struct ieee80211_bss_conf *conf); 887 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 888 u8 fixrate_en, u8 *new_rate); 889 void (*adaptivity_init)(struct rtw_dev *rtwdev); 890 void (*adaptivity)(struct rtw_dev *rtwdev); 891 void (*cfo_init)(struct rtw_dev *rtwdev); 892 void (*cfo_track)(struct rtw_dev *rtwdev); 893 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 894 enum rtw_bb_path tx_path_1ss, 895 enum rtw_bb_path tx_path_cck, 896 bool is_tx2_path); 897 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 898 u8 rx_path, bool is_tx2_path); 899 void (*led_set)(struct led_classdev *led, enum led_brightness brightness); 900 /* for USB/SDIO only */ 901 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 902 struct rtw_tx_pkt_info *pkt_info, 903 u8 *txdesc); 904 905 /* for coex */ 906 void (*coex_set_init)(struct rtw_dev *rtwdev); 907 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 908 u8 ctrl_type, u8 pos_type); 909 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 910 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 911 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 912 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 913 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 914 }; 915 916 #define RTW_PWR_POLLING_CNT 20000 917 918 #define RTW_PWR_CMD_READ 0x00 919 #define RTW_PWR_CMD_WRITE 0x01 920 #define RTW_PWR_CMD_POLLING 0x02 921 #define RTW_PWR_CMD_DELAY 0x03 922 #define RTW_PWR_CMD_END 0x04 923 924 /* define the base address of each block */ 925 #define RTW_PWR_ADDR_MAC 0x00 926 #define RTW_PWR_ADDR_USB 0x01 927 #define RTW_PWR_ADDR_PCIE 0x02 928 #define RTW_PWR_ADDR_SDIO 0x03 929 930 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 931 #define RTW_PWR_INTF_USB_MSK BIT(1) 932 #define RTW_PWR_INTF_PCI_MSK BIT(2) 933 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 934 935 #define RTW_PWR_CUT_TEST_MSK BIT(0) 936 #define RTW_PWR_CUT_A_MSK BIT(1) 937 #define RTW_PWR_CUT_B_MSK BIT(2) 938 #define RTW_PWR_CUT_C_MSK BIT(3) 939 #define RTW_PWR_CUT_D_MSK BIT(4) 940 #define RTW_PWR_CUT_E_MSK BIT(5) 941 #define RTW_PWR_CUT_F_MSK BIT(6) 942 #define RTW_PWR_CUT_G_MSK BIT(7) 943 #define RTW_PWR_CUT_ALL_MSK 0xFF 944 945 enum rtw_pwr_seq_cmd_delay_unit { 946 RTW_PWR_DELAY_US, 947 RTW_PWR_DELAY_MS, 948 }; 949 950 struct rtw_pwr_seq_cmd { 951 u16 offset; 952 u8 cut_mask; 953 u8 intf_mask; 954 u8 base:4; 955 u8 cmd:4; 956 u8 mask; 957 u8 value; 958 }; 959 960 enum rtw_chip_ver { 961 RTW_CHIP_VER_CUT_A = 0x00, 962 RTW_CHIP_VER_CUT_B = 0x01, 963 RTW_CHIP_VER_CUT_C = 0x02, 964 RTW_CHIP_VER_CUT_D = 0x03, 965 RTW_CHIP_VER_CUT_E = 0x04, 966 RTW_CHIP_VER_CUT_F = 0x05, 967 RTW_CHIP_VER_CUT_G = 0x06, 968 }; 969 970 #define RTW_INTF_PHY_PLATFORM_ALL 0 971 972 enum rtw_intf_phy_cut { 973 RTW_INTF_PHY_CUT_A = BIT(0), 974 RTW_INTF_PHY_CUT_B = BIT(1), 975 RTW_INTF_PHY_CUT_C = BIT(2), 976 RTW_INTF_PHY_CUT_D = BIT(3), 977 RTW_INTF_PHY_CUT_E = BIT(4), 978 RTW_INTF_PHY_CUT_F = BIT(5), 979 RTW_INTF_PHY_CUT_G = BIT(6), 980 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 981 }; 982 983 enum rtw_ip_sel { 984 RTW_IP_SEL_PHY = 0, 985 RTW_IP_SEL_MAC = 1, 986 RTW_IP_SEL_DBI = 2, 987 988 RTW_IP_SEL_UNDEF = 0xFFFF 989 }; 990 991 enum rtw_pq_map_id { 992 RTW_PQ_MAP_VO = 0x0, 993 RTW_PQ_MAP_VI = 0x1, 994 RTW_PQ_MAP_BE = 0x2, 995 RTW_PQ_MAP_BK = 0x3, 996 RTW_PQ_MAP_MG = 0x4, 997 RTW_PQ_MAP_HI = 0x5, 998 RTW_PQ_MAP_NUM = 0x6, 999 1000 RTW_PQ_MAP_UNDEF, 1001 }; 1002 1003 enum rtw_dma_mapping { 1004 RTW_DMA_MAPPING_EXTRA = 0, 1005 RTW_DMA_MAPPING_LOW = 1, 1006 RTW_DMA_MAPPING_NORMAL = 2, 1007 RTW_DMA_MAPPING_HIGH = 3, 1008 1009 RTW_DMA_MAPPING_MAX, 1010 RTW_DMA_MAPPING_UNDEF, 1011 }; 1012 1013 struct rtw_rqpn { 1014 enum rtw_dma_mapping dma_map_vo; 1015 enum rtw_dma_mapping dma_map_vi; 1016 enum rtw_dma_mapping dma_map_be; 1017 enum rtw_dma_mapping dma_map_bk; 1018 enum rtw_dma_mapping dma_map_mg; 1019 enum rtw_dma_mapping dma_map_hi; 1020 }; 1021 1022 struct rtw_prioq_addr { 1023 u32 rsvd; 1024 u32 avail; 1025 }; 1026 1027 struct rtw_prioq_addrs { 1028 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1029 bool wsize; 1030 }; 1031 1032 struct rtw_page_table { 1033 u16 hq_num; 1034 u16 nq_num; 1035 u16 lq_num; 1036 u16 exq_num; 1037 u16 gapq_num; 1038 }; 1039 1040 struct rtw_intf_phy_para { 1041 u16 offset; 1042 u16 value; 1043 u16 ip_sel; 1044 u16 cut_mask; 1045 u16 platform; 1046 }; 1047 1048 struct rtw_wow_pattern { 1049 u16 crc; 1050 u8 type; 1051 u8 valid; 1052 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1053 }; 1054 1055 struct rtw_pno_request { 1056 bool inited; 1057 u32 match_set_cnt; 1058 struct cfg80211_match_set *match_sets; 1059 u8 channel_cnt; 1060 struct ieee80211_channel *channels; 1061 struct cfg80211_sched_scan_plan scan_plan; 1062 }; 1063 1064 struct rtw_wow_param { 1065 struct ieee80211_vif *wow_vif; 1066 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1067 u8 txpause; 1068 u8 pattern_cnt; 1069 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1070 1071 bool ips_enabled; 1072 struct rtw_pno_request pno_req; 1073 }; 1074 1075 struct rtw_intf_phy_para_table { 1076 const struct rtw_intf_phy_para *usb2_para; 1077 const struct rtw_intf_phy_para *usb3_para; 1078 const struct rtw_intf_phy_para *gen1_para; 1079 const struct rtw_intf_phy_para *gen2_para; 1080 u8 n_usb2_para; 1081 u8 n_usb3_para; 1082 u8 n_gen1_para; 1083 u8 n_gen2_para; 1084 }; 1085 1086 struct rtw_table { 1087 const void *data; 1088 const u32 size; 1089 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1090 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1091 u32 addr, u32 data); 1092 enum rtw_rf_path rf_path; 1093 }; 1094 1095 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1096 const struct rtw_table *tbl) 1097 { 1098 (*tbl->parse)(rtwdev, tbl); 1099 } 1100 1101 enum rtw_rfe_fem { 1102 RTW_RFE_IFEM, 1103 RTW_RFE_EFEM, 1104 RTW_RFE_IFEM2G_EFEM5G, 1105 RTW_RFE_NUM, 1106 }; 1107 1108 struct rtw_rfe_def { 1109 const struct rtw_table *phy_pg_tbl; 1110 const struct rtw_table *txpwr_lmt_tbl; 1111 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1112 const struct rtw_table *agc_btg_tbl; 1113 }; 1114 1115 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt, track) { \ 1116 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1117 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1118 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \ 1119 } 1120 1121 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, track, btg) { \ 1122 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1123 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1124 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \ 1125 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1126 } 1127 1128 #define RTW_PWR_TRK_5G_1 0 1129 #define RTW_PWR_TRK_5G_2 1 1130 #define RTW_PWR_TRK_5G_3 2 1131 #define RTW_PWR_TRK_5G_NUM 3 1132 1133 #define RTW_PWR_TRK_TBL_SZ 30 1134 1135 /* This table stores the values of TX power that will be adjusted by power 1136 * tracking. 1137 * 1138 * For 5G bands, there are 3 different settings. 1139 * For 2G there are cck rate and ofdm rate with different settings. 1140 */ 1141 struct rtw_pwr_track_tbl { 1142 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1143 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1144 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1145 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1146 const u8 *pwrtrk_2gb_n; 1147 const u8 *pwrtrk_2gb_p; 1148 const u8 *pwrtrk_2ga_n; 1149 const u8 *pwrtrk_2ga_p; 1150 const u8 *pwrtrk_2g_cckb_n; 1151 const u8 *pwrtrk_2g_cckb_p; 1152 const u8 *pwrtrk_2g_ccka_n; 1153 const u8 *pwrtrk_2g_ccka_p; 1154 const s8 *pwrtrk_xtal_n; 1155 const s8 *pwrtrk_xtal_p; 1156 }; 1157 1158 enum rtw_wlan_cpu { 1159 RTW_WCPU_11AC, 1160 RTW_WCPU_11N, 1161 }; 1162 1163 enum rtw_fw_fifo_sel { 1164 RTW_FW_FIFO_SEL_TX, 1165 RTW_FW_FIFO_SEL_RX, 1166 RTW_FW_FIFO_SEL_RSVD_PAGE, 1167 RTW_FW_FIFO_SEL_REPORT, 1168 RTW_FW_FIFO_SEL_LLT, 1169 RTW_FW_FIFO_SEL_RXBUF_FW, 1170 1171 RTW_FW_FIFO_MAX, 1172 }; 1173 1174 enum rtw_fwcd_item { 1175 RTW_FWCD_TLV, 1176 RTW_FWCD_REG, 1177 RTW_FWCD_ROM, 1178 RTW_FWCD_IMEM, 1179 RTW_FWCD_DMEM, 1180 RTW_FWCD_EMEM, 1181 }; 1182 1183 /* hardware configuration for each IC */ 1184 struct rtw_chip_info { 1185 const struct rtw_chip_ops *ops; 1186 u8 id; 1187 1188 const char *fw_name; 1189 enum rtw_wlan_cpu wlan_cpu; 1190 u8 tx_pkt_desc_sz; 1191 u8 tx_buf_desc_sz; 1192 u8 rx_pkt_desc_sz; 1193 u8 rx_buf_desc_sz; 1194 u32 phy_efuse_size; 1195 u32 log_efuse_size; 1196 u32 ptct_efuse_size; 1197 u32 txff_size; 1198 u32 rxff_size; 1199 u32 fw_rxff_size; 1200 u16 rsvd_drv_pg_num; 1201 u8 band; 1202 u16 page_size; 1203 u8 csi_buf_pg_num; 1204 u8 dig_max; 1205 u8 dig_min; 1206 u8 txgi_factor; 1207 bool is_pwr_by_rate_dec; 1208 bool rx_ldpc; 1209 bool tx_stbc; 1210 u8 max_power_index; 1211 u8 ampdu_density; 1212 1213 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1214 const struct rtw_fwcd_segs *fwcd_segs; 1215 1216 u8 usb_tx_agg_desc_num; 1217 bool hw_feature_report; 1218 u8 c2h_ra_report_size; 1219 bool old_datarate_fb_limit; 1220 1221 u8 default_1ss_tx_path; 1222 1223 bool path_div_supported; 1224 bool ht_supported; 1225 bool vht_supported; 1226 u8 lps_deep_mode_supported; 1227 1228 /* init values */ 1229 u8 sys_func_en; 1230 const struct rtw_pwr_seq_cmd * const *pwr_on_seq; 1231 const struct rtw_pwr_seq_cmd * const *pwr_off_seq; 1232 const struct rtw_rqpn *rqpn_table; 1233 const struct rtw_prioq_addrs *prioq_addrs; 1234 const struct rtw_page_table *page_table; 1235 const struct rtw_intf_phy_para_table *intf_table; 1236 1237 const struct rtw_hw_reg *dig; 1238 const struct rtw_hw_reg *dig_cck; 1239 u32 rf_base_addr[2]; 1240 u32 rf_sipi_addr[2]; 1241 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1242 u8 fix_rf_phy_num; 1243 const struct rtw_ltecoex_addr *ltecoex_addr; 1244 1245 const struct rtw_table *mac_tbl; 1246 const struct rtw_table *agc_tbl; 1247 const struct rtw_table *bb_tbl; 1248 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1249 const struct rtw_table *rfk_init_tbl; 1250 1251 const struct rtw_rfe_def *rfe_defs; 1252 u32 rfe_defs_size; 1253 1254 bool en_dis_dpd; 1255 u16 dpd_ratemask; 1256 u8 iqk_threshold; 1257 u8 lck_threshold; 1258 1259 u8 bfer_su_max_num; 1260 u8 bfer_mu_max_num; 1261 1262 const struct rtw_hw_reg_offset *edcca_th; 1263 s8 l2h_th_ini_cs; 1264 s8 l2h_th_ini_ad; 1265 1266 const char *wow_fw_name; 1267 const struct wiphy_wowlan_support *wowlan_stub; 1268 const u8 max_sched_scan_ssids; 1269 const u16 max_scan_ie_len; 1270 1271 /* coex paras */ 1272 u32 coex_para_ver; 1273 u8 bt_desired_ver; 1274 bool scbd_support; 1275 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1276 bool ble_hid_profile_support; 1277 bool wl_mimo_ps_support; 1278 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1279 u8 bt_rssi_type; 1280 u8 ant_isolation; 1281 u8 rssi_tolerance; 1282 u8 table_sant_num; 1283 u8 table_nsant_num; 1284 u8 tdma_sant_num; 1285 u8 tdma_nsant_num; 1286 u8 bt_afh_span_bw20; 1287 u8 bt_afh_span_bw40; 1288 u8 afh_5g_num; 1289 u8 wl_rf_para_num; 1290 u8 coex_info_hw_regs_num; 1291 const u8 *bt_rssi_step; 1292 const u8 *wl_rssi_step; 1293 const struct coex_table_para *table_nsant; 1294 const struct coex_table_para *table_sant; 1295 const struct coex_tdma_para *tdma_sant; 1296 const struct coex_tdma_para *tdma_nsant; 1297 const struct coex_rf_para *wl_rf_para_tx; 1298 const struct coex_rf_para *wl_rf_para_rx; 1299 const struct coex_5g_afh_map *afh_5g; 1300 const struct rtw_hw_reg *btg_reg; 1301 const struct rtw_reg_domain *coex_info_hw_regs; 1302 u32 wl_fw_desired_ver; 1303 }; 1304 1305 enum rtw_coex_bt_state_cnt { 1306 COEX_CNT_BT_RETRY, 1307 COEX_CNT_BT_REINIT, 1308 COEX_CNT_BT_REENABLE, 1309 COEX_CNT_BT_POPEVENT, 1310 COEX_CNT_BT_SETUPLINK, 1311 COEX_CNT_BT_IGNWLANACT, 1312 COEX_CNT_BT_INQ, 1313 COEX_CNT_BT_PAGE, 1314 COEX_CNT_BT_ROLESWITCH, 1315 COEX_CNT_BT_AFHUPDATE, 1316 COEX_CNT_BT_INFOUPDATE, 1317 COEX_CNT_BT_IQK, 1318 COEX_CNT_BT_IQKFAIL, 1319 1320 COEX_CNT_BT_MAX 1321 }; 1322 1323 enum rtw_coex_wl_state_cnt { 1324 COEX_CNT_WL_SCANAP, 1325 COEX_CNT_WL_CONNPKT, 1326 COEX_CNT_WL_COEXRUN, 1327 COEX_CNT_WL_NOISY0, 1328 COEX_CNT_WL_NOISY1, 1329 COEX_CNT_WL_NOISY2, 1330 COEX_CNT_WL_5MS_NOEXTEND, 1331 COEX_CNT_WL_FW_NOTIFY, 1332 1333 COEX_CNT_WL_MAX 1334 }; 1335 1336 struct rtw_coex_rfe { 1337 bool ant_switch_exist; 1338 bool ant_switch_diversity; 1339 bool ant_switch_with_bt; 1340 u8 rfe_module_type; 1341 u8 ant_switch_polarity; 1342 1343 /* true if WLG at BTG, else at WLAG */ 1344 bool wlg_at_btg; 1345 }; 1346 1347 #define COEX_WL_TDMA_PARA_LENGTH 5 1348 1349 struct rtw_coex_dm { 1350 bool cur_ps_tdma_on; 1351 bool cur_wl_rx_low_gain_en; 1352 bool ignore_wl_act; 1353 1354 u8 reason; 1355 u8 bt_rssi_state[4]; 1356 u8 wl_rssi_state[4]; 1357 u8 wl_ch_info[3]; 1358 u8 cur_ps_tdma; 1359 u8 cur_table; 1360 u8 ps_tdma_para[5]; 1361 u8 cur_bt_pwr_lvl; 1362 u8 cur_bt_lna_lvl; 1363 u8 cur_wl_pwr_lvl; 1364 u8 bt_status; 1365 u32 cur_ant_pos_type; 1366 u32 cur_switch_status; 1367 u32 setting_tdma; 1368 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1369 }; 1370 1371 #define COEX_BTINFO_SRC_WL_FW 0x0 1372 #define COEX_BTINFO_SRC_BT_RSP 0x1 1373 #define COEX_BTINFO_SRC_BT_ACT 0x2 1374 #define COEX_BTINFO_SRC_BT_IQK 0x3 1375 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1376 #define COEX_BTINFO_SRC_H2C60 0x5 1377 #define COEX_BTINFO_SRC_MAX 0x6 1378 1379 #define COEX_INFO_FTP BIT(7) 1380 #define COEX_INFO_A2DP BIT(6) 1381 #define COEX_INFO_HID BIT(5) 1382 #define COEX_INFO_SCO_BUSY BIT(4) 1383 #define COEX_INFO_ACL_BUSY BIT(3) 1384 #define COEX_INFO_INQ_PAGE BIT(2) 1385 #define COEX_INFO_SCO_ESCO BIT(1) 1386 #define COEX_INFO_CONNECTION BIT(0) 1387 #define COEX_BTINFO_LENGTH_MAX 10 1388 #define COEX_BTINFO_LENGTH 7 1389 1390 #define COEX_BT_HIDINFO_LIST 0x0 1391 #define COEX_BT_HIDINFO_A 0x1 1392 #define COEX_BT_HIDINFO_NAME 3 1393 1394 #define COEX_BT_HIDINFO_LENGTH 6 1395 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1396 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1397 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1398 #define COEX_BT_BLE_HANDLE_THRS 0x10 1399 #define COEX_BT_HIDINFO_NOTCON 0xff 1400 1401 struct rtw_coex_hid { 1402 u8 hid_handle; 1403 u8 hid_vendor; 1404 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1405 bool hid_info_completed; 1406 bool is_game_hid; 1407 }; 1408 1409 struct rtw_coex_hid_handle_list { 1410 u8 cmd_id; 1411 u8 len; 1412 u8 subid; 1413 u8 handle_cnt; 1414 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1415 } __packed; 1416 1417 struct rtw_coex_hid_info_a { 1418 u8 cmd_id; 1419 u8 len; 1420 u8 subid; 1421 u8 handle; 1422 u8 vendor; 1423 u8 name[COEX_BT_HIDINFO_NAME]; 1424 } __packed; 1425 1426 struct rtw_coex_stat { 1427 bool bt_disabled; 1428 bool bt_disabled_pre; 1429 bool bt_link_exist; 1430 bool bt_whck_test; 1431 bool bt_inq_page; 1432 bool bt_inq_remain; 1433 bool bt_inq; 1434 bool bt_page; 1435 bool bt_ble_voice; 1436 bool bt_ble_exist; 1437 bool bt_hfp_exist; 1438 bool bt_a2dp_exist; 1439 bool bt_hid_exist; 1440 bool bt_pan_exist; /* PAN or OPP */ 1441 bool bt_opp_exist; /* OPP only */ 1442 bool bt_acl_busy; 1443 bool bt_fix_2M; 1444 bool bt_setup_link; 1445 bool bt_multi_link; 1446 bool bt_multi_link_pre; 1447 bool bt_multi_link_remain; 1448 bool bt_a2dp_sink; 1449 bool bt_a2dp_active; 1450 bool bt_reenable; 1451 bool bt_ble_scan_en; 1452 bool bt_init_scan; 1453 bool bt_slave; 1454 bool bt_418_hid_exist; 1455 bool bt_ble_hid_exist; 1456 bool bt_game_hid_exist; 1457 bool bt_hid_handle_cnt; 1458 bool bt_mailbox_reply; 1459 1460 bool wl_under_lps; 1461 bool wl_under_ips; 1462 bool wl_hi_pri_task1; 1463 bool wl_hi_pri_task2; 1464 bool wl_force_lps_ctrl; 1465 bool wl_gl_busy; 1466 bool wl_linkscan_proc; 1467 bool wl_ps_state_fail; 1468 bool wl_tx_limit_en; 1469 bool wl_ampdu_limit_en; 1470 bool wl_connected; 1471 bool wl_slot_extend; 1472 bool wl_cck_lock; 1473 bool wl_cck_lock_pre; 1474 bool wl_cck_lock_ever; 1475 bool wl_connecting; 1476 bool wl_slot_toggle; 1477 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1478 bool wl_mimo_ps; 1479 1480 u32 bt_supported_version; 1481 u32 bt_supported_feature; 1482 u32 hi_pri_tx; 1483 u32 hi_pri_rx; 1484 u32 lo_pri_tx; 1485 u32 lo_pri_rx; 1486 u32 patch_ver; 1487 u16 bt_reg_vendor_ae; 1488 u16 bt_reg_vendor_ac; 1489 s8 bt_rssi; 1490 u8 kt_ver; 1491 u8 gnt_workaround_state; 1492 u8 tdma_timer_base; 1493 u8 bt_profile_num; 1494 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1495 u8 bt_info_lb2; 1496 u8 bt_info_lb3; 1497 u8 bt_info_hb0; 1498 u8 bt_info_hb1; 1499 u8 bt_info_hb2; 1500 u8 bt_info_hb3; 1501 u8 bt_ble_scan_type; 1502 u8 bt_hid_pair_num; 1503 u8 bt_hid_slot; 1504 u8 bt_a2dp_bitpool; 1505 u8 bt_iqk_state; 1506 u8 bt_disable_cnt; 1507 1508 u16 wl_beacon_interval; 1509 u8 wl_noisy_level; 1510 u8 wl_fw_dbg_info[10]; 1511 u8 wl_fw_dbg_info_pre[10]; 1512 u8 wl_rx_rate; 1513 u8 wl_tx_rate; 1514 u8 wl_rts_rx_rate; 1515 u8 wl_coex_mode; 1516 u8 wl_iot_peer; 1517 u8 ampdu_max_time; 1518 u8 wl_tput_dir; 1519 1520 u8 wl_toggle_para[6]; 1521 u8 wl_toggle_interval; 1522 1523 u16 score_board; 1524 u16 retry_limit; 1525 1526 /* counters to record bt states */ 1527 u32 cnt_bt[COEX_CNT_BT_MAX]; 1528 1529 /* counters to record wifi states */ 1530 u32 cnt_wl[COEX_CNT_WL_MAX]; 1531 1532 /* counters to record bt c2h data */ 1533 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1534 1535 u32 darfrc; 1536 u32 darfrch; 1537 1538 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1539 struct rtw_coex_hid_handle_list hid_handle_list; 1540 }; 1541 1542 struct rtw_coex { 1543 struct sk_buff_head queue; 1544 wait_queue_head_t wait; 1545 1546 bool under_5g; 1547 bool stop_dm; 1548 bool freeze; 1549 bool freerun; 1550 bool wl_rf_off; 1551 bool manual_control; 1552 1553 struct rtw_coex_stat stat; 1554 struct rtw_coex_dm dm; 1555 struct rtw_coex_rfe rfe; 1556 1557 struct delayed_work bt_relink_work; 1558 struct delayed_work bt_reenable_work; 1559 struct delayed_work defreeze_work; 1560 struct delayed_work wl_remain_work; 1561 struct delayed_work bt_remain_work; 1562 struct delayed_work wl_connecting_work; 1563 struct delayed_work bt_multi_link_remain_work; 1564 struct delayed_work wl_ccklock_work; 1565 1566 }; 1567 1568 #define DPK_RF_REG_NUM 7 1569 #define DPK_RF_PATH_NUM 2 1570 #define DPK_BB_REG_NUM 18 1571 #define DPK_CHANNEL_WIDTH_80 1 1572 1573 DECLARE_EWMA(thermal, 10, 4); 1574 1575 struct rtw_dpk_info { 1576 bool is_dpk_pwr_on; 1577 bool is_reload; 1578 1579 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1580 1581 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1582 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1583 1584 u32 gnt_control; 1585 u32 gnt_value; 1586 1587 u8 result[RTW_RF_PATH_MAX]; 1588 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1589 u32 coef[RTW_RF_PATH_MAX][20]; 1590 u16 dpk_gs[RTW_RF_PATH_MAX]; 1591 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1592 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1593 1594 u8 dpk_band; 1595 u8 dpk_ch; 1596 u8 dpk_bw; 1597 }; 1598 1599 struct rtw_phy_cck_pd_reg { 1600 u32 reg_pd; 1601 u32 mask_pd; 1602 u32 reg_cs; 1603 u32 mask_cs; 1604 }; 1605 1606 #define DACK_MSBK_BACKUP_NUM 0xf 1607 #define DACK_DCK_BACKUP_NUM 0x2 1608 1609 struct rtw_swing_table { 1610 const u8 *p[RTW_RF_PATH_MAX]; 1611 const u8 *n[RTW_RF_PATH_MAX]; 1612 }; 1613 1614 struct rtw_pkt_count { 1615 u16 num_bcn_pkt; 1616 u16 num_qry_pkt[DESC_RATE_MAX]; 1617 }; 1618 1619 DECLARE_EWMA(evm, 10, 4); 1620 DECLARE_EWMA(snr, 10, 4); 1621 1622 struct rtw_iqk_info { 1623 bool done; 1624 struct { 1625 u32 s1_x; 1626 u32 s1_y; 1627 u32 s0_x; 1628 u32 s0_y; 1629 } result; 1630 }; 1631 1632 enum rtw_rf_band { 1633 RF_BAND_2G_CCK, 1634 RF_BAND_2G_OFDM, 1635 RF_BAND_5G_L, 1636 RF_BAND_5G_M, 1637 RF_BAND_5G_H, 1638 RF_BAND_MAX 1639 }; 1640 1641 #define RF_GAIN_NUM 11 1642 #define RF_HW_OFFSET_NUM 10 1643 1644 struct rtw_gapk_info { 1645 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1646 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1647 bool txgapk_bp_done; 1648 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1649 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1650 u8 read_txgain; 1651 u8 channel; 1652 }; 1653 1654 #define EDCCA_TH_L2H_IDX 0 1655 #define EDCCA_TH_H2L_IDX 1 1656 #define EDCCA_TH_L2H_LB 48 1657 #define EDCCA_ADC_BACKOFF 12 1658 #define EDCCA_IGI_BASE 50 1659 #define EDCCA_IGI_L2H_DIFF 8 1660 #define EDCCA_L2H_H2L_DIFF 7 1661 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1662 1663 enum rtw_edcca_mode { 1664 RTW_EDCCA_NORMAL = 0, 1665 RTW_EDCCA_ADAPTIVITY = 1, 1666 }; 1667 1668 struct rtw_cfo_track { 1669 bool is_adjust; 1670 u8 crystal_cap; 1671 s32 cfo_tail[RTW_RF_PATH_MAX]; 1672 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1673 u32 packet_count; 1674 u32 packet_count_pre; 1675 }; 1676 1677 #define RRSR_INIT_2G 0x15f 1678 #define RRSR_INIT_5G 0x150 1679 1680 enum rtw_dm_cap { 1681 RTW_DM_CAP_NA, 1682 RTW_DM_CAP_TXGAPK, 1683 RTW_DM_CAP_NUM 1684 }; 1685 1686 struct rtw_dm_info { 1687 u32 cck_fa_cnt; 1688 u32 ofdm_fa_cnt; 1689 u32 total_fa_cnt; 1690 u32 cck_cca_cnt; 1691 u32 ofdm_cca_cnt; 1692 u32 total_cca_cnt; 1693 1694 u32 cck_ok_cnt; 1695 u32 cck_err_cnt; 1696 u32 ofdm_ok_cnt; 1697 u32 ofdm_err_cnt; 1698 u32 ht_ok_cnt; 1699 u32 ht_err_cnt; 1700 u32 vht_ok_cnt; 1701 u32 vht_err_cnt; 1702 1703 u8 min_rssi; 1704 u8 pre_min_rssi; 1705 u16 fa_history[4]; 1706 u8 igi_history[4]; 1707 u8 igi_bitmap; 1708 bool damping; 1709 u8 damping_cnt; 1710 u8 damping_rssi; 1711 1712 u8 cck_gi_u_bnd; 1713 u8 cck_gi_l_bnd; 1714 1715 u8 fix_rate; 1716 u8 tx_rate; 1717 u32 rrsr_val_init; 1718 u32 rrsr_mask_min; 1719 u8 thermal_avg[RTW_RF_PATH_MAX]; 1720 u8 thermal_meter_k; 1721 u8 thermal_meter_lck; 1722 s8 delta_power_index[RTW_RF_PATH_MAX]; 1723 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1724 u8 default_ofdm_index; 1725 u8 default_cck_index; 1726 bool pwr_trk_triggered; 1727 bool pwr_trk_init_trigger; 1728 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1729 s8 txagc_remnant_cck; 1730 s8 txagc_remnant_ofdm[RTW_RF_PATH_MAX]; 1731 u8 rx_cck_agc_report_type; 1732 1733 /* backup dack results for each path and I/Q */ 1734 u32 dack_adck[RTW_RF_PATH_MAX]; 1735 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1736 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1737 1738 struct rtw_dpk_info dpk_info; 1739 struct rtw_cfo_track cfo_track; 1740 1741 /* [bandwidth 0:20M/1:40M][number of path] */ 1742 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1743 u32 cck_fa_avg; 1744 u8 cck_pd_default; 1745 1746 /* save the last rx phy status for debug */ 1747 s8 rx_snr[RTW_RF_PATH_MAX]; 1748 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1749 s16 cfo_tail[RTW_RF_PATH_MAX]; 1750 u8 rssi[RTW_RF_PATH_MAX]; 1751 u8 curr_rx_rate; 1752 struct rtw_pkt_count cur_pkt_count; 1753 struct rtw_pkt_count last_pkt_count; 1754 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1755 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1756 1757 u32 dm_flags; /* enum rtw_dm_cap */ 1758 struct rtw_iqk_info iqk; 1759 struct rtw_gapk_info gapk; 1760 bool is_bt_iqk_timeout; 1761 1762 s8 l2h_th_ini; 1763 enum rtw_edcca_mode edcca_mode; 1764 u8 scan_density; 1765 }; 1766 1767 struct rtw_efuse { 1768 u32 size; 1769 u32 physical_size; 1770 u32 logical_size; 1771 u32 protect_size; 1772 1773 u8 addr[ETH_ALEN]; 1774 u8 channel_plan; 1775 u8 country_code[2]; 1776 u8 rf_board_option; 1777 u8 rfe_option; 1778 u8 power_track_type; 1779 u8 thermal_meter[RTW_RF_PATH_MAX]; 1780 u8 thermal_meter_k; 1781 u8 crystal_cap; 1782 u8 ant_div_cfg; 1783 u8 ant_div_type; 1784 u8 regd; 1785 u8 afe; 1786 1787 u8 lna_type_2g; 1788 u8 lna_type_5g; 1789 u8 glna_type; 1790 u8 alna_type; 1791 bool ext_lna_2g; 1792 bool ext_lna_5g; 1793 u8 pa_type_2g; 1794 u8 pa_type_5g; 1795 u8 gpa_type; 1796 u8 apa_type; 1797 bool ext_pa_2g; 1798 bool ext_pa_5g; 1799 u8 tx_bb_swing_setting_2g; 1800 u8 tx_bb_swing_setting_5g; 1801 1802 bool btcoex; 1803 /* bt share antenna with wifi */ 1804 bool share_ant; 1805 u8 bt_setting; 1806 1807 u8 usb_mode_switch; 1808 1809 struct { 1810 u8 hci; 1811 u8 bw; 1812 u8 ptcl; 1813 u8 nss; 1814 u8 ant_num; 1815 } hw_cap; 1816 1817 struct rtw_txpwr_idx txpwr_idx_table[4]; 1818 }; 1819 1820 struct rtw_phy_cond { 1821 #ifdef __LITTLE_ENDIAN 1822 u32 rfe:8; 1823 u32 intf:4; 1824 u32 pkg:4; 1825 u32 plat:4; 1826 u32 intf_rsvd:4; 1827 u32 cut:4; 1828 u32 branch:2; 1829 u32 neg:1; 1830 u32 pos:1; 1831 #else 1832 u32 pos:1; 1833 u32 neg:1; 1834 u32 branch:2; 1835 u32 cut:4; 1836 u32 intf_rsvd:4; 1837 u32 plat:4; 1838 u32 pkg:4; 1839 u32 intf:4; 1840 u32 rfe:8; 1841 #endif 1842 /* for intf:4 */ 1843 #define INTF_PCIE BIT(0) 1844 #define INTF_USB BIT(1) 1845 #define INTF_SDIO BIT(2) 1846 /* for branch:2 */ 1847 #define BRANCH_IF 0 1848 #define BRANCH_ELIF 1 1849 #define BRANCH_ELSE 2 1850 #define BRANCH_ENDIF 3 1851 }; 1852 1853 struct rtw_phy_cond2 { 1854 #ifdef __LITTLE_ENDIAN 1855 u8 type_glna; 1856 u8 type_gpa; 1857 u8 type_alna; 1858 u8 type_apa; 1859 #else 1860 u8 type_apa; 1861 u8 type_alna; 1862 u8 type_gpa; 1863 u8 type_glna; 1864 #endif 1865 }; 1866 1867 struct rtw_fifo_conf { 1868 /* tx fifo information */ 1869 u16 rsvd_boundary; 1870 u16 rsvd_pg_num; 1871 u16 rsvd_drv_pg_num; 1872 u16 txff_pg_num; 1873 u16 acq_pg_num; 1874 u16 rsvd_drv_addr; 1875 u16 rsvd_h2c_info_addr; 1876 u16 rsvd_h2c_sta_info_addr; 1877 u16 rsvd_h2cq_addr; 1878 u16 rsvd_cpu_instr_addr; 1879 u16 rsvd_fw_txbuf_addr; 1880 u16 rsvd_csibuf_addr; 1881 const struct rtw_rqpn *rqpn; 1882 }; 1883 1884 struct rtw_fwcd_desc { 1885 u32 size; 1886 u8 *next; 1887 u8 *data; 1888 }; 1889 1890 struct rtw_fwcd_segs { 1891 const u32 *segs; 1892 u8 num; 1893 }; 1894 1895 #define FW_CD_TYPE 0xffff 1896 #define FW_CD_LEN 4 1897 #define FW_CD_VAL 0xaabbccdd 1898 struct rtw_fw_state { 1899 const struct firmware *firmware; 1900 struct rtw_dev *rtwdev; 1901 struct completion completion; 1902 struct rtw_fwcd_desc fwcd_desc; 1903 u16 version; 1904 u8 sub_version; 1905 u8 sub_index; 1906 u16 h2c_version; 1907 u32 feature; 1908 u32 feature_ext; 1909 enum rtw_fw_type type; 1910 }; 1911 1912 enum rtw_sar_sources { 1913 RTW_SAR_SOURCE_NONE, 1914 RTW_SAR_SOURCE_COMMON, 1915 }; 1916 1917 enum rtw_sar_bands { 1918 RTW_SAR_BAND_0, 1919 RTW_SAR_BAND_1, 1920 /* RTW_SAR_BAND_2, not used now */ 1921 RTW_SAR_BAND_3, 1922 RTW_SAR_BAND_4, 1923 1924 RTW_SAR_BAND_NR, 1925 }; 1926 1927 /* the union is reserved for other kinds of SAR sources 1928 * which might not re-use same format with array common. 1929 */ 1930 union rtw_sar_cfg { 1931 s8 common[RTW_SAR_BAND_NR]; 1932 }; 1933 1934 struct rtw_sar { 1935 enum rtw_sar_sources src; 1936 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1937 }; 1938 1939 struct rtw_hal { 1940 u32 rcr; 1941 1942 u32 chip_version; 1943 u8 cut_version; 1944 u8 mp_chip; 1945 u8 oem_id; 1946 u8 pkg_type; 1947 struct rtw_phy_cond phy_cond; 1948 struct rtw_phy_cond2 phy_cond2; 1949 bool rfe_btg; 1950 1951 u8 ps_mode; 1952 u8 current_channel; 1953 u8 current_primary_channel_index; 1954 u8 current_band_width; 1955 u8 current_band_type; 1956 u8 primary_channel; 1957 1958 /* center channel for different available bandwidth, 1959 * val of (bw > current_band_width) is invalid 1960 */ 1961 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1962 1963 u8 sec_ch_offset; 1964 u8 rf_type; 1965 u8 rf_path_num; 1966 u8 rf_phy_num; 1967 u32 antenna_tx; 1968 u32 antenna_rx; 1969 u8 bfee_sts_cap; 1970 bool txrx_1ss; 1971 bool cck_high_power; 1972 1973 /* protect tx power section */ 1974 struct mutex tx_power_mutex; 1975 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1976 [DESC_RATE_MAX]; 1977 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1978 [DESC_RATE_MAX]; 1979 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1980 [RTW_RATE_SECTION_MAX]; 1981 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1982 [RTW_RATE_SECTION_MAX]; 1983 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1984 [RTW_CHANNEL_WIDTH_MAX] 1985 [RTW_RATE_SECTION_MAX] 1986 [RTW_MAX_CHANNEL_NUM_2G]; 1987 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1988 [RTW_CHANNEL_WIDTH_MAX] 1989 [RTW_RATE_SECTION_MAX] 1990 [RTW_MAX_CHANNEL_NUM_5G]; 1991 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1992 [DESC_RATE_MAX]; 1993 1994 enum rtw_sar_bands sar_band; 1995 struct rtw_sar sar; 1996 1997 /* for 8821c set channel */ 1998 u32 ch_param[3]; 1999 }; 2000 2001 struct rtw_path_div { 2002 enum rtw_bb_path current_tx_path; 2003 u32 path_a_sum; 2004 u32 path_b_sum; 2005 u16 path_a_cnt; 2006 u16 path_b_cnt; 2007 }; 2008 2009 struct rtw_chan_info { 2010 int pri_ch_idx; 2011 int action_id; 2012 int bw; 2013 u8 extra_info; 2014 u8 channel; 2015 u16 timeout; 2016 }; 2017 2018 struct rtw_chan_list { 2019 u32 buf_size; 2020 u32 ch_num; 2021 u32 size; 2022 u16 addr; 2023 }; 2024 2025 struct rtw_hw_scan_info { 2026 struct ieee80211_vif *scanning_vif; 2027 u8 probe_pg_size; 2028 u8 op_pri_ch_idx; 2029 u8 op_pri_ch; 2030 u8 op_chan; 2031 u8 op_bw; 2032 }; 2033 2034 struct rtw_dev { 2035 struct ieee80211_hw *hw; 2036 struct device *dev; 2037 2038 struct rtw_hci hci; 2039 2040 struct rtw_hw_scan_info scan_info; 2041 const struct rtw_chip_info *chip; 2042 struct rtw_hal hal; 2043 struct rtw_fifo_conf fifo; 2044 struct rtw_fw_state fw; 2045 struct rtw_efuse efuse; 2046 struct rtw_sec_desc sec; 2047 struct rtw_traffic_stats stats; 2048 struct rtw_regd regd; 2049 struct rtw_bf_info bf_info; 2050 2051 struct rtw_dm_info dm_info; 2052 struct rtw_coex coex; 2053 2054 /* ensures exclusive access from mac80211 callbacks */ 2055 struct mutex mutex; 2056 2057 /* watch dog every 2 sec */ 2058 struct delayed_work watch_dog_work; 2059 u32 watch_dog_cnt; 2060 2061 struct list_head rsvd_page_list; 2062 2063 /* c2h cmd queue & handler work */ 2064 struct sk_buff_head c2h_queue; 2065 struct work_struct c2h_work; 2066 struct work_struct ips_work; 2067 struct work_struct fw_recovery_work; 2068 struct work_struct update_beacon_work; 2069 2070 /* used to protect txqs list */ 2071 spinlock_t txq_lock; 2072 struct list_head txqs; 2073 struct workqueue_struct *tx_wq; 2074 struct work_struct tx_work; 2075 struct work_struct ba_work; 2076 2077 struct rtw_tx_report tx_report; 2078 2079 struct { 2080 /* indicate the mail box to use with fw */ 2081 u8 last_box_num; 2082 u32 seq; 2083 } h2c; 2084 2085 /* lps power state & handler work */ 2086 struct rtw_lps_conf lps_conf; 2087 bool ps_enabled; 2088 bool beacon_loss; 2089 struct completion lps_leave_check; 2090 2091 struct rtw_debugfs *debugfs; 2092 2093 u8 sta_cnt; 2094 u32 rts_threshold; 2095 2096 DECLARE_BITMAP(hw_port, RTW_PORT_NUM); 2097 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2098 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2099 2100 u8 mp_mode; 2101 struct rtw_path_div dm_path_div; 2102 2103 struct rtw_fw_state wow_fw; 2104 struct rtw_wow_param wow; 2105 2106 bool need_rfk; 2107 struct completion fw_scan_density; 2108 bool ap_active; 2109 2110 bool led_registered; 2111 char led_name[32]; 2112 struct led_classdev led_cdev; 2113 2114 /* hci related data, must be last */ 2115 u8 priv[] __aligned(sizeof(void *)); 2116 }; 2117 2118 #include "hci.h" 2119 2120 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2121 { 2122 return !!rtwdev->sta_cnt; 2123 } 2124 2125 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2126 { 2127 void *p = rtwtxq; 2128 2129 return container_of(p, struct ieee80211_txq, drv_priv); 2130 } 2131 2132 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2133 { 2134 void *p = rtwvif; 2135 2136 return container_of(p, struct ieee80211_vif, drv_priv); 2137 } 2138 2139 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2140 { 2141 if (rtwdev->chip->ops->efuse_grant) 2142 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2143 } 2144 2145 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2146 { 2147 if (rtwdev->chip->ops->efuse_grant) 2148 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2149 } 2150 2151 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2152 { 2153 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2154 } 2155 2156 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2157 { 2158 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2159 } 2160 2161 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2162 { 2163 return rtwdev->chip->rx_ldpc; 2164 } 2165 2166 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2167 { 2168 return rtwdev->chip->tx_stbc; 2169 } 2170 2171 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 2172 { 2173 unsigned long mac_id; 2174 2175 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 2176 if (mac_id < RTW_MAX_MAC_ID_NUM) 2177 set_bit(mac_id, rtwdev->mac_id_map); 2178 2179 return mac_id; 2180 } 2181 2182 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2183 { 2184 clear_bit(mac_id, rtwdev->mac_id_map); 2185 } 2186 2187 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2188 { 2189 if (rtwdev->chip->ops->dump_fw_crash) 2190 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2191 2192 return 0; 2193 } 2194 2195 static inline 2196 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band) 2197 { 2198 switch (hw_band) { 2199 default: 2200 case RTW_BAND_2G: 2201 return NL80211_BAND_2GHZ; 2202 case RTW_BAND_5G: 2203 return NL80211_BAND_5GHZ; 2204 case RTW_BAND_60G: 2205 return NL80211_BAND_60GHZ; 2206 } 2207 } 2208 2209 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2210 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period); 2211 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2212 struct rtw_channel_params *ch_param); 2213 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2214 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2215 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2216 void rtw_restore_reg(struct rtw_dev *rtwdev, 2217 struct rtw_backup_info *bckp, u32 num); 2218 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2219 void rtw_set_channel(struct rtw_dev *rtwdev); 2220 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2221 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2222 u32 config); 2223 void rtw_tx_report_purge_timer(struct timer_list *t); 2224 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2225 bool reset_ra_mask); 2226 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2227 const u8 *mac_addr, bool hw_scan); 2228 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2229 bool hw_scan); 2230 int rtw_core_start(struct rtw_dev *rtwdev); 2231 void rtw_power_off(struct rtw_dev *rtwdev); 2232 void rtw_core_stop(struct rtw_dev *rtwdev); 2233 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2234 int rtw_core_init(struct rtw_dev *rtwdev); 2235 void rtw_core_deinit(struct rtw_dev *rtwdev); 2236 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2237 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2238 u16 rtw_desc_to_bitrate(u8 desc_rate); 2239 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2240 struct ieee80211_bss_conf *conf); 2241 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2242 struct ieee80211_vif *vif); 2243 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2244 bool fw_exist); 2245 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2246 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev); 2247 int rtw_power_on(struct rtw_dev *rtwdev); 2248 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2249 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2250 u32 fwcd_item); 2251 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2252 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2253 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 2254 u8 primary_channel, enum rtw_supported_band band, 2255 enum rtw_bandwidth bandwidth); 2256 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2257 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev); 2258 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable); 2259 #if defined(__linux__) 2260 #define rtw88_static_assert(_x) static_assert(_x) 2261 #elif defined(__FreeBSD__) 2262 #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size") 2263 #endif 2264 2265 #endif 2266