1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_STATS_H 9 #define __NET_TI_ICSSG_STATS_H 10 11 #include "icssg_prueth.h" 12 13 #define STATS_TIME_LIMIT_1G_MS 25000 /* 25 seconds @ 1G */ 14 15 struct miig_stats_regs { 16 /* Rx */ 17 u32 rx_packets; 18 u32 rx_broadcast_frames; 19 u32 rx_multicast_frames; 20 u32 rx_crc_errors; 21 u32 rx_mii_error_frames; 22 u32 rx_odd_nibble_frames; 23 u32 rx_frame_max_size; 24 u32 rx_max_size_error_frames; 25 u32 rx_frame_min_size; 26 u32 rx_min_size_error_frames; 27 u32 rx_over_errors; 28 u32 rx_class0_hits; 29 u32 rx_class1_hits; 30 u32 rx_class2_hits; 31 u32 rx_class3_hits; 32 u32 rx_class4_hits; 33 u32 rx_class5_hits; 34 u32 rx_class6_hits; 35 u32 rx_class7_hits; 36 u32 rx_class8_hits; 37 u32 rx_class9_hits; 38 u32 rx_class10_hits; 39 u32 rx_class11_hits; 40 u32 rx_class12_hits; 41 u32 rx_class13_hits; 42 u32 rx_class14_hits; 43 u32 rx_class15_hits; 44 u32 rx_smd_frags; 45 u32 rx_bucket1_size; 46 u32 rx_bucket2_size; 47 u32 rx_bucket3_size; 48 u32 rx_bucket4_size; 49 u32 rx_64B_frames; 50 u32 rx_bucket1_frames; 51 u32 rx_bucket2_frames; 52 u32 rx_bucket3_frames; 53 u32 rx_bucket4_frames; 54 u32 rx_bucket5_frames; 55 u32 rx_bytes; 56 u32 rx_tx_total_bytes; 57 /* Tx */ 58 u32 tx_packets; 59 u32 tx_broadcast_frames; 60 u32 tx_multicast_frames; 61 u32 tx_odd_nibble_frames; 62 u32 tx_underflow_errors; 63 u32 tx_frame_max_size; 64 u32 tx_max_size_error_frames; 65 u32 tx_frame_min_size; 66 u32 tx_min_size_error_frames; 67 u32 tx_bucket1_size; 68 u32 tx_bucket2_size; 69 u32 tx_bucket3_size; 70 u32 tx_bucket4_size; 71 u32 tx_64B_frames; 72 u32 tx_bucket1_frames; 73 u32 tx_bucket2_frames; 74 u32 tx_bucket3_frames; 75 u32 tx_bucket4_frames; 76 u32 tx_bucket5_frames; 77 u32 tx_bytes; 78 }; 79 80 #define ICSSG_MIIG_STATS(field, stats_type) \ 81 { \ 82 #field, \ 83 offsetof(struct miig_stats_regs, field), \ 84 stats_type \ 85 } 86 87 struct icssg_miig_stats { 88 char name[ETH_GSTRING_LEN]; 89 u32 offset; 90 bool standard_stats; 91 }; 92 93 static const struct icssg_miig_stats icssg_all_miig_stats[] = { 94 /* Rx */ 95 ICSSG_MIIG_STATS(rx_packets, true), 96 ICSSG_MIIG_STATS(rx_broadcast_frames, false), 97 ICSSG_MIIG_STATS(rx_multicast_frames, true), 98 ICSSG_MIIG_STATS(rx_crc_errors, true), 99 ICSSG_MIIG_STATS(rx_mii_error_frames, false), 100 ICSSG_MIIG_STATS(rx_odd_nibble_frames, false), 101 ICSSG_MIIG_STATS(rx_frame_max_size, true), 102 ICSSG_MIIG_STATS(rx_max_size_error_frames, false), 103 ICSSG_MIIG_STATS(rx_frame_min_size, true), 104 ICSSG_MIIG_STATS(rx_min_size_error_frames, false), 105 ICSSG_MIIG_STATS(rx_over_errors, true), 106 ICSSG_MIIG_STATS(rx_class0_hits, false), 107 ICSSG_MIIG_STATS(rx_class1_hits, false), 108 ICSSG_MIIG_STATS(rx_class2_hits, false), 109 ICSSG_MIIG_STATS(rx_class3_hits, false), 110 ICSSG_MIIG_STATS(rx_class4_hits, false), 111 ICSSG_MIIG_STATS(rx_class5_hits, false), 112 ICSSG_MIIG_STATS(rx_class6_hits, false), 113 ICSSG_MIIG_STATS(rx_class7_hits, false), 114 ICSSG_MIIG_STATS(rx_class8_hits, false), 115 ICSSG_MIIG_STATS(rx_class9_hits, false), 116 ICSSG_MIIG_STATS(rx_class10_hits, false), 117 ICSSG_MIIG_STATS(rx_class11_hits, false), 118 ICSSG_MIIG_STATS(rx_class12_hits, false), 119 ICSSG_MIIG_STATS(rx_class13_hits, false), 120 ICSSG_MIIG_STATS(rx_class14_hits, false), 121 ICSSG_MIIG_STATS(rx_class15_hits, false), 122 ICSSG_MIIG_STATS(rx_smd_frags, false), 123 ICSSG_MIIG_STATS(rx_bucket1_size, true), 124 ICSSG_MIIG_STATS(rx_bucket2_size, true), 125 ICSSG_MIIG_STATS(rx_bucket3_size, true), 126 ICSSG_MIIG_STATS(rx_bucket4_size, true), 127 ICSSG_MIIG_STATS(rx_64B_frames, true), 128 ICSSG_MIIG_STATS(rx_bucket1_frames, true), 129 ICSSG_MIIG_STATS(rx_bucket2_frames, true), 130 ICSSG_MIIG_STATS(rx_bucket3_frames, true), 131 ICSSG_MIIG_STATS(rx_bucket4_frames, true), 132 ICSSG_MIIG_STATS(rx_bucket5_frames, true), 133 ICSSG_MIIG_STATS(rx_bytes, true), 134 ICSSG_MIIG_STATS(rx_tx_total_bytes, false), 135 /* Tx */ 136 ICSSG_MIIG_STATS(tx_packets, true), 137 ICSSG_MIIG_STATS(tx_broadcast_frames, false), 138 ICSSG_MIIG_STATS(tx_multicast_frames, false), 139 ICSSG_MIIG_STATS(tx_odd_nibble_frames, false), 140 ICSSG_MIIG_STATS(tx_underflow_errors, false), 141 ICSSG_MIIG_STATS(tx_frame_max_size, true), 142 ICSSG_MIIG_STATS(tx_max_size_error_frames, false), 143 ICSSG_MIIG_STATS(tx_frame_min_size, true), 144 ICSSG_MIIG_STATS(tx_min_size_error_frames, false), 145 ICSSG_MIIG_STATS(tx_bucket1_size, true), 146 ICSSG_MIIG_STATS(tx_bucket2_size, true), 147 ICSSG_MIIG_STATS(tx_bucket3_size, true), 148 ICSSG_MIIG_STATS(tx_bucket4_size, true), 149 ICSSG_MIIG_STATS(tx_64B_frames, true), 150 ICSSG_MIIG_STATS(tx_bucket1_frames, true), 151 ICSSG_MIIG_STATS(tx_bucket2_frames, true), 152 ICSSG_MIIG_STATS(tx_bucket3_frames, true), 153 ICSSG_MIIG_STATS(tx_bucket4_frames, true), 154 ICSSG_MIIG_STATS(tx_bucket5_frames, true), 155 ICSSG_MIIG_STATS(tx_bytes, true), 156 }; 157 158 /** 159 * struct pa_stats_regs - ICSSG Firmware maintained PA Stats register 160 * @fw_rx_cnt: Number of valid packets sent by Rx PRU to Host on PSI 161 * @fw_tx_cnt: Number of valid packets copied by RTU0 to Tx queues 162 * @fw_tx_pre_overflow: Host Egress Q (Pre-emptible) Overflow Counter 163 * @fw_tx_exp_overflow: Host Egress Q (Express) Overflow Counter 164 */ 165 struct pa_stats_regs { 166 u32 fw_rx_cnt; 167 u32 fw_tx_cnt; 168 u32 fw_tx_pre_overflow; 169 u32 fw_tx_exp_overflow; 170 }; 171 172 #define ICSSG_PA_STATS(field) \ 173 { \ 174 #field, \ 175 offsetof(struct pa_stats_regs, field), \ 176 } 177 178 struct icssg_pa_stats { 179 char name[ETH_GSTRING_LEN]; 180 u32 offset; 181 }; 182 183 static const struct icssg_pa_stats icssg_all_pa_stats[] = { 184 ICSSG_PA_STATS(fw_rx_cnt), 185 ICSSG_PA_STATS(fw_tx_cnt), 186 ICSSG_PA_STATS(fw_tx_pre_overflow), 187 ICSSG_PA_STATS(fw_tx_exp_overflow), 188 }; 189 190 #endif /* __NET_TI_ICSSG_STATS_H */ 191