1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/irq.h>
12 #include <linux/pci.h>
13 #include <linux/sysfs.h>
14
15 #include "cgx.h"
16 #include "rvu.h"
17 #include "rvu_reg.h"
18 #include "ptp.h"
19 #include "mcs.h"
20
21 #include "rvu_trace.h"
22 #include "rvu_npc_hash.h"
23 #include "cn20k/reg.h"
24 #include "cn20k/api.h"
25
26 #define DRV_NAME "rvu_af"
27 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
28
29 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
30 struct rvu_block *block, int lf);
31 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
32 struct rvu_block *block, int lf);
33 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
34
35 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
36 int type, int num,
37 void (mbox_handler)(struct work_struct *),
38 void (mbox_up_handler)(struct work_struct *));
39 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq);
40 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq);
41
42 /* Supported devices */
43 static const struct pci_device_id rvu_id_table[] = {
44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
45 { 0, } /* end of table */
46 };
47
48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
49 MODULE_DESCRIPTION(DRV_STRING);
50 MODULE_LICENSE("GPL v2");
51 MODULE_DEVICE_TABLE(pci, rvu_id_table);
52
53 static char *mkex_profile; /* MKEX profile name */
54 module_param(mkex_profile, charp, 0000);
55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
56
57 static char *kpu_profile; /* KPU profile name */
58 module_param(kpu_profile, charp, 0000);
59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string");
60
rvu_setup_hw_capabilities(struct rvu * rvu)61 static void rvu_setup_hw_capabilities(struct rvu *rvu)
62 {
63 struct rvu_hwinfo *hw = rvu->hw;
64
65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
66 hw->cap.nix_fixed_txschq_mapping = false;
67 hw->cap.nix_shaping = true;
68 hw->cap.nix_tx_link_bp = true;
69 hw->cap.nix_rx_multicast = true;
70 hw->cap.nix_shaper_toggle_wait = false;
71 hw->cap.npc_hash_extract = false;
72 hw->cap.npc_exact_match_enabled = false;
73 hw->rvu = rvu;
74
75 if (is_rvu_pre_96xx_C0(rvu)) {
76 hw->cap.nix_fixed_txschq_mapping = true;
77 hw->cap.nix_txsch_per_cgx_lmac = 4;
78 hw->cap.nix_txsch_per_lbk_lmac = 132;
79 hw->cap.nix_txsch_per_sdp_lmac = 76;
80 hw->cap.nix_shaping = false;
81 hw->cap.nix_tx_link_bp = false;
82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))
83 hw->cap.nix_rx_multicast = false;
84 }
85 if (!is_rvu_pre_96xx_C0(rvu))
86 hw->cap.nix_shaper_toggle_wait = true;
87
88 if (!is_rvu_otx2(rvu))
89 hw->cap.per_pf_mbox_regs = true;
90
91 if (is_rvu_npc_hash_extract_en(rvu))
92 hw->cap.npc_hash_extract = true;
93 }
94
95 /* Poll a RVU block's register 'offset', for a 'zero'
96 * or 'nonzero' at bits specified by 'mask'
97 */
rvu_poll_reg(struct rvu * rvu,u64 block,u64 offset,u64 mask,bool zero)98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
99 {
100 unsigned long timeout = jiffies + usecs_to_jiffies(20000);
101 bool twice = false;
102 void __iomem *reg;
103 u64 reg_val;
104
105 reg = rvu->afreg_base + ((block << 28) | offset);
106 again:
107 reg_val = readq(reg);
108 if (zero && !(reg_val & mask))
109 return 0;
110 if (!zero && (reg_val & mask))
111 return 0;
112 if (time_before(jiffies, timeout)) {
113 usleep_range(1, 5);
114 goto again;
115 }
116 /* In scenarios where CPU is scheduled out before checking
117 * 'time_before' (above) and gets scheduled in such that
118 * jiffies are beyond timeout value, then check again if HW is
119 * done with the operation in the meantime.
120 */
121 if (!twice) {
122 twice = true;
123 goto again;
124 }
125 return -EBUSY;
126 }
127
rvu_alloc_rsrc(struct rsrc_bmap * rsrc)128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
129 {
130 int id;
131
132 if (!rsrc->bmap)
133 return -EINVAL;
134
135 id = find_first_zero_bit(rsrc->bmap, rsrc->max);
136 if (id >= rsrc->max)
137 return -ENOSPC;
138
139 __set_bit(id, rsrc->bmap);
140
141 return id;
142 }
143
rvu_alloc_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc)144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
145 {
146 int start;
147
148 if (!rsrc->bmap)
149 return -EINVAL;
150
151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
152 if (start >= rsrc->max)
153 return -ENOSPC;
154
155 bitmap_set(rsrc->bmap, start, nrsrc);
156 return start;
157 }
158
rvu_free_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc,int start)159 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
160 {
161 if (!rsrc->bmap)
162 return;
163 if (start >= rsrc->max)
164 return;
165
166 bitmap_clear(rsrc->bmap, start, nrsrc);
167 }
168
rvu_rsrc_check_contig(struct rsrc_bmap * rsrc,int nrsrc)169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
170 {
171 int start;
172
173 if (!rsrc->bmap)
174 return false;
175
176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
177 if (start >= rsrc->max)
178 return false;
179
180 return true;
181 }
182
rvu_free_rsrc(struct rsrc_bmap * rsrc,int id)183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
184 {
185 if (!rsrc->bmap)
186 return;
187
188 __clear_bit(id, rsrc->bmap);
189 }
190
rvu_rsrc_free_count(struct rsrc_bmap * rsrc)191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
192 {
193 int used;
194
195 if (!rsrc->bmap)
196 return 0;
197
198 used = bitmap_weight(rsrc->bmap, rsrc->max);
199 return (rsrc->max - used);
200 }
201
is_rsrc_free(struct rsrc_bmap * rsrc,int id)202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id)
203 {
204 if (!rsrc->bmap)
205 return false;
206
207 return !test_bit(id, rsrc->bmap);
208 }
209
rvu_alloc_bitmap(struct rsrc_bmap * rsrc)210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
211 {
212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
213 sizeof(long), GFP_KERNEL);
214 if (!rsrc->bmap)
215 return -ENOMEM;
216 return 0;
217 }
218
rvu_free_bitmap(struct rsrc_bmap * rsrc)219 void rvu_free_bitmap(struct rsrc_bmap *rsrc)
220 {
221 kfree(rsrc->bmap);
222 }
223
224 /* Get block LF's HW index from a PF_FUNC's block slot number */
rvu_get_lf(struct rvu * rvu,struct rvu_block * block,u16 pcifunc,u16 slot)225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
226 {
227 u16 match = 0;
228 int lf;
229
230 mutex_lock(&rvu->rsrc_lock);
231 for (lf = 0; lf < block->lf.max; lf++) {
232 if (block->fn_map[lf] == pcifunc) {
233 if (slot == match) {
234 mutex_unlock(&rvu->rsrc_lock);
235 return lf;
236 }
237 match++;
238 }
239 }
240 mutex_unlock(&rvu->rsrc_lock);
241 return -ENODEV;
242 }
243
244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
245 * Some silicon variants of OcteonTX2 supports
246 * multiple blocks of same type.
247 *
248 * @pcifunc has to be zero when no LF is yet attached.
249 *
250 * For a pcifunc if LFs are attached from multiple blocks of same type, then
251 * return blkaddr of first encountered block.
252 */
rvu_get_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc)253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
254 {
255 int devnum, blkaddr = -ENODEV;
256 u64 cfg, reg;
257 bool is_pf;
258
259 switch (blktype) {
260 case BLKTYPE_NPC:
261 blkaddr = BLKADDR_NPC;
262 goto exit;
263 case BLKTYPE_NPA:
264 blkaddr = BLKADDR_NPA;
265 goto exit;
266 case BLKTYPE_NIX:
267 /* For now assume NIX0 */
268 if (!pcifunc) {
269 blkaddr = BLKADDR_NIX0;
270 goto exit;
271 }
272 break;
273 case BLKTYPE_SSO:
274 blkaddr = BLKADDR_SSO;
275 goto exit;
276 case BLKTYPE_SSOW:
277 blkaddr = BLKADDR_SSOW;
278 goto exit;
279 case BLKTYPE_TIM:
280 blkaddr = BLKADDR_TIM;
281 goto exit;
282 case BLKTYPE_CPT:
283 /* For now assume CPT0 */
284 if (!pcifunc) {
285 blkaddr = BLKADDR_CPT0;
286 goto exit;
287 }
288 break;
289 }
290
291 /* Check if this is a RVU PF or VF */
292 if (pcifunc & RVU_PFVF_FUNC_MASK) {
293 is_pf = false;
294 devnum = rvu_get_hwvf(rvu, pcifunc);
295 } else {
296 is_pf = true;
297 devnum = rvu_get_pf(rvu->pdev, pcifunc);
298 }
299
300 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or
301 * 'BLKADDR_NIX1'.
302 */
303 if (blktype == BLKTYPE_NIX) {
304 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) :
305 RVU_PRIV_HWVFX_NIXX_CFG(0);
306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
307 if (cfg) {
308 blkaddr = BLKADDR_NIX0;
309 goto exit;
310 }
311
312 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) :
313 RVU_PRIV_HWVFX_NIXX_CFG(1);
314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
315 if (cfg)
316 blkaddr = BLKADDR_NIX1;
317 }
318
319 if (blktype == BLKTYPE_CPT) {
320 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) :
321 RVU_PRIV_HWVFX_CPTX_CFG(0);
322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
323 if (cfg) {
324 blkaddr = BLKADDR_CPT0;
325 goto exit;
326 }
327
328 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) :
329 RVU_PRIV_HWVFX_CPTX_CFG(1);
330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
331 if (cfg)
332 blkaddr = BLKADDR_CPT1;
333 }
334
335 exit:
336 if (is_block_implemented(rvu->hw, blkaddr))
337 return blkaddr;
338 return -ENODEV;
339 }
340
rvu_update_rsrc_map(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,u16 pcifunc,u16 lf,bool attach)341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
342 struct rvu_block *block, u16 pcifunc,
343 u16 lf, bool attach)
344 {
345 int devnum, num_lfs = 0;
346 bool is_pf;
347 u64 reg;
348
349 if (lf >= block->lf.max) {
350 dev_err(&rvu->pdev->dev,
351 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
352 __func__, lf, block->name, block->lf.max);
353 return;
354 }
355
356 /* Check if this is for a RVU PF or VF */
357 if (pcifunc & RVU_PFVF_FUNC_MASK) {
358 is_pf = false;
359 devnum = rvu_get_hwvf(rvu, pcifunc);
360 } else {
361 is_pf = true;
362 devnum = rvu_get_pf(rvu->pdev, pcifunc);
363 }
364
365 block->fn_map[lf] = attach ? pcifunc : 0;
366
367 switch (block->addr) {
368 case BLKADDR_NPA:
369 pfvf->npalf = attach ? true : false;
370 num_lfs = pfvf->npalf;
371 break;
372 case BLKADDR_NIX0:
373 case BLKADDR_NIX1:
374 pfvf->nixlf = attach ? true : false;
375 num_lfs = pfvf->nixlf;
376 break;
377 case BLKADDR_SSO:
378 attach ? pfvf->sso++ : pfvf->sso--;
379 num_lfs = pfvf->sso;
380 break;
381 case BLKADDR_SSOW:
382 attach ? pfvf->ssow++ : pfvf->ssow--;
383 num_lfs = pfvf->ssow;
384 break;
385 case BLKADDR_TIM:
386 attach ? pfvf->timlfs++ : pfvf->timlfs--;
387 num_lfs = pfvf->timlfs;
388 break;
389 case BLKADDR_CPT0:
390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
391 num_lfs = pfvf->cptlfs;
392 break;
393 case BLKADDR_CPT1:
394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--;
395 num_lfs = pfvf->cpt1_lfs;
396 break;
397 }
398
399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
400 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
401 }
402
rvu_get_pf_numvfs(struct rvu * rvu,int pf,int * numvfs,int * hwvf)403 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
404 {
405 u64 cfg;
406
407 /* Get numVFs attached to this PF and first HWVF */
408 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
409 if (numvfs)
410 *numvfs = (cfg >> 12) & 0xFF;
411 if (hwvf)
412 *hwvf = cfg & 0xFFF;
413 }
414
rvu_get_hwvf(struct rvu * rvu,int pcifunc)415 int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
416 {
417 int pf, func;
418 u64 cfg;
419
420 pf = rvu_get_pf(rvu->pdev, pcifunc);
421 func = pcifunc & RVU_PFVF_FUNC_MASK;
422
423 /* Get first HWVF attached to this PF */
424 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
425
426 return ((cfg & 0xFFF) + func - 1);
427 }
428
rvu_get_pfvf(struct rvu * rvu,int pcifunc)429 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
430 {
431 /* Check if it is a PF or VF */
432 if (pcifunc & RVU_PFVF_FUNC_MASK)
433 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
434 else
435 return &rvu->pf[rvu_get_pf(rvu->pdev, pcifunc)];
436 }
437
is_pf_func_valid(struct rvu * rvu,u16 pcifunc)438 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
439 {
440 int pf, vf, nvfs;
441 u64 cfg;
442
443 pf = rvu_get_pf(rvu->pdev, pcifunc);
444 if (pf >= rvu->hw->total_pfs)
445 return false;
446
447 if (!(pcifunc & RVU_PFVF_FUNC_MASK))
448 return true;
449
450 /* Check if VF is within number of VFs attached to this PF */
451 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
452 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
453 nvfs = (cfg >> 12) & 0xFF;
454 if (vf >= nvfs)
455 return false;
456
457 return true;
458 }
459
is_block_implemented(struct rvu_hwinfo * hw,int blkaddr)460 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
461 {
462 struct rvu_block *block;
463
464 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
465 return false;
466
467 block = &hw->block[blkaddr];
468 return block->implemented;
469 }
470
rvu_check_block_implemented(struct rvu * rvu)471 static void rvu_check_block_implemented(struct rvu *rvu)
472 {
473 struct rvu_hwinfo *hw = rvu->hw;
474 struct rvu_block *block;
475 int blkid;
476 u64 cfg;
477
478 /* For each block check if 'implemented' bit is set */
479 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
480 block = &hw->block[blkid];
481 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
482 if (cfg & BIT_ULL(11))
483 block->implemented = true;
484 }
485 }
486
rvu_setup_rvum_blk_revid(struct rvu * rvu)487 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
488 {
489 rvu_write64(rvu, BLKADDR_RVUM,
490 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
491 RVU_BLK_RVUM_REVID);
492 }
493
rvu_clear_rvum_blk_revid(struct rvu * rvu)494 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
495 {
496 rvu_write64(rvu, BLKADDR_RVUM,
497 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
498 }
499
rvu_lf_reset(struct rvu * rvu,struct rvu_block * block,int lf)500 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
501 {
502 int err;
503
504 if (!block->implemented)
505 return 0;
506
507 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
508 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
509 true);
510 return err;
511 }
512
rvu_block_reset(struct rvu * rvu,int blkaddr,u64 rst_reg)513 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
514 {
515 struct rvu_block *block = &rvu->hw->block[blkaddr];
516 int err;
517
518 if (!block->implemented)
519 return;
520
521 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
522 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
523 if (err) {
524 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr);
525 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY)
526 ;
527 }
528 }
529
rvu_reset_all_blocks(struct rvu * rvu)530 static void rvu_reset_all_blocks(struct rvu *rvu)
531 {
532 /* Do a HW reset of all RVU blocks */
533 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
534 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
535 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST);
536 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
537 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
538 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
539 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
540 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST);
541 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
542 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
543 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST);
544 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST);
545 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
546 }
547
rvu_scan_block(struct rvu * rvu,struct rvu_block * block)548 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
549 {
550 struct rvu_pfvf *pfvf;
551 u64 cfg;
552 int lf;
553
554 for (lf = 0; lf < block->lf.max; lf++) {
555 cfg = rvu_read64(rvu, block->addr,
556 block->lfcfg_reg | (lf << block->lfshift));
557 if (!(cfg & BIT_ULL(63)))
558 continue;
559
560 /* Set this resource as being used */
561 __set_bit(lf, block->lf.bmap);
562
563 /* Get, to whom this LF is attached */
564 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
565 rvu_update_rsrc_map(rvu, pfvf, block,
566 (cfg >> 8) & 0xFFFF, lf, true);
567
568 /* Set start MSIX vector for this LF within this PF/VF */
569 rvu_set_msix_offset(rvu, pfvf, block, lf);
570 }
571 }
572
rvu_check_min_msix_vec(struct rvu * rvu,int nvecs,int pf,int vf)573 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
574 {
575 int min_vecs;
576
577 if (!vf)
578 goto check_pf;
579
580 if (!nvecs) {
581 dev_warn(rvu->dev,
582 "PF%d:VF%d is configured with zero msix vectors, %d\n",
583 pf, vf - 1, nvecs);
584 }
585 return;
586
587 check_pf:
588 if (pf == 0)
589 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
590 else
591 min_vecs = RVU_PF_INT_VEC_CNT;
592
593 if (!(nvecs < min_vecs))
594 return;
595 dev_warn(rvu->dev,
596 "PF%d is configured with too few vectors, %d, min is %d\n",
597 pf, nvecs, min_vecs);
598 }
599
rvu_setup_msix_resources(struct rvu * rvu)600 static int rvu_setup_msix_resources(struct rvu *rvu)
601 {
602 struct rvu_hwinfo *hw = rvu->hw;
603 int pf, vf, numvfs, hwvf, err;
604 int nvecs, offset, max_msix;
605 struct rvu_pfvf *pfvf;
606 u64 cfg, phy_addr;
607 dma_addr_t iova;
608
609 for (pf = 0; pf < hw->total_pfs; pf++) {
610 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
611 /* If PF is not enabled, nothing to do */
612 if (!((cfg >> 20) & 0x01))
613 continue;
614
615 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
616
617 pfvf = &rvu->pf[pf];
618 /* Get num of MSIX vectors attached to this PF */
619 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
620 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
621 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
622
623 /* Alloc msix bitmap for this PF */
624 err = rvu_alloc_bitmap(&pfvf->msix);
625 if (err)
626 return err;
627
628 /* Allocate memory for MSIX vector to RVU block LF mapping */
629 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
630 sizeof(u16), GFP_KERNEL);
631 if (!pfvf->msix_lfmap)
632 return -ENOMEM;
633
634 /* For PF0 (AF) firmware will set msix vector offsets for
635 * AF, block AF and PF0_INT vectors, so jump to VFs.
636 */
637 if (!pf)
638 goto setup_vfmsix;
639
640 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
641 * These are allocated on driver init and never freed,
642 * so no need to set 'msix_lfmap' for these.
643 */
644 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
645 nvecs = (cfg >> 12) & 0xFF;
646 cfg &= ~0x7FFULL;
647 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
648 rvu_write64(rvu, BLKADDR_RVUM,
649 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
650 setup_vfmsix:
651 /* Alloc msix bitmap for VFs */
652 for (vf = 0; vf < numvfs; vf++) {
653 pfvf = &rvu->hwvf[hwvf + vf];
654 /* Get num of MSIX vectors attached to this VF */
655 cfg = rvu_read64(rvu, BLKADDR_RVUM,
656 RVU_PRIV_PFX_MSIX_CFG(pf));
657 pfvf->msix.max = (cfg & 0xFFF) + 1;
658 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
659
660 /* Alloc msix bitmap for this VF */
661 err = rvu_alloc_bitmap(&pfvf->msix);
662 if (err)
663 return err;
664
665 pfvf->msix_lfmap =
666 devm_kcalloc(rvu->dev, pfvf->msix.max,
667 sizeof(u16), GFP_KERNEL);
668 if (!pfvf->msix_lfmap)
669 return -ENOMEM;
670
671 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
672 * These are allocated on driver init and never freed,
673 * so no need to set 'msix_lfmap' for these.
674 */
675 cfg = rvu_read64(rvu, BLKADDR_RVUM,
676 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
677 nvecs = (cfg >> 12) & 0xFF;
678 cfg &= ~0x7FFULL;
679 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
680 rvu_write64(rvu, BLKADDR_RVUM,
681 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
682 cfg | offset);
683 }
684 }
685
686 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
687 * create an IOMMU mapping for the physical address configured by
688 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
689 */
690 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
691 max_msix = cfg & 0xFFFFF;
692 if (rvu->fwdata && rvu->fwdata->msixtr_base)
693 phy_addr = rvu->fwdata->msixtr_base;
694 else
695 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
696
697 iova = dma_map_resource(rvu->dev, phy_addr,
698 max_msix * PCI_MSIX_ENTRY_SIZE,
699 DMA_BIDIRECTIONAL, 0);
700
701 if (dma_mapping_error(rvu->dev, iova))
702 return -ENOMEM;
703
704 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
705 rvu->msix_base_iova = iova;
706 rvu->msixtr_base_phy = phy_addr;
707
708 return 0;
709 }
710
rvu_reset_msix(struct rvu * rvu)711 static void rvu_reset_msix(struct rvu *rvu)
712 {
713 /* Restore msixtr base register */
714 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
715 rvu->msixtr_base_phy);
716 }
717
rvu_free_hw_resources(struct rvu * rvu)718 static void rvu_free_hw_resources(struct rvu *rvu)
719 {
720 struct rvu_hwinfo *hw = rvu->hw;
721 struct rvu_block *block;
722 struct rvu_pfvf *pfvf;
723 int id, max_msix;
724 u64 cfg;
725
726 rvu_npa_freemem(rvu);
727 rvu_npc_freemem(rvu);
728 rvu_nix_freemem(rvu);
729
730 /* Free block LF bitmaps */
731 for (id = 0; id < BLK_COUNT; id++) {
732 block = &hw->block[id];
733 kfree(block->lf.bmap);
734 }
735
736 /* Free MSIX bitmaps */
737 for (id = 0; id < hw->total_pfs; id++) {
738 pfvf = &rvu->pf[id];
739 kfree(pfvf->msix.bmap);
740 }
741
742 for (id = 0; id < hw->total_vfs; id++) {
743 pfvf = &rvu->hwvf[id];
744 kfree(pfvf->msix.bmap);
745 }
746
747 /* Unmap MSIX vector base IOVA mapping */
748 if (!rvu->msix_base_iova)
749 return;
750 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
751 max_msix = cfg & 0xFFFFF;
752 dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
753 max_msix * PCI_MSIX_ENTRY_SIZE,
754 DMA_BIDIRECTIONAL, 0);
755
756 rvu_reset_msix(rvu);
757 mutex_destroy(&rvu->rsrc_lock);
758
759 /* Free the QINT/CINT memory */
760 pfvf = &rvu->pf[RVU_AFPF];
761 qmem_free(rvu->dev, pfvf->nix_qints_ctx);
762 qmem_free(rvu->dev, pfvf->cq_ints_ctx);
763 }
764
rvu_setup_pfvf_macaddress(struct rvu * rvu)765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
766 {
767 struct rvu_hwinfo *hw = rvu->hw;
768 int pf, vf, numvfs, hwvf;
769 struct rvu_pfvf *pfvf;
770 u64 *mac;
771
772 for (pf = 0; pf < hw->total_pfs; pf++) {
773 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */
774 if (!pf)
775 goto lbkvf;
776
777 if (!is_pf_cgxmapped(rvu, pf))
778 continue;
779 /* Assign MAC address to PF */
780 pfvf = &rvu->pf[pf];
781 if (rvu->fwdata && pf < PF_MACNUM_MAX) {
782 mac = &rvu->fwdata->pf_macs[pf];
783 if (*mac)
784 u64_to_ether_addr(*mac, pfvf->mac_addr);
785 else
786 eth_random_addr(pfvf->mac_addr);
787 } else {
788 eth_random_addr(pfvf->mac_addr);
789 }
790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
791
792 lbkvf:
793 /* Assign MAC address to VFs*/
794 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
795 for (vf = 0; vf < numvfs; vf++, hwvf++) {
796 pfvf = &rvu->hwvf[hwvf];
797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
798 mac = &rvu->fwdata->vf_macs[hwvf];
799 if (*mac)
800 u64_to_ether_addr(*mac, pfvf->mac_addr);
801 else
802 eth_random_addr(pfvf->mac_addr);
803 } else {
804 eth_random_addr(pfvf->mac_addr);
805 }
806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
807 }
808 }
809 }
810
rvu_fwdata_init(struct rvu * rvu)811 static int rvu_fwdata_init(struct rvu *rvu)
812 {
813 u64 fwdbase;
814 int err;
815
816 /* Get firmware data base address */
817 err = cgx_get_fwdata_base(&fwdbase);
818 if (err)
819 goto fail;
820
821 BUILD_BUG_ON(offsetof(struct rvu_fwdata, cgx_fw_data) > FWDATA_CGX_LMAC_OFFSET);
822 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
823 if (!rvu->fwdata)
824 goto fail;
825 if (!is_rvu_fwdata_valid(rvu)) {
826 dev_err(rvu->dev,
827 "Mismatch in 'fwdata' struct btw kernel and firmware\n");
828 iounmap(rvu->fwdata);
829 rvu->fwdata = NULL;
830 return -EINVAL;
831 }
832 return 0;
833 fail:
834 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
835 return -EIO;
836 }
837
rvu_fwdata_exit(struct rvu * rvu)838 static void rvu_fwdata_exit(struct rvu *rvu)
839 {
840 if (rvu->fwdata)
841 iounmap(rvu->fwdata);
842 }
843
rvu_setup_nix_hw_resource(struct rvu * rvu,int blkaddr)844 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr)
845 {
846 struct rvu_hwinfo *hw = rvu->hw;
847 struct rvu_block *block;
848 int blkid;
849 u64 cfg;
850
851 /* Init NIX LF's bitmap */
852 block = &hw->block[blkaddr];
853 if (!block->implemented)
854 return 0;
855 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
856 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
857 block->lf.max = cfg & 0xFFF;
858 block->addr = blkaddr;
859 block->type = BLKTYPE_NIX;
860 block->lfshift = 8;
861 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
862 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid);
863 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid);
864 block->lfcfg_reg = NIX_PRIV_LFX_CFG;
865 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
866 block->lfreset_reg = NIX_AF_LF_RST;
867 block->rvu = rvu;
868 sprintf(block->name, "NIX%d", blkid);
869 rvu->nix_blkaddr[blkid] = blkaddr;
870 return rvu_alloc_bitmap(&block->lf);
871 }
872
rvu_setup_cpt_hw_resource(struct rvu * rvu,int blkaddr)873 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr)
874 {
875 struct rvu_hwinfo *hw = rvu->hw;
876 struct rvu_block *block;
877 int blkid;
878 u64 cfg;
879
880 /* Init CPT LF's bitmap */
881 block = &hw->block[blkaddr];
882 if (!block->implemented)
883 return 0;
884 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
885 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
886 block->lf.max = cfg & 0xFF;
887 block->addr = blkaddr;
888 block->type = BLKTYPE_CPT;
889 block->multislot = true;
890 block->lfshift = 3;
891 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
892 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid);
893 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid);
894 block->lfcfg_reg = CPT_PRIV_LFX_CFG;
895 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
896 block->lfreset_reg = CPT_AF_LF_RST;
897 block->rvu = rvu;
898 sprintf(block->name, "CPT%d", blkid);
899 return rvu_alloc_bitmap(&block->lf);
900 }
901
rvu_get_lbk_bufsize(struct rvu * rvu)902 static void rvu_get_lbk_bufsize(struct rvu *rvu)
903 {
904 struct pci_dev *pdev = NULL;
905 void __iomem *base;
906 u64 lbk_const;
907
908 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
909 PCI_DEVID_OCTEONTX2_LBK, pdev);
910 if (!pdev)
911 return;
912
913 base = pci_ioremap_bar(pdev, 0);
914 if (!base)
915 goto err_put;
916
917 lbk_const = readq(base + LBK_CONST);
918
919 /* cache fifo size */
920 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const);
921
922 iounmap(base);
923 err_put:
924 pci_dev_put(pdev);
925 }
926
rvu_setup_hw_resources(struct rvu * rvu)927 static int rvu_setup_hw_resources(struct rvu *rvu)
928 {
929 struct rvu_hwinfo *hw = rvu->hw;
930 struct rvu_block *block;
931 int blkid, err;
932 u64 cfg;
933
934 /* Get HW supported max RVU PF & VF count */
935 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
936 hw->total_pfs = (cfg >> 32) & 0xFF;
937 hw->total_vfs = (cfg >> 20) & 0xFFF;
938 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
939
940 if (!is_rvu_otx2(rvu))
941 rvu_apr_block_cn10k_init(rvu);
942
943 /* Init NPA LF's bitmap */
944 block = &hw->block[BLKADDR_NPA];
945 if (!block->implemented)
946 goto nix;
947 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
948 block->lf.max = (cfg >> 16) & 0xFFF;
949 block->addr = BLKADDR_NPA;
950 block->type = BLKTYPE_NPA;
951 block->lfshift = 8;
952 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
953 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
954 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
955 block->lfcfg_reg = NPA_PRIV_LFX_CFG;
956 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
957 block->lfreset_reg = NPA_AF_LF_RST;
958 block->rvu = rvu;
959 sprintf(block->name, "NPA");
960 err = rvu_alloc_bitmap(&block->lf);
961 if (err) {
962 dev_err(rvu->dev,
963 "%s: Failed to allocate NPA LF bitmap\n", __func__);
964 return err;
965 }
966
967 nix:
968 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0);
969 if (err) {
970 dev_err(rvu->dev,
971 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__);
972 return err;
973 }
974
975 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1);
976 if (err) {
977 dev_err(rvu->dev,
978 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__);
979 return err;
980 }
981
982 /* Init SSO group's bitmap */
983 block = &hw->block[BLKADDR_SSO];
984 if (!block->implemented)
985 goto ssow;
986 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
987 block->lf.max = cfg & 0xFFFF;
988 block->addr = BLKADDR_SSO;
989 block->type = BLKTYPE_SSO;
990 block->multislot = true;
991 block->lfshift = 3;
992 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
993 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
994 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
995 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
996 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
997 block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
998 block->rvu = rvu;
999 sprintf(block->name, "SSO GROUP");
1000 err = rvu_alloc_bitmap(&block->lf);
1001 if (err) {
1002 dev_err(rvu->dev,
1003 "%s: Failed to allocate SSO LF bitmap\n", __func__);
1004 return err;
1005 }
1006
1007 ssow:
1008 /* Init SSO workslot's bitmap */
1009 block = &hw->block[BLKADDR_SSOW];
1010 if (!block->implemented)
1011 goto tim;
1012 block->lf.max = (cfg >> 56) & 0xFF;
1013 block->addr = BLKADDR_SSOW;
1014 block->type = BLKTYPE_SSOW;
1015 block->multislot = true;
1016 block->lfshift = 3;
1017 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
1018 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
1019 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
1020 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
1021 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
1022 block->lfreset_reg = SSOW_AF_LF_HWS_RST;
1023 block->rvu = rvu;
1024 sprintf(block->name, "SSOWS");
1025 err = rvu_alloc_bitmap(&block->lf);
1026 if (err) {
1027 dev_err(rvu->dev,
1028 "%s: Failed to allocate SSOW LF bitmap\n", __func__);
1029 return err;
1030 }
1031
1032 tim:
1033 /* Init TIM LF's bitmap */
1034 block = &hw->block[BLKADDR_TIM];
1035 if (!block->implemented)
1036 goto cpt;
1037 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
1038 block->lf.max = cfg & 0xFFFF;
1039 block->addr = BLKADDR_TIM;
1040 block->type = BLKTYPE_TIM;
1041 block->multislot = true;
1042 block->lfshift = 3;
1043 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
1044 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
1045 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
1046 block->lfcfg_reg = TIM_PRIV_LFX_CFG;
1047 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
1048 block->lfreset_reg = TIM_AF_LF_RST;
1049 block->rvu = rvu;
1050 sprintf(block->name, "TIM");
1051 err = rvu_alloc_bitmap(&block->lf);
1052 if (err) {
1053 dev_err(rvu->dev,
1054 "%s: Failed to allocate TIM LF bitmap\n", __func__);
1055 return err;
1056 }
1057
1058 cpt:
1059 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0);
1060 if (err) {
1061 dev_err(rvu->dev,
1062 "%s: Failed to allocate CPT0 LF bitmap\n", __func__);
1063 return err;
1064 }
1065 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1);
1066 if (err) {
1067 dev_err(rvu->dev,
1068 "%s: Failed to allocate CPT1 LF bitmap\n", __func__);
1069 return err;
1070 }
1071
1072 /* Allocate memory for PFVF data */
1073 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
1074 sizeof(struct rvu_pfvf), GFP_KERNEL);
1075 if (!rvu->pf) {
1076 dev_err(rvu->dev,
1077 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__);
1078 return -ENOMEM;
1079 }
1080
1081 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
1082 sizeof(struct rvu_pfvf), GFP_KERNEL);
1083 if (!rvu->hwvf) {
1084 dev_err(rvu->dev,
1085 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__);
1086 return -ENOMEM;
1087 }
1088
1089 mutex_init(&rvu->rsrc_lock);
1090
1091 rvu_fwdata_init(rvu);
1092
1093 err = rvu_setup_msix_resources(rvu);
1094 if (err) {
1095 dev_err(rvu->dev,
1096 "%s: Failed to setup MSIX resources\n", __func__);
1097 return err;
1098 }
1099
1100 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1101 block = &hw->block[blkid];
1102 if (!block->lf.bmap)
1103 continue;
1104
1105 /* Allocate memory for block LF/slot to pcifunc mapping info */
1106 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
1107 sizeof(u16), GFP_KERNEL);
1108 if (!block->fn_map) {
1109 err = -ENOMEM;
1110 goto msix_err;
1111 }
1112
1113 /* Scan all blocks to check if low level firmware has
1114 * already provisioned any of the resources to a PF/VF.
1115 */
1116 rvu_scan_block(rvu, block);
1117 }
1118
1119 err = rvu_set_channels_base(rvu);
1120 if (err)
1121 goto msix_err;
1122
1123 err = rvu_npc_init(rvu);
1124 if (err) {
1125 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__);
1126 goto npc_err;
1127 }
1128
1129 err = rvu_cgx_init(rvu);
1130 if (err) {
1131 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__);
1132 goto cgx_err;
1133 }
1134
1135 err = rvu_npc_exact_init(rvu);
1136 if (err) {
1137 dev_err(rvu->dev, "failed to initialize exact match table\n");
1138 return err;
1139 }
1140
1141 /* Assign MACs for CGX mapped functions */
1142 rvu_setup_pfvf_macaddress(rvu);
1143
1144 err = rvu_npa_init(rvu);
1145 if (err) {
1146 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__);
1147 goto npa_err;
1148 }
1149
1150 rvu_get_lbk_bufsize(rvu);
1151
1152 err = rvu_nix_init(rvu);
1153 if (err) {
1154 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__);
1155 goto nix_err;
1156 }
1157
1158 err = rvu_sdp_init(rvu);
1159 if (err) {
1160 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);
1161 goto nix_err;
1162 }
1163
1164 rvu_program_channels(rvu);
1165 cgx_start_linkup(rvu);
1166
1167 err = rvu_mcs_init(rvu);
1168 if (err) {
1169 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__);
1170 goto nix_err;
1171 }
1172
1173 err = rvu_cpt_init(rvu);
1174 if (err) {
1175 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__);
1176 goto mcs_err;
1177 }
1178
1179 return 0;
1180
1181 mcs_err:
1182 rvu_mcs_exit(rvu);
1183 nix_err:
1184 rvu_nix_freemem(rvu);
1185 npa_err:
1186 rvu_npa_freemem(rvu);
1187 cgx_err:
1188 rvu_cgx_exit(rvu);
1189 npc_err:
1190 rvu_npc_freemem(rvu);
1191 rvu_fwdata_exit(rvu);
1192 msix_err:
1193 rvu_reset_msix(rvu);
1194 return err;
1195 }
1196
1197 /* NPA and NIX admin queue APIs */
rvu_aq_free(struct rvu * rvu,struct admin_queue * aq)1198 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
1199 {
1200 if (!aq)
1201 return;
1202
1203 qmem_free(rvu->dev, aq->inst);
1204 qmem_free(rvu->dev, aq->res);
1205 devm_kfree(rvu->dev, aq);
1206 }
1207
rvu_aq_alloc(struct rvu * rvu,struct admin_queue ** ad_queue,int qsize,int inst_size,int res_size)1208 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
1209 int qsize, int inst_size, int res_size)
1210 {
1211 struct admin_queue *aq;
1212 int err;
1213
1214 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
1215 if (!*ad_queue)
1216 return -ENOMEM;
1217 aq = *ad_queue;
1218
1219 /* Alloc memory for instructions i.e AQ */
1220 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
1221 if (err) {
1222 devm_kfree(rvu->dev, aq);
1223 return err;
1224 }
1225
1226 /* Alloc memory for results */
1227 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1228 if (err) {
1229 rvu_aq_free(rvu, aq);
1230 return err;
1231 }
1232
1233 spin_lock_init(&aq->lock);
1234 return 0;
1235 }
1236
rvu_mbox_handler_ready(struct rvu * rvu,struct msg_req * req,struct ready_msg_rsp * rsp)1237 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1238 struct ready_msg_rsp *rsp)
1239 {
1240 if (rvu->fwdata) {
1241 rsp->rclk_freq = rvu->fwdata->rclk;
1242 rsp->sclk_freq = rvu->fwdata->sclk;
1243 }
1244 return 0;
1245 }
1246
1247 /* Get current count of a RVU block's LF/slots
1248 * provisioned to a given RVU func.
1249 */
rvu_get_rsrc_mapcount(struct rvu_pfvf * pfvf,int blkaddr)1250 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr)
1251 {
1252 switch (blkaddr) {
1253 case BLKADDR_NPA:
1254 return pfvf->npalf ? 1 : 0;
1255 case BLKADDR_NIX0:
1256 case BLKADDR_NIX1:
1257 return pfvf->nixlf ? 1 : 0;
1258 case BLKADDR_SSO:
1259 return pfvf->sso;
1260 case BLKADDR_SSOW:
1261 return pfvf->ssow;
1262 case BLKADDR_TIM:
1263 return pfvf->timlfs;
1264 case BLKADDR_CPT0:
1265 return pfvf->cptlfs;
1266 case BLKADDR_CPT1:
1267 return pfvf->cpt1_lfs;
1268 }
1269 return 0;
1270 }
1271
1272 /* Return true if LFs of block type are attached to pcifunc */
is_blktype_attached(struct rvu_pfvf * pfvf,int blktype)1273 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype)
1274 {
1275 switch (blktype) {
1276 case BLKTYPE_NPA:
1277 return pfvf->npalf ? 1 : 0;
1278 case BLKTYPE_NIX:
1279 return pfvf->nixlf ? 1 : 0;
1280 case BLKTYPE_SSO:
1281 return !!pfvf->sso;
1282 case BLKTYPE_SSOW:
1283 return !!pfvf->ssow;
1284 case BLKTYPE_TIM:
1285 return !!pfvf->timlfs;
1286 case BLKTYPE_CPT:
1287 return pfvf->cptlfs || pfvf->cpt1_lfs;
1288 }
1289
1290 return false;
1291 }
1292
is_pffunc_map_valid(struct rvu * rvu,u16 pcifunc,int blktype)1293 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1294 {
1295 struct rvu_pfvf *pfvf;
1296
1297 if (!is_pf_func_valid(rvu, pcifunc))
1298 return false;
1299
1300 pfvf = rvu_get_pfvf(rvu, pcifunc);
1301
1302 /* Check if this PFFUNC has a LF of type blktype attached */
1303 if (!is_blktype_attached(pfvf, blktype))
1304 return false;
1305
1306 return true;
1307 }
1308
rvu_lookup_rsrc(struct rvu * rvu,struct rvu_block * block,int pcifunc,int slot)1309 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1310 int pcifunc, int slot)
1311 {
1312 u64 val;
1313
1314 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1315 rvu_write64(rvu, block->addr, block->lookup_reg, val);
1316 /* Wait for the lookup to finish */
1317 /* TODO: put some timeout here */
1318 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1319 ;
1320
1321 val = rvu_read64(rvu, block->addr, block->lookup_reg);
1322
1323 /* Check LF valid bit */
1324 if (!(val & (1ULL << 12)))
1325 return -1;
1326
1327 return (val & 0xFFF);
1328 }
1329
rvu_get_blkaddr_from_slot(struct rvu * rvu,int blktype,u16 pcifunc,u16 global_slot,u16 * slot_in_block)1330 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
1331 u16 global_slot, u16 *slot_in_block)
1332 {
1333 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1334 int numlfs, total_lfs = 0, nr_blocks = 0;
1335 int i, num_blkaddr[BLK_COUNT] = { 0 };
1336 struct rvu_block *block;
1337 int blkaddr;
1338 u16 start_slot;
1339
1340 if (!is_blktype_attached(pfvf, blktype))
1341 return -ENODEV;
1342
1343 /* Get all the block addresses from which LFs are attached to
1344 * the given pcifunc in num_blkaddr[].
1345 */
1346 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) {
1347 block = &rvu->hw->block[blkaddr];
1348 if (block->type != blktype)
1349 continue;
1350 if (!is_block_implemented(rvu->hw, blkaddr))
1351 continue;
1352
1353 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr);
1354 if (numlfs) {
1355 total_lfs += numlfs;
1356 num_blkaddr[nr_blocks] = blkaddr;
1357 nr_blocks++;
1358 }
1359 }
1360
1361 if (global_slot >= total_lfs)
1362 return -ENODEV;
1363
1364 /* Based on the given global slot number retrieve the
1365 * correct block address out of all attached block
1366 * addresses and slot number in that block.
1367 */
1368 total_lfs = 0;
1369 blkaddr = -ENODEV;
1370 for (i = 0; i < nr_blocks; i++) {
1371 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]);
1372 total_lfs += numlfs;
1373 if (global_slot < total_lfs) {
1374 blkaddr = num_blkaddr[i];
1375 start_slot = total_lfs - numlfs;
1376 *slot_in_block = global_slot - start_slot;
1377 break;
1378 }
1379 }
1380
1381 return blkaddr;
1382 }
1383
rvu_detach_block(struct rvu * rvu,int pcifunc,int blktype)1384 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1385 {
1386 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1387 struct rvu_hwinfo *hw = rvu->hw;
1388 struct rvu_block *block;
1389 int slot, lf, num_lfs;
1390 int blkaddr;
1391
1392 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1393 if (blkaddr < 0)
1394 return;
1395
1396
1397 block = &hw->block[blkaddr];
1398
1399 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1400 if (!num_lfs)
1401 return;
1402
1403 for (slot = 0; slot < num_lfs; slot++) {
1404 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1405 if (lf < 0) /* This should never happen */
1406 continue;
1407
1408 if (blktype == BLKTYPE_NIX) {
1409 rvu_nix_reset_mac(pfvf, pcifunc);
1410 rvu_npc_clear_ucast_entry(rvu, pcifunc, lf);
1411 }
1412 /* Disable the LF */
1413 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1414 (lf << block->lfshift), 0x00ULL);
1415
1416 /* Update SW maintained mapping info as well */
1417 rvu_update_rsrc_map(rvu, pfvf, block,
1418 pcifunc, lf, false);
1419
1420 /* Free the resource */
1421 rvu_free_rsrc(&block->lf, lf);
1422
1423 /* Clear MSIX vector offset for this LF */
1424 rvu_clear_msix_offset(rvu, pfvf, block, lf);
1425 }
1426 }
1427
rvu_detach_rsrcs(struct rvu * rvu,struct rsrc_detach * detach,u16 pcifunc)1428 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1429 u16 pcifunc)
1430 {
1431 struct rvu_hwinfo *hw = rvu->hw;
1432 bool detach_all = true;
1433 struct rvu_block *block;
1434 int blkid;
1435
1436 mutex_lock(&rvu->rsrc_lock);
1437
1438 /* Check for partial resource detach */
1439 if (detach && detach->partial)
1440 detach_all = false;
1441
1442 /* Check for RVU block's LFs attached to this func,
1443 * if so, detach them.
1444 */
1445 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1446 block = &hw->block[blkid];
1447 if (!block->lf.bmap)
1448 continue;
1449 if (!detach_all && detach) {
1450 if (blkid == BLKADDR_NPA && !detach->npalf)
1451 continue;
1452 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1453 continue;
1454 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf)
1455 continue;
1456 else if ((blkid == BLKADDR_SSO) && !detach->sso)
1457 continue;
1458 else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1459 continue;
1460 else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1461 continue;
1462 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1463 continue;
1464 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs)
1465 continue;
1466 }
1467 rvu_detach_block(rvu, pcifunc, block->type);
1468 }
1469
1470 mutex_unlock(&rvu->rsrc_lock);
1471 return 0;
1472 }
1473
rvu_mbox_handler_detach_resources(struct rvu * rvu,struct rsrc_detach * detach,struct msg_rsp * rsp)1474 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1475 struct rsrc_detach *detach,
1476 struct msg_rsp *rsp)
1477 {
1478 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1479 }
1480
rvu_get_nix_blkaddr(struct rvu * rvu,u16 pcifunc)1481 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
1482 {
1483 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1484 int blkaddr = BLKADDR_NIX0, vf;
1485 struct rvu_pfvf *pf;
1486
1487 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1488
1489 /* All CGX mapped PFs are set with assigned NIX block during init */
1490 if (is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))) {
1491 blkaddr = pf->nix_blkaddr;
1492 } else if (is_lbk_vf(rvu, pcifunc)) {
1493 vf = pcifunc - 1;
1494 /* Assign NIX based on VF number. All even numbered VFs get
1495 * NIX0 and odd numbered gets NIX1
1496 */
1497 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0;
1498 /* NIX1 is not present on all silicons */
1499 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1500 blkaddr = BLKADDR_NIX0;
1501 }
1502
1503 /* if SDP1 then the blkaddr is NIX1 */
1504 if (is_sdp_pfvf(rvu, pcifunc) && pf->sdp_info->node_id == 1)
1505 blkaddr = BLKADDR_NIX1;
1506
1507 switch (blkaddr) {
1508 case BLKADDR_NIX1:
1509 pfvf->nix_blkaddr = BLKADDR_NIX1;
1510 pfvf->nix_rx_intf = NIX_INTFX_RX(1);
1511 pfvf->nix_tx_intf = NIX_INTFX_TX(1);
1512 break;
1513 case BLKADDR_NIX0:
1514 default:
1515 pfvf->nix_blkaddr = BLKADDR_NIX0;
1516 pfvf->nix_rx_intf = NIX_INTFX_RX(0);
1517 pfvf->nix_tx_intf = NIX_INTFX_TX(0);
1518 break;
1519 }
1520
1521 return pfvf->nix_blkaddr;
1522 }
1523
rvu_get_attach_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc,struct rsrc_attach * attach)1524 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype,
1525 u16 pcifunc, struct rsrc_attach *attach)
1526 {
1527 int blkaddr;
1528
1529 switch (blktype) {
1530 case BLKTYPE_NIX:
1531 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc);
1532 break;
1533 case BLKTYPE_CPT:
1534 if (attach->hdr.ver < RVU_MULTI_BLK_VER)
1535 return rvu_get_blkaddr(rvu, blktype, 0);
1536 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr :
1537 BLKADDR_CPT0;
1538 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
1539 return -ENODEV;
1540 break;
1541 default:
1542 return rvu_get_blkaddr(rvu, blktype, 0);
1543 }
1544
1545 if (is_block_implemented(rvu->hw, blkaddr))
1546 return blkaddr;
1547
1548 return -ENODEV;
1549 }
1550
rvu_attach_block(struct rvu * rvu,int pcifunc,int blktype,int num_lfs,struct rsrc_attach * attach)1551 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype,
1552 int num_lfs, struct rsrc_attach *attach)
1553 {
1554 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1555 struct rvu_hwinfo *hw = rvu->hw;
1556 struct rvu_block *block;
1557 int slot, lf;
1558 int blkaddr;
1559 u64 cfg;
1560
1561 if (!num_lfs)
1562 return;
1563
1564 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach);
1565 if (blkaddr < 0)
1566 return;
1567
1568 block = &hw->block[blkaddr];
1569 if (!block->lf.bmap)
1570 return;
1571
1572 for (slot = 0; slot < num_lfs; slot++) {
1573 /* Allocate the resource */
1574 lf = rvu_alloc_rsrc(&block->lf);
1575 if (lf < 0)
1576 return;
1577
1578 cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1579 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1580 (lf << block->lfshift), cfg);
1581 rvu_update_rsrc_map(rvu, pfvf, block,
1582 pcifunc, lf, true);
1583
1584 /* Set start MSIX vector for this LF within this PF/VF */
1585 rvu_set_msix_offset(rvu, pfvf, block, lf);
1586 }
1587 }
1588
rvu_check_rsrc_availability(struct rvu * rvu,struct rsrc_attach * req,u16 pcifunc)1589 static int rvu_check_rsrc_availability(struct rvu *rvu,
1590 struct rsrc_attach *req, u16 pcifunc)
1591 {
1592 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1593 int free_lfs, mappedlfs, blkaddr;
1594 struct rvu_hwinfo *hw = rvu->hw;
1595 struct rvu_block *block;
1596
1597 /* Only one NPA LF can be attached */
1598 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) {
1599 block = &hw->block[BLKADDR_NPA];
1600 free_lfs = rvu_rsrc_free_count(&block->lf);
1601 if (!free_lfs)
1602 goto fail;
1603 } else if (req->npalf) {
1604 dev_err(&rvu->pdev->dev,
1605 "Func 0x%x: Invalid req, already has NPA\n",
1606 pcifunc);
1607 return -EINVAL;
1608 }
1609
1610 /* Only one NIX LF can be attached */
1611 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) {
1612 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX,
1613 pcifunc, req);
1614 if (blkaddr < 0)
1615 return blkaddr;
1616 block = &hw->block[blkaddr];
1617 free_lfs = rvu_rsrc_free_count(&block->lf);
1618 if (!free_lfs)
1619 goto fail;
1620 } else if (req->nixlf) {
1621 dev_err(&rvu->pdev->dev,
1622 "Func 0x%x: Invalid req, already has NIX\n",
1623 pcifunc);
1624 return -EINVAL;
1625 }
1626
1627 if (req->sso) {
1628 block = &hw->block[BLKADDR_SSO];
1629 /* Is request within limits ? */
1630 if (req->sso > block->lf.max) {
1631 dev_err(&rvu->pdev->dev,
1632 "Func 0x%x: Invalid SSO req, %d > max %d\n",
1633 pcifunc, req->sso, block->lf.max);
1634 return -EINVAL;
1635 }
1636 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1637 free_lfs = rvu_rsrc_free_count(&block->lf);
1638 /* Check if additional resources are available */
1639 if (req->sso > mappedlfs &&
1640 ((req->sso - mappedlfs) > free_lfs))
1641 goto fail;
1642 }
1643
1644 if (req->ssow) {
1645 block = &hw->block[BLKADDR_SSOW];
1646 if (req->ssow > block->lf.max) {
1647 dev_err(&rvu->pdev->dev,
1648 "Func 0x%x: Invalid SSOW req, %d > max %d\n",
1649 pcifunc, req->ssow, block->lf.max);
1650 return -EINVAL;
1651 }
1652 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1653 free_lfs = rvu_rsrc_free_count(&block->lf);
1654 if (req->ssow > mappedlfs &&
1655 ((req->ssow - mappedlfs) > free_lfs))
1656 goto fail;
1657 }
1658
1659 if (req->timlfs) {
1660 block = &hw->block[BLKADDR_TIM];
1661 if (req->timlfs > block->lf.max) {
1662 dev_err(&rvu->pdev->dev,
1663 "Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1664 pcifunc, req->timlfs, block->lf.max);
1665 return -EINVAL;
1666 }
1667 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1668 free_lfs = rvu_rsrc_free_count(&block->lf);
1669 if (req->timlfs > mappedlfs &&
1670 ((req->timlfs - mappedlfs) > free_lfs))
1671 goto fail;
1672 }
1673
1674 if (req->cptlfs) {
1675 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT,
1676 pcifunc, req);
1677 if (blkaddr < 0)
1678 return blkaddr;
1679 block = &hw->block[blkaddr];
1680 if (req->cptlfs > block->lf.max) {
1681 dev_err(&rvu->pdev->dev,
1682 "Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1683 pcifunc, req->cptlfs, block->lf.max);
1684 return -EINVAL;
1685 }
1686 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1687 free_lfs = rvu_rsrc_free_count(&block->lf);
1688 if (req->cptlfs > mappedlfs &&
1689 ((req->cptlfs - mappedlfs) > free_lfs))
1690 goto fail;
1691 }
1692
1693 return 0;
1694
1695 fail:
1696 dev_info(rvu->dev, "Request for %s failed\n", block->name);
1697 return -ENOSPC;
1698 }
1699
rvu_attach_from_same_block(struct rvu * rvu,int blktype,struct rsrc_attach * attach)1700 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype,
1701 struct rsrc_attach *attach)
1702 {
1703 int blkaddr, num_lfs;
1704
1705 blkaddr = rvu_get_attach_blkaddr(rvu, blktype,
1706 attach->hdr.pcifunc, attach);
1707 if (blkaddr < 0)
1708 return false;
1709
1710 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc),
1711 blkaddr);
1712 /* Requester already has LFs from given block ? */
1713 return !!num_lfs;
1714 }
1715
rvu_mbox_handler_attach_resources(struct rvu * rvu,struct rsrc_attach * attach,struct msg_rsp * rsp)1716 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1717 struct rsrc_attach *attach,
1718 struct msg_rsp *rsp)
1719 {
1720 u16 pcifunc = attach->hdr.pcifunc;
1721 int err;
1722
1723 /* If first request, detach all existing attached resources */
1724 if (!attach->modify)
1725 rvu_detach_rsrcs(rvu, NULL, pcifunc);
1726
1727 mutex_lock(&rvu->rsrc_lock);
1728
1729 /* Check if the request can be accommodated */
1730 err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1731 if (err)
1732 goto exit;
1733
1734 /* Now attach the requested resources */
1735 if (attach->npalf)
1736 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach);
1737
1738 if (attach->nixlf)
1739 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach);
1740
1741 if (attach->sso) {
1742 /* RVU func doesn't know which exact LF or slot is attached
1743 * to it, it always sees as slot 0,1,2. So for a 'modify'
1744 * request, simply detach all existing attached LFs/slots
1745 * and attach a fresh.
1746 */
1747 if (attach->modify)
1748 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1749 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO,
1750 attach->sso, attach);
1751 }
1752
1753 if (attach->ssow) {
1754 if (attach->modify)
1755 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1756 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW,
1757 attach->ssow, attach);
1758 }
1759
1760 if (attach->timlfs) {
1761 if (attach->modify)
1762 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1763 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM,
1764 attach->timlfs, attach);
1765 }
1766
1767 if (attach->cptlfs) {
1768 if (attach->modify &&
1769 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach))
1770 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1771 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT,
1772 attach->cptlfs, attach);
1773 }
1774
1775 exit:
1776 mutex_unlock(&rvu->rsrc_lock);
1777 return err;
1778 }
1779
rvu_get_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,int blkaddr,int lf)1780 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1781 int blkaddr, int lf)
1782 {
1783 u16 vec;
1784
1785 if (lf < 0)
1786 return MSIX_VECTOR_INVALID;
1787
1788 for (vec = 0; vec < pfvf->msix.max; vec++) {
1789 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1790 return vec;
1791 }
1792 return MSIX_VECTOR_INVALID;
1793 }
1794
rvu_set_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1795 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1796 struct rvu_block *block, int lf)
1797 {
1798 u16 nvecs, vec, offset;
1799 u64 cfg;
1800
1801 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1802 (lf << block->lfshift));
1803 nvecs = (cfg >> 12) & 0xFF;
1804
1805 /* Check and alloc MSIX vectors, must be contiguous */
1806 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1807 return;
1808
1809 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1810
1811 /* Config MSIX offset in LF */
1812 rvu_write64(rvu, block->addr, block->msixcfg_reg |
1813 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1814
1815 /* Update the bitmap as well */
1816 for (vec = 0; vec < nvecs; vec++)
1817 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1818 }
1819
rvu_clear_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1820 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1821 struct rvu_block *block, int lf)
1822 {
1823 u16 nvecs, vec, offset;
1824 u64 cfg;
1825
1826 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1827 (lf << block->lfshift));
1828 nvecs = (cfg >> 12) & 0xFF;
1829
1830 /* Clear MSIX offset in LF */
1831 rvu_write64(rvu, block->addr, block->msixcfg_reg |
1832 (lf << block->lfshift), cfg & ~0x7FFULL);
1833
1834 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1835
1836 /* Update the mapping */
1837 for (vec = 0; vec < nvecs; vec++)
1838 pfvf->msix_lfmap[offset + vec] = 0;
1839
1840 /* Free the same in MSIX bitmap */
1841 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1842 }
1843
rvu_mbox_handler_msix_offset(struct rvu * rvu,struct msg_req * req,struct msix_offset_rsp * rsp)1844 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1845 struct msix_offset_rsp *rsp)
1846 {
1847 struct rvu_hwinfo *hw = rvu->hw;
1848 u16 pcifunc = req->hdr.pcifunc;
1849 struct rvu_pfvf *pfvf;
1850 int lf, slot, blkaddr;
1851
1852 pfvf = rvu_get_pfvf(rvu, pcifunc);
1853 if (!pfvf->msix.bmap)
1854 return 0;
1855
1856 /* Set MSIX offsets for each block's LFs attached to this PF/VF */
1857 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1858 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1859
1860 /* Get BLKADDR from which LFs are attached to pcifunc */
1861 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1862 if (blkaddr < 0) {
1863 rsp->nix_msixoff = MSIX_VECTOR_INVALID;
1864 } else {
1865 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
1866 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf);
1867 }
1868
1869 rsp->sso = pfvf->sso;
1870 for (slot = 0; slot < rsp->sso; slot++) {
1871 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1872 rsp->sso_msixoff[slot] =
1873 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1874 }
1875
1876 rsp->ssow = pfvf->ssow;
1877 for (slot = 0; slot < rsp->ssow; slot++) {
1878 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1879 rsp->ssow_msixoff[slot] =
1880 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1881 }
1882
1883 rsp->timlfs = pfvf->timlfs;
1884 for (slot = 0; slot < rsp->timlfs; slot++) {
1885 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1886 rsp->timlf_msixoff[slot] =
1887 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1888 }
1889
1890 rsp->cptlfs = pfvf->cptlfs;
1891 for (slot = 0; slot < rsp->cptlfs; slot++) {
1892 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1893 rsp->cptlf_msixoff[slot] =
1894 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1895 }
1896
1897 rsp->cpt1_lfs = pfvf->cpt1_lfs;
1898 for (slot = 0; slot < rsp->cpt1_lfs; slot++) {
1899 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot);
1900 rsp->cpt1_lf_msixoff[slot] =
1901 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf);
1902 }
1903
1904 return 0;
1905 }
1906
rvu_mbox_handler_free_rsrc_cnt(struct rvu * rvu,struct msg_req * req,struct free_rsrcs_rsp * rsp)1907 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,
1908 struct free_rsrcs_rsp *rsp)
1909 {
1910 struct rvu_hwinfo *hw = rvu->hw;
1911 struct rvu_block *block;
1912 struct nix_txsch *txsch;
1913 struct nix_hw *nix_hw;
1914
1915 mutex_lock(&rvu->rsrc_lock);
1916
1917 block = &hw->block[BLKADDR_NPA];
1918 rsp->npa = rvu_rsrc_free_count(&block->lf);
1919
1920 block = &hw->block[BLKADDR_NIX0];
1921 rsp->nix = rvu_rsrc_free_count(&block->lf);
1922
1923 block = &hw->block[BLKADDR_NIX1];
1924 rsp->nix1 = rvu_rsrc_free_count(&block->lf);
1925
1926 block = &hw->block[BLKADDR_SSO];
1927 rsp->sso = rvu_rsrc_free_count(&block->lf);
1928
1929 block = &hw->block[BLKADDR_SSOW];
1930 rsp->ssow = rvu_rsrc_free_count(&block->lf);
1931
1932 block = &hw->block[BLKADDR_TIM];
1933 rsp->tim = rvu_rsrc_free_count(&block->lf);
1934
1935 block = &hw->block[BLKADDR_CPT0];
1936 rsp->cpt = rvu_rsrc_free_count(&block->lf);
1937
1938 block = &hw->block[BLKADDR_CPT1];
1939 rsp->cpt1 = rvu_rsrc_free_count(&block->lf);
1940
1941 if (rvu->hw->cap.nix_fixed_txschq_mapping) {
1942 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1;
1943 rsp->schq[NIX_TXSCH_LVL_TL4] = 1;
1944 rsp->schq[NIX_TXSCH_LVL_TL3] = 1;
1945 rsp->schq[NIX_TXSCH_LVL_TL2] = 1;
1946 /* NIX1 */
1947 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1948 goto out;
1949 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1;
1950 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1;
1951 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1;
1952 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1;
1953 } else {
1954 nix_hw = get_nix_hw(hw, BLKADDR_NIX0);
1955 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1956 rsp->schq[NIX_TXSCH_LVL_SMQ] =
1957 rvu_rsrc_free_count(&txsch->schq);
1958
1959 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1960 rsp->schq[NIX_TXSCH_LVL_TL4] =
1961 rvu_rsrc_free_count(&txsch->schq);
1962
1963 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1964 rsp->schq[NIX_TXSCH_LVL_TL3] =
1965 rvu_rsrc_free_count(&txsch->schq);
1966
1967 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1968 rsp->schq[NIX_TXSCH_LVL_TL2] =
1969 rvu_rsrc_free_count(&txsch->schq);
1970
1971 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1972 goto out;
1973
1974 nix_hw = get_nix_hw(hw, BLKADDR_NIX1);
1975 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1976 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] =
1977 rvu_rsrc_free_count(&txsch->schq);
1978
1979 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1980 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] =
1981 rvu_rsrc_free_count(&txsch->schq);
1982
1983 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1984 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] =
1985 rvu_rsrc_free_count(&txsch->schq);
1986
1987 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1988 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] =
1989 rvu_rsrc_free_count(&txsch->schq);
1990 }
1991
1992 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1;
1993 out:
1994 rsp->schq[NIX_TXSCH_LVL_TL1] = 1;
1995 mutex_unlock(&rvu->rsrc_lock);
1996
1997 return 0;
1998 }
1999
rvu_mbox_handler_vf_flr(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)2000 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
2001 struct msg_rsp *rsp)
2002 {
2003 u16 pcifunc = req->hdr.pcifunc;
2004 u16 vf, numvfs;
2005 u64 cfg;
2006
2007 vf = pcifunc & RVU_PFVF_FUNC_MASK;
2008 cfg = rvu_read64(rvu, BLKADDR_RVUM,
2009 RVU_PRIV_PFX_CFG(rvu_get_pf(rvu->pdev, pcifunc)));
2010 numvfs = (cfg >> 12) & 0xFF;
2011
2012 if (vf && vf <= numvfs)
2013 __rvu_flr_handler(rvu, pcifunc);
2014 else
2015 return RVU_INVALID_VF_ID;
2016
2017 return 0;
2018 }
2019
rvu_ndc_sync(struct rvu * rvu,int lfblkaddr,int lfidx,u64 lfoffset)2020 int rvu_ndc_sync(struct rvu *rvu, int lfblkaddr, int lfidx, u64 lfoffset)
2021 {
2022 /* Sync cached info for this LF in NDC to LLC/DRAM */
2023 rvu_write64(rvu, lfblkaddr, lfoffset, BIT_ULL(12) | lfidx);
2024 return rvu_poll_reg(rvu, lfblkaddr, lfoffset, BIT_ULL(12), true);
2025 }
2026
rvu_mbox_handler_get_hw_cap(struct rvu * rvu,struct msg_req * req,struct get_hw_cap_rsp * rsp)2027 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
2028 struct get_hw_cap_rsp *rsp)
2029 {
2030 struct rvu_hwinfo *hw = rvu->hw;
2031
2032 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
2033 rsp->nix_shaping = hw->cap.nix_shaping;
2034 rsp->npc_hash_extract = hw->cap.npc_hash_extract;
2035
2036 if (rvu->mcs_blk_cnt)
2037 rsp->hw_caps = HW_CAP_MACSEC;
2038
2039 return 0;
2040 }
2041
rvu_mbox_handler_set_vf_perm(struct rvu * rvu,struct set_vf_perm * req,struct msg_rsp * rsp)2042 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
2043 struct msg_rsp *rsp)
2044 {
2045 struct rvu_hwinfo *hw = rvu->hw;
2046 u16 pcifunc = req->hdr.pcifunc;
2047 struct rvu_pfvf *pfvf;
2048 int blkaddr, nixlf;
2049 u16 target;
2050
2051 /* Only PF can add VF permissions */
2052 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_lbk_vf(rvu, pcifunc))
2053 return -EOPNOTSUPP;
2054
2055 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
2056 pfvf = rvu_get_pfvf(rvu, target);
2057
2058 if (req->flags & RESET_VF_PERM) {
2059 pfvf->flags &= RVU_CLEAR_VF_PERM;
2060 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^
2061 (req->flags & VF_TRUSTED)) {
2062 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags);
2063 /* disable multicast and promisc entries */
2064 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) {
2065 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target);
2066 if (blkaddr < 0)
2067 return 0;
2068 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
2069 target, 0);
2070 if (nixlf < 0)
2071 return 0;
2072 npc_enadis_default_mce_entry(rvu, target, nixlf,
2073 NIXLF_ALLMULTI_ENTRY,
2074 false);
2075 npc_enadis_default_mce_entry(rvu, target, nixlf,
2076 NIXLF_PROMISC_ENTRY,
2077 false);
2078 }
2079 }
2080
2081 return 0;
2082 }
2083
rvu_mbox_handler_ndc_sync_op(struct rvu * rvu,struct ndc_sync_op * req,struct msg_rsp * rsp)2084 int rvu_mbox_handler_ndc_sync_op(struct rvu *rvu,
2085 struct ndc_sync_op *req,
2086 struct msg_rsp *rsp)
2087 {
2088 struct rvu_hwinfo *hw = rvu->hw;
2089 u16 pcifunc = req->hdr.pcifunc;
2090 int err, lfidx, lfblkaddr;
2091
2092 if (req->npa_lf_sync) {
2093 /* Get NPA LF data */
2094 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
2095 if (lfblkaddr < 0)
2096 return NPA_AF_ERR_AF_LF_INVALID;
2097
2098 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0);
2099 if (lfidx < 0)
2100 return NPA_AF_ERR_AF_LF_INVALID;
2101
2102 /* Sync NPA NDC */
2103 err = rvu_ndc_sync(rvu, lfblkaddr,
2104 lfidx, NPA_AF_NDC_SYNC);
2105 if (err)
2106 dev_err(rvu->dev,
2107 "NDC-NPA sync failed for LF %u\n", lfidx);
2108 }
2109
2110 if (!req->nix_lf_tx_sync && !req->nix_lf_rx_sync)
2111 return 0;
2112
2113 /* Get NIX LF data */
2114 lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
2115 if (lfblkaddr < 0)
2116 return NIX_AF_ERR_AF_LF_INVALID;
2117
2118 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0);
2119 if (lfidx < 0)
2120 return NIX_AF_ERR_AF_LF_INVALID;
2121
2122 if (req->nix_lf_tx_sync) {
2123 /* Sync NIX TX NDC */
2124 err = rvu_ndc_sync(rvu, lfblkaddr,
2125 lfidx, NIX_AF_NDC_TX_SYNC);
2126 if (err)
2127 dev_err(rvu->dev,
2128 "NDC-NIX-TX sync fail for LF %u\n", lfidx);
2129 }
2130
2131 if (req->nix_lf_rx_sync) {
2132 /* Sync NIX RX NDC */
2133 err = rvu_ndc_sync(rvu, lfblkaddr,
2134 lfidx, NIX_AF_NDC_RX_SYNC);
2135 if (err)
2136 dev_err(rvu->dev,
2137 "NDC-NIX-RX sync failed for LF %u\n", lfidx);
2138 }
2139
2140 return 0;
2141 }
2142
rvu_process_mbox_msg(struct otx2_mbox * mbox,int devid,struct mbox_msghdr * req)2143 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
2144 struct mbox_msghdr *req)
2145 {
2146 struct rvu *rvu = pci_get_drvdata(mbox->pdev);
2147
2148 /* Check if valid, if not reply with a invalid msg */
2149 if (req->sig != OTX2_MBOX_REQ_SIG)
2150 goto bad_message;
2151
2152 switch (req->id) {
2153 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
2154 case _id: { \
2155 struct _rsp_type *rsp; \
2156 int err; \
2157 \
2158 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
2159 mbox, devid, \
2160 sizeof(struct _rsp_type)); \
2161 /* some handlers should complete even if reply */ \
2162 /* could not be allocated */ \
2163 if (!rsp && \
2164 _id != MBOX_MSG_DETACH_RESOURCES && \
2165 _id != MBOX_MSG_NIX_TXSCH_FREE && \
2166 _id != MBOX_MSG_VF_FLR) \
2167 return -ENOMEM; \
2168 if (rsp) { \
2169 rsp->hdr.id = _id; \
2170 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
2171 rsp->hdr.pcifunc = req->pcifunc; \
2172 rsp->hdr.rc = 0; \
2173 } \
2174 \
2175 err = rvu_mbox_handler_ ## _fn_name(rvu, \
2176 (struct _req_type *)req, \
2177 rsp); \
2178 if (rsp && err) \
2179 rsp->hdr.rc = err; \
2180 \
2181 trace_otx2_msg_process(mbox->pdev, _id, err, req->pcifunc); \
2182 return rsp ? err : -ENOMEM; \
2183 }
2184 MBOX_MESSAGES
2185 #undef M
2186
2187 bad_message:
2188 default:
2189 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
2190 return -ENODEV;
2191 }
2192 }
2193
__rvu_mbox_handler(struct rvu_work * mwork,int type,bool poll)2194 static void __rvu_mbox_handler(struct rvu_work *mwork, int type, bool poll)
2195 {
2196 struct rvu *rvu = mwork->rvu;
2197 int offset, err, id, devid;
2198 struct otx2_mbox_dev *mdev;
2199 struct mbox_hdr *req_hdr;
2200 struct mbox_msghdr *msg;
2201 struct mbox_wq_info *mw;
2202 struct otx2_mbox *mbox;
2203
2204 switch (type) {
2205 case TYPE_AFPF:
2206 mw = &rvu->afpf_wq_info;
2207 break;
2208 case TYPE_AFVF:
2209 mw = &rvu->afvf_wq_info;
2210 break;
2211 default:
2212 return;
2213 }
2214
2215 devid = mwork - mw->mbox_wrk;
2216 mbox = &mw->mbox;
2217 mdev = &mbox->dev[devid];
2218
2219 /* Process received mbox messages */
2220 req_hdr = mdev->mbase + mbox->rx_start;
2221 if (mw->mbox_wrk[devid].num_msgs == 0)
2222 return;
2223
2224 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
2225
2226 if (req_hdr->sig && !(is_rvu_otx2(rvu) || is_cn20k(rvu->pdev))) {
2227 req_hdr->opt_msg = mw->mbox_wrk[devid].num_msgs;
2228 rvu_write64(rvu, BLKADDR_NIX0, RVU_AF_BAR2_SEL,
2229 RVU_AF_BAR2_PFID);
2230 if (type == TYPE_AFPF)
2231 rvu_write64(rvu, BLKADDR_NIX0,
2232 AF_BAR2_ALIASX(0, NIX_CINTX_INT_W1S(devid)),
2233 0x1);
2234 else
2235 rvu_write64(rvu, BLKADDR_NIX0,
2236 AF_BAR2_ALIASX(0, NIX_QINTX_CNT(devid)),
2237 0x1);
2238 usleep_range(5000, 6000);
2239 goto done;
2240 }
2241
2242 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
2243 msg = mdev->mbase + offset;
2244
2245 /* Set which PF/VF sent this message based on mbox IRQ */
2246 switch (type) {
2247 case TYPE_AFPF:
2248 msg->pcifunc &= rvu_pcifunc_pf_mask(rvu->pdev);
2249 msg->pcifunc |= rvu_make_pcifunc(rvu->pdev, devid, 0);
2250 break;
2251 case TYPE_AFVF:
2252 msg->pcifunc &=
2253 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
2254 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
2255 break;
2256 }
2257
2258 err = rvu_process_mbox_msg(mbox, devid, msg);
2259 if (!err) {
2260 offset = mbox->rx_start + msg->next_msgoff;
2261 continue;
2262 }
2263
2264 if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
2265 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
2266 err, otx2_mbox_id2name(msg->id),
2267 msg->id, rvu_get_pf(rvu->pdev, msg->pcifunc),
2268 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
2269 else
2270 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
2271 err, otx2_mbox_id2name(msg->id),
2272 msg->id, devid);
2273 }
2274 done:
2275 mw->mbox_wrk[devid].num_msgs = 0;
2276
2277 if (!is_cn20k(mbox->pdev) && poll)
2278 otx2_mbox_wait_for_zero(mbox, devid);
2279
2280 /* Send mbox responses to VF/PF */
2281 otx2_mbox_msg_send(mbox, devid);
2282 }
2283
rvu_afpf_mbox_handler(struct work_struct * work)2284 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
2285 {
2286 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2287 struct rvu *rvu = mwork->rvu;
2288
2289 mutex_lock(&rvu->mbox_lock);
2290 __rvu_mbox_handler(mwork, TYPE_AFPF, true);
2291 mutex_unlock(&rvu->mbox_lock);
2292 }
2293
rvu_afvf_mbox_handler(struct work_struct * work)2294 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
2295 {
2296 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2297
2298 __rvu_mbox_handler(mwork, TYPE_AFVF, false);
2299 }
2300
__rvu_mbox_up_handler(struct rvu_work * mwork,int type)2301 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
2302 {
2303 struct rvu *rvu = mwork->rvu;
2304 struct otx2_mbox_dev *mdev;
2305 struct mbox_hdr *rsp_hdr;
2306 struct mbox_msghdr *msg;
2307 struct mbox_wq_info *mw;
2308 struct otx2_mbox *mbox;
2309 int offset, id, devid;
2310
2311 switch (type) {
2312 case TYPE_AFPF:
2313 mw = &rvu->afpf_wq_info;
2314 break;
2315 case TYPE_AFVF:
2316 mw = &rvu->afvf_wq_info;
2317 break;
2318 default:
2319 return;
2320 }
2321
2322 devid = mwork - mw->mbox_wrk_up;
2323 mbox = &mw->mbox_up;
2324 mdev = &mbox->dev[devid];
2325
2326 rsp_hdr = mdev->mbase + mbox->rx_start;
2327 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
2328 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
2329 return;
2330 }
2331
2332 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
2333
2334 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
2335 msg = mdev->mbase + offset;
2336
2337 if (msg->id >= MBOX_MSG_MAX) {
2338 dev_err(rvu->dev,
2339 "Mbox msg with unknown ID 0x%x\n", msg->id);
2340 goto end;
2341 }
2342
2343 if (msg->sig != OTX2_MBOX_RSP_SIG) {
2344 dev_err(rvu->dev,
2345 "Mbox msg with wrong signature %x, ID 0x%x\n",
2346 msg->sig, msg->id);
2347 goto end;
2348 }
2349
2350 switch (msg->id) {
2351 case MBOX_MSG_CGX_LINK_EVENT:
2352 break;
2353 default:
2354 if (msg->rc)
2355 dev_err(rvu->dev,
2356 "Mbox msg response has err %d, ID 0x%x\n",
2357 msg->rc, msg->id);
2358 break;
2359 }
2360 end:
2361 offset = mbox->rx_start + msg->next_msgoff;
2362 mdev->msgs_acked++;
2363 }
2364 mw->mbox_wrk_up[devid].up_num_msgs = 0;
2365
2366 otx2_mbox_reset(mbox, devid);
2367 }
2368
rvu_afpf_mbox_up_handler(struct work_struct * work)2369 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
2370 {
2371 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2372
2373 __rvu_mbox_up_handler(mwork, TYPE_AFPF);
2374 }
2375
rvu_afvf_mbox_up_handler(struct work_struct * work)2376 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
2377 {
2378 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2379
2380 __rvu_mbox_up_handler(mwork, TYPE_AFVF);
2381 }
2382
rvu_get_mbox_regions(struct rvu * rvu,void __iomem ** mbox_addr,int num,int type,unsigned long * pf_bmap)2383 static int rvu_get_mbox_regions(struct rvu *rvu, void __iomem **mbox_addr,
2384 int num, int type, unsigned long *pf_bmap)
2385 {
2386 struct rvu_hwinfo *hw = rvu->hw;
2387 int region;
2388 u64 bar4;
2389
2390 /* For cn20k platform AF mailbox region is allocated by software
2391 * and the corresponding IOVA is programmed in hardware unlike earlier
2392 * silicons where software uses the hardware region after ioremap.
2393 */
2394 if (is_cn20k(rvu->pdev))
2395 return cn20k_rvu_get_mbox_regions(rvu, (void *)mbox_addr,
2396 num, type, pf_bmap);
2397
2398 /* For cn10k platform VF mailbox regions of a PF follows after the
2399 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from
2400 * RVU_PF_VF_BAR4_ADDR register.
2401 */
2402 if (type == TYPE_AFVF) {
2403 for (region = 0; region < num; region++) {
2404 if (!test_bit(region, pf_bmap))
2405 continue;
2406
2407 if (hw->cap.per_pf_mbox_regs) {
2408 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2409 RVU_AF_PFX_BAR4_ADDR(0)) +
2410 MBOX_SIZE;
2411 bar4 += region * MBOX_SIZE;
2412 } else {
2413 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
2414 bar4 += region * MBOX_SIZE;
2415 }
2416 mbox_addr[region] = ioremap_wc(bar4, MBOX_SIZE);
2417 if (!mbox_addr[region])
2418 goto error;
2419 }
2420 return 0;
2421 }
2422
2423 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per
2424 * PF registers. Whereas for Octeontx2 it is read from
2425 * RVU_AF_PF_BAR4_ADDR register.
2426 */
2427 for (region = 0; region < num; region++) {
2428 if (!test_bit(region, pf_bmap))
2429 continue;
2430
2431 if (hw->cap.per_pf_mbox_regs) {
2432 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2433 RVU_AF_PFX_BAR4_ADDR(region));
2434 } else {
2435 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2436 RVU_AF_PF_BAR4_ADDR);
2437 bar4 += region * MBOX_SIZE;
2438 }
2439 mbox_addr[region] = ioremap_wc(bar4, MBOX_SIZE);
2440 if (!mbox_addr[region])
2441 goto error;
2442 }
2443 return 0;
2444
2445 error:
2446 while (region--)
2447 iounmap(mbox_addr[region]);
2448 return -ENOMEM;
2449 }
2450
2451 static struct mbox_ops rvu_mbox_ops = {
2452 .pf_intr_handler = rvu_mbox_pf_intr_handler,
2453 .afvf_intr_handler = rvu_mbox_intr_handler,
2454 };
2455
rvu_mbox_init(struct rvu * rvu,struct mbox_wq_info * mw,int type,int num,void (mbox_handler)(struct work_struct *),void (mbox_up_handler)(struct work_struct *))2456 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2457 int type, int num,
2458 void (mbox_handler)(struct work_struct *),
2459 void (mbox_up_handler)(struct work_struct *))
2460 {
2461 void __iomem **mbox_regions;
2462 struct ng_rvu *ng_rvu_mbox;
2463 int err, i, dir, dir_up;
2464 void __iomem *reg_base;
2465 struct rvu_work *mwork;
2466 unsigned long *pf_bmap;
2467 const char *name;
2468 u64 cfg;
2469
2470 pf_bmap = bitmap_zalloc(num, GFP_KERNEL);
2471 if (!pf_bmap)
2472 return -ENOMEM;
2473
2474 ng_rvu_mbox = kzalloc(sizeof(*ng_rvu_mbox), GFP_KERNEL);
2475 if (!ng_rvu_mbox) {
2476 err = -ENOMEM;
2477 goto free_bitmap;
2478 }
2479
2480 /* RVU VFs */
2481 if (type == TYPE_AFVF)
2482 bitmap_set(pf_bmap, 0, num);
2483
2484 if (type == TYPE_AFPF) {
2485 /* Mark enabled PFs in bitmap */
2486 for (i = 0; i < num; i++) {
2487 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i));
2488 if (cfg & BIT_ULL(20))
2489 set_bit(i, pf_bmap);
2490 }
2491 }
2492
2493 rvu->ng_rvu = ng_rvu_mbox;
2494
2495 rvu->ng_rvu->rvu_mbox_ops = &rvu_mbox_ops;
2496
2497 err = cn20k_rvu_mbox_init(rvu, type, num);
2498 if (err)
2499 goto free_mem;
2500
2501 mutex_init(&rvu->mbox_lock);
2502
2503 mbox_regions = kcalloc(num, sizeof(void __iomem *), GFP_KERNEL);
2504 if (!mbox_regions) {
2505 err = -ENOMEM;
2506 goto free_qmem;
2507 }
2508
2509 switch (type) {
2510 case TYPE_AFPF:
2511 name = "rvu_afpf_mailbox";
2512 dir = MBOX_DIR_AFPF;
2513 dir_up = MBOX_DIR_AFPF_UP;
2514 reg_base = rvu->afreg_base;
2515 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap);
2516 if (err)
2517 goto free_regions;
2518 break;
2519 case TYPE_AFVF:
2520 name = "rvu_afvf_mailbox";
2521 dir = MBOX_DIR_PFVF;
2522 dir_up = MBOX_DIR_PFVF_UP;
2523 reg_base = rvu->pfreg_base;
2524 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap);
2525 if (err)
2526 goto free_regions;
2527 break;
2528 default:
2529 err = -EINVAL;
2530 goto free_regions;
2531 }
2532
2533 mw->mbox_wq = alloc_workqueue("%s",
2534 WQ_HIGHPRI | WQ_MEM_RECLAIM,
2535 num, name);
2536 if (!mw->mbox_wq) {
2537 err = -ENOMEM;
2538 goto unmap_regions;
2539 }
2540
2541 mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
2542 sizeof(struct rvu_work), GFP_KERNEL);
2543 if (!mw->mbox_wrk) {
2544 err = -ENOMEM;
2545 goto exit;
2546 }
2547
2548 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
2549 sizeof(struct rvu_work), GFP_KERNEL);
2550 if (!mw->mbox_wrk_up) {
2551 err = -ENOMEM;
2552 goto exit;
2553 }
2554
2555 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev,
2556 reg_base, dir, num, pf_bmap);
2557 if (err)
2558 goto exit;
2559
2560 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev,
2561 reg_base, dir_up, num, pf_bmap);
2562 if (err)
2563 goto exit;
2564
2565 for (i = 0; i < num; i++) {
2566 if (!test_bit(i, pf_bmap))
2567 continue;
2568
2569 mwork = &mw->mbox_wrk[i];
2570 mwork->rvu = rvu;
2571 INIT_WORK(&mwork->work, mbox_handler);
2572
2573 mwork = &mw->mbox_wrk_up[i];
2574 mwork->rvu = rvu;
2575 INIT_WORK(&mwork->work, mbox_up_handler);
2576 }
2577
2578 kfree(mbox_regions);
2579 bitmap_free(pf_bmap);
2580
2581 return 0;
2582
2583 exit:
2584 destroy_workqueue(mw->mbox_wq);
2585 unmap_regions:
2586 while (num--)
2587 iounmap((void __iomem *)mbox_regions[num]);
2588 free_regions:
2589 kfree(mbox_regions);
2590 free_qmem:
2591 cn20k_free_mbox_memory(rvu);
2592 free_mem:
2593 kfree(rvu->ng_rvu);
2594 free_bitmap:
2595 bitmap_free(pf_bmap);
2596 return err;
2597 }
2598
rvu_mbox_destroy(struct mbox_wq_info * mw)2599 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
2600 {
2601 struct otx2_mbox *mbox = &mw->mbox;
2602 struct otx2_mbox_dev *mdev;
2603 int devid;
2604
2605 if (mw->mbox_wq) {
2606 destroy_workqueue(mw->mbox_wq);
2607 mw->mbox_wq = NULL;
2608 }
2609
2610 for (devid = 0; devid < mbox->ndevs; devid++) {
2611 mdev = &mbox->dev[devid];
2612 if (mdev->hwbase)
2613 iounmap((void __iomem *)mdev->hwbase);
2614 }
2615
2616 otx2_mbox_destroy(&mw->mbox);
2617 otx2_mbox_destroy(&mw->mbox_up);
2618 }
2619
rvu_queue_work(struct mbox_wq_info * mw,int first,int mdevs,u64 intr)2620 void rvu_queue_work(struct mbox_wq_info *mw, int first,
2621 int mdevs, u64 intr)
2622 {
2623 struct otx2_mbox_dev *mdev;
2624 struct otx2_mbox *mbox;
2625 struct mbox_hdr *hdr;
2626 int i;
2627
2628 for (i = first; i < mdevs; i++) {
2629 /* start from 0 */
2630 if (!(intr & BIT_ULL(i - first)))
2631 continue;
2632
2633 mbox = &mw->mbox;
2634 mdev = &mbox->dev[i];
2635 hdr = mdev->mbase + mbox->rx_start;
2636
2637 /*The hdr->num_msgs is set to zero immediately in the interrupt
2638 * handler to ensure that it holds a correct value next time
2639 * when the interrupt handler is called.
2640 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
2641 * pf>mbox.up_num_msgs holds the data for use in
2642 * pfaf_mbox_up_handler.
2643 */
2644
2645 if (hdr->num_msgs) {
2646 mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
2647 hdr->num_msgs = 0;
2648 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
2649 }
2650 mbox = &mw->mbox_up;
2651 mdev = &mbox->dev[i];
2652 hdr = mdev->mbase + mbox->rx_start;
2653 if (hdr->num_msgs) {
2654 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
2655 hdr->num_msgs = 0;
2656 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
2657 }
2658 }
2659 }
2660
rvu_mbox_pf_intr_handler(int irq,void * rvu_irq)2661 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq)
2662 {
2663 struct rvu *rvu = (struct rvu *)rvu_irq;
2664 u64 intr;
2665
2666 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
2667 /* Clear interrupts */
2668 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
2669 if (intr)
2670 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
2671
2672 /* Sync with mbox memory region */
2673 rmb();
2674
2675 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
2676
2677 return IRQ_HANDLED;
2678 }
2679
rvu_mbox_intr_handler(int irq,void * rvu_irq)2680 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
2681 {
2682 struct rvu *rvu = (struct rvu *)rvu_irq;
2683 int vfs = rvu->vfs;
2684 u64 intr;
2685
2686 /* Sync with mbox memory region */
2687 rmb();
2688
2689 /* Handle VF interrupts */
2690 if (vfs > 64) {
2691 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
2692 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
2693
2694 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
2695 vfs = 64;
2696 }
2697
2698 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
2699 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
2700 if (intr)
2701 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
2702
2703 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
2704
2705 return IRQ_HANDLED;
2706 }
2707
rvu_enable_mbox_intr(struct rvu * rvu)2708 static void rvu_enable_mbox_intr(struct rvu *rvu)
2709 {
2710 struct rvu_hwinfo *hw = rvu->hw;
2711
2712 if (is_cn20k(rvu->pdev)) {
2713 cn20k_rvu_enable_mbox_intr(rvu);
2714 return;
2715 }
2716
2717 /* Clear spurious irqs, if any */
2718 rvu_write64(rvu, BLKADDR_RVUM,
2719 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
2720
2721 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
2722 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
2723 INTR_MASK(hw->total_pfs) & ~1ULL);
2724 }
2725
rvu_blklf_teardown(struct rvu * rvu,u16 pcifunc,u8 blkaddr)2726 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
2727 {
2728 struct rvu_block *block;
2729 int slot, lf, num_lfs;
2730 int err;
2731
2732 block = &rvu->hw->block[blkaddr];
2733 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
2734 block->addr);
2735 if (!num_lfs)
2736 return;
2737 for (slot = 0; slot < num_lfs; slot++) {
2738 lf = rvu_get_lf(rvu, block, pcifunc, slot);
2739 if (lf < 0)
2740 continue;
2741
2742 /* Cleanup LF and reset it */
2743 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1)
2744 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
2745 else if (block->addr == BLKADDR_NPA)
2746 rvu_npa_lf_teardown(rvu, pcifunc, lf);
2747 else if ((block->addr == BLKADDR_CPT0) ||
2748 (block->addr == BLKADDR_CPT1))
2749 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf,
2750 slot);
2751
2752 err = rvu_lf_reset(rvu, block, lf);
2753 if (err) {
2754 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
2755 block->addr, lf);
2756 }
2757 }
2758 }
2759
__rvu_flr_handler(struct rvu * rvu,u16 pcifunc)2760 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
2761 {
2762 if (rvu_npc_exact_has_match_table(rvu))
2763 rvu_npc_exact_reset(rvu, pcifunc);
2764
2765 mutex_lock(&rvu->flr_lock);
2766 /* Reset order should reflect inter-block dependencies:
2767 * 1. Reset any packet/work sources (NIX, CPT, TIM)
2768 * 2. Flush and reset SSO/SSOW
2769 * 3. Cleanup pools (NPA)
2770 */
2771
2772 /* Free allocated BPIDs */
2773 rvu_nix_flr_free_bpids(rvu, pcifunc);
2774
2775 /* Free multicast/mirror node associated with the 'pcifunc' */
2776 rvu_nix_mcast_flr_free_entries(rvu, pcifunc);
2777
2778 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
2779 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);
2780 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
2781 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1);
2782 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
2783 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2784 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2785 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2786 rvu_reset_lmt_map_tbl(rvu, pcifunc);
2787 rvu_detach_rsrcs(rvu, NULL, pcifunc);
2788 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM
2789 * entries, check and free the MCAM entries explicitly to avoid leak.
2790 * Since LF is detached use LF number as -1.
2791 */
2792 rvu_npc_free_mcam_entries(rvu, pcifunc, -1);
2793 rvu_mac_reset(rvu, pcifunc);
2794
2795 if (rvu->mcs_blk_cnt)
2796 rvu_mcs_flr_handler(rvu, pcifunc);
2797
2798 mutex_unlock(&rvu->flr_lock);
2799 }
2800
rvu_afvf_flr_handler(struct rvu * rvu,int vf)2801 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
2802 {
2803 int reg = 0;
2804
2805 /* pcifunc = 0(PF0) | (vf + 1) */
2806 __rvu_flr_handler(rvu, vf + 1);
2807
2808 if (vf >= 64) {
2809 reg = 1;
2810 vf = vf - 64;
2811 }
2812
2813 /* Signal FLR finish and enable IRQ */
2814 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
2815 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
2816 }
2817
rvu_flr_handler(struct work_struct * work)2818 static void rvu_flr_handler(struct work_struct *work)
2819 {
2820 struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
2821 struct rvu *rvu = flrwork->rvu;
2822 u16 pcifunc, numvfs, vf;
2823 u64 cfg;
2824 int pf;
2825
2826 pf = flrwork - rvu->flr_wrk;
2827 if (pf >= rvu->hw->total_pfs) {
2828 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2829 return;
2830 }
2831
2832 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2833 numvfs = (cfg >> 12) & 0xFF;
2834 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0);
2835
2836 for (vf = 0; vf < numvfs; vf++)
2837 __rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2838
2839 __rvu_flr_handler(rvu, pcifunc);
2840
2841 /* Signal FLR finish */
2842 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2843
2844 /* Enable interrupt */
2845 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf));
2846 }
2847
rvu_afvf_queue_flr_work(struct rvu * rvu,int start_vf,int numvfs)2848 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2849 {
2850 int dev, vf, reg = 0;
2851 u64 intr;
2852
2853 if (start_vf >= 64)
2854 reg = 1;
2855
2856 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2857 if (!intr)
2858 return;
2859
2860 for (vf = 0; vf < numvfs; vf++) {
2861 if (!(intr & BIT_ULL(vf)))
2862 continue;
2863 /* Clear and disable the interrupt */
2864 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2865 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2866
2867 dev = vf + start_vf + rvu->hw->total_pfs;
2868 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2869 }
2870 }
2871
rvu_flr_intr_handler(int irq,void * rvu_irq)2872 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2873 {
2874 struct rvu *rvu = (struct rvu *)rvu_irq;
2875 u64 intr;
2876 u8 pf;
2877
2878 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2879 if (!intr)
2880 goto afvf_flr;
2881
2882 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2883 if (intr & (1ULL << pf)) {
2884 /* clear interrupt */
2885 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2886 BIT_ULL(pf));
2887 /* Disable the interrupt */
2888 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2889 BIT_ULL(pf));
2890 /* PF is already dead do only AF related operations */
2891 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2892 }
2893 }
2894
2895 afvf_flr:
2896 rvu_afvf_queue_flr_work(rvu, 0, 64);
2897 if (rvu->vfs > 64)
2898 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2899
2900 return IRQ_HANDLED;
2901 }
2902
rvu_me_handle_vfset(struct rvu * rvu,int idx,u64 intr)2903 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2904 {
2905 int vf;
2906
2907 /* Nothing to be done here other than clearing the
2908 * TRPEND bit.
2909 */
2910 for (vf = 0; vf < 64; vf++) {
2911 if (intr & (1ULL << vf)) {
2912 /* clear the trpend due to ME(master enable) */
2913 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2914 /* clear interrupt */
2915 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2916 }
2917 }
2918 }
2919
2920 /* Handles ME interrupts from VFs of AF */
rvu_me_vf_intr_handler(int irq,void * rvu_irq)2921 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2922 {
2923 struct rvu *rvu = (struct rvu *)rvu_irq;
2924 int vfset;
2925 u64 intr;
2926
2927 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2928
2929 for (vfset = 0; vfset <= 1; vfset++) {
2930 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2931 if (intr)
2932 rvu_me_handle_vfset(rvu, vfset, intr);
2933 }
2934
2935 return IRQ_HANDLED;
2936 }
2937
2938 /* Handles ME interrupts from PFs */
rvu_me_pf_intr_handler(int irq,void * rvu_irq)2939 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2940 {
2941 struct rvu *rvu = (struct rvu *)rvu_irq;
2942 u64 intr;
2943 u8 pf;
2944
2945 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2946
2947 /* Nothing to be done here other than clearing the
2948 * TRPEND bit.
2949 */
2950 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2951 if (intr & (1ULL << pf)) {
2952 /* clear the trpend due to ME(master enable) */
2953 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2954 BIT_ULL(pf));
2955 /* clear interrupt */
2956 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2957 BIT_ULL(pf));
2958 }
2959 }
2960
2961 return IRQ_HANDLED;
2962 }
2963
rvu_unregister_interrupts(struct rvu * rvu)2964 static void rvu_unregister_interrupts(struct rvu *rvu)
2965 {
2966 int irq;
2967
2968 rvu_cpt_unregister_interrupts(rvu);
2969
2970 if (!is_cn20k(rvu->pdev))
2971 /* Disable the Mbox interrupt */
2972 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2973 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2974 else
2975 cn20k_rvu_unregister_interrupts(rvu);
2976
2977 /* Disable the PF FLR interrupt */
2978 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2979 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2980
2981 /* Disable the PF ME interrupt */
2982 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2983 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2984
2985 for (irq = 0; irq < rvu->num_vec; irq++) {
2986 if (rvu->irq_allocated[irq]) {
2987 free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2988 rvu->irq_allocated[irq] = false;
2989 }
2990 }
2991
2992 pci_free_irq_vectors(rvu->pdev);
2993 rvu->num_vec = 0;
2994 }
2995
rvu_afvf_msix_vectors_num_ok(struct rvu * rvu)2996 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2997 {
2998 struct rvu_pfvf *pfvf = &rvu->pf[0];
2999 int offset;
3000
3001 pfvf = &rvu->pf[0];
3002 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
3003
3004 /* Make sure there are enough MSIX vectors configured so that
3005 * VF interrupts can be handled. Offset equal to zero means
3006 * that PF vectors are not configured and overlapping AF vectors.
3007 */
3008 if (is_cn20k(rvu->pdev))
3009 return (pfvf->msix.max >= RVU_AF_CN20K_INT_VEC_CNT +
3010 RVU_MBOX_PF_INT_VEC_CNT) && offset;
3011
3012 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
3013 offset;
3014 }
3015
rvu_register_interrupts(struct rvu * rvu)3016 static int rvu_register_interrupts(struct rvu *rvu)
3017 {
3018 int ret, offset, pf_vec_start;
3019
3020 rvu->num_vec = pci_msix_vec_count(rvu->pdev);
3021
3022 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
3023 NAME_SIZE, GFP_KERNEL);
3024 if (!rvu->irq_name)
3025 return -ENOMEM;
3026
3027 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
3028 sizeof(bool), GFP_KERNEL);
3029 if (!rvu->irq_allocated)
3030 return -ENOMEM;
3031
3032 /* Enable MSI-X */
3033 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
3034 rvu->num_vec, PCI_IRQ_MSIX);
3035 if (ret < 0) {
3036 dev_err(rvu->dev,
3037 "RVUAF: Request for %d msix vectors failed, ret %d\n",
3038 rvu->num_vec, ret);
3039 return ret;
3040 }
3041
3042 if (!is_cn20k(rvu->pdev)) {
3043 /* Register mailbox interrupt handler */
3044 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE],
3045 "RVUAF Mbox");
3046 ret = request_irq(pci_irq_vector
3047 (rvu->pdev, RVU_AF_INT_VEC_MBOX),
3048 rvu->ng_rvu->rvu_mbox_ops->pf_intr_handler, 0,
3049 &rvu->irq_name[RVU_AF_INT_VEC_MBOX *
3050 NAME_SIZE], rvu);
3051 if (ret) {
3052 dev_err(rvu->dev,
3053 "RVUAF: IRQ registration failed for mbox\n");
3054 goto fail;
3055 }
3056
3057 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
3058 } else {
3059 ret = cn20k_register_afpf_mbox_intr(rvu);
3060 if (ret) {
3061 dev_err(rvu->dev,
3062 "RVUAF: IRQ registration failed for mbox\n");
3063 goto fail;
3064 }
3065 }
3066
3067 /* Enable mailbox interrupts from all PFs */
3068 rvu_enable_mbox_intr(rvu);
3069
3070 /* Register FLR interrupt handler */
3071 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
3072 "RVUAF FLR");
3073 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
3074 rvu_flr_intr_handler, 0,
3075 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
3076 rvu);
3077 if (ret) {
3078 dev_err(rvu->dev,
3079 "RVUAF: IRQ registration failed for FLR\n");
3080 goto fail;
3081 }
3082 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
3083
3084 /* Enable FLR interrupt for all PFs*/
3085 rvu_write64(rvu, BLKADDR_RVUM,
3086 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
3087
3088 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
3089 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
3090
3091 /* Register ME interrupt handler */
3092 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
3093 "RVUAF ME");
3094 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
3095 rvu_me_pf_intr_handler, 0,
3096 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
3097 rvu);
3098 if (ret) {
3099 dev_err(rvu->dev,
3100 "RVUAF: IRQ registration failed for ME\n");
3101 }
3102 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
3103
3104 /* Clear TRPEND bit for all PF */
3105 rvu_write64(rvu, BLKADDR_RVUM,
3106 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
3107 /* Enable ME interrupt for all PFs*/
3108 rvu_write64(rvu, BLKADDR_RVUM,
3109 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
3110
3111 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
3112 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
3113
3114 if (!rvu_afvf_msix_vectors_num_ok(rvu))
3115 return 0;
3116
3117 /* Get PF MSIX vectors offset. */
3118 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
3119 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
3120 if (!is_cn20k(rvu->pdev)) {
3121 /* Register MBOX0 interrupt. */
3122 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
3123 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
3124 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3125 rvu->ng_rvu->rvu_mbox_ops->afvf_intr_handler, 0,
3126 &rvu->irq_name[offset * NAME_SIZE],
3127 rvu);
3128 if (ret)
3129 dev_err(rvu->dev,
3130 "RVUAF: IRQ registration failed for Mbox0\n");
3131
3132 rvu->irq_allocated[offset] = true;
3133
3134 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
3135 * simply increment current offset by 1.
3136 */
3137 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
3138 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
3139 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3140 rvu->ng_rvu->rvu_mbox_ops->afvf_intr_handler, 0,
3141 &rvu->irq_name[offset * NAME_SIZE],
3142 rvu);
3143 if (ret)
3144 dev_err(rvu->dev,
3145 "RVUAF: IRQ registration failed for Mbox1\n");
3146
3147 rvu->irq_allocated[offset] = true;
3148 } else {
3149 ret = cn20k_register_afvf_mbox_intr(rvu, pf_vec_start);
3150 if (ret)
3151 dev_err(rvu->dev,
3152 "RVUAF: IRQ registration failed for Mbox\n");
3153 }
3154
3155 /* Register FLR interrupt handler for AF's VFs */
3156 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
3157 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
3158 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3159 rvu_flr_intr_handler, 0,
3160 &rvu->irq_name[offset * NAME_SIZE], rvu);
3161 if (ret) {
3162 dev_err(rvu->dev,
3163 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
3164 goto fail;
3165 }
3166 rvu->irq_allocated[offset] = true;
3167
3168 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
3169 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
3170 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3171 rvu_flr_intr_handler, 0,
3172 &rvu->irq_name[offset * NAME_SIZE], rvu);
3173 if (ret) {
3174 dev_err(rvu->dev,
3175 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
3176 goto fail;
3177 }
3178 rvu->irq_allocated[offset] = true;
3179
3180 /* Register ME interrupt handler for AF's VFs */
3181 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
3182 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
3183 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3184 rvu_me_vf_intr_handler, 0,
3185 &rvu->irq_name[offset * NAME_SIZE], rvu);
3186 if (ret) {
3187 dev_err(rvu->dev,
3188 "RVUAF: IRQ registration failed for RVUAFVF ME0\n");
3189 goto fail;
3190 }
3191 rvu->irq_allocated[offset] = true;
3192
3193 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
3194 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
3195 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3196 rvu_me_vf_intr_handler, 0,
3197 &rvu->irq_name[offset * NAME_SIZE], rvu);
3198 if (ret) {
3199 dev_err(rvu->dev,
3200 "RVUAF: IRQ registration failed for RVUAFVF ME1\n");
3201 goto fail;
3202 }
3203 rvu->irq_allocated[offset] = true;
3204
3205 ret = rvu_cpt_register_interrupts(rvu);
3206 if (ret)
3207 goto fail;
3208
3209 return 0;
3210
3211 fail:
3212 rvu_unregister_interrupts(rvu);
3213 return ret;
3214 }
3215
rvu_flr_wq_destroy(struct rvu * rvu)3216 static void rvu_flr_wq_destroy(struct rvu *rvu)
3217 {
3218 if (rvu->flr_wq) {
3219 destroy_workqueue(rvu->flr_wq);
3220 rvu->flr_wq = NULL;
3221 }
3222 }
3223
rvu_flr_init(struct rvu * rvu)3224 static int rvu_flr_init(struct rvu *rvu)
3225 {
3226 int dev, num_devs;
3227 u64 cfg;
3228 int pf;
3229
3230 /* Enable FLR for all PFs*/
3231 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
3232 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
3233 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
3234 cfg | BIT_ULL(22));
3235 }
3236
3237 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr",
3238 WQ_HIGHPRI | WQ_MEM_RECLAIM);
3239 if (!rvu->flr_wq)
3240 return -ENOMEM;
3241
3242 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
3243 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
3244 sizeof(struct rvu_work), GFP_KERNEL);
3245 if (!rvu->flr_wrk) {
3246 destroy_workqueue(rvu->flr_wq);
3247 return -ENOMEM;
3248 }
3249
3250 for (dev = 0; dev < num_devs; dev++) {
3251 rvu->flr_wrk[dev].rvu = rvu;
3252 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
3253 }
3254
3255 mutex_init(&rvu->flr_lock);
3256
3257 return 0;
3258 }
3259
rvu_disable_afvf_intr(struct rvu * rvu)3260 static void rvu_disable_afvf_intr(struct rvu *rvu)
3261 {
3262 int vfs = rvu->vfs;
3263
3264 if (is_cn20k(rvu->pdev))
3265 return cn20k_rvu_disable_afvf_intr(rvu, vfs);
3266
3267 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
3268 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
3269 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
3270 if (vfs <= 64)
3271 return;
3272
3273 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
3274 INTR_MASK(vfs - 64));
3275 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3276 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3277 }
3278
rvu_enable_afvf_intr(struct rvu * rvu)3279 static void rvu_enable_afvf_intr(struct rvu *rvu)
3280 {
3281 int vfs = rvu->vfs;
3282
3283 if (is_cn20k(rvu->pdev))
3284 return cn20k_rvu_enable_afvf_intr(rvu, vfs);
3285
3286 /* Clear any pending interrupts and enable AF VF interrupts for
3287 * the first 64 VFs.
3288 */
3289 /* Mbox */
3290 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
3291 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
3292
3293 /* FLR */
3294 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
3295 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
3296 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
3297
3298 /* Same for remaining VFs, if any. */
3299 if (vfs <= 64)
3300 return;
3301
3302 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
3303 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
3304 INTR_MASK(vfs - 64));
3305
3306 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
3307 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3308 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3309 }
3310
rvu_get_num_lbk_chans(void)3311 int rvu_get_num_lbk_chans(void)
3312 {
3313 struct pci_dev *pdev;
3314 void __iomem *base;
3315 int ret = -EIO;
3316
3317 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
3318 NULL);
3319 if (!pdev)
3320 goto err;
3321
3322 base = pci_ioremap_bar(pdev, 0);
3323 if (!base)
3324 goto err_put;
3325
3326 /* Read number of available LBK channels from LBK(0)_CONST register. */
3327 ret = (readq(base + 0x10) >> 32) & 0xffff;
3328 iounmap(base);
3329 err_put:
3330 pci_dev_put(pdev);
3331 err:
3332 return ret;
3333 }
3334
rvu_enable_sriov(struct rvu * rvu)3335 static int rvu_enable_sriov(struct rvu *rvu)
3336 {
3337 struct pci_dev *pdev = rvu->pdev;
3338 int err, chans, vfs;
3339 int pos = 0;
3340
3341 if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
3342 dev_warn(&pdev->dev,
3343 "Skipping SRIOV enablement since not enough IRQs are available\n");
3344 return 0;
3345 }
3346
3347 /* Get RVU VFs device id */
3348 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
3349 if (!pos)
3350 return 0;
3351 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &rvu->vf_devid);
3352
3353 chans = rvu_get_num_lbk_chans();
3354 if (chans < 0)
3355 return chans;
3356
3357 vfs = pci_sriov_get_totalvfs(pdev);
3358
3359 /* Limit VFs in case we have more VFs than LBK channels available. */
3360 if (vfs > chans)
3361 vfs = chans;
3362
3363 if (!vfs)
3364 return 0;
3365
3366 /* LBK channel number 63 is used for switching packets between
3367 * CGX mapped VFs. Hence limit LBK pairs till 62 only.
3368 */
3369 if (vfs > 62)
3370 vfs = 62;
3371
3372 /* Save VFs number for reference in VF interrupts handlers.
3373 * Since interrupts might start arriving during SRIOV enablement
3374 * ordinary API cannot be used to get number of enabled VFs.
3375 */
3376 rvu->vfs = vfs;
3377
3378 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
3379 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
3380 if (err)
3381 return err;
3382
3383 rvu_enable_afvf_intr(rvu);
3384 /* Make sure IRQs are enabled before SRIOV. */
3385 mb();
3386
3387 err = pci_enable_sriov(pdev, vfs);
3388 if (err) {
3389 rvu_disable_afvf_intr(rvu);
3390 rvu_mbox_destroy(&rvu->afvf_wq_info);
3391 return err;
3392 }
3393
3394 return 0;
3395 }
3396
rvu_disable_sriov(struct rvu * rvu)3397 static void rvu_disable_sriov(struct rvu *rvu)
3398 {
3399 rvu_disable_afvf_intr(rvu);
3400 rvu_mbox_destroy(&rvu->afvf_wq_info);
3401 pci_disable_sriov(rvu->pdev);
3402 }
3403
rvu_update_module_params(struct rvu * rvu)3404 static void rvu_update_module_params(struct rvu *rvu)
3405 {
3406 const char *default_pfl_name = "default";
3407
3408 strscpy(rvu->mkex_pfl_name,
3409 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
3410 strscpy(rvu->kpu_pfl_name,
3411 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN);
3412 }
3413
rvu_probe(struct pci_dev * pdev,const struct pci_device_id * id)3414 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3415 {
3416 struct device *dev = &pdev->dev;
3417 struct rvu *rvu;
3418 int err;
3419
3420 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
3421 if (!rvu)
3422 return -ENOMEM;
3423
3424 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
3425 if (!rvu->hw) {
3426 devm_kfree(dev, rvu);
3427 return -ENOMEM;
3428 }
3429
3430 pci_set_drvdata(pdev, rvu);
3431 rvu->pdev = pdev;
3432 rvu->dev = &pdev->dev;
3433
3434 err = pci_enable_device(pdev);
3435 if (err) {
3436 dev_err(dev, "Failed to enable PCI device\n");
3437 goto err_freemem;
3438 }
3439
3440 err = pci_request_regions(pdev, DRV_NAME);
3441 if (err) {
3442 dev_err(dev, "PCI request regions failed 0x%x\n", err);
3443 goto err_disable_device;
3444 }
3445
3446 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
3447 if (err) {
3448 dev_err(dev, "DMA mask config failed, abort\n");
3449 goto err_release_regions;
3450 }
3451
3452 pci_set_master(pdev);
3453
3454 rvu->ptp = ptp_get();
3455 if (IS_ERR(rvu->ptp)) {
3456 err = PTR_ERR(rvu->ptp);
3457 if (err)
3458 goto err_release_regions;
3459 rvu->ptp = NULL;
3460 }
3461
3462 /* Map Admin function CSRs */
3463 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
3464 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
3465 if (!rvu->afreg_base || !rvu->pfreg_base) {
3466 dev_err(dev, "Unable to map admin function CSRs, aborting\n");
3467 err = -ENOMEM;
3468 goto err_put_ptp;
3469 }
3470
3471 /* Store module params in rvu structure */
3472 rvu_update_module_params(rvu);
3473
3474 /* Check which blocks the HW supports */
3475 rvu_check_block_implemented(rvu);
3476
3477 rvu_reset_all_blocks(rvu);
3478
3479 rvu_setup_hw_capabilities(rvu);
3480
3481 err = rvu_setup_hw_resources(rvu);
3482 if (err)
3483 goto err_put_ptp;
3484
3485 /* Init mailbox btw AF and PFs */
3486 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
3487 rvu->hw->total_pfs, rvu_afpf_mbox_handler,
3488 rvu_afpf_mbox_up_handler);
3489 if (err) {
3490 dev_err(dev, "%s: Failed to initialize mbox\n", __func__);
3491 goto err_hwsetup;
3492 }
3493
3494 err = rvu_flr_init(rvu);
3495 if (err) {
3496 dev_err(dev, "%s: Failed to initialize flr\n", __func__);
3497 goto err_mbox;
3498 }
3499
3500 err = rvu_register_interrupts(rvu);
3501 if (err) {
3502 dev_err(dev, "%s: Failed to register interrupts\n", __func__);
3503 goto err_flr;
3504 }
3505
3506 err = rvu_register_dl(rvu);
3507 if (err) {
3508 dev_err(dev, "%s: Failed to register devlink\n", __func__);
3509 goto err_irq;
3510 }
3511
3512 rvu_setup_rvum_blk_revid(rvu);
3513
3514 /* Enable AF's VFs (if any) */
3515 err = rvu_enable_sriov(rvu);
3516 if (err) {
3517 dev_err(dev, "%s: Failed to enable sriov\n", __func__);
3518 goto err_dl;
3519 }
3520
3521 /* Initialize debugfs */
3522 rvu_dbg_init(rvu);
3523
3524 mutex_init(&rvu->rswitch.switch_lock);
3525
3526 if (rvu->fwdata)
3527 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate,
3528 rvu->fwdata->ptp_ext_tstamp);
3529
3530 /* Alloc CINT and QINT memory */
3531 rvu_alloc_cint_qint_mem(rvu, &rvu->pf[RVU_AFPF], BLKADDR_NIX0,
3532 (rvu->hw->block[BLKADDR_NIX0].lf.max));
3533 return 0;
3534 err_dl:
3535 rvu_unregister_dl(rvu);
3536 err_irq:
3537 rvu_unregister_interrupts(rvu);
3538 err_flr:
3539 rvu_flr_wq_destroy(rvu);
3540 err_mbox:
3541 rvu_mbox_destroy(&rvu->afpf_wq_info);
3542 err_hwsetup:
3543 rvu_cgx_exit(rvu);
3544 rvu_fwdata_exit(rvu);
3545 rvu_mcs_exit(rvu);
3546 rvu_reset_all_blocks(rvu);
3547 rvu_free_hw_resources(rvu);
3548 rvu_clear_rvum_blk_revid(rvu);
3549 err_put_ptp:
3550 ptp_put(rvu->ptp);
3551 err_release_regions:
3552 pci_release_regions(pdev);
3553 err_disable_device:
3554 pci_disable_device(pdev);
3555 err_freemem:
3556 pci_set_drvdata(pdev, NULL);
3557 devm_kfree(&pdev->dev, rvu->hw);
3558 devm_kfree(dev, rvu);
3559 return err;
3560 }
3561
rvu_remove(struct pci_dev * pdev)3562 static void rvu_remove(struct pci_dev *pdev)
3563 {
3564 struct rvu *rvu = pci_get_drvdata(pdev);
3565
3566 rvu_dbg_exit(rvu);
3567 rvu_unregister_dl(rvu);
3568 rvu_unregister_interrupts(rvu);
3569 rvu_flr_wq_destroy(rvu);
3570 rvu_cgx_exit(rvu);
3571 rvu_fwdata_exit(rvu);
3572 rvu_mcs_exit(rvu);
3573 rvu_mbox_destroy(&rvu->afpf_wq_info);
3574 rvu_disable_sriov(rvu);
3575 rvu_reset_all_blocks(rvu);
3576 rvu_free_hw_resources(rvu);
3577 rvu_clear_rvum_blk_revid(rvu);
3578 ptp_put(rvu->ptp);
3579 pci_release_regions(pdev);
3580 pci_disable_device(pdev);
3581 pci_set_drvdata(pdev, NULL);
3582
3583 devm_kfree(&pdev->dev, rvu->hw);
3584 if (is_cn20k(rvu->pdev))
3585 cn20k_free_mbox_memory(rvu);
3586 kfree(rvu->ng_rvu);
3587 devm_kfree(&pdev->dev, rvu);
3588 }
3589
3590 static struct pci_driver rvu_driver = {
3591 .name = DRV_NAME,
3592 .id_table = rvu_id_table,
3593 .probe = rvu_probe,
3594 .remove = rvu_remove,
3595 };
3596
rvu_init_module(void)3597 static int __init rvu_init_module(void)
3598 {
3599 int err;
3600
3601 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3602
3603 err = pci_register_driver(&cgx_driver);
3604 if (err < 0)
3605 return err;
3606
3607 err = pci_register_driver(&ptp_driver);
3608 if (err < 0)
3609 goto ptp_err;
3610
3611 err = pci_register_driver(&mcs_driver);
3612 if (err < 0)
3613 goto mcs_err;
3614
3615 err = pci_register_driver(&rvu_driver);
3616 if (err < 0)
3617 goto rvu_err;
3618
3619 return 0;
3620 rvu_err:
3621 pci_unregister_driver(&mcs_driver);
3622 mcs_err:
3623 pci_unregister_driver(&ptp_driver);
3624 ptp_err:
3625 pci_unregister_driver(&cgx_driver);
3626
3627 return err;
3628 }
3629
rvu_cleanup_module(void)3630 static void __exit rvu_cleanup_module(void)
3631 {
3632 pci_unregister_driver(&rvu_driver);
3633 pci_unregister_driver(&mcs_driver);
3634 pci_unregister_driver(&ptp_driver);
3635 pci_unregister_driver(&cgx_driver);
3636 }
3637
3638 module_init(rvu_init_module);
3639 module_exit(rvu_cleanup_module);
3640