xref: /linux/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c (revision 65ae975e97d5aab3ee9dc5ec701b12090572ed43)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/types.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 
12 #include "rvu.h"
13 #include "cgx.h"
14 #include "lmac_common.h"
15 #include "rvu_reg.h"
16 #include "rvu_trace.h"
17 #include "rvu_npc_hash.h"
18 
19 struct cgx_evq_entry {
20 	struct list_head evq_node;
21 	struct cgx_link_event link_event;
22 };
23 
24 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
25 static struct _req_type __maybe_unused					\
26 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid)		\
27 {									\
28 	struct _req_type *req;						\
29 									\
30 	req = (struct _req_type *)otx2_mbox_alloc_msg_rsp(		\
31 		&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
32 		sizeof(struct _rsp_type));				\
33 	if (!req)							\
34 		return NULL;						\
35 	req->hdr.sig = OTX2_MBOX_REQ_SIG;				\
36 	req->hdr.id = _id;						\
37 	trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req));		\
38 	return req;							\
39 }
40 
41 MBOX_UP_CGX_MESSAGES
42 #undef M
43 
is_mac_feature_supported(struct rvu * rvu,int pf,int feature)44 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
45 {
46 	u8 cgx_id, lmac_id;
47 	void *cgxd;
48 
49 	if (!is_pf_cgxmapped(rvu, pf))
50 		return 0;
51 
52 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
53 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
54 
55 	return  (cgx_features_get(cgxd) & feature);
56 }
57 
58 #define CGX_OFFSET(x)			((x) * rvu->hw->lmac_per_cgx)
59 /* Returns bitmap of mapped PFs */
cgxlmac_to_pfmap(struct rvu * rvu,u8 cgx_id,u8 lmac_id)60 static u64 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
61 {
62 	return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
63 }
64 
cgxlmac_to_pf(struct rvu * rvu,int cgx_id,int lmac_id)65 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
66 {
67 	unsigned long pfmap;
68 
69 	pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
70 
71 	/* Assumes only one pf mapped to a cgx lmac port */
72 	if (!pfmap)
73 		return -ENODEV;
74 	else
75 		return find_first_bit(&pfmap,
76 				      rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);
77 }
78 
cgxlmac_id_to_bmap(u8 cgx_id,u8 lmac_id)79 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
80 {
81 	return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
82 }
83 
rvu_cgx_pdata(u8 cgx_id,struct rvu * rvu)84 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
85 {
86 	if (cgx_id >= rvu->cgx_cnt_max)
87 		return NULL;
88 
89 	return rvu->cgx_idmap[cgx_id];
90 }
91 
92 /* Return first enabled CGX instance if none are enabled then return NULL */
rvu_first_cgx_pdata(struct rvu * rvu)93 void *rvu_first_cgx_pdata(struct rvu *rvu)
94 {
95 	int first_enabled_cgx = 0;
96 	void *cgxd = NULL;
97 
98 	for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
99 		cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
100 		if (cgxd)
101 			break;
102 	}
103 
104 	return cgxd;
105 }
106 
107 /* Based on P2X connectivity find mapped NIX block for a PF */
rvu_map_cgx_nix_block(struct rvu * rvu,int pf,int cgx_id,int lmac_id)108 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
109 				  int cgx_id, int lmac_id)
110 {
111 	struct rvu_pfvf *pfvf = &rvu->pf[pf];
112 	u8 p2x;
113 
114 	p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);
115 	/* Firmware sets P2X_SELECT as either NIX0 or NIX1 */
116 	pfvf->nix_blkaddr = BLKADDR_NIX0;
117 	if (is_rvu_supports_nix1(rvu) && p2x == CMR_P2X_SEL_NIX1)
118 		pfvf->nix_blkaddr = BLKADDR_NIX1;
119 }
120 
rvu_map_cgx_lmac_pf(struct rvu * rvu)121 static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
122 {
123 	struct npc_pkind *pkind = &rvu->hw->pkind;
124 	int cgx_cnt_max = rvu->cgx_cnt_max;
125 	int pf = PF_CGXMAP_BASE;
126 	unsigned long lmac_bmap;
127 	int size, free_pkind;
128 	int cgx, lmac, iter;
129 	int numvfs, hwvfs;
130 
131 	if (!cgx_cnt_max)
132 		return 0;
133 
134 	if (cgx_cnt_max > 0xF || rvu->hw->lmac_per_cgx > 0xF)
135 		return -EINVAL;
136 
137 	/* Alloc map table
138 	 * An additional entry is required since PF id starts from 1 and
139 	 * hence entry at offset 0 is invalid.
140 	 */
141 	size = (cgx_cnt_max * rvu->hw->lmac_per_cgx + 1) * sizeof(u8);
142 	rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);
143 	if (!rvu->pf2cgxlmac_map)
144 		return -ENOMEM;
145 
146 	/* Initialize all entries with an invalid cgx and lmac id */
147 	memset(rvu->pf2cgxlmac_map, 0xFF, size);
148 
149 	/* Reverse map table */
150 	rvu->cgxlmac2pf_map =
151 		devm_kzalloc(rvu->dev,
152 			     cgx_cnt_max * rvu->hw->lmac_per_cgx * sizeof(u64),
153 			     GFP_KERNEL);
154 	if (!rvu->cgxlmac2pf_map)
155 		return -ENOMEM;
156 
157 	rvu->cgx_mapped_pfs = 0;
158 	for (cgx = 0; cgx < cgx_cnt_max; cgx++) {
159 		if (!rvu_cgx_pdata(cgx, rvu))
160 			continue;
161 		lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
162 		for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) {
163 			if (iter >= MAX_LMAC_COUNT)
164 				continue;
165 			lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),
166 					      iter);
167 			rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
168 			rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
169 			free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
170 			pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
171 			rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
172 			rvu->cgx_mapped_pfs++;
173 			rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
174 			rvu->cgx_mapped_vfs += numvfs;
175 			pf++;
176 		}
177 	}
178 	return 0;
179 }
180 
rvu_cgx_send_link_info(int cgx_id,int lmac_id,struct rvu * rvu)181 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)
182 {
183 	struct cgx_evq_entry *qentry;
184 	unsigned long flags;
185 	int err;
186 
187 	qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);
188 	if (!qentry)
189 		return -ENOMEM;
190 
191 	/* Lock the event queue before we read the local link status */
192 	spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
193 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
194 				&qentry->link_event.link_uinfo);
195 	qentry->link_event.cgx_id = cgx_id;
196 	qentry->link_event.lmac_id = lmac_id;
197 	if (err) {
198 		kfree(qentry);
199 		goto skip_add;
200 	}
201 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
202 skip_add:
203 	spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
204 
205 	/* start worker to process the events */
206 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
207 
208 	return 0;
209 }
210 
211 /* This is called from interrupt context and is expected to be atomic */
cgx_lmac_postevent(struct cgx_link_event * event,void * data)212 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)
213 {
214 	struct cgx_evq_entry *qentry;
215 	struct rvu *rvu = data;
216 
217 	/* post event to the event queue */
218 	qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);
219 	if (!qentry)
220 		return -ENOMEM;
221 	qentry->link_event = *event;
222 	spin_lock(&rvu->cgx_evq_lock);
223 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
224 	spin_unlock(&rvu->cgx_evq_lock);
225 
226 	/* start worker to process the events */
227 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
228 
229 	return 0;
230 }
231 
cgx_notify_pfs(struct cgx_link_event * event,struct rvu * rvu)232 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)
233 {
234 	struct cgx_link_user_info *linfo;
235 	struct cgx_link_info_msg *msg;
236 	unsigned long pfmap;
237 	int pfid;
238 
239 	linfo = &event->link_uinfo;
240 	pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);
241 	if (!pfmap) {
242 		dev_err(rvu->dev, "CGX port%d:%d not mapped with PF\n",
243 			event->cgx_id, event->lmac_id);
244 		return;
245 	}
246 
247 	do {
248 		pfid = find_first_bit(&pfmap,
249 				      rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);
250 		clear_bit(pfid, &pfmap);
251 
252 		/* check if notification is enabled */
253 		if (!test_bit(pfid, &rvu->pf_notify_bmap)) {
254 			dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",
255 				 event->cgx_id, event->lmac_id,
256 				 linfo->link_up ? "UP" : "DOWN");
257 			continue;
258 		}
259 
260 		mutex_lock(&rvu->mbox_lock);
261 
262 		/* Send mbox message to PF */
263 		msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);
264 		if (!msg) {
265 			mutex_unlock(&rvu->mbox_lock);
266 			continue;
267 		}
268 
269 		msg->link_info = *linfo;
270 
271 		otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pfid);
272 
273 		otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pfid);
274 
275 		mutex_unlock(&rvu->mbox_lock);
276 	} while (pfmap);
277 }
278 
cgx_evhandler_task(struct work_struct * work)279 static void cgx_evhandler_task(struct work_struct *work)
280 {
281 	struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);
282 	struct cgx_evq_entry *qentry;
283 	struct cgx_link_event *event;
284 	unsigned long flags;
285 
286 	do {
287 		/* Dequeue an event */
288 		spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
289 		qentry = list_first_entry_or_null(&rvu->cgx_evq_head,
290 						  struct cgx_evq_entry,
291 						  evq_node);
292 		if (qentry)
293 			list_del(&qentry->evq_node);
294 		spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
295 		if (!qentry)
296 			break; /* nothing more to process */
297 
298 		event = &qentry->link_event;
299 
300 		/* process event */
301 		cgx_notify_pfs(event, rvu);
302 		kfree(qentry);
303 	} while (1);
304 }
305 
cgx_lmac_event_handler_init(struct rvu * rvu)306 static int cgx_lmac_event_handler_init(struct rvu *rvu)
307 {
308 	unsigned long lmac_bmap;
309 	struct cgx_event_cb cb;
310 	int cgx, lmac, err;
311 	void *cgxd;
312 
313 	spin_lock_init(&rvu->cgx_evq_lock);
314 	INIT_LIST_HEAD(&rvu->cgx_evq_head);
315 	INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);
316 	rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
317 	if (!rvu->cgx_evh_wq) {
318 		dev_err(rvu->dev, "alloc workqueue failed");
319 		return -ENOMEM;
320 	}
321 
322 	cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
323 	cb.data = rvu;
324 
325 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
326 		cgxd = rvu_cgx_pdata(cgx, rvu);
327 		if (!cgxd)
328 			continue;
329 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
330 		for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx) {
331 			err = cgx_lmac_evh_register(&cb, cgxd, lmac);
332 			if (err)
333 				dev_err(rvu->dev,
334 					"%d:%d handler register failed\n",
335 					cgx, lmac);
336 		}
337 	}
338 
339 	return 0;
340 }
341 
rvu_cgx_wq_destroy(struct rvu * rvu)342 static void rvu_cgx_wq_destroy(struct rvu *rvu)
343 {
344 	if (rvu->cgx_evh_wq) {
345 		destroy_workqueue(rvu->cgx_evh_wq);
346 		rvu->cgx_evh_wq = NULL;
347 	}
348 }
349 
rvu_cgx_init(struct rvu * rvu)350 int rvu_cgx_init(struct rvu *rvu)
351 {
352 	struct mac_ops *mac_ops;
353 	int cgx, err;
354 	void *cgxd;
355 
356 	/* CGX port id starts from 0 and are not necessarily contiguous
357 	 * Hence we allocate resources based on the maximum port id value.
358 	 */
359 	rvu->cgx_cnt_max = cgx_get_cgxcnt_max();
360 	if (!rvu->cgx_cnt_max) {
361 		dev_info(rvu->dev, "No CGX devices found!\n");
362 		return 0;
363 	}
364 
365 	rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *
366 				      sizeof(void *), GFP_KERNEL);
367 	if (!rvu->cgx_idmap)
368 		return -ENOMEM;
369 
370 	/* Initialize the cgxdata table */
371 	for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)
372 		rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
373 
374 	/* Map CGX LMAC interfaces to RVU PFs */
375 	err = rvu_map_cgx_lmac_pf(rvu);
376 	if (err)
377 		return err;
378 
379 	/* Clear X2P reset on all MAC blocks */
380 	for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) {
381 		cgxd = rvu_cgx_pdata(cgx, rvu);
382 		if (!cgxd)
383 			continue;
384 		mac_ops = get_mac_ops(cgxd);
385 		mac_ops->mac_x2p_reset(cgxd, false);
386 	}
387 
388 	/* Register for CGX events */
389 	err = cgx_lmac_event_handler_init(rvu);
390 	if (err)
391 		return err;
392 
393 	mutex_init(&rvu->cgx_cfg_lock);
394 
395 	return 0;
396 }
397 
cgx_start_linkup(struct rvu * rvu)398 void cgx_start_linkup(struct rvu *rvu)
399 {
400 	unsigned long lmac_bmap;
401 	struct mac_ops *mac_ops;
402 	int cgx, lmac, err;
403 	void *cgxd;
404 
405 	/* Enable receive on all LMACS */
406 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
407 		cgxd = rvu_cgx_pdata(cgx, rvu);
408 		if (!cgxd)
409 			continue;
410 		mac_ops = get_mac_ops(cgxd);
411 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
412 		for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx)
413 			mac_ops->mac_enadis_rx(cgxd, lmac, true);
414 	}
415 
416 	/* Do link up for all CGX ports */
417 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
418 		cgxd = rvu_cgx_pdata(cgx, rvu);
419 		if (!cgxd)
420 			continue;
421 		err = cgx_lmac_linkup_start(cgxd);
422 		if (err)
423 			dev_err(rvu->dev,
424 				"Link up process failed to start on cgx %d\n",
425 				cgx);
426 	}
427 }
428 
rvu_cgx_exit(struct rvu * rvu)429 int rvu_cgx_exit(struct rvu *rvu)
430 {
431 	unsigned long lmac_bmap;
432 	int cgx, lmac;
433 	void *cgxd;
434 
435 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
436 		cgxd = rvu_cgx_pdata(cgx, rvu);
437 		if (!cgxd)
438 			continue;
439 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
440 		for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx)
441 			cgx_lmac_evh_unregister(cgxd, lmac);
442 	}
443 
444 	/* Ensure event handler unregister is completed */
445 	mb();
446 
447 	rvu_cgx_wq_destroy(rvu);
448 	return 0;
449 }
450 
451 /* Most of the CGX configuration is restricted to the mapped PF only,
452  * VF's of mapped PF and other PFs are not allowed. This fn() checks
453  * whether a PFFUNC is permitted to do the config or not.
454  */
is_cgx_config_permitted(struct rvu * rvu,u16 pcifunc)455 inline bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)
456 {
457 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
458 	    !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
459 		return false;
460 	return true;
461 }
462 
rvu_cgx_enadis_rx_bp(struct rvu * rvu,int pf,bool enable)463 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)
464 {
465 	struct mac_ops *mac_ops;
466 	u8 cgx_id, lmac_id;
467 	void *cgxd;
468 
469 	if (!is_pf_cgxmapped(rvu, pf))
470 		return;
471 
472 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
473 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
474 
475 	mac_ops = get_mac_ops(cgxd);
476 	/* Set / clear CTL_BCK to control pause frame forwarding to NIX */
477 	if (enable)
478 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);
479 	else
480 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);
481 }
482 
rvu_cgx_config_rxtx(struct rvu * rvu,u16 pcifunc,bool start)483 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)
484 {
485 	int pf = rvu_get_pf(pcifunc);
486 	struct mac_ops *mac_ops;
487 	u8 cgx_id, lmac_id;
488 	void *cgxd;
489 
490 	if (!is_cgx_config_permitted(rvu, pcifunc))
491 		return LMAC_AF_ERR_PERM_DENIED;
492 
493 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
494 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
495 	mac_ops = get_mac_ops(cgxd);
496 
497 	return mac_ops->mac_rx_tx_enable(cgxd, lmac_id, start);
498 }
499 
rvu_cgx_tx_enable(struct rvu * rvu,u16 pcifunc,bool enable)500 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable)
501 {
502 	int pf = rvu_get_pf(pcifunc);
503 	struct mac_ops *mac_ops;
504 	u8 cgx_id, lmac_id;
505 	void *cgxd;
506 
507 	if (!is_cgx_config_permitted(rvu, pcifunc))
508 		return LMAC_AF_ERR_PERM_DENIED;
509 
510 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
511 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
512 	mac_ops = get_mac_ops(cgxd);
513 
514 	return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);
515 }
516 
rvu_cgx_config_tx(void * cgxd,int lmac_id,bool enable)517 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable)
518 {
519 	struct mac_ops *mac_ops;
520 
521 	mac_ops = get_mac_ops(cgxd);
522 	return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);
523 }
524 
rvu_cgx_disable_dmac_entries(struct rvu * rvu,u16 pcifunc)525 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)
526 {
527 	int pf = rvu_get_pf(pcifunc);
528 	int i = 0, lmac_count = 0;
529 	struct mac_ops *mac_ops;
530 	u8 max_dmac_filters;
531 	u8 cgx_id, lmac_id;
532 	void *cgx_dev;
533 
534 	if (!is_cgx_config_permitted(rvu, pcifunc))
535 		return;
536 
537 	if (rvu_npc_exact_has_match_table(rvu)) {
538 		rvu_npc_exact_reset(rvu, pcifunc);
539 		return;
540 	}
541 
542 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
543 	cgx_dev = cgx_get_pdata(cgx_id);
544 	lmac_count = cgx_get_lmac_cnt(cgx_dev);
545 
546 	mac_ops = get_mac_ops(cgx_dev);
547 	if (!mac_ops)
548 		return;
549 
550 	max_dmac_filters = mac_ops->dmac_filter_count / lmac_count;
551 
552 	for (i = 0; i < max_dmac_filters; i++)
553 		cgx_lmac_addr_del(cgx_id, lmac_id, i);
554 
555 	/* As cgx_lmac_addr_del does not clear entry for index 0
556 	 * so it needs to be done explicitly
557 	 */
558 	cgx_lmac_addr_reset(cgx_id, lmac_id);
559 }
560 
rvu_mbox_handler_cgx_start_rxtx(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)561 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
562 				    struct msg_rsp *rsp)
563 {
564 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);
565 	return 0;
566 }
567 
rvu_mbox_handler_cgx_stop_rxtx(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)568 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
569 				   struct msg_rsp *rsp)
570 {
571 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
572 	return 0;
573 }
574 
rvu_lmac_get_stats(struct rvu * rvu,struct msg_req * req,void * rsp)575 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,
576 			      void *rsp)
577 {
578 	int pf = rvu_get_pf(req->hdr.pcifunc);
579 	struct mac_ops *mac_ops;
580 	int stat = 0, err = 0;
581 	u64 tx_stat, rx_stat;
582 	u8 cgx_idx, lmac;
583 	void *cgxd;
584 
585 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
586 		return LMAC_AF_ERR_PERM_DENIED;
587 
588 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
589 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
590 	mac_ops = get_mac_ops(cgxd);
591 
592 	/* Rx stats */
593 	while (stat < mac_ops->rx_stats_cnt) {
594 		err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);
595 		if (err)
596 			return err;
597 		if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)
598 			((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
599 		else
600 			((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
601 		stat++;
602 	}
603 
604 	/* Tx stats */
605 	stat = 0;
606 	while (stat < mac_ops->tx_stats_cnt) {
607 		err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);
608 		if (err)
609 			return err;
610 		if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)
611 			((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
612 		else
613 			((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
614 		stat++;
615 	}
616 	return 0;
617 }
618 
rvu_mbox_handler_cgx_stats(struct rvu * rvu,struct msg_req * req,struct cgx_stats_rsp * rsp)619 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
620 			       struct cgx_stats_rsp *rsp)
621 {
622 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
623 }
624 
rvu_mbox_handler_rpm_stats(struct rvu * rvu,struct msg_req * req,struct rpm_stats_rsp * rsp)625 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,
626 			       struct rpm_stats_rsp *rsp)
627 {
628 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
629 }
630 
rvu_mbox_handler_cgx_stats_rst(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)631 int rvu_mbox_handler_cgx_stats_rst(struct rvu *rvu, struct msg_req *req,
632 				   struct msg_rsp *rsp)
633 {
634 	int pf = rvu_get_pf(req->hdr.pcifunc);
635 	struct rvu_pfvf	*parent_pf;
636 	struct mac_ops *mac_ops;
637 	u8 cgx_idx, lmac;
638 	void *cgxd;
639 
640 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
641 		return LMAC_AF_ERR_PERM_DENIED;
642 
643 	parent_pf = &rvu->pf[pf];
644 	/* To ensure reset cgx stats won't affect VF stats,
645 	 *  check if it used by only PF interface.
646 	 *  If not, return
647 	 */
648 	if (parent_pf->cgx_users > 1) {
649 		dev_info(rvu->dev, "CGX busy, could not reset statistics\n");
650 		return 0;
651 	}
652 
653 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
654 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
655 	mac_ops = get_mac_ops(cgxd);
656 
657 	return mac_ops->mac_stats_reset(cgxd, lmac);
658 }
659 
rvu_mbox_handler_cgx_fec_stats(struct rvu * rvu,struct msg_req * req,struct cgx_fec_stats_rsp * rsp)660 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,
661 				   struct msg_req *req,
662 				   struct cgx_fec_stats_rsp *rsp)
663 {
664 	int pf = rvu_get_pf(req->hdr.pcifunc);
665 	struct mac_ops *mac_ops;
666 	u8 cgx_idx, lmac;
667 	void *cgxd;
668 
669 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
670 		return LMAC_AF_ERR_PERM_DENIED;
671 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
672 
673 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
674 	mac_ops = get_mac_ops(cgxd);
675 	return  mac_ops->get_fec_stats(cgxd, lmac, rsp);
676 }
677 
rvu_mbox_handler_cgx_mac_addr_set(struct rvu * rvu,struct cgx_mac_addr_set_or_get * req,struct cgx_mac_addr_set_or_get * rsp)678 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
679 				      struct cgx_mac_addr_set_or_get *req,
680 				      struct cgx_mac_addr_set_or_get *rsp)
681 {
682 	int pf = rvu_get_pf(req->hdr.pcifunc);
683 	u8 cgx_id, lmac_id;
684 
685 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
686 		return -EPERM;
687 
688 	if (rvu_npc_exact_has_match_table(rvu))
689 		return rvu_npc_exact_mac_addr_set(rvu, req, rsp);
690 
691 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
692 
693 	cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
694 
695 	return 0;
696 }
697 
rvu_mbox_handler_cgx_mac_addr_add(struct rvu * rvu,struct cgx_mac_addr_add_req * req,struct cgx_mac_addr_add_rsp * rsp)698 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,
699 				      struct cgx_mac_addr_add_req *req,
700 				      struct cgx_mac_addr_add_rsp *rsp)
701 {
702 	int pf = rvu_get_pf(req->hdr.pcifunc);
703 	u8 cgx_id, lmac_id;
704 	int rc = 0;
705 
706 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
707 		return -EPERM;
708 
709 	if (rvu_npc_exact_has_match_table(rvu))
710 		return rvu_npc_exact_mac_addr_add(rvu, req, rsp);
711 
712 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
713 	rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);
714 	if (rc >= 0) {
715 		rsp->index = rc;
716 		return 0;
717 	}
718 
719 	return rc;
720 }
721 
rvu_mbox_handler_cgx_mac_addr_del(struct rvu * rvu,struct cgx_mac_addr_del_req * req,struct msg_rsp * rsp)722 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,
723 				      struct cgx_mac_addr_del_req *req,
724 				      struct msg_rsp *rsp)
725 {
726 	int pf = rvu_get_pf(req->hdr.pcifunc);
727 	u8 cgx_id, lmac_id;
728 
729 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
730 		return -EPERM;
731 
732 	if (rvu_npc_exact_has_match_table(rvu))
733 		return rvu_npc_exact_mac_addr_del(rvu, req, rsp);
734 
735 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
736 	return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);
737 }
738 
rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu * rvu,struct msg_req * req,struct cgx_max_dmac_entries_get_rsp * rsp)739 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,
740 					     struct msg_req *req,
741 					     struct cgx_max_dmac_entries_get_rsp
742 					     *rsp)
743 {
744 	int pf = rvu_get_pf(req->hdr.pcifunc);
745 	u8 cgx_id, lmac_id;
746 
747 	/* If msg is received from PFs(which are not mapped to CGX LMACs)
748 	 * or VF then no entries are allocated for DMAC filters at CGX level.
749 	 * So returning zero.
750 	 */
751 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {
752 		rsp->max_dmac_filters = 0;
753 		return 0;
754 	}
755 
756 	if (rvu_npc_exact_has_match_table(rvu)) {
757 		rsp->max_dmac_filters = rvu_npc_exact_get_max_entries(rvu);
758 		return 0;
759 	}
760 
761 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
762 	rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);
763 	return 0;
764 }
765 
rvu_mbox_handler_cgx_mac_addr_get(struct rvu * rvu,struct cgx_mac_addr_set_or_get * req,struct cgx_mac_addr_set_or_get * rsp)766 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
767 				      struct cgx_mac_addr_set_or_get *req,
768 				      struct cgx_mac_addr_set_or_get *rsp)
769 {
770 	int pf = rvu_get_pf(req->hdr.pcifunc);
771 	u8 cgx_id, lmac_id;
772 	int rc = 0;
773 	u64 cfg;
774 
775 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
776 		return -EPERM;
777 
778 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
779 
780 	rsp->hdr.rc = rc;
781 	cfg = cgx_lmac_addr_get(cgx_id, lmac_id);
782 	/* copy 48 bit mac address to req->mac_addr */
783 	u64_to_ether_addr(cfg, rsp->mac_addr);
784 	return 0;
785 }
786 
rvu_mbox_handler_cgx_promisc_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)787 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
788 					struct msg_rsp *rsp)
789 {
790 	u16 pcifunc = req->hdr.pcifunc;
791 	int pf = rvu_get_pf(pcifunc);
792 	u8 cgx_id, lmac_id;
793 
794 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
795 		return -EPERM;
796 
797 	/* Disable drop on non hit rule */
798 	if (rvu_npc_exact_has_match_table(rvu))
799 		return rvu_npc_exact_promisc_enable(rvu, req->hdr.pcifunc);
800 
801 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
802 
803 	cgx_lmac_promisc_config(cgx_id, lmac_id, true);
804 	return 0;
805 }
806 
rvu_mbox_handler_cgx_promisc_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)807 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
808 					 struct msg_rsp *rsp)
809 {
810 	int pf = rvu_get_pf(req->hdr.pcifunc);
811 	u8 cgx_id, lmac_id;
812 
813 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
814 		return -EPERM;
815 
816 	/* Disable drop on non hit rule */
817 	if (rvu_npc_exact_has_match_table(rvu))
818 		return rvu_npc_exact_promisc_disable(rvu, req->hdr.pcifunc);
819 
820 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
821 
822 	cgx_lmac_promisc_config(cgx_id, lmac_id, false);
823 	return 0;
824 }
825 
rvu_cgx_ptp_rx_cfg(struct rvu * rvu,u16 pcifunc,bool enable)826 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
827 {
828 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
829 	int pf = rvu_get_pf(pcifunc);
830 	struct mac_ops *mac_ops;
831 	u8 cgx_id, lmac_id;
832 	void *cgxd;
833 
834 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
835 		return 0;
836 
837 	/* This msg is expected only from PF/VFs that are mapped to CGX/RPM LMACs,
838 	 * if received from other PF/VF simply ACK, nothing to do.
839 	 */
840 	if (!is_pf_cgxmapped(rvu, pf))
841 		return -EPERM;
842 
843 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
844 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
845 
846 	mac_ops = get_mac_ops(cgxd);
847 	mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, enable);
848 	/* If PTP is enabled then inform NPC that packets to be
849 	 * parsed by this PF will have their data shifted by 8 bytes
850 	 * and if PTP is disabled then no shift is required
851 	 */
852 	if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))
853 		return -EINVAL;
854 	/* This flag is required to clean up CGX conf if app gets killed */
855 	pfvf->hw_rx_tstamp_en = enable;
856 
857 	/* Inform MCS about 8B RX header */
858 	rvu_mcs_ptp_cfg(rvu, cgx_id, lmac_id, enable);
859 	return 0;
860 }
861 
rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)862 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,
863 				       struct msg_rsp *rsp)
864 {
865 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(req->hdr.pcifunc)))
866 		return -EPERM;
867 
868 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);
869 }
870 
rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)871 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,
872 					struct msg_rsp *rsp)
873 {
874 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);
875 }
876 
rvu_cgx_config_linkevents(struct rvu * rvu,u16 pcifunc,bool en)877 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)
878 {
879 	int pf = rvu_get_pf(pcifunc);
880 	u8 cgx_id, lmac_id;
881 
882 	if (!is_cgx_config_permitted(rvu, pcifunc))
883 		return -EPERM;
884 
885 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
886 
887 	if (en) {
888 		set_bit(pf, &rvu->pf_notify_bmap);
889 		/* Send the current link status to PF */
890 		rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);
891 	} else {
892 		clear_bit(pf, &rvu->pf_notify_bmap);
893 	}
894 
895 	return 0;
896 }
897 
rvu_mbox_handler_cgx_start_linkevents(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)898 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
899 					  struct msg_rsp *rsp)
900 {
901 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);
902 	return 0;
903 }
904 
rvu_mbox_handler_cgx_stop_linkevents(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)905 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
906 					 struct msg_rsp *rsp)
907 {
908 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);
909 	return 0;
910 }
911 
rvu_mbox_handler_cgx_get_linkinfo(struct rvu * rvu,struct msg_req * req,struct cgx_link_info_msg * rsp)912 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
913 				      struct cgx_link_info_msg *rsp)
914 {
915 	u8 cgx_id, lmac_id;
916 	int pf, err;
917 
918 	pf = rvu_get_pf(req->hdr.pcifunc);
919 
920 	if (!is_pf_cgxmapped(rvu, pf))
921 		return -ENODEV;
922 
923 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
924 
925 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
926 				&rsp->link_info);
927 	return err;
928 }
929 
rvu_mbox_handler_cgx_features_get(struct rvu * rvu,struct msg_req * req,struct cgx_features_info_msg * rsp)930 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,
931 				      struct msg_req *req,
932 				      struct cgx_features_info_msg *rsp)
933 {
934 	int pf = rvu_get_pf(req->hdr.pcifunc);
935 	u8 cgx_idx, lmac;
936 	void *cgxd;
937 
938 	if (!is_pf_cgxmapped(rvu, pf))
939 		return 0;
940 
941 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
942 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
943 	rsp->lmac_features = cgx_features_get(cgxd);
944 
945 	return 0;
946 }
947 
rvu_cgx_get_fifolen(struct rvu * rvu)948 u32 rvu_cgx_get_fifolen(struct rvu *rvu)
949 {
950 	void *cgxd = rvu_first_cgx_pdata(rvu);
951 
952 	if (!cgxd)
953 		return 0;
954 
955 	return cgx_get_fifo_len(cgxd);
956 }
957 
rvu_cgx_get_lmac_fifolen(struct rvu * rvu,int cgx,int lmac)958 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac)
959 {
960 	struct mac_ops *mac_ops;
961 	void *cgxd;
962 
963 	cgxd = rvu_cgx_pdata(cgx, rvu);
964 	if (!cgxd)
965 		return 0;
966 
967 	mac_ops = get_mac_ops(cgxd);
968 	if (!mac_ops->lmac_fifo_len)
969 		return 0;
970 
971 	return mac_ops->lmac_fifo_len(cgxd, lmac);
972 }
973 
rvu_cgx_config_intlbk(struct rvu * rvu,u16 pcifunc,bool en)974 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)
975 {
976 	int pf = rvu_get_pf(pcifunc);
977 	struct mac_ops *mac_ops;
978 	u8 cgx_id, lmac_id;
979 
980 	if (!is_cgx_config_permitted(rvu, pcifunc))
981 		return -EPERM;
982 
983 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
984 	mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
985 
986 	return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
987 					  lmac_id, en);
988 }
989 
rvu_mbox_handler_cgx_intlbk_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)990 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
991 				       struct msg_rsp *rsp)
992 {
993 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);
994 	return 0;
995 }
996 
rvu_mbox_handler_cgx_intlbk_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)997 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
998 					struct msg_rsp *rsp)
999 {
1000 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);
1001 	return 0;
1002 }
1003 
rvu_cgx_cfg_pause_frm(struct rvu * rvu,u16 pcifunc,u8 tx_pause,u8 rx_pause)1004 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause)
1005 {
1006 	int pf = rvu_get_pf(pcifunc);
1007 	u8 rx_pfc = 0, tx_pfc = 0;
1008 	struct mac_ops *mac_ops;
1009 	u8 cgx_id, lmac_id;
1010 	void *cgxd;
1011 
1012 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))
1013 		return 0;
1014 
1015 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1016 	 * if received from other PF/VF simply ACK, nothing to do.
1017 	 */
1018 	if (!is_pf_cgxmapped(rvu, pf))
1019 		return LMAC_AF_ERR_PF_NOT_MAPPED;
1020 
1021 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1022 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1023 	mac_ops = get_mac_ops(cgxd);
1024 
1025 	mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &tx_pfc, &rx_pfc);
1026 	if (tx_pfc || rx_pfc) {
1027 		dev_warn(rvu->dev,
1028 			 "Can not configure 802.3X flow control as PFC frames are enabled");
1029 		return LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED;
1030 	}
1031 
1032 	mutex_lock(&rvu->rsrc_lock);
1033 	if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause,
1034 			       pcifunc & RVU_PFVF_FUNC_MASK)) {
1035 		mutex_unlock(&rvu->rsrc_lock);
1036 		return LMAC_AF_ERR_PERM_DENIED;
1037 	}
1038 	mutex_unlock(&rvu->rsrc_lock);
1039 
1040 	return mac_ops->mac_enadis_pause_frm(cgxd, lmac_id, tx_pause, rx_pause);
1041 }
1042 
rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu * rvu,struct cgx_pause_frm_cfg * req,struct cgx_pause_frm_cfg * rsp)1043 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,
1044 				       struct cgx_pause_frm_cfg *req,
1045 				       struct cgx_pause_frm_cfg *rsp)
1046 {
1047 	int pf = rvu_get_pf(req->hdr.pcifunc);
1048 	struct mac_ops *mac_ops;
1049 	u8 cgx_id, lmac_id;
1050 	int err = 0;
1051 	void *cgxd;
1052 
1053 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1054 	 * if received from other PF/VF simply ACK, nothing to do.
1055 	 */
1056 	if (!is_pf_cgxmapped(rvu, pf))
1057 		return -ENODEV;
1058 
1059 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1060 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1061 	mac_ops = get_mac_ops(cgxd);
1062 
1063 	if (req->set)
1064 		err = rvu_cgx_cfg_pause_frm(rvu, req->hdr.pcifunc, req->tx_pause, req->rx_pause);
1065 	else
1066 		mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause);
1067 
1068 	return err;
1069 }
1070 
rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1071 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,
1072 					   struct msg_rsp *rsp)
1073 {
1074 	int pf = rvu_get_pf(req->hdr.pcifunc);
1075 	u8 cgx_id, lmac_id;
1076 
1077 	if (!is_pf_cgxmapped(rvu, pf))
1078 		return LMAC_AF_ERR_PF_NOT_MAPPED;
1079 
1080 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1081 	return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);
1082 }
1083 
1084 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those
1085  * from its VFs as well. ie. NIX rx/tx counters at the CGX port level
1086  */
rvu_cgx_nix_cuml_stats(struct rvu * rvu,void * cgxd,int lmac_id,int index,int rxtxflag,u64 * stat)1087 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,
1088 			   int index, int rxtxflag, u64 *stat)
1089 {
1090 	struct rvu_block *block;
1091 	int blkaddr;
1092 	u16 pcifunc;
1093 	int pf, lf;
1094 
1095 	*stat = 0;
1096 
1097 	if (!cgxd || !rvu)
1098 		return -EINVAL;
1099 
1100 	pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);
1101 	if (pf < 0)
1102 		return pf;
1103 
1104 	/* Assumes LF of a PF and all of its VF belongs to the same
1105 	 * NIX block
1106 	 */
1107 	pcifunc = pf << RVU_PFVF_PF_SHIFT;
1108 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1109 	if (blkaddr < 0)
1110 		return 0;
1111 	block = &rvu->hw->block[blkaddr];
1112 
1113 	for (lf = 0; lf < block->lf.max; lf++) {
1114 		/* Check if a lf is attached to this PF or one of its VFs */
1115 		if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &
1116 			 ~RVU_PFVF_FUNC_MASK)))
1117 			continue;
1118 		if (rxtxflag == NIX_STATS_RX)
1119 			*stat += rvu_read64(rvu, blkaddr,
1120 					    NIX_AF_LFX_RX_STATX(lf, index));
1121 		else
1122 			*stat += rvu_read64(rvu, blkaddr,
1123 					    NIX_AF_LFX_TX_STATX(lf, index));
1124 	}
1125 
1126 	return 0;
1127 }
1128 
rvu_cgx_start_stop_io(struct rvu * rvu,u16 pcifunc,bool start)1129 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)
1130 {
1131 	struct rvu_pfvf *parent_pf, *pfvf;
1132 	int cgx_users, err = 0;
1133 
1134 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
1135 		return 0;
1136 
1137 	parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
1138 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1139 
1140 	mutex_lock(&rvu->cgx_cfg_lock);
1141 
1142 	if (start && pfvf->cgx_in_use)
1143 		goto exit;  /* CGX is already started hence nothing to do */
1144 	if (!start && !pfvf->cgx_in_use)
1145 		goto exit; /* CGX is already stopped hence nothing to do */
1146 
1147 	if (start) {
1148 		cgx_users = parent_pf->cgx_users;
1149 		parent_pf->cgx_users++;
1150 	} else {
1151 		parent_pf->cgx_users--;
1152 		cgx_users = parent_pf->cgx_users;
1153 	}
1154 
1155 	/* Start CGX when first of all NIXLFs is started.
1156 	 * Stop CGX when last of all NIXLFs is stopped.
1157 	 */
1158 	if (!cgx_users) {
1159 		err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,
1160 					  start);
1161 		if (err) {
1162 			dev_err(rvu->dev, "Unable to %s CGX\n",
1163 				start ? "start" : "stop");
1164 			/* Revert the usage count in case of error */
1165 			parent_pf->cgx_users = start ? parent_pf->cgx_users  - 1
1166 					       : parent_pf->cgx_users  + 1;
1167 			goto exit;
1168 		}
1169 	}
1170 	pfvf->cgx_in_use = start;
1171 exit:
1172 	mutex_unlock(&rvu->cgx_cfg_lock);
1173 	return err;
1174 }
1175 
rvu_mbox_handler_cgx_set_fec_param(struct rvu * rvu,struct fec_mode * req,struct fec_mode * rsp)1176 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,
1177 				       struct fec_mode *req,
1178 				       struct fec_mode *rsp)
1179 {
1180 	int pf = rvu_get_pf(req->hdr.pcifunc);
1181 	u8 cgx_id, lmac_id;
1182 
1183 	if (!is_pf_cgxmapped(rvu, pf))
1184 		return -EPERM;
1185 
1186 	if (req->fec == OTX2_FEC_OFF)
1187 		req->fec = OTX2_FEC_NONE;
1188 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1189 	rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);
1190 	return 0;
1191 }
1192 
rvu_mbox_handler_cgx_get_aux_link_info(struct rvu * rvu,struct msg_req * req,struct cgx_fw_data * rsp)1193 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,
1194 					   struct cgx_fw_data *rsp)
1195 {
1196 	int pf = rvu_get_pf(req->hdr.pcifunc);
1197 	u8 cgx_id, lmac_id;
1198 
1199 	if (!rvu->fwdata)
1200 		return LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED;
1201 
1202 	if (!is_pf_cgxmapped(rvu, pf))
1203 		return -EPERM;
1204 
1205 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1206 
1207 	if (rvu->hw->lmac_per_cgx == CGX_LMACS_USX)
1208 		memcpy(&rsp->fwdata,
1209 		       &rvu->fwdata->cgx_fw_data_usx[cgx_id][lmac_id],
1210 		       sizeof(struct cgx_lmac_fwdata_s));
1211 	else
1212 		memcpy(&rsp->fwdata,
1213 		       &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],
1214 		       sizeof(struct cgx_lmac_fwdata_s));
1215 
1216 	return 0;
1217 }
1218 
rvu_mbox_handler_cgx_set_link_mode(struct rvu * rvu,struct cgx_set_link_mode_req * req,struct cgx_set_link_mode_rsp * rsp)1219 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
1220 				       struct cgx_set_link_mode_req *req,
1221 				       struct cgx_set_link_mode_rsp *rsp)
1222 {
1223 	int pf = rvu_get_pf(req->hdr.pcifunc);
1224 	u8 cgx_idx, lmac;
1225 	void *cgxd;
1226 
1227 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1228 		return -EPERM;
1229 
1230 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
1231 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
1232 	rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
1233 	return 0;
1234 }
1235 
rvu_mbox_handler_cgx_mac_addr_reset(struct rvu * rvu,struct cgx_mac_addr_reset_req * req,struct msg_rsp * rsp)1236 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req,
1237 					struct msg_rsp *rsp)
1238 {
1239 	int pf = rvu_get_pf(req->hdr.pcifunc);
1240 	u8 cgx_id, lmac_id;
1241 
1242 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1243 		return LMAC_AF_ERR_PERM_DENIED;
1244 
1245 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1246 
1247 	if (rvu_npc_exact_has_match_table(rvu))
1248 		return rvu_npc_exact_mac_addr_reset(rvu, req, rsp);
1249 
1250 	return cgx_lmac_addr_reset(cgx_id, lmac_id);
1251 }
1252 
rvu_mbox_handler_cgx_mac_addr_update(struct rvu * rvu,struct cgx_mac_addr_update_req * req,struct cgx_mac_addr_update_rsp * rsp)1253 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
1254 					 struct cgx_mac_addr_update_req *req,
1255 					 struct cgx_mac_addr_update_rsp *rsp)
1256 {
1257 	int pf = rvu_get_pf(req->hdr.pcifunc);
1258 	u8 cgx_id, lmac_id;
1259 
1260 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1261 		return LMAC_AF_ERR_PERM_DENIED;
1262 
1263 	if (rvu_npc_exact_has_match_table(rvu))
1264 		return rvu_npc_exact_mac_addr_update(rvu, req, rsp);
1265 
1266 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1267 	return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);
1268 }
1269 
rvu_cgx_prio_flow_ctrl_cfg(struct rvu * rvu,u16 pcifunc,u8 tx_pause,u8 rx_pause,u16 pfc_en)1270 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause,
1271 			       u8 rx_pause, u16 pfc_en)
1272 {
1273 	int pf = rvu_get_pf(pcifunc);
1274 	u8 rx_8023 = 0, tx_8023 = 0;
1275 	struct mac_ops *mac_ops;
1276 	u8 cgx_id, lmac_id;
1277 	void *cgxd;
1278 
1279 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1280 	 * if received from other PF/VF simply ACK, nothing to do.
1281 	 */
1282 	if (!is_pf_cgxmapped(rvu, pf))
1283 		return -ENODEV;
1284 
1285 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1286 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1287 	mac_ops = get_mac_ops(cgxd);
1288 
1289 	mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &tx_8023, &rx_8023);
1290 	if (tx_8023 || rx_8023) {
1291 		dev_warn(rvu->dev,
1292 			 "Can not configure PFC as 802.3X pause frames are enabled");
1293 		return LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED;
1294 	}
1295 
1296 	mutex_lock(&rvu->rsrc_lock);
1297 	if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause,
1298 			       pcifunc & RVU_PFVF_FUNC_MASK)) {
1299 		mutex_unlock(&rvu->rsrc_lock);
1300 		return LMAC_AF_ERR_PERM_DENIED;
1301 	}
1302 	mutex_unlock(&rvu->rsrc_lock);
1303 
1304 	return mac_ops->pfc_config(cgxd, lmac_id, tx_pause, rx_pause, pfc_en);
1305 }
1306 
rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu * rvu,struct cgx_pfc_cfg * req,struct cgx_pfc_rsp * rsp)1307 int rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu *rvu,
1308 					    struct cgx_pfc_cfg *req,
1309 					    struct cgx_pfc_rsp *rsp)
1310 {
1311 	int pf = rvu_get_pf(req->hdr.pcifunc);
1312 	struct mac_ops *mac_ops;
1313 	u8 cgx_id, lmac_id;
1314 	void *cgxd;
1315 	int err;
1316 
1317 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
1318 	 * if received from other PF/VF simply ACK, nothing to do.
1319 	 */
1320 	if (!is_pf_cgxmapped(rvu, pf))
1321 		return -ENODEV;
1322 
1323 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1324 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
1325 	mac_ops = get_mac_ops(cgxd);
1326 
1327 	err = rvu_cgx_prio_flow_ctrl_cfg(rvu, req->hdr.pcifunc, req->tx_pause,
1328 					 req->rx_pause, req->pfc_en);
1329 
1330 	mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause);
1331 	return err;
1332 }
1333 
rvu_mac_reset(struct rvu * rvu,u16 pcifunc)1334 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc)
1335 {
1336 	int pf = rvu_get_pf(pcifunc);
1337 	struct mac_ops *mac_ops;
1338 	struct cgx *cgxd;
1339 	u8 cgx, lmac;
1340 
1341 	if (!is_pf_cgxmapped(rvu, pf))
1342 		return;
1343 
1344 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac);
1345 	cgxd = rvu_cgx_pdata(cgx, rvu);
1346 	mac_ops = get_mac_ops(cgxd);
1347 
1348 	if (mac_ops->mac_reset(cgxd, lmac, !is_vf(pcifunc)))
1349 		dev_err(rvu->dev, "Failed to reset MAC\n");
1350 }
1351