1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #if defined(__FreeBSD__)
6 #define LINUXKPI_PARAM_PREFIX rtw89_debug_
7 #endif
8
9 #include <linux/vmalloc.h>
10
11 #include "coex.h"
12 #include "debug.h"
13 #include "fw.h"
14 #include "mac.h"
15 #include "pci.h"
16 #include "phy.h"
17 #include "ps.h"
18 #include "reg.h"
19 #include "sar.h"
20 #include "util.h"
21 #if defined(__FreeBSD__)
22 #ifdef CONFIG_RTW89_DEBUGFS
23 #include <linux/debugfs.h>
24 #endif
25 #endif
26
27 #ifdef CONFIG_RTW89_DEBUGMSG
28 unsigned int rtw89_debug_mask;
29 EXPORT_SYMBOL(rtw89_debug_mask);
30 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644);
31 MODULE_PARM_DESC(debug_mask, "Debugging mask");
32 #endif
33
34 #ifdef CONFIG_RTW89_DEBUGFS
35 struct rtw89_debugfs_priv_opt {
36 bool rlock:1;
37 bool wlock:1;
38 size_t rsize;
39 };
40
41 struct rtw89_debugfs_priv {
42 struct rtw89_dev *rtwdev;
43 ssize_t (*cb_read)(struct rtw89_dev *rtwdev,
44 struct rtw89_debugfs_priv *debugfs_priv,
45 char *buf, size_t bufsz);
46 ssize_t (*cb_write)(struct rtw89_dev *rtwdev,
47 struct rtw89_debugfs_priv *debugfs_priv,
48 const char *buf, size_t count);
49 struct rtw89_debugfs_priv_opt opt;
50 union {
51 u32 cb_data;
52 struct {
53 u32 addr;
54 u32 len;
55 } read_reg;
56 struct {
57 u32 addr;
58 u32 mask;
59 u8 path;
60 } read_rf;
61 struct {
62 u8 ss_dbg:1;
63 u8 dle_dbg:1;
64 u8 dmac_dbg:1;
65 u8 cmac_dbg:1;
66 u8 dbg_port:1;
67 } dbgpkg_en;
68 struct {
69 u32 start;
70 u32 len;
71 u8 sel;
72 } mac_mem;
73 };
74 ssize_t rused;
75 char *rbuf;
76 };
77
78 struct rtw89_debugfs {
79 struct rtw89_debugfs_priv read_reg;
80 struct rtw89_debugfs_priv write_reg;
81 struct rtw89_debugfs_priv read_rf;
82 struct rtw89_debugfs_priv write_rf;
83 struct rtw89_debugfs_priv rf_reg_dump;
84 struct rtw89_debugfs_priv txpwr_table;
85 struct rtw89_debugfs_priv mac_reg_dump;
86 struct rtw89_debugfs_priv mac_mem_dump;
87 struct rtw89_debugfs_priv mac_dbg_port_dump;
88 struct rtw89_debugfs_priv send_h2c;
89 struct rtw89_debugfs_priv early_h2c;
90 struct rtw89_debugfs_priv fw_crash;
91 struct rtw89_debugfs_priv btc_info;
92 struct rtw89_debugfs_priv btc_manual;
93 struct rtw89_debugfs_priv fw_log_manual;
94 struct rtw89_debugfs_priv phy_info;
95 struct rtw89_debugfs_priv stations;
96 struct rtw89_debugfs_priv disable_dm;
97 struct rtw89_debugfs_priv mlo_mode;
98 };
99
100 struct rtw89_debugfs_iter_data {
101 char *buf;
102 size_t bufsz;
103 int written_sz;
104 };
105
rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data * iter_data,char * buf,size_t bufsz)106 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data,
107 char *buf, size_t bufsz)
108 {
109 iter_data->buf = buf;
110 iter_data->bufsz = bufsz;
111 iter_data->written_sz = 0;
112 }
113
rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data * iter_data,char * buf,size_t bufsz,int written_sz)114 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data,
115 char *buf, size_t bufsz, int written_sz)
116 {
117 iter_data->buf = buf;
118 iter_data->bufsz = bufsz;
119 iter_data->written_sz += written_sz;
120 }
121
122 static const u16 rtw89_rate_info_bw_to_mhz_map[] = {
123 [RATE_INFO_BW_20] = 20,
124 [RATE_INFO_BW_40] = 40,
125 [RATE_INFO_BW_80] = 80,
126 [RATE_INFO_BW_160] = 160,
127 [RATE_INFO_BW_320] = 320,
128 };
129
rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)130 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)
131 {
132 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map))
133 return rtw89_rate_info_bw_to_mhz_map[bw];
134
135 return 0;
136 }
137
rtw89_debugfs_file_read_helper(struct wiphy * wiphy,struct file * file,char * buf,size_t bufsz,void * data)138 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file,
139 char *buf, size_t bufsz, void *data)
140 {
141 struct rtw89_debugfs_priv *debugfs_priv = data;
142 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
143 ssize_t n;
144
145 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz);
146 rtw89_might_trailing_ellipsis(buf, bufsz, n);
147
148 return n;
149 }
150
rtw89_debugfs_file_read(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)151 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf,
152 size_t count, loff_t *ppos)
153 {
154 struct rtw89_debugfs_priv *debugfs_priv = file->private_data;
155 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt;
156 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
157 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE;
158 char *buf;
159 ssize_t n;
160
161 if (!debugfs_priv->rbuf)
162 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL);
163
164 buf = debugfs_priv->rbuf;
165 if (!buf)
166 return -ENOMEM;
167
168 if (*ppos) {
169 n = debugfs_priv->rused;
170 goto out;
171 }
172
173 if (opt->rlock) {
174 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz,
175 userbuf, count, ppos,
176 rtw89_debugfs_file_read_helper,
177 debugfs_priv);
178 debugfs_priv->rused = n;
179
180 return n;
181 }
182
183 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz,
184 debugfs_priv);
185 debugfs_priv->rused = n;
186
187 out:
188 return simple_read_from_buffer(userbuf, count, ppos, buf, n);
189 }
190
rtw89_debugfs_file_write_helper(struct wiphy * wiphy,struct file * file,char * buf,size_t count,void * data)191 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file,
192 char *buf, size_t count, void *data)
193 {
194 struct rtw89_debugfs_priv *debugfs_priv = data;
195 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
196
197 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count);
198 }
199
rtw89_debugfs_file_write(struct file * file,const char __user * userbuf,size_t count,loff_t * loff)200 static ssize_t rtw89_debugfs_file_write(struct file *file,
201 const char __user *userbuf,
202 size_t count, loff_t *loff)
203 {
204 struct rtw89_debugfs_priv *debugfs_priv = file->private_data;
205 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt;
206 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
207 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL);
208 ssize_t n;
209
210 if (!buf)
211 return -ENOMEM;
212
213 if (opt->wlock) {
214 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy,
215 file, buf, count + 1,
216 userbuf, count,
217 rtw89_debugfs_file_write_helper,
218 debugfs_priv);
219 return n;
220 }
221
222 if (copy_from_user(buf, userbuf, count))
223 return -EFAULT;
224
225 buf[count] = '\0';
226
227 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count);
228 }
229
230 static const struct debugfs_short_fops file_ops_single_r = {
231 .read = rtw89_debugfs_file_read,
232 .llseek = generic_file_llseek,
233 };
234
235 static const struct debugfs_short_fops file_ops_common_rw = {
236 .read = rtw89_debugfs_file_read,
237 .write = rtw89_debugfs_file_write,
238 .llseek = generic_file_llseek,
239 };
240
241 static const struct debugfs_short_fops file_ops_single_w = {
242 .write = rtw89_debugfs_file_write,
243 .llseek = generic_file_llseek,
244 };
245
246 static ssize_t
rtw89_debug_priv_read_reg_select(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)247 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev,
248 struct rtw89_debugfs_priv *debugfs_priv,
249 const char *buf, size_t count)
250 {
251 u32 addr, len;
252 int num;
253
254 num = sscanf(buf, "%x %x", &addr, &len);
255 if (num != 2) {
256 rtw89_info(rtwdev, "invalid format: <addr> <len>\n");
257 return -EINVAL;
258 }
259
260 debugfs_priv->read_reg.addr = addr;
261 debugfs_priv->read_reg.len = len;
262
263 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr);
264
265 return count;
266 }
267
268 static
rtw89_debug_priv_read_reg_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)269 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev,
270 struct rtw89_debugfs_priv *debugfs_priv,
271 char *buf, size_t bufsz)
272 {
273 char *p = buf, *end = buf + bufsz;
274 u32 addr, addr_end, data, k;
275 u32 len;
276
277 len = debugfs_priv->read_reg.len;
278 addr = debugfs_priv->read_reg.addr;
279
280 if (len > 4)
281 goto ndata;
282
283 switch (len) {
284 case 1:
285 data = rtw89_read8(rtwdev, addr);
286 break;
287 case 2:
288 data = rtw89_read16(rtwdev, addr);
289 break;
290 case 4:
291 data = rtw89_read32(rtwdev, addr);
292 break;
293 default:
294 rtw89_info(rtwdev, "invalid read reg len %d\n", len);
295 return -EINVAL;
296 }
297
298 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len,
299 addr, data);
300
301 return p - buf;
302
303 ndata:
304 addr_end = addr + len;
305
306 for (; addr < addr_end; addr += 16) {
307 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr);
308 for (k = 0; k < 16; k += 4) {
309 data = rtw89_read32(rtwdev, addr + k);
310 p += scnprintf(p, end - p, "%08x ", data);
311 }
312 p += scnprintf(p, end - p, "\n");
313 }
314
315 return p - buf;
316 }
317
318 static
rtw89_debug_priv_write_reg_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)319 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev,
320 struct rtw89_debugfs_priv *debugfs_priv,
321 const char *buf, size_t count)
322 {
323 u32 addr, val, len;
324 int num;
325
326 num = sscanf(buf, "%x %x %x", &addr, &val, &len);
327 if (num != 3) {
328 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n");
329 return -EINVAL;
330 }
331
332 switch (len) {
333 case 1:
334 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val);
335 rtw89_write8(rtwdev, addr, (u8)val);
336 break;
337 case 2:
338 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val);
339 rtw89_write16(rtwdev, addr, (u16)val);
340 break;
341 case 4:
342 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val);
343 rtw89_write32(rtwdev, addr, (u32)val);
344 break;
345 default:
346 rtw89_info(rtwdev, "invalid read write len %d\n", len);
347 break;
348 }
349
350 return count;
351 }
352
353 static ssize_t
rtw89_debug_priv_read_rf_select(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)354 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev,
355 struct rtw89_debugfs_priv *debugfs_priv,
356 const char *buf, size_t count)
357 {
358 u32 addr, mask;
359 u8 path;
360 int num;
361
362 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask);
363 if (num != 3) {
364 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n");
365 return -EINVAL;
366 }
367
368 if (path >= rtwdev->chip->rf_path_num) {
369 rtw89_info(rtwdev, "wrong rf path\n");
370 return -EINVAL;
371 }
372 debugfs_priv->read_rf.addr = addr;
373 debugfs_priv->read_rf.mask = mask;
374 debugfs_priv->read_rf.path = path;
375
376 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr);
377
378 return count;
379 }
380
381 static
rtw89_debug_priv_read_rf_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)382 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev,
383 struct rtw89_debugfs_priv *debugfs_priv,
384 char *buf, size_t bufsz)
385 {
386 char *p = buf, *end = buf + bufsz;
387 u32 addr, data, mask;
388 u8 path;
389
390 addr = debugfs_priv->read_rf.addr;
391 mask = debugfs_priv->read_rf.mask;
392 path = debugfs_priv->read_rf.path;
393
394 data = rtw89_read_rf(rtwdev, path, addr, mask);
395
396 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n",
397 path, addr, data);
398
399 return p - buf;
400 }
401
402 static
rtw89_debug_priv_write_rf_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)403 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev,
404 struct rtw89_debugfs_priv *debugfs_priv,
405 const char *buf, size_t count)
406 {
407 u32 addr, val, mask;
408 u8 path;
409 int num;
410
411 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val);
412 if (num != 4) {
413 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n");
414 return -EINVAL;
415 }
416
417 if (path >= rtwdev->chip->rf_path_num) {
418 rtw89_info(rtwdev, "wrong rf path\n");
419 return -EINVAL;
420 }
421
422 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n",
423 path, addr, val, mask);
424 rtw89_write_rf(rtwdev, path, addr, mask, val);
425
426 return count;
427 }
428
429 static
rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)430 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev,
431 struct rtw89_debugfs_priv *debugfs_priv,
432 char *buf, size_t bufsz)
433 {
434 const struct rtw89_chip_info *chip = rtwdev->chip;
435 char *p = buf, *end = buf + bufsz;
436 u32 addr, offset, data;
437 u8 path;
438
439 for (path = 0; path < chip->rf_path_num; path++) {
440 p += scnprintf(p, end - p, "RF path %d:\n\n", path);
441 for (addr = 0; addr < 0x100; addr += 4) {
442 p += scnprintf(p, end - p, "0x%08x: ", addr);
443 for (offset = 0; offset < 4; offset++) {
444 data = rtw89_read_rf(rtwdev, path,
445 addr + offset, RFREG_MASK);
446 p += scnprintf(p, end - p, "0x%05x ", data);
447 }
448 p += scnprintf(p, end - p, "\n");
449 }
450 p += scnprintf(p, end - p, "\n");
451 }
452
453 return p - buf;
454 }
455
456 struct txpwr_ent {
457 bool nested;
458 union {
459 const char *txt;
460 const struct txpwr_ent *ptr;
461 };
462 u8 len;
463 };
464
465 struct txpwr_map {
466 const struct txpwr_ent *ent;
467 u8 size;
468 u32 addr_from;
469 u32 addr_to;
470 u32 addr_to_1ss;
471 };
472
473 #define __GEN_TXPWR_ENT_NESTED(_e) \
474 { .nested = true, .ptr = __txpwr_ent_##_e, \
475 .len = ARRAY_SIZE(__txpwr_ent_##_e) }
476
477 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t }
478
479 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
480 { .len = 2, .txt = _t "\t- " _e0 " " _e1 }
481
482 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \
483 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 }
484
485 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \
486 { .len = 8, .txt = _t "\t- " \
487 _e0 " " _e1 " " _e2 " " _e3 " " \
488 _e4 " " _e5 " " _e6 " " _e7 }
489
490 static const struct txpwr_ent __txpwr_ent_byr_ax[] = {
491 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
492 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
493 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
494 /* 1NSS */
495 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
496 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
497 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
498 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
499 /* 2NSS */
500 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
501 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
502 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
503 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
504 };
505
506 #if defined(__linux__)
507 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) ==
508 #elif defined(__FreeBSD__)
509 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) ==
510 #endif
511 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4));
512
513 static const struct txpwr_map __txpwr_map_byr_ax = {
514 .ent = __txpwr_ent_byr_ax,
515 .size = ARRAY_SIZE(__txpwr_ent_byr_ax),
516 .addr_from = R_AX_PWR_BY_RATE,
517 .addr_to = R_AX_PWR_BY_RATE_MAX,
518 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX,
519 };
520
521 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = {
522 /* 1TX */
523 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"),
524 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"),
525 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"),
526 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"),
527 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"),
528 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"),
529 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"),
530 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"),
531 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"),
532 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"),
533 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"),
534 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"),
535 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"),
536 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"),
537 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"),
538 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"),
539 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"),
540 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"),
541 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"),
542 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"),
543 /* 2TX */
544 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"),
545 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"),
546 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"),
547 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"),
548 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"),
549 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"),
550 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"),
551 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"),
552 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"),
553 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"),
554 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"),
555 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"),
556 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"),
557 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"),
558 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"),
559 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"),
560 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"),
561 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"),
562 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"),
563 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"),
564 };
565
566 #if defined(__linux__)
567 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) ==
568 #elif defined(__FreeBSD__)
569 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) ==
570 #endif
571 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4));
572
573 static const struct txpwr_map __txpwr_map_lmt_ax = {
574 .ent = __txpwr_ent_lmt_ax,
575 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax),
576 .addr_from = R_AX_PWR_LMT,
577 .addr_to = R_AX_PWR_LMT_MAX,
578 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX,
579 };
580
581 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = {
582 /* 1TX */
583 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
584 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
585 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
586 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
587 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
588 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
589 /* 2TX */
590 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
591 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
592 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
593 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
594 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
595 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
596 };
597
598 #if defined(__linux__)
599 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) ==
600 #elif defined(__FreeBSD__)
601 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) ==
602 #endif
603 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4));
604
605 static const struct txpwr_map __txpwr_map_lmt_ru_ax = {
606 .ent = __txpwr_ent_lmt_ru_ax,
607 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax),
608 .addr_from = R_AX_PWR_RU_LMT,
609 .addr_to = R_AX_PWR_RU_LMT_MAX,
610 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX,
611 };
612
613 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = {
614 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
615 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
616 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
617 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"),
618 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
619 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
620 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
621 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
622 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"),
623 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
624 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
625 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
626 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
627 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"),
628 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
629 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
630 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
631 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
632 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"),
633 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
634 };
635
636 static const struct txpwr_ent __txpwr_ent_byr_be[] = {
637 __GEN_TXPWR_ENT0("BW20"),
638 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
639 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
640 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
641 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
642 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
643 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
644
645 __GEN_TXPWR_ENT0("BW40"),
646 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
647 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
648 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
649 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
650 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
651 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
652
653 /* there is no CCK section after BW80 */
654 __GEN_TXPWR_ENT0("BW80"),
655 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
656 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
657 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
658 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
659 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
660
661 __GEN_TXPWR_ENT0("BW160"),
662 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
663 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
664 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
665 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
666 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
667
668 __GEN_TXPWR_ENT0("BW320"),
669 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
670 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
671 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
672 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
673 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
674 };
675
676 static const struct txpwr_map __txpwr_map_byr_be = {
677 .ent = __txpwr_ent_byr_be,
678 .size = ARRAY_SIZE(__txpwr_ent_byr_be),
679 .addr_from = R_BE_PWR_BY_RATE,
680 .addr_to = R_BE_PWR_BY_RATE_MAX,
681 .addr_to_1ss = 0, /* not support */
682 };
683
684 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = {
685 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"),
686 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"),
687 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"),
688 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"),
689 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"),
690 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"),
691 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"),
692 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"),
693 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"),
694 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"),
695 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"),
696 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"),
697 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"),
698 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"),
699 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"),
700 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"),
701 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"),
702 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"),
703 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"),
704 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"),
705 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"),
706 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"),
707 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"),
708 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"),
709 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"),
710 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"),
711 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"),
712 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"),
713 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"),
714 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"),
715 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"),
716 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"),
717 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"),
718 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"),
719 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"),
720 };
721
722 static const struct txpwr_ent __txpwr_ent_lmt_be[] = {
723 __GEN_TXPWR_ENT0("1TX"),
724 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"),
725 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"),
726 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"),
727 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be),
728
729 __GEN_TXPWR_ENT0("2TX"),
730 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"),
731 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"),
732 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"),
733 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be),
734 };
735
736 static const struct txpwr_map __txpwr_map_lmt_be = {
737 .ent = __txpwr_ent_lmt_be,
738 .size = ARRAY_SIZE(__txpwr_ent_lmt_be),
739 .addr_from = R_BE_PWR_LMT,
740 .addr_to = R_BE_PWR_LMT_MAX,
741 .addr_to_1ss = 0, /* not support */
742 };
743
744 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = {
745 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
746 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
747 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
748 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
749 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
750 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
751 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
752 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
753 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
754 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
755 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
756 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
757 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
758 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
759 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
760 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
761 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
762 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
763 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
764 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
765 };
766
767 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = {
768 __GEN_TXPWR_ENT0("1TX"),
769 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be),
770
771 __GEN_TXPWR_ENT0("2TX"),
772 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be),
773 };
774
775 static const struct txpwr_map __txpwr_map_lmt_ru_be = {
776 .ent = __txpwr_ent_lmt_ru_be,
777 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be),
778 .addr_from = R_BE_PWR_RU_LMT,
779 .addr_to = R_BE_PWR_RU_LMT_MAX,
780 .addr_to_1ss = 0, /* not support */
781 };
782
783 static unsigned int
__print_txpwr_ent(char * buf,size_t bufsz,const struct txpwr_ent * ent,const s8 * bufp,const unsigned int cur,unsigned int * ate)784 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent,
785 const s8 *bufp, const unsigned int cur, unsigned int *ate)
786 {
787 char *p = buf, *end = buf + bufsz;
788 unsigned int cnt, i;
789 unsigned int eaten;
790 char *fmt;
791
792 if (ent->nested) {
793 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten)
794 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp,
795 cur + cnt, &eaten);
796 *ate = cnt;
797 goto out;
798 }
799
800 switch (ent->len) {
801 case 0:
802 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt);
803 *ate = 0;
804 goto out;
805 case 2:
806 fmt = "%s\t| %3d, %3d,\t\tdBm\n";
807 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur],
808 bufp[cur + 1]);
809 *ate = 2;
810 goto out;
811 case 4:
812 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n";
813 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur],
814 bufp[cur + 1],
815 bufp[cur + 2], bufp[cur + 3]);
816 *ate = 4;
817 goto out;
818 case 8:
819 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n";
820 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur],
821 bufp[cur + 1],
822 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4],
823 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]);
824 *ate = 8;
825 goto out;
826 default:
827 return 0;
828 }
829
830 out:
831 return p - buf;
832 }
833
__print_txpwr_map(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct txpwr_map * map)834 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
835 const struct txpwr_map *map)
836 {
837 u8 fct = rtwdev->chip->txpwr_factor_mac;
838 u8 path_num = rtwdev->chip->rf_path_num;
839 char *p = buf, *end = buf + bufsz;
840 unsigned int cur, i;
841 unsigned int eaten;
842 u32 max_valid_addr;
843 u32 val, addr;
844 s8 *bufp, tmp;
845 int ret;
846
847 bufp = vzalloc(map->addr_to - map->addr_from + 4);
848 if (!bufp)
849 return -ENOMEM;
850
851 if (path_num == 1)
852 max_valid_addr = map->addr_to_1ss;
853 else
854 max_valid_addr = map->addr_to;
855
856 if (max_valid_addr == 0)
857 return -EOPNOTSUPP;
858
859 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) {
860 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
861 if (ret)
862 val = MASKDWORD;
863
864 cur = addr - map->addr_from;
865 for (i = 0; i < 4; i++, val >>= 8) {
866 /* signed 7 bits, and reserved BIT(7) */
867 tmp = sign_extend32(val, 6);
868 bufp[cur + i] = tmp >> fct;
869 }
870 }
871
872 for (cur = 0, i = 0; i < map->size; i++, cur += eaten)
873 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten);
874
875 vfree(bufp);
876 return p - buf;
877 }
878
__print_regd(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_chan * chan)879 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
880 const struct rtw89_chan *chan)
881 {
882 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
883 char *p = buf, *end = buf + bufsz;
884 u8 band = chan->band_type;
885 u8 regd = rtw89_regd_get(rtwdev, band);
886
887 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd));
888 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n",
889 str_yes_no(regulatory->txpwr_uk_follow_etsi));
890
891 return p - buf;
892 }
893
894 struct dbgfs_txpwr_table {
895 const struct txpwr_map *byr;
896 const struct txpwr_map *lmt;
897 const struct txpwr_map *lmt_ru;
898 };
899
900 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = {
901 .byr = &__txpwr_map_byr_ax,
902 .lmt = &__txpwr_map_lmt_ax,
903 .lmt_ru = &__txpwr_map_lmt_ru_ax,
904 };
905
906 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = {
907 .byr = &__txpwr_map_byr_be,
908 .lmt = &__txpwr_map_lmt_be,
909 .lmt_ru = &__txpwr_map_lmt_ru_be,
910 };
911
912 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = {
913 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax,
914 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be,
915 };
916
917 static
rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_chan * chan)918 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev,
919 char *buf, size_t bufsz,
920 const struct rtw89_chan *chan)
921 {
922 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
923 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe;
924 char *p = buf, *end = buf + bufsz;
925
926 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n",
927 chan->band_type, chan->channel, chan->band_width);
928
929 p += scnprintf(p, end - p, "[Regulatory] ");
930 p += __print_regd(rtwdev, p, end - p, chan);
931
932 if (chan->band_type == RTW89_BAND_6G) {
933 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n",
934 regulatory->reg_6ghz_power);
935
936 if (tpe6->valid)
937 p += scnprintf(p, end - p, "[TPE] %d dBm\n",
938 tpe6->constraint);
939 }
940
941 return p - buf;
942 }
943
944 static
rtw89_debug_priv_txpwr_table_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)945 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev,
946 struct rtw89_debugfs_priv *debugfs_priv,
947 char *buf, size_t bufsz)
948 {
949 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
950 struct rtw89_sar_parm sar_parm = {};
951 const struct dbgfs_txpwr_table *tbl;
952 const struct rtw89_chan *chan;
953 char *p = buf, *end = buf + bufsz;
954 ssize_t n;
955
956 lockdep_assert_wiphy(rtwdev->hw->wiphy);
957
958 rtw89_leave_ps_mode(rtwdev);
959 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
960 sar_parm.center_freq = chan->freq;
961
962 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan);
963
964 p += scnprintf(p, end - p, "[SAR]\n");
965 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm);
966
967 p += scnprintf(p, end - p, "[TAS]\n");
968 p += rtw89_print_tas(rtwdev, p, end - p);
969
970 p += scnprintf(p, end - p, "[DAG]\n");
971 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan);
972
973 tbl = dbgfs_txpwr_tables[chip_gen];
974 if (!tbl)
975 return -EOPNOTSUPP;
976
977 p += scnprintf(p, end - p, "\n[TX power byrate]\n");
978 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr);
979 if (n < 0)
980 return n;
981 p += n;
982
983 p += scnprintf(p, end - p, "\n[TX power limit]\n");
984 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt);
985 if (n < 0)
986 return n;
987 p += n;
988
989 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n");
990 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru);
991 if (n < 0)
992 return n;
993 p += n;
994
995 return p - buf;
996 }
997
998 static ssize_t
rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)999 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev,
1000 struct rtw89_debugfs_priv *debugfs_priv,
1001 const char *buf, size_t count)
1002 {
1003 const struct rtw89_chip_info *chip = rtwdev->chip;
1004 int sel;
1005 int ret;
1006
1007 ret = kstrtoint(buf, 0, &sel);
1008 if (ret)
1009 return ret;
1010
1011 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) {
1012 rtw89_info(rtwdev, "invalid args: %d\n", sel);
1013 return -EINVAL;
1014 }
1015
1016 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) {
1017 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel,
1018 chip->chip_id);
1019 return -EINVAL;
1020 }
1021
1022 debugfs_priv->cb_data = sel;
1023 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data);
1024
1025 return count;
1026 }
1027
1028 #define RTW89_MAC_PAGE_SIZE 0x100
1029
1030 static
rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)1031 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev,
1032 struct rtw89_debugfs_priv *debugfs_priv,
1033 char *buf, size_t bufsz)
1034 {
1035 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data;
1036 char *p = buf, *end = buf + bufsz;
1037 u32 start, end_addr;
1038 u32 i, j, k, page;
1039 u32 val;
1040
1041 switch (reg_sel) {
1042 case RTW89_DBG_SEL_MAC_00:
1043 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n");
1044 start = 0x000;
1045 end_addr = 0x014;
1046 break;
1047 case RTW89_DBG_SEL_MAC_30:
1048 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n");
1049 start = 0x030;
1050 end_addr = 0x033;
1051 break;
1052 case RTW89_DBG_SEL_MAC_40:
1053 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n");
1054 start = 0x040;
1055 end_addr = 0x07f;
1056 break;
1057 case RTW89_DBG_SEL_MAC_80:
1058 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n");
1059 start = 0x080;
1060 end_addr = 0x09f;
1061 break;
1062 case RTW89_DBG_SEL_MAC_C0:
1063 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n");
1064 start = 0x0c0;
1065 end_addr = 0x0df;
1066 break;
1067 case RTW89_DBG_SEL_MAC_E0:
1068 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n");
1069 start = 0x0e0;
1070 end_addr = 0x0ff;
1071 break;
1072 case RTW89_DBG_SEL_BB:
1073 p += scnprintf(p, end - p, "Debug selected BB register\n");
1074 start = 0x100;
1075 end_addr = 0x17f;
1076 break;
1077 case RTW89_DBG_SEL_IQK:
1078 p += scnprintf(p, end - p, "Debug selected IQK register\n");
1079 start = 0x180;
1080 end_addr = 0x1bf;
1081 break;
1082 case RTW89_DBG_SEL_RFC:
1083 p += scnprintf(p, end - p, "Debug selected RFC register\n");
1084 start = 0x1c0;
1085 end_addr = 0x1ff;
1086 break;
1087 default:
1088 p += scnprintf(p, end - p, "Selected invalid register page\n");
1089 return -EINVAL;
1090 }
1091
1092 for (i = start; i <= end_addr; i++) {
1093 page = i << 8;
1094 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) {
1095 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j);
1096 for (k = 0; k < 4; k++) {
1097 val = rtw89_read32(rtwdev, j + (k << 2));
1098 p += scnprintf(p, end - p, "%08x ", val);
1099 }
1100 p += scnprintf(p, end - p, "\n");
1101 }
1102 }
1103
1104 return p - buf;
1105 }
1106
1107 static ssize_t
rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)1108 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev,
1109 struct rtw89_debugfs_priv *debugfs_priv,
1110 const char *buf, size_t count)
1111 {
1112 u32 sel, start_addr, len;
1113 int num;
1114
1115 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len);
1116 if (num != 3) {
1117 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n");
1118 return -EINVAL;
1119 }
1120
1121 debugfs_priv->mac_mem.sel = sel;
1122 debugfs_priv->mac_mem.start = start_addr;
1123 debugfs_priv->mac_mem.len = len;
1124
1125 rtw89_info(rtwdev, "select mem %d start %d len %d\n",
1126 sel, start_addr, len);
1127
1128 return count;
1129 }
1130
rtw89_debug_dump_mac_mem(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,u8 sel,u32 start_addr,u32 len)1131 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev,
1132 char *buf, size_t bufsz,
1133 u8 sel, u32 start_addr, u32 len)
1134 {
1135 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1136 u32 filter_model_addr = mac->filter_model_addr;
1137 u32 indir_access_addr = mac->indir_access_addr;
1138 u32 mem_page_size = mac->mem_page_size;
1139 u32 base_addr, start_page, residue;
1140 char *p = buf, *end = buf + bufsz;
1141 u32 i, j, pp, pages;
1142 u32 dump_len, remain;
1143 u32 val;
1144
1145 remain = len;
1146 pages = len / mem_page_size + 1;
1147 start_page = start_addr / mem_page_size;
1148 residue = start_addr % mem_page_size;
1149 base_addr = mac->mem_base_addrs[sel];
1150 base_addr += start_page * mem_page_size;
1151
1152 for (pp = 0; pp < pages; pp++) {
1153 dump_len = min_t(u32, remain, mem_page_size);
1154 rtw89_write32(rtwdev, filter_model_addr, base_addr);
1155 for (i = indir_access_addr + residue;
1156 i < indir_access_addr + dump_len;) {
1157 p += scnprintf(p, end - p, "%08xh:", i);
1158 for (j = 0;
1159 j < 4 && i < indir_access_addr + dump_len;
1160 j++, i += 4) {
1161 val = rtw89_read32(rtwdev, i);
1162 p += scnprintf(p, end - p, " %08x", val);
1163 remain -= 4;
1164 }
1165 p += scnprintf(p, end - p, "\n");
1166 }
1167 base_addr += mem_page_size;
1168 }
1169
1170 return p - buf;
1171 }
1172
1173 static ssize_t
rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)1174 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev,
1175 struct rtw89_debugfs_priv *debugfs_priv,
1176 char *buf, size_t bufsz)
1177 {
1178 char *p = buf, *end = buf + bufsz;
1179 bool grant_read = false;
1180
1181 lockdep_assert_wiphy(rtwdev->hw->wiphy);
1182
1183 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
1184 return -ENOENT;
1185
1186 if (rtwdev->chip->chip_id == RTL8852C) {
1187 switch (debugfs_priv->mac_mem.sel) {
1188 case RTW89_MAC_MEM_TXD_FIFO_0_V1:
1189 case RTW89_MAC_MEM_TXD_FIFO_1_V1:
1190 case RTW89_MAC_MEM_TXDATA_FIFO_0:
1191 case RTW89_MAC_MEM_TXDATA_FIFO_1:
1192 grant_read = true;
1193 break;
1194 default:
1195 break;
1196 }
1197 }
1198
1199 rtw89_leave_ps_mode(rtwdev);
1200 if (grant_read)
1201 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
1202 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p,
1203 debugfs_priv->mac_mem.sel,
1204 debugfs_priv->mac_mem.start,
1205 debugfs_priv->mac_mem.len);
1206 if (grant_read)
1207 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
1208
1209 return p - buf;
1210 }
1211
1212 static ssize_t
rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)1213 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev,
1214 struct rtw89_debugfs_priv *debugfs_priv,
1215 const char *buf, size_t count)
1216 {
1217 int sel, set;
1218 int num;
1219 bool enable;
1220
1221 num = sscanf(buf, "%d %d", &sel, &set);
1222 if (num != 2) {
1223 rtw89_info(rtwdev, "invalid format: <sel> <set>\n");
1224 return -EINVAL;
1225 }
1226
1227 enable = set != 0;
1228 switch (sel) {
1229 case 0:
1230 debugfs_priv->dbgpkg_en.ss_dbg = enable;
1231 break;
1232 case 1:
1233 debugfs_priv->dbgpkg_en.dle_dbg = enable;
1234 break;
1235 case 2:
1236 debugfs_priv->dbgpkg_en.dmac_dbg = enable;
1237 break;
1238 case 3:
1239 debugfs_priv->dbgpkg_en.cmac_dbg = enable;
1240 break;
1241 case 4:
1242 debugfs_priv->dbgpkg_en.dbg_port = enable;
1243 break;
1244 default:
1245 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set);
1246 return -EINVAL;
1247 }
1248
1249 rtw89_info(rtwdev, "%s debug port dump %d\n",
1250 enable ? "Enable" : "Disable", sel);
1251
1252 return count;
1253 }
1254
rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)1255 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,
1256 char *buf, size_t bufsz)
1257 {
1258 return 0;
1259 }
1260
rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)1261 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,
1262 char *buf, size_t bufsz)
1263 {
1264 #define DLE_DFI_DUMP(__type, __target, __sel) \
1265 ({ \
1266 u32 __ctrl; \
1267 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \
1268 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \
1269 u32 __data, __val32; \
1270 int __ret; \
1271 \
1272 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \
1273 DLE_DFI_TYPE_##__target) | \
1274 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \
1275 B_AX_WDE_DFI_ACTIVE; \
1276 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \
1277 __ret = read_poll_timeout(rtw89_read32, __val32, \
1278 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \
1279 1000, 50000, false, \
1280 rtwdev, __reg_ctrl); \
1281 if (__ret) { \
1282 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \
1283 #__type, #__target, __sel); \
1284 return __ret; \
1285 } \
1286 \
1287 __data = rtw89_read32(rtwdev, __reg_data); \
1288 __data; \
1289 })
1290
1291 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \
1292 ({ \
1293 u32 __freepg, __pubpg; \
1294 u32 __freepg_head, __freepg_tail, __pubpg_num; \
1295 \
1296 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \
1297 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \
1298 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \
1299 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \
1300 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \
1301 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \
1302 #__type, __freepg_head); \
1303 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \
1304 #__type, __freepg_tail); \
1305 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \
1306 #__type, __pubpg_num); \
1307 })
1308
1309 #define case_QUOTA(__p, __end, __type, __id) \
1310 case __type##_QTAID_##__id: \
1311 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \
1312 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \
1313 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \
1314 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \
1315 #__type, #__id, rsv_pgnum); \
1316 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \
1317 #__type, #__id, use_pgnum); \
1318 break
1319 char *p = buf, *end = buf + bufsz;
1320 u32 quota_id;
1321 u32 val32;
1322 u16 rsv_pgnum, use_pgnum;
1323 int ret;
1324
1325 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
1326 if (ret) {
1327 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n");
1328 goto out;
1329 }
1330
1331 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE);
1332 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE);
1333 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) {
1334 switch (quota_id) {
1335 case_QUOTA(p, end, WDE, HOST_IF);
1336 case_QUOTA(p, end, WDE, WLAN_CPU);
1337 case_QUOTA(p, end, WDE, DATA_CPU);
1338 case_QUOTA(p, end, WDE, PKTIN);
1339 case_QUOTA(p, end, WDE, CPUIO);
1340 }
1341 }
1342 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) {
1343 switch (quota_id) {
1344 case_QUOTA(p, end, PLE, B0_TXPL);
1345 case_QUOTA(p, end, PLE, B1_TXPL);
1346 case_QUOTA(p, end, PLE, C2H);
1347 case_QUOTA(p, end, PLE, H2C);
1348 case_QUOTA(p, end, PLE, WLAN_CPU);
1349 case_QUOTA(p, end, PLE, MPDU);
1350 case_QUOTA(p, end, PLE, CMAC0_RX);
1351 case_QUOTA(p, end, PLE, CMAC1_RX);
1352 case_QUOTA(p, end, PLE, CMAC1_BBRPT);
1353 case_QUOTA(p, end, PLE, WDRLS);
1354 case_QUOTA(p, end, PLE, CPUIO);
1355 }
1356 }
1357
1358 out:
1359 return p - buf;
1360
1361 #undef case_QUOTA
1362 #undef DLE_DFI_DUMP
1363 #undef DLE_DFI_FREE_PAGE_DUMP
1364 }
1365
rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)1366 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
1367 char *buf, size_t bufsz)
1368 {
1369 const struct rtw89_chip_info *chip = rtwdev->chip;
1370 char *p = buf, *end = buf + bufsz;
1371 u32 dmac_err;
1372 int i, ret;
1373
1374 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
1375 if (ret) {
1376 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n");
1377 goto out;
1378 }
1379
1380 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
1381 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
1382 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n",
1383 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
1384
1385 if (dmac_err) {
1386 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
1387 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
1388 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
1389 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
1390 if (chip->chip_id == RTL8852C) {
1391 p += scnprintf(p, end - p,
1392 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
1393 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
1394 p += scnprintf(p, end - p,
1395 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
1396 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
1397 p += scnprintf(p, end - p,
1398 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
1399 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
1400 p += scnprintf(p, end - p,
1401 "R_AX_PLE_DBGERR_STS=0x%08x\n",
1402 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
1403 }
1404 }
1405
1406 if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
1407 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
1408 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
1409 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
1410 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
1411 if (chip->chip_id == RTL8852C)
1412 p += scnprintf(p, end - p,
1413 "R_AX_RPQ_RXBD_IDX=0x%08x\n",
1414 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
1415 else
1416 p += scnprintf(p, end - p,
1417 "R_AX_RPQ_RXBD_IDX=0x%08x\n",
1418 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
1419 }
1420
1421 if (dmac_err & B_AX_WSEC_ERR_FLAG) {
1422 if (chip->chip_id == RTL8852C) {
1423 p += scnprintf(p, end - p,
1424 "R_AX_SEC_ERR_IMR=0x%08x\n",
1425 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
1426 p += scnprintf(p, end - p,
1427 "R_AX_SEC_ERR_ISR=0x%08x\n",
1428 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
1429 p += scnprintf(p, end - p,
1430 "R_AX_SEC_ENG_CTRL=0x%08x\n",
1431 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
1432 p += scnprintf(p, end - p,
1433 "R_AX_SEC_MPDU_PROC=0x%08x\n",
1434 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
1435 p += scnprintf(p, end - p,
1436 "R_AX_SEC_CAM_ACCESS=0x%08x\n",
1437 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
1438 p += scnprintf(p, end - p,
1439 "R_AX_SEC_CAM_RDATA=0x%08x\n",
1440 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
1441 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n",
1442 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
1443 p += scnprintf(p, end - p,
1444 "R_AX_SEC_TX_DEBUG=0x%08x\n",
1445 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
1446 p += scnprintf(p, end - p,
1447 "R_AX_SEC_RX_DEBUG=0x%08x\n",
1448 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
1449
1450 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
1451 B_AX_DBG_SEL0, 0x8B);
1452 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
1453 B_AX_DBG_SEL1, 0x8B);
1454 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
1455 B_AX_SEL_0XC0_MASK, 1);
1456 for (i = 0; i < 0x10; i++) {
1457 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
1458 B_AX_SEC_DBG_PORT_FIELD_MASK, i);
1459 p += scnprintf(p, end - p,
1460 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
1461 i,
1462 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
1463 }
1464 } else {
1465 p += scnprintf(p, end - p,
1466 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
1467 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
1468 p += scnprintf(p, end - p,
1469 "R_AX_SEC_ENG_CTRL=0x%08x\n",
1470 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
1471 p += scnprintf(p, end - p,
1472 "R_AX_SEC_MPDU_PROC=0x%08x\n",
1473 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
1474 p += scnprintf(p, end - p,
1475 "R_AX_SEC_CAM_ACCESS=0x%08x\n",
1476 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
1477 p += scnprintf(p, end - p,
1478 "R_AX_SEC_CAM_RDATA=0x%08x\n",
1479 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
1480 p += scnprintf(p, end - p,
1481 "R_AX_SEC_CAM_WDATA=0x%08x\n",
1482 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
1483 p += scnprintf(p, end - p,
1484 "R_AX_SEC_TX_DEBUG=0x%08x\n",
1485 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
1486 p += scnprintf(p, end - p,
1487 "R_AX_SEC_RX_DEBUG=0x%08x\n",
1488 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
1489 p += scnprintf(p, end - p,
1490 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
1491 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
1492 p += scnprintf(p, end - p,
1493 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
1494 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
1495 }
1496 }
1497
1498 if (dmac_err & B_AX_MPDU_ERR_FLAG) {
1499 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
1500 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
1501 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
1502 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
1503 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
1504 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
1505 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
1506 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
1507 }
1508
1509 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
1510 p += scnprintf(p, end - p,
1511 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
1512 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
1513 p += scnprintf(p, end - p,
1514 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
1515 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
1516 }
1517
1518 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
1519 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n",
1520 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
1521 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n",
1522 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1523 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n",
1524 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
1525 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1526 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1527 }
1528
1529 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
1530 if (chip->chip_id == RTL8852C) {
1531 p += scnprintf(p, end - p,
1532 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
1533 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
1534 p += scnprintf(p, end - p,
1535 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
1536 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
1537 p += scnprintf(p, end - p,
1538 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
1539 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
1540 p += scnprintf(p, end - p,
1541 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
1542 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
1543 } else {
1544 p += scnprintf(p, end - p,
1545 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
1546 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
1547 p += scnprintf(p, end - p,
1548 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
1549 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
1550 }
1551 }
1552
1553 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
1554 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n",
1555 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
1556 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n",
1557 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1558 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n",
1559 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
1560 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1561 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1562 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
1563 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
1564 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
1565 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
1566 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
1567 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
1568 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
1569 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
1570 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
1571 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
1572 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
1573 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
1574 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
1575 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
1576 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
1577 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
1578 if (chip->chip_id == RTL8852C) {
1579 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n",
1580 rtw89_read32(rtwdev, R_AX_RX_CTRL0));
1581 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n",
1582 rtw89_read32(rtwdev, R_AX_RX_CTRL1));
1583 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n",
1584 rtw89_read32(rtwdev, R_AX_RX_CTRL2));
1585 } else {
1586 p += scnprintf(p, end - p,
1587 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
1588 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
1589 p += scnprintf(p, end - p,
1590 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
1591 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
1592 p += scnprintf(p, end - p,
1593 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
1594 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
1595 }
1596 }
1597
1598 if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
1599 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
1600 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
1601 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
1602 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
1603 }
1604
1605 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
1606 p += scnprintf(p, end - p,
1607 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
1608 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
1609 p += scnprintf(p, end - p,
1610 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
1611 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
1612 p += scnprintf(p, end - p,
1613 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
1614 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
1615 p += scnprintf(p, end - p,
1616 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
1617 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
1618 p += scnprintf(p, end - p,
1619 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
1620 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
1621 p += scnprintf(p, end - p,
1622 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
1623 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
1624 }
1625
1626 if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
1627 if (chip->chip_id == RTL8852C) {
1628 p += scnprintf(p, end - p,
1629 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
1630 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
1631 p += scnprintf(p, end - p,
1632 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
1633 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
1634 p += scnprintf(p, end - p,
1635 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
1636 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
1637 p += scnprintf(p, end - p,
1638 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
1639 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
1640 p += scnprintf(p, end - p,
1641 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
1642 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
1643 p += scnprintf(p, end - p,
1644 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
1645 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
1646 } else {
1647 p += scnprintf(p, end - p,
1648 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
1649 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
1650 p += scnprintf(p, end - p,
1651 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
1652 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
1653 p += scnprintf(p, end - p,
1654 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
1655 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
1656 p += scnprintf(p, end - p,
1657 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
1658 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
1659 p += scnprintf(p, end - p,
1660 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
1661 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
1662 }
1663 }
1664
1665 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
1666 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
1667 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
1668 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
1669 rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
1670 }
1671
1672 out:
1673 return p - buf;
1674 }
1675
rtw89_debug_mac_dump_cmac_err(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,enum rtw89_mac_idx band)1676 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev,
1677 char *buf, size_t bufsz,
1678 enum rtw89_mac_idx band)
1679 {
1680 const struct rtw89_chip_info *chip = rtwdev->chip;
1681 char *p = buf, *end = buf + bufsz;
1682 u32 offset = 0;
1683 u32 cmac_err;
1684 int ret;
1685
1686 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
1687 if (ret) {
1688 if (band)
1689 p += scnprintf(p, end - p,
1690 "[CMAC] : CMAC1 not enabled\n");
1691 else
1692 p += scnprintf(p, end - p,
1693 "[CMAC] : CMAC0 not enabled\n");
1694 goto out;
1695 }
1696
1697 if (band)
1698 offset = RTW89_MAC_AX_BAND_REG_OFFSET;
1699
1700 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
1701 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
1702 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
1703 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
1704 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
1705 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band,
1706 rtw89_read32(rtwdev, R_AX_CK_EN + offset));
1707
1708 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
1709 p += scnprintf(p, end - p,
1710 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
1711 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
1712 p += scnprintf(p, end - p,
1713 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
1714 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
1715 }
1716
1717 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
1718 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n",
1719 band,
1720 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
1721 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n",
1722 band,
1723 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
1724 }
1725
1726 if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
1727 if (chip->chip_id == RTL8852C) {
1728 p += scnprintf(p, end - p,
1729 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
1730 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
1731 p += scnprintf(p, end - p,
1732 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n",
1733 band,
1734 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
1735 } else {
1736 p += scnprintf(p, end - p,
1737 "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
1738 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
1739 }
1740 }
1741
1742 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
1743 if (chip->chip_id == RTL8852C) {
1744 p += scnprintf(p, end - p,
1745 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n",
1746 band,
1747 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
1748 p += scnprintf(p, end - p,
1749 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n",
1750 band,
1751 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
1752 } else {
1753 p += scnprintf(p, end - p,
1754 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n",
1755 band,
1756 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
1757 }
1758 }
1759
1760 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
1761 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n",
1762 band,
1763 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
1764 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n",
1765 band,
1766 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
1767 }
1768
1769 if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
1770 if (chip->chip_id == RTL8852C) {
1771 p += scnprintf(p, end - p,
1772 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n",
1773 band,
1774 rtw89_read32(rtwdev,
1775 R_AX_TRXPTCL_ERROR_INDICA + offset));
1776 p += scnprintf(p, end - p,
1777 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n",
1778 band,
1779 rtw89_read32(rtwdev,
1780 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
1781 } else {
1782 p += scnprintf(p, end - p,
1783 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n",
1784 band,
1785 rtw89_read32(rtwdev,
1786 R_AX_TMAC_ERR_IMR_ISR + offset));
1787 }
1788 p += scnprintf(p, end - p,
1789 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
1790 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
1791 }
1792
1793 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
1794 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
1795
1796 out:
1797 return p - buf;
1798 }
1799
rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)1800 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
1801 char *buf, size_t bufsz)
1802 {
1803 char *p = buf, *end = buf + bufsz;
1804
1805 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0);
1806 if (rtwdev->dbcc_en)
1807 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1);
1808
1809 return p - buf;
1810 }
1811
1812 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {
1813 .sel_addr = R_AX_PTCL_DBG,
1814 .sel_byte = 1,
1815 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1816 .srt = 0x00,
1817 .end = 0x3F,
1818 .rd_addr = R_AX_PTCL_DBG_INFO,
1819 .rd_byte = 4,
1820 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1821 };
1822
1823 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {
1824 .sel_addr = R_AX_PTCL_DBG_C1,
1825 .sel_byte = 1,
1826 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1827 .srt = 0x00,
1828 .end = 0x3F,
1829 .rd_addr = R_AX_PTCL_DBG_INFO_C1,
1830 .rd_byte = 4,
1831 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1832 };
1833
1834 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = {
1835 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1836 .sel_byte = 2,
1837 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1838 .srt = 0x0,
1839 .end = 0xD,
1840 .rd_addr = R_AX_DBG_PORT_SEL,
1841 .rd_byte = 4,
1842 .rd_msk = B_AX_DEBUG_ST_MASK
1843 };
1844
1845 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = {
1846 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1847 .sel_byte = 2,
1848 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1849 .srt = 0x0,
1850 .end = 0x5,
1851 .rd_addr = R_AX_DBG_PORT_SEL,
1852 .rd_byte = 4,
1853 .rd_msk = B_AX_DEBUG_ST_MASK
1854 };
1855
1856 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = {
1857 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1858 .sel_byte = 2,
1859 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1860 .srt = 0x0,
1861 .end = 0x9,
1862 .rd_addr = R_AX_DBG_PORT_SEL,
1863 .rd_byte = 4,
1864 .rd_msk = B_AX_DEBUG_ST_MASK
1865 };
1866
1867 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = {
1868 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1869 .sel_byte = 2,
1870 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1871 .srt = 0x0,
1872 .end = 0x3,
1873 .rd_addr = R_AX_DBG_PORT_SEL,
1874 .rd_byte = 4,
1875 .rd_msk = B_AX_DEBUG_ST_MASK
1876 };
1877
1878 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = {
1879 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1880 .sel_byte = 2,
1881 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1882 .srt = 0x0,
1883 .end = 0x1,
1884 .rd_addr = R_AX_DBG_PORT_SEL,
1885 .rd_byte = 4,
1886 .rd_msk = B_AX_DEBUG_ST_MASK
1887 };
1888
1889 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = {
1890 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1891 .sel_byte = 2,
1892 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1893 .srt = 0x0,
1894 .end = 0x0,
1895 .rd_addr = R_AX_DBG_PORT_SEL,
1896 .rd_byte = 4,
1897 .rd_msk = B_AX_DEBUG_ST_MASK
1898 };
1899
1900 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = {
1901 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1902 .sel_byte = 2,
1903 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1904 .srt = 0x0,
1905 .end = 0xB,
1906 .rd_addr = R_AX_DBG_PORT_SEL,
1907 .rd_byte = 4,
1908 .rd_msk = B_AX_DEBUG_ST_MASK
1909 };
1910
1911 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = {
1912 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1913 .sel_byte = 2,
1914 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1915 .srt = 0x0,
1916 .end = 0x4,
1917 .rd_addr = R_AX_DBG_PORT_SEL,
1918 .rd_byte = 4,
1919 .rd_msk = B_AX_DEBUG_ST_MASK
1920 };
1921
1922 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = {
1923 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1924 .sel_byte = 2,
1925 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1926 .srt = 0x0,
1927 .end = 0x8,
1928 .rd_addr = R_AX_DBG_PORT_SEL,
1929 .rd_byte = 4,
1930 .rd_msk = B_AX_DEBUG_ST_MASK
1931 };
1932
1933 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = {
1934 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1935 .sel_byte = 2,
1936 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1937 .srt = 0x0,
1938 .end = 0x7,
1939 .rd_addr = R_AX_DBG_PORT_SEL,
1940 .rd_byte = 4,
1941 .rd_msk = B_AX_DEBUG_ST_MASK
1942 };
1943
1944 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = {
1945 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1946 .sel_byte = 2,
1947 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1948 .srt = 0x0,
1949 .end = 0x1,
1950 .rd_addr = R_AX_DBG_PORT_SEL,
1951 .rd_byte = 4,
1952 .rd_msk = B_AX_DEBUG_ST_MASK
1953 };
1954
1955 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = {
1956 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1957 .sel_byte = 2,
1958 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1959 .srt = 0x0,
1960 .end = 0x3,
1961 .rd_addr = R_AX_DBG_PORT_SEL,
1962 .rd_byte = 4,
1963 .rd_msk = B_AX_DEBUG_ST_MASK
1964 };
1965
1966 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = {
1967 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1968 .sel_byte = 2,
1969 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1970 .srt = 0x0,
1971 .end = 0x0,
1972 .rd_addr = R_AX_DBG_PORT_SEL,
1973 .rd_byte = 4,
1974 .rd_msk = B_AX_DEBUG_ST_MASK
1975 };
1976
1977 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = {
1978 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1979 .sel_byte = 2,
1980 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1981 .srt = 0x0,
1982 .end = 0x8,
1983 .rd_addr = R_AX_DBG_PORT_SEL,
1984 .rd_byte = 4,
1985 .rd_msk = B_AX_DEBUG_ST_MASK
1986 };
1987
1988 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = {
1989 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1990 .sel_byte = 2,
1991 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1992 .srt = 0x0,
1993 .end = 0x0,
1994 .rd_addr = R_AX_DBG_PORT_SEL,
1995 .rd_byte = 4,
1996 .rd_msk = B_AX_DEBUG_ST_MASK
1997 };
1998
1999 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = {
2000 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2001 .sel_byte = 2,
2002 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
2003 .srt = 0x0,
2004 .end = 0x6,
2005 .rd_addr = R_AX_DBG_PORT_SEL,
2006 .rd_byte = 4,
2007 .rd_msk = B_AX_DEBUG_ST_MASK
2008 };
2009
2010 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = {
2011 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2012 .sel_byte = 2,
2013 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
2014 .srt = 0x0,
2015 .end = 0x0,
2016 .rd_addr = R_AX_DBG_PORT_SEL,
2017 .rd_byte = 4,
2018 .rd_msk = B_AX_DEBUG_ST_MASK
2019 };
2020
2021 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = {
2022 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2023 .sel_byte = 2,
2024 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
2025 .srt = 0x0,
2026 .end = 0x0,
2027 .rd_addr = R_AX_DBG_PORT_SEL,
2028 .rd_byte = 4,
2029 .rd_msk = B_AX_DEBUG_ST_MASK
2030 };
2031
2032 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = {
2033 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2034 .sel_byte = 1,
2035 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2036 .srt = 0x0,
2037 .end = 0x3,
2038 .rd_addr = R_AX_DBG_PORT_SEL,
2039 .rd_byte = 4,
2040 .rd_msk = B_AX_DEBUG_ST_MASK
2041 };
2042
2043 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = {
2044 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2045 .sel_byte = 1,
2046 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2047 .srt = 0x0,
2048 .end = 0x6,
2049 .rd_addr = R_AX_DBG_PORT_SEL,
2050 .rd_byte = 4,
2051 .rd_msk = B_AX_DEBUG_ST_MASK
2052 };
2053
2054 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = {
2055 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2056 .sel_byte = 1,
2057 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2058 .srt = 0x0,
2059 .end = 0x0,
2060 .rd_addr = R_AX_DBG_PORT_SEL,
2061 .rd_byte = 4,
2062 .rd_msk = B_AX_DEBUG_ST_MASK
2063 };
2064
2065 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = {
2066 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2067 .sel_byte = 1,
2068 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2069 .srt = 0x8,
2070 .end = 0xE,
2071 .rd_addr = R_AX_DBG_PORT_SEL,
2072 .rd_byte = 4,
2073 .rd_msk = B_AX_DEBUG_ST_MASK
2074 };
2075
2076 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = {
2077 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2078 .sel_byte = 1,
2079 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2080 .srt = 0x0,
2081 .end = 0x5,
2082 .rd_addr = R_AX_DBG_PORT_SEL,
2083 .rd_byte = 4,
2084 .rd_msk = B_AX_DEBUG_ST_MASK
2085 };
2086
2087 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = {
2088 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2089 .sel_byte = 1,
2090 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2091 .srt = 0x0,
2092 .end = 0x6,
2093 .rd_addr = R_AX_DBG_PORT_SEL,
2094 .rd_byte = 4,
2095 .rd_msk = B_AX_DEBUG_ST_MASK
2096 };
2097
2098 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = {
2099 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2100 .sel_byte = 1,
2101 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2102 .srt = 0x0,
2103 .end = 0xF,
2104 .rd_addr = R_AX_DBG_PORT_SEL,
2105 .rd_byte = 4,
2106 .rd_msk = B_AX_DEBUG_ST_MASK
2107 };
2108
2109 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = {
2110 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2111 .sel_byte = 1,
2112 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2113 .srt = 0x0,
2114 .end = 0x9,
2115 .rd_addr = R_AX_DBG_PORT_SEL,
2116 .rd_byte = 4,
2117 .rd_msk = B_AX_DEBUG_ST_MASK
2118 };
2119
2120 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = {
2121 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
2122 .sel_byte = 1,
2123 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
2124 .srt = 0x0,
2125 .end = 0x3,
2126 .rd_addr = R_AX_DBG_PORT_SEL,
2127 .rd_byte = 4,
2128 .rd_msk = B_AX_DEBUG_ST_MASK
2129 };
2130
2131 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
2132 .sel_addr = R_AX_SCH_DBG_SEL,
2133 .sel_byte = 1,
2134 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
2135 .srt = 0x00,
2136 .end = 0x2F,
2137 .rd_addr = R_AX_SCH_DBG,
2138 .rd_byte = 4,
2139 .rd_msk = B_AX_SCHEDULER_DBG_MASK
2140 };
2141
2142 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {
2143 .sel_addr = R_AX_SCH_DBG_SEL_C1,
2144 .sel_byte = 1,
2145 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
2146 .srt = 0x00,
2147 .end = 0x2F,
2148 .rd_addr = R_AX_SCH_DBG_C1,
2149 .rd_byte = 4,
2150 .rd_msk = B_AX_SCHEDULER_DBG_MASK
2151 };
2152
2153 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {
2154 .sel_addr = R_AX_MACTX_DBG_SEL_CNT,
2155 .sel_byte = 1,
2156 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
2157 .srt = 0x00,
2158 .end = 0x19,
2159 .rd_addr = R_AX_DBG_PORT_SEL,
2160 .rd_byte = 4,
2161 .rd_msk = B_AX_DEBUG_ST_MASK
2162 };
2163
2164 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {
2165 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1,
2166 .sel_byte = 1,
2167 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
2168 .srt = 0x00,
2169 .end = 0x19,
2170 .rd_addr = R_AX_DBG_PORT_SEL,
2171 .rd_byte = 4,
2172 .rd_msk = B_AX_DEBUG_ST_MASK
2173 };
2174
2175 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {
2176 .sel_addr = R_AX_RX_DEBUG_SELECT,
2177 .sel_byte = 1,
2178 .sel_msk = B_AX_DEBUG_SEL_MASK,
2179 .srt = 0x00,
2180 .end = 0x58,
2181 .rd_addr = R_AX_DBG_PORT_SEL,
2182 .rd_byte = 4,
2183 .rd_msk = B_AX_DEBUG_ST_MASK
2184 };
2185
2186 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {
2187 .sel_addr = R_AX_RX_DEBUG_SELECT_C1,
2188 .sel_byte = 1,
2189 .sel_msk = B_AX_DEBUG_SEL_MASK,
2190 .srt = 0x00,
2191 .end = 0x58,
2192 .rd_addr = R_AX_DBG_PORT_SEL,
2193 .rd_byte = 4,
2194 .rd_msk = B_AX_DEBUG_ST_MASK
2195 };
2196
2197 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {
2198 .sel_addr = R_AX_RX_STATE_MONITOR,
2199 .sel_byte = 1,
2200 .sel_msk = B_AX_STATE_SEL_MASK,
2201 .srt = 0x00,
2202 .end = 0x17,
2203 .rd_addr = R_AX_RX_STATE_MONITOR,
2204 .rd_byte = 4,
2205 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
2206 };
2207
2208 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {
2209 .sel_addr = R_AX_RX_STATE_MONITOR_C1,
2210 .sel_byte = 1,
2211 .sel_msk = B_AX_STATE_SEL_MASK,
2212 .srt = 0x00,
2213 .end = 0x17,
2214 .rd_addr = R_AX_RX_STATE_MONITOR_C1,
2215 .rd_byte = 4,
2216 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
2217 };
2218
2219 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {
2220 .sel_addr = R_AX_RMAC_PLCP_MON,
2221 .sel_byte = 4,
2222 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
2223 .srt = 0x0,
2224 .end = 0xF,
2225 .rd_addr = R_AX_RMAC_PLCP_MON,
2226 .rd_byte = 4,
2227 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
2228 };
2229
2230 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {
2231 .sel_addr = R_AX_RMAC_PLCP_MON_C1,
2232 .sel_byte = 4,
2233 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
2234 .srt = 0x0,
2235 .end = 0xF,
2236 .rd_addr = R_AX_RMAC_PLCP_MON_C1,
2237 .rd_byte = 4,
2238 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
2239 };
2240
2241 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {
2242 .sel_addr = R_AX_DBGSEL_TRXPTCL,
2243 .sel_byte = 1,
2244 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
2245 .srt = 0x08,
2246 .end = 0x10,
2247 .rd_addr = R_AX_DBG_PORT_SEL,
2248 .rd_byte = 4,
2249 .rd_msk = B_AX_DEBUG_ST_MASK
2250 };
2251
2252 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {
2253 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1,
2254 .sel_byte = 1,
2255 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
2256 .srt = 0x08,
2257 .end = 0x10,
2258 .rd_addr = R_AX_DBG_PORT_SEL,
2259 .rd_byte = 4,
2260 .rd_msk = B_AX_DEBUG_ST_MASK
2261 };
2262
2263 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {
2264 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
2265 .sel_byte = 1,
2266 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2267 .srt = 0x00,
2268 .end = 0x07,
2269 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG,
2270 .rd_byte = 4,
2271 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
2272 };
2273
2274 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {
2275 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
2276 .sel_byte = 1,
2277 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2278 .srt = 0x00,
2279 .end = 0x07,
2280 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG,
2281 .rd_byte = 4,
2282 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
2283 };
2284
2285 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {
2286 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
2287 .sel_byte = 1,
2288 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2289 .srt = 0x00,
2290 .end = 0x07,
2291 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1,
2292 .rd_byte = 4,
2293 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
2294 };
2295
2296 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {
2297 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
2298 .sel_byte = 1,
2299 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2300 .srt = 0x00,
2301 .end = 0x07,
2302 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1,
2303 .rd_byte = 4,
2304 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
2305 };
2306
2307 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {
2308 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
2309 .sel_byte = 1,
2310 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2311 .srt = 0x00,
2312 .end = 0x04,
2313 .rd_addr = R_AX_WMAC_TX_TF_INFO_1,
2314 .rd_byte = 4,
2315 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
2316 };
2317
2318 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {
2319 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
2320 .sel_byte = 1,
2321 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2322 .srt = 0x00,
2323 .end = 0x04,
2324 .rd_addr = R_AX_WMAC_TX_TF_INFO_2,
2325 .rd_byte = 4,
2326 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
2327 };
2328
2329 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {
2330 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
2331 .sel_byte = 1,
2332 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2333 .srt = 0x00,
2334 .end = 0x04,
2335 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1,
2336 .rd_byte = 4,
2337 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
2338 };
2339
2340 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {
2341 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
2342 .sel_byte = 1,
2343 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2344 .srt = 0x00,
2345 .end = 0x04,
2346 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1,
2347 .rd_byte = 4,
2348 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
2349 };
2350
2351 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {
2352 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2353 .sel_byte = 4,
2354 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2355 .srt = 0x80000000,
2356 .end = 0x80000001,
2357 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2358 .rd_byte = 4,
2359 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2360 };
2361
2362 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {
2363 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2364 .sel_byte = 4,
2365 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2366 .srt = 0x80010000,
2367 .end = 0x80010004,
2368 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2369 .rd_byte = 4,
2370 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2371 };
2372
2373 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {
2374 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2375 .sel_byte = 4,
2376 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2377 .srt = 0x80020000,
2378 .end = 0x80020FFF,
2379 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2380 .rd_byte = 4,
2381 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2382 };
2383
2384 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {
2385 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2386 .sel_byte = 4,
2387 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2388 .srt = 0x80030000,
2389 .end = 0x80030FFF,
2390 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2391 .rd_byte = 4,
2392 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2393 };
2394
2395 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {
2396 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2397 .sel_byte = 4,
2398 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2399 .srt = 0x80040000,
2400 .end = 0x80040FFF,
2401 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2402 .rd_byte = 4,
2403 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2404 };
2405
2406 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {
2407 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2408 .sel_byte = 4,
2409 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2410 .srt = 0x80050000,
2411 .end = 0x80050FFF,
2412 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2413 .rd_byte = 4,
2414 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2415 };
2416
2417 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {
2418 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2419 .sel_byte = 4,
2420 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2421 .srt = 0x80060000,
2422 .end = 0x80060453,
2423 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2424 .rd_byte = 4,
2425 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2426 };
2427
2428 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {
2429 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2430 .sel_byte = 4,
2431 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2432 .srt = 0x80070000,
2433 .end = 0x80070011,
2434 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2435 .rd_byte = 4,
2436 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2437 };
2438
2439 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {
2440 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2441 .sel_byte = 4,
2442 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2443 .srt = 0x80000000,
2444 .end = 0x80000001,
2445 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2446 .rd_byte = 4,
2447 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2448 };
2449
2450 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {
2451 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2452 .sel_byte = 4,
2453 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2454 .srt = 0x80010000,
2455 .end = 0x8001000A,
2456 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2457 .rd_byte = 4,
2458 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2459 };
2460
2461 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {
2462 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2463 .sel_byte = 4,
2464 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2465 .srt = 0x80020000,
2466 .end = 0x80020DBF,
2467 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2468 .rd_byte = 4,
2469 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2470 };
2471
2472 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {
2473 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2474 .sel_byte = 4,
2475 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2476 .srt = 0x80030000,
2477 .end = 0x80030DBF,
2478 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2479 .rd_byte = 4,
2480 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2481 };
2482
2483 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {
2484 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2485 .sel_byte = 4,
2486 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2487 .srt = 0x80040000,
2488 .end = 0x80040DBF,
2489 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2490 .rd_byte = 4,
2491 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2492 };
2493
2494 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {
2495 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2496 .sel_byte = 4,
2497 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2498 .srt = 0x80050000,
2499 .end = 0x80050DBF,
2500 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2501 .rd_byte = 4,
2502 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2503 };
2504
2505 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {
2506 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2507 .sel_byte = 4,
2508 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2509 .srt = 0x80060000,
2510 .end = 0x80060041,
2511 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2512 .rd_byte = 4,
2513 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2514 };
2515
2516 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {
2517 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2518 .sel_byte = 4,
2519 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2520 .srt = 0x80070000,
2521 .end = 0x80070001,
2522 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2523 .rd_byte = 4,
2524 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2525 };
2526
2527 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {
2528 .sel_addr = R_AX_DBG_FUN_INTF_CTL,
2529 .sel_byte = 4,
2530 .sel_msk = B_AX_DFI_DATA_MASK,
2531 .srt = 0x80000000,
2532 .end = 0x8000017f,
2533 .rd_addr = R_AX_DBG_FUN_INTF_DATA,
2534 .rd_byte = 4,
2535 .rd_msk = B_AX_DFI_DATA_MASK
2536 };
2537
2538 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
2539 .sel_addr = R_AX_PCIE_DBG_CTRL,
2540 .sel_byte = 2,
2541 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2542 .srt = 0x00,
2543 .end = 0x03,
2544 .rd_addr = R_AX_DBG_PORT_SEL,
2545 .rd_byte = 4,
2546 .rd_msk = B_AX_DEBUG_ST_MASK
2547 };
2548
2549 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
2550 .sel_addr = R_AX_PCIE_DBG_CTRL,
2551 .sel_byte = 2,
2552 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2553 .srt = 0x00,
2554 .end = 0x04,
2555 .rd_addr = R_AX_DBG_PORT_SEL,
2556 .rd_byte = 4,
2557 .rd_msk = B_AX_DEBUG_ST_MASK
2558 };
2559
2560 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
2561 .sel_addr = R_AX_PCIE_DBG_CTRL,
2562 .sel_byte = 2,
2563 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2564 .srt = 0x00,
2565 .end = 0x01,
2566 .rd_addr = R_AX_DBG_PORT_SEL,
2567 .rd_byte = 4,
2568 .rd_msk = B_AX_DEBUG_ST_MASK
2569 };
2570
2571 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
2572 .sel_addr = R_AX_PCIE_DBG_CTRL,
2573 .sel_byte = 2,
2574 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2575 .srt = 0x00,
2576 .end = 0x05,
2577 .rd_addr = R_AX_DBG_PORT_SEL,
2578 .rd_byte = 4,
2579 .rd_msk = B_AX_DEBUG_ST_MASK
2580 };
2581
2582 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
2583 .sel_addr = R_AX_PCIE_DBG_CTRL,
2584 .sel_byte = 2,
2585 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2586 .srt = 0x00,
2587 .end = 0x05,
2588 .rd_addr = R_AX_DBG_PORT_SEL,
2589 .rd_byte = 4,
2590 .rd_msk = B_AX_DEBUG_ST_MASK
2591 };
2592
2593 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
2594 .sel_addr = R_AX_PCIE_DBG_CTRL,
2595 .sel_byte = 2,
2596 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2597 .srt = 0x00,
2598 .end = 0x06,
2599 .rd_addr = R_AX_DBG_PORT_SEL,
2600 .rd_byte = 4,
2601 .rd_msk = B_AX_DEBUG_ST_MASK
2602 };
2603
2604 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {
2605 .sel_addr = R_AX_DBG_CTRL,
2606 .sel_byte = 1,
2607 .sel_msk = B_AX_DBG_SEL0,
2608 .srt = 0x34,
2609 .end = 0x3C,
2610 .rd_addr = R_AX_DBG_PORT_SEL,
2611 .rd_byte = 4,
2612 .rd_msk = B_AX_DEBUG_ST_MASK
2613 };
2614
2615 static int
rtw89_debug_mac_dbg_port_sel(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,u32 sel,const struct rtw89_mac_dbg_port_info ** ppinfo)2616 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
2617 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo)
2618 {
2619 const struct rtw89_mac_dbg_port_info *info = NULL;
2620 char *p = buf, *end = buf + bufsz;
2621 u32 index;
2622 u32 val32;
2623 u16 val16;
2624 u8 val8;
2625
2626 switch (sel) {
2627 case RTW89_DBG_PORT_SEL_PTCL_C0:
2628 info = &dbg_port_ptcl_c0;
2629 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG);
2630 val16 |= B_AX_PTCL_DBG_EN;
2631 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16);
2632 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n");
2633 break;
2634 case RTW89_DBG_PORT_SEL_PTCL_C1:
2635 info = &dbg_port_ptcl_c1;
2636 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1);
2637 val16 |= B_AX_PTCL_DBG_EN;
2638 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16);
2639 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n");
2640 break;
2641 case RTW89_DBG_PORT_SEL_SCH_C0:
2642 info = &dbg_port_sch_c0;
2643 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL);
2644 val32 |= B_AX_SCH_DBG_EN;
2645 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32);
2646 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n");
2647 break;
2648 case RTW89_DBG_PORT_SEL_SCH_C1:
2649 info = &dbg_port_sch_c1;
2650 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1);
2651 val32 |= B_AX_SCH_DBG_EN;
2652 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32);
2653 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n");
2654 break;
2655 case RTW89_DBG_PORT_SEL_TMAC_C0:
2656 info = &dbg_port_tmac_c0;
2657 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
2658 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
2659 B_AX_DBGSEL_TRXPTCL_MASK);
2660 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
2661
2662 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2663 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
2664 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
2665 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2666
2667 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2668 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2669 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2670 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n");
2671 break;
2672 case RTW89_DBG_PORT_SEL_TMAC_C1:
2673 info = &dbg_port_tmac_c1;
2674 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2675 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
2676 B_AX_DBGSEL_TRXPTCL_MASK);
2677 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
2678
2679 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2680 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
2681 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
2682 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2683
2684 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2685 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2686 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2687 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n");
2688 break;
2689 case RTW89_DBG_PORT_SEL_RMAC_C0:
2690 info = &dbg_port_rmac_c0;
2691 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
2692 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
2693 B_AX_DBGSEL_TRXPTCL_MASK);
2694 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
2695
2696 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2697 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
2698 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
2699 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2700
2701 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2702 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2703 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2704
2705 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
2706 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
2707 B_AX_DBGSEL_TRXPTCL_MASK);
2708 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
2709 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n");
2710 break;
2711 case RTW89_DBG_PORT_SEL_RMAC_C1:
2712 info = &dbg_port_rmac_c1;
2713 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2714 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
2715 B_AX_DBGSEL_TRXPTCL_MASK);
2716 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
2717
2718 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2719 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
2720 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
2721 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2722
2723 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2724 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2725 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2726
2727 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2728 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
2729 B_AX_DBGSEL_TRXPTCL_MASK);
2730 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
2731 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n");
2732 break;
2733 case RTW89_DBG_PORT_SEL_RMACST_C0:
2734 info = &dbg_port_rmacst_c0;
2735 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n");
2736 break;
2737 case RTW89_DBG_PORT_SEL_RMACST_C1:
2738 info = &dbg_port_rmacst_c1;
2739 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n");
2740 break;
2741 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0:
2742 info = &dbg_port_rmac_plcp_c0;
2743 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n");
2744 break;
2745 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1:
2746 info = &dbg_port_rmac_plcp_c1;
2747 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n");
2748 break;
2749 case RTW89_DBG_PORT_SEL_TRXPTCL_C0:
2750 info = &dbg_port_trxptcl_c0;
2751 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2752 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
2753 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
2754 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2755
2756 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2757 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2758 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2759 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n");
2760 break;
2761 case RTW89_DBG_PORT_SEL_TRXPTCL_C1:
2762 info = &dbg_port_trxptcl_c1;
2763 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2764 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
2765 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
2766 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2767
2768 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2769 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2770 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2771 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n");
2772 break;
2773 case RTW89_DBG_PORT_SEL_TX_INFOL_C0:
2774 info = &dbg_port_tx_infol_c0;
2775 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2776 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2777 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2778 p += scnprintf(p, end - p, "Enable tx infol dump.\n");
2779 break;
2780 case RTW89_DBG_PORT_SEL_TX_INFOH_C0:
2781 info = &dbg_port_tx_infoh_c0;
2782 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2783 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2784 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2785 p += scnprintf(p, end - p, "Enable tx infoh dump.\n");
2786 break;
2787 case RTW89_DBG_PORT_SEL_TX_INFOL_C1:
2788 info = &dbg_port_tx_infol_c1;
2789 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2790 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2791 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2792 p += scnprintf(p, end - p, "Enable tx infol dump.\n");
2793 break;
2794 case RTW89_DBG_PORT_SEL_TX_INFOH_C1:
2795 info = &dbg_port_tx_infoh_c1;
2796 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2797 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2798 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2799 p += scnprintf(p, end - p, "Enable tx infoh dump.\n");
2800 break;
2801 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0:
2802 info = &dbg_port_txtf_infol_c0;
2803 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2804 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2805 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2806 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n");
2807 break;
2808 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0:
2809 info = &dbg_port_txtf_infoh_c0;
2810 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2811 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2812 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2813 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n");
2814 break;
2815 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1:
2816 info = &dbg_port_txtf_infol_c1;
2817 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2818 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2819 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2820 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n");
2821 break;
2822 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1:
2823 info = &dbg_port_txtf_infoh_c1;
2824 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2825 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2826 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2827 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n");
2828 break;
2829 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG:
2830 info = &dbg_port_wde_bufmgn_freepg;
2831 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n");
2832 break;
2833 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA:
2834 info = &dbg_port_wde_bufmgn_quota;
2835 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n");
2836 break;
2837 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT:
2838 info = &dbg_port_wde_bufmgn_pagellt;
2839 p += scnprintf(p, end - p,
2840 "Enable wde bufmgn pagellt dump.\n");
2841 break;
2842 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO:
2843 info = &dbg_port_wde_bufmgn_pktinfo;
2844 p += scnprintf(p, end - p,
2845 "Enable wde bufmgn pktinfo dump.\n");
2846 break;
2847 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT:
2848 info = &dbg_port_wde_quemgn_prepkt;
2849 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n");
2850 break;
2851 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT:
2852 info = &dbg_port_wde_quemgn_nxtpkt;
2853 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n");
2854 break;
2855 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL:
2856 info = &dbg_port_wde_quemgn_qlnktbl;
2857 p += scnprintf(p, end - p,
2858 "Enable wde quemgn qlnktbl dump.\n");
2859 break;
2860 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY:
2861 info = &dbg_port_wde_quemgn_qempty;
2862 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n");
2863 break;
2864 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG:
2865 info = &dbg_port_ple_bufmgn_freepg;
2866 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n");
2867 break;
2868 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA:
2869 info = &dbg_port_ple_bufmgn_quota;
2870 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n");
2871 break;
2872 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT:
2873 info = &dbg_port_ple_bufmgn_pagellt;
2874 p += scnprintf(p, end - p,
2875 "Enable ple bufmgn pagellt dump.\n");
2876 break;
2877 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO:
2878 info = &dbg_port_ple_bufmgn_pktinfo;
2879 p += scnprintf(p, end - p,
2880 "Enable ple bufmgn pktinfo dump.\n");
2881 break;
2882 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT:
2883 info = &dbg_port_ple_quemgn_prepkt;
2884 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n");
2885 break;
2886 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT:
2887 info = &dbg_port_ple_quemgn_nxtpkt;
2888 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n");
2889 break;
2890 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL:
2891 info = &dbg_port_ple_quemgn_qlnktbl;
2892 p += scnprintf(p, end - p,
2893 "Enable ple quemgn qlnktbl dump.\n");
2894 break;
2895 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY:
2896 info = &dbg_port_ple_quemgn_qempty;
2897 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n");
2898 break;
2899 case RTW89_DBG_PORT_SEL_PKTINFO:
2900 info = &dbg_port_pktinfo;
2901 p += scnprintf(p, end - p, "Enable pktinfo dump.\n");
2902 break;
2903 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0:
2904 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
2905 B_AX_DBG_SEL0, 0x80);
2906 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
2907 B_AX_SEL_0XC0_MASK, 1);
2908 fallthrough;
2909 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1:
2910 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2:
2911 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3:
2912 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4:
2913 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5:
2914 info = &dbg_port_dspt_hdt_tx0_5;
2915 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0;
2916 rtw89_write16_mask(rtwdev, info->sel_addr,
2917 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2918 rtw89_write16_mask(rtwdev, info->sel_addr,
2919 B_AX_DISPATCHER_CH_SEL_MASK, index);
2920 p += scnprintf(p, end - p,
2921 "Enable Dispatcher hdt tx%x dump.\n", index);
2922 break;
2923 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6:
2924 info = &dbg_port_dspt_hdt_tx6;
2925 rtw89_write16_mask(rtwdev, info->sel_addr,
2926 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2927 rtw89_write16_mask(rtwdev, info->sel_addr,
2928 B_AX_DISPATCHER_CH_SEL_MASK, 6);
2929 p += scnprintf(p, end - p,
2930 "Enable Dispatcher hdt tx6 dump.\n");
2931 break;
2932 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7:
2933 info = &dbg_port_dspt_hdt_tx7;
2934 rtw89_write16_mask(rtwdev, info->sel_addr,
2935 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2936 rtw89_write16_mask(rtwdev, info->sel_addr,
2937 B_AX_DISPATCHER_CH_SEL_MASK, 7);
2938 p += scnprintf(p, end - p,
2939 "Enable Dispatcher hdt tx7 dump.\n");
2940 break;
2941 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8:
2942 info = &dbg_port_dspt_hdt_tx8;
2943 rtw89_write16_mask(rtwdev, info->sel_addr,
2944 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2945 rtw89_write16_mask(rtwdev, info->sel_addr,
2946 B_AX_DISPATCHER_CH_SEL_MASK, 8);
2947 p += scnprintf(p, end - p,
2948 "Enable Dispatcher hdt tx8 dump.\n");
2949 break;
2950 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9:
2951 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA:
2952 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB:
2953 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC:
2954 info = &dbg_port_dspt_hdt_tx9_C;
2955 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9;
2956 rtw89_write16_mask(rtwdev, info->sel_addr,
2957 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2958 rtw89_write16_mask(rtwdev, info->sel_addr,
2959 B_AX_DISPATCHER_CH_SEL_MASK, index);
2960 p += scnprintf(p, end - p,
2961 "Enable Dispatcher hdt tx%x dump.\n", index);
2962 break;
2963 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD:
2964 info = &dbg_port_dspt_hdt_txD;
2965 rtw89_write16_mask(rtwdev, info->sel_addr,
2966 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2967 rtw89_write16_mask(rtwdev, info->sel_addr,
2968 B_AX_DISPATCHER_CH_SEL_MASK, 0xD);
2969 p += scnprintf(p, end - p,
2970 "Enable Dispatcher hdt txD dump.\n");
2971 break;
2972 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0:
2973 info = &dbg_port_dspt_cdt_tx0;
2974 rtw89_write16_mask(rtwdev, info->sel_addr,
2975 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2976 rtw89_write16_mask(rtwdev, info->sel_addr,
2977 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2978 p += scnprintf(p, end - p,
2979 "Enable Dispatcher cdt tx0 dump.\n");
2980 break;
2981 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1:
2982 info = &dbg_port_dspt_cdt_tx1;
2983 rtw89_write16_mask(rtwdev, info->sel_addr,
2984 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2985 rtw89_write16_mask(rtwdev, info->sel_addr,
2986 B_AX_DISPATCHER_CH_SEL_MASK, 1);
2987 p += scnprintf(p, end - p,
2988 "Enable Dispatcher cdt tx1 dump.\n");
2989 break;
2990 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3:
2991 info = &dbg_port_dspt_cdt_tx3;
2992 rtw89_write16_mask(rtwdev, info->sel_addr,
2993 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2994 rtw89_write16_mask(rtwdev, info->sel_addr,
2995 B_AX_DISPATCHER_CH_SEL_MASK, 3);
2996 p += scnprintf(p, end - p,
2997 "Enable Dispatcher cdt tx3 dump.\n");
2998 break;
2999 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4:
3000 info = &dbg_port_dspt_cdt_tx4;
3001 rtw89_write16_mask(rtwdev, info->sel_addr,
3002 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
3003 rtw89_write16_mask(rtwdev, info->sel_addr,
3004 B_AX_DISPATCHER_CH_SEL_MASK, 4);
3005 p += scnprintf(p, end - p,
3006 "Enable Dispatcher cdt tx4 dump.\n");
3007 break;
3008 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5:
3009 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6:
3010 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7:
3011 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8:
3012 info = &dbg_port_dspt_cdt_tx5_8;
3013 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5;
3014 rtw89_write16_mask(rtwdev, info->sel_addr,
3015 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
3016 rtw89_write16_mask(rtwdev, info->sel_addr,
3017 B_AX_DISPATCHER_CH_SEL_MASK, index);
3018 p += scnprintf(p, end - p,
3019 "Enable Dispatcher cdt tx%x dump.\n", index);
3020 break;
3021 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9:
3022 info = &dbg_port_dspt_cdt_tx9;
3023 rtw89_write16_mask(rtwdev, info->sel_addr,
3024 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
3025 rtw89_write16_mask(rtwdev, info->sel_addr,
3026 B_AX_DISPATCHER_CH_SEL_MASK, 9);
3027 p += scnprintf(p, end - p,
3028 "Enable Dispatcher cdt tx9 dump.\n");
3029 break;
3030 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA:
3031 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB:
3032 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC:
3033 info = &dbg_port_dspt_cdt_txA_C;
3034 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA;
3035 rtw89_write16_mask(rtwdev, info->sel_addr,
3036 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
3037 rtw89_write16_mask(rtwdev, info->sel_addr,
3038 B_AX_DISPATCHER_CH_SEL_MASK, index);
3039 p += scnprintf(p, end - p,
3040 "Enable Dispatcher cdt tx%x dump.\n", index);
3041 break;
3042 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0:
3043 info = &dbg_port_dspt_hdt_rx0;
3044 rtw89_write16_mask(rtwdev, info->sel_addr,
3045 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
3046 rtw89_write16_mask(rtwdev, info->sel_addr,
3047 B_AX_DISPATCHER_CH_SEL_MASK, 0);
3048 p += scnprintf(p, end - p,
3049 "Enable Dispatcher hdt rx0 dump.\n");
3050 break;
3051 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1:
3052 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2:
3053 info = &dbg_port_dspt_hdt_rx1_2;
3054 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1;
3055 rtw89_write16_mask(rtwdev, info->sel_addr,
3056 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
3057 rtw89_write16_mask(rtwdev, info->sel_addr,
3058 B_AX_DISPATCHER_CH_SEL_MASK, index);
3059 p += scnprintf(p, end - p,
3060 "Enable Dispatcher hdt rx%x dump.\n", index);
3061 break;
3062 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3:
3063 info = &dbg_port_dspt_hdt_rx3;
3064 rtw89_write16_mask(rtwdev, info->sel_addr,
3065 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
3066 rtw89_write16_mask(rtwdev, info->sel_addr,
3067 B_AX_DISPATCHER_CH_SEL_MASK, 3);
3068 p += scnprintf(p, end - p,
3069 "Enable Dispatcher hdt rx3 dump.\n");
3070 break;
3071 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4:
3072 info = &dbg_port_dspt_hdt_rx4;
3073 rtw89_write16_mask(rtwdev, info->sel_addr,
3074 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
3075 rtw89_write16_mask(rtwdev, info->sel_addr,
3076 B_AX_DISPATCHER_CH_SEL_MASK, 4);
3077 p += scnprintf(p, end - p,
3078 "Enable Dispatcher hdt rx4 dump.\n");
3079 break;
3080 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5:
3081 info = &dbg_port_dspt_hdt_rx5;
3082 rtw89_write16_mask(rtwdev, info->sel_addr,
3083 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
3084 rtw89_write16_mask(rtwdev, info->sel_addr,
3085 B_AX_DISPATCHER_CH_SEL_MASK, 5);
3086 p += scnprintf(p, end - p,
3087 "Enable Dispatcher hdt rx5 dump.\n");
3088 break;
3089 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0:
3090 info = &dbg_port_dspt_cdt_rx_p0_0;
3091 rtw89_write16_mask(rtwdev, info->sel_addr,
3092 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
3093 rtw89_write16_mask(rtwdev, info->sel_addr,
3094 B_AX_DISPATCHER_CH_SEL_MASK, 0);
3095 p += scnprintf(p, end - p,
3096 "Enable Dispatcher cdt rx part0 0 dump.\n");
3097 break;
3098 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0:
3099 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1:
3100 info = &dbg_port_dspt_cdt_rx_p0_1;
3101 rtw89_write16_mask(rtwdev, info->sel_addr,
3102 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
3103 rtw89_write16_mask(rtwdev, info->sel_addr,
3104 B_AX_DISPATCHER_CH_SEL_MASK, 1);
3105 p += scnprintf(p, end - p,
3106 "Enable Dispatcher cdt rx part0 1 dump.\n");
3107 break;
3108 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2:
3109 info = &dbg_port_dspt_cdt_rx_p0_2;
3110 rtw89_write16_mask(rtwdev, info->sel_addr,
3111 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
3112 rtw89_write16_mask(rtwdev, info->sel_addr,
3113 B_AX_DISPATCHER_CH_SEL_MASK, 2);
3114 p += scnprintf(p, end - p,
3115 "Enable Dispatcher cdt rx part0 2 dump.\n");
3116 break;
3117 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1:
3118 info = &dbg_port_dspt_cdt_rx_p1;
3119 rtw89_write8_mask(rtwdev, info->sel_addr,
3120 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
3121 p += scnprintf(p, end - p,
3122 "Enable Dispatcher cdt rx part1 dump.\n");
3123 break;
3124 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL:
3125 info = &dbg_port_dspt_stf_ctrl;
3126 rtw89_write8_mask(rtwdev, info->sel_addr,
3127 B_AX_DISPATCHER_INTN_SEL_MASK, 4);
3128 p += scnprintf(p, end - p,
3129 "Enable Dispatcher stf control dump.\n");
3130 break;
3131 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL:
3132 info = &dbg_port_dspt_addr_ctrl;
3133 rtw89_write8_mask(rtwdev, info->sel_addr,
3134 B_AX_DISPATCHER_INTN_SEL_MASK, 5);
3135 p += scnprintf(p, end - p,
3136 "Enable Dispatcher addr control dump.\n");
3137 break;
3138 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF:
3139 info = &dbg_port_dspt_wde_intf;
3140 rtw89_write8_mask(rtwdev, info->sel_addr,
3141 B_AX_DISPATCHER_INTN_SEL_MASK, 6);
3142 p += scnprintf(p, end - p,
3143 "Enable Dispatcher wde interface dump.\n");
3144 break;
3145 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF:
3146 info = &dbg_port_dspt_ple_intf;
3147 rtw89_write8_mask(rtwdev, info->sel_addr,
3148 B_AX_DISPATCHER_INTN_SEL_MASK, 7);
3149 p += scnprintf(p, end - p,
3150 "Enable Dispatcher ple interface dump.\n");
3151 break;
3152 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL:
3153 info = &dbg_port_dspt_flow_ctrl;
3154 rtw89_write8_mask(rtwdev, info->sel_addr,
3155 B_AX_DISPATCHER_INTN_SEL_MASK, 8);
3156 p += scnprintf(p, end - p,
3157 "Enable Dispatcher flow control dump.\n");
3158 break;
3159 case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
3160 info = &dbg_port_pcie_txdma;
3161 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3162 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
3163 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
3164 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3165 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n");
3166 break;
3167 case RTW89_DBG_PORT_SEL_PCIE_RXDMA:
3168 info = &dbg_port_pcie_rxdma;
3169 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3170 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
3171 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
3172 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3173 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n");
3174 break;
3175 case RTW89_DBG_PORT_SEL_PCIE_CVT:
3176 info = &dbg_port_pcie_cvt;
3177 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3178 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
3179 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
3180 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3181 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n");
3182 break;
3183 case RTW89_DBG_PORT_SEL_PCIE_CXPL:
3184 info = &dbg_port_pcie_cxpl;
3185 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3186 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0);
3187 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1);
3188 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3189 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n");
3190 break;
3191 case RTW89_DBG_PORT_SEL_PCIE_IO:
3192 info = &dbg_port_pcie_io;
3193 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3194 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0);
3195 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1);
3196 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3197 p += scnprintf(p, end - p, "Enable pcie io dump.\n");
3198 break;
3199 case RTW89_DBG_PORT_SEL_PCIE_MISC:
3200 info = &dbg_port_pcie_misc;
3201 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3202 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0);
3203 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1);
3204 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3205 p += scnprintf(p, end - p, "Enable pcie misc dump.\n");
3206 break;
3207 case RTW89_DBG_PORT_SEL_PCIE_MISC2:
3208 info = &dbg_port_pcie_misc2;
3209 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
3210 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
3211 B_AX_PCIE_DBG_SEL_MASK);
3212 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
3213 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n");
3214 break;
3215 default:
3216 p += scnprintf(p, end - p, "Dbg port select err\n");
3217 break;
3218 }
3219
3220 *ppinfo = info;
3221
3222 return p - buf;
3223 }
3224
is_dbg_port_valid(struct rtw89_dev * rtwdev,u32 sel)3225 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
3226 {
3227 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE &&
3228 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
3229 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
3230 return false;
3231 if (rtw89_is_rtl885xb(rtwdev) &&
3232 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
3233 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
3234 return false;
3235 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
3236 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
3237 sel <= RTW89_DBG_PORT_SEL_PKTINFO)
3238 return false;
3239 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
3240 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 &&
3241 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL)
3242 return false;
3243 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
3244 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
3245 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
3246 return false;
3247 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) &&
3248 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
3249 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
3250 return false;
3251
3252 return true;
3253 }
3254
rtw89_debug_mac_dbg_port_dump(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,u32 sel)3255 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,
3256 char *buf, size_t bufsz, u32 sel)
3257 {
3258 const struct rtw89_mac_dbg_port_info *info = NULL;
3259 char *p = buf, *end = buf + bufsz;
3260 u32 val32;
3261 u16 val16;
3262 u8 val8;
3263 u32 i;
3264
3265 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info);
3266
3267 if (!info) {
3268 rtw89_err(rtwdev, "failed to select debug port %d\n", sel);
3269 goto out;
3270 }
3271
3272 #define case_DBG_SEL(__sel) \
3273 case RTW89_DBG_PORT_SEL_##__sel: \
3274 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \
3275 break
3276
3277 switch (sel) {
3278 case_DBG_SEL(PTCL_C0);
3279 case_DBG_SEL(PTCL_C1);
3280 case_DBG_SEL(SCH_C0);
3281 case_DBG_SEL(SCH_C1);
3282 case_DBG_SEL(TMAC_C0);
3283 case_DBG_SEL(TMAC_C1);
3284 case_DBG_SEL(RMAC_C0);
3285 case_DBG_SEL(RMAC_C1);
3286 case_DBG_SEL(RMACST_C0);
3287 case_DBG_SEL(RMACST_C1);
3288 case_DBG_SEL(TRXPTCL_C0);
3289 case_DBG_SEL(TRXPTCL_C1);
3290 case_DBG_SEL(TX_INFOL_C0);
3291 case_DBG_SEL(TX_INFOH_C0);
3292 case_DBG_SEL(TX_INFOL_C1);
3293 case_DBG_SEL(TX_INFOH_C1);
3294 case_DBG_SEL(TXTF_INFOL_C0);
3295 case_DBG_SEL(TXTF_INFOH_C0);
3296 case_DBG_SEL(TXTF_INFOL_C1);
3297 case_DBG_SEL(TXTF_INFOH_C1);
3298 case_DBG_SEL(WDE_BUFMGN_FREEPG);
3299 case_DBG_SEL(WDE_BUFMGN_QUOTA);
3300 case_DBG_SEL(WDE_BUFMGN_PAGELLT);
3301 case_DBG_SEL(WDE_BUFMGN_PKTINFO);
3302 case_DBG_SEL(WDE_QUEMGN_PREPKT);
3303 case_DBG_SEL(WDE_QUEMGN_NXTPKT);
3304 case_DBG_SEL(WDE_QUEMGN_QLNKTBL);
3305 case_DBG_SEL(WDE_QUEMGN_QEMPTY);
3306 case_DBG_SEL(PLE_BUFMGN_FREEPG);
3307 case_DBG_SEL(PLE_BUFMGN_QUOTA);
3308 case_DBG_SEL(PLE_BUFMGN_PAGELLT);
3309 case_DBG_SEL(PLE_BUFMGN_PKTINFO);
3310 case_DBG_SEL(PLE_QUEMGN_PREPKT);
3311 case_DBG_SEL(PLE_QUEMGN_NXTPKT);
3312 case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
3313 case_DBG_SEL(PLE_QUEMGN_QEMPTY);
3314 case_DBG_SEL(PKTINFO);
3315 case_DBG_SEL(DSPT_HDT_TX0);
3316 case_DBG_SEL(DSPT_HDT_TX1);
3317 case_DBG_SEL(DSPT_HDT_TX2);
3318 case_DBG_SEL(DSPT_HDT_TX3);
3319 case_DBG_SEL(DSPT_HDT_TX4);
3320 case_DBG_SEL(DSPT_HDT_TX5);
3321 case_DBG_SEL(DSPT_HDT_TX6);
3322 case_DBG_SEL(DSPT_HDT_TX7);
3323 case_DBG_SEL(DSPT_HDT_TX8);
3324 case_DBG_SEL(DSPT_HDT_TX9);
3325 case_DBG_SEL(DSPT_HDT_TXA);
3326 case_DBG_SEL(DSPT_HDT_TXB);
3327 case_DBG_SEL(DSPT_HDT_TXC);
3328 case_DBG_SEL(DSPT_HDT_TXD);
3329 case_DBG_SEL(DSPT_HDT_TXE);
3330 case_DBG_SEL(DSPT_HDT_TXF);
3331 case_DBG_SEL(DSPT_CDT_TX0);
3332 case_DBG_SEL(DSPT_CDT_TX1);
3333 case_DBG_SEL(DSPT_CDT_TX3);
3334 case_DBG_SEL(DSPT_CDT_TX4);
3335 case_DBG_SEL(DSPT_CDT_TX5);
3336 case_DBG_SEL(DSPT_CDT_TX6);
3337 case_DBG_SEL(DSPT_CDT_TX7);
3338 case_DBG_SEL(DSPT_CDT_TX8);
3339 case_DBG_SEL(DSPT_CDT_TX9);
3340 case_DBG_SEL(DSPT_CDT_TXA);
3341 case_DBG_SEL(DSPT_CDT_TXB);
3342 case_DBG_SEL(DSPT_CDT_TXC);
3343 case_DBG_SEL(DSPT_HDT_RX0);
3344 case_DBG_SEL(DSPT_HDT_RX1);
3345 case_DBG_SEL(DSPT_HDT_RX2);
3346 case_DBG_SEL(DSPT_HDT_RX3);
3347 case_DBG_SEL(DSPT_HDT_RX4);
3348 case_DBG_SEL(DSPT_HDT_RX5);
3349 case_DBG_SEL(DSPT_CDT_RX_P0);
3350 case_DBG_SEL(DSPT_CDT_RX_P0_0);
3351 case_DBG_SEL(DSPT_CDT_RX_P0_1);
3352 case_DBG_SEL(DSPT_CDT_RX_P0_2);
3353 case_DBG_SEL(DSPT_CDT_RX_P1);
3354 case_DBG_SEL(DSPT_STF_CTRL);
3355 case_DBG_SEL(DSPT_ADDR_CTRL);
3356 case_DBG_SEL(DSPT_WDE_INTF);
3357 case_DBG_SEL(DSPT_PLE_INTF);
3358 case_DBG_SEL(DSPT_FLOW_CTRL);
3359 case_DBG_SEL(PCIE_TXDMA);
3360 case_DBG_SEL(PCIE_RXDMA);
3361 case_DBG_SEL(PCIE_CVT);
3362 case_DBG_SEL(PCIE_CXPL);
3363 case_DBG_SEL(PCIE_IO);
3364 case_DBG_SEL(PCIE_MISC);
3365 case_DBG_SEL(PCIE_MISC2);
3366 }
3367
3368 #undef case_DBG_SEL
3369
3370 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr);
3371 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr);
3372
3373 for (i = info->srt; i <= info->end; i++) {
3374 switch (info->sel_byte) {
3375 case 1:
3376 default:
3377 rtw89_write8_mask(rtwdev, info->sel_addr,
3378 info->sel_msk, i);
3379 p += scnprintf(p, end - p, "0x%02X: ", i);
3380 break;
3381 case 2:
3382 rtw89_write16_mask(rtwdev, info->sel_addr,
3383 info->sel_msk, i);
3384 p += scnprintf(p, end - p, "0x%04X: ", i);
3385 break;
3386 case 4:
3387 rtw89_write32_mask(rtwdev, info->sel_addr,
3388 info->sel_msk, i);
3389 p += scnprintf(p, end - p, "0x%04X: ", i);
3390 break;
3391 }
3392
3393 udelay(10);
3394
3395 switch (info->rd_byte) {
3396 case 1:
3397 default:
3398 val8 = rtw89_read8_mask(rtwdev,
3399 info->rd_addr, info->rd_msk);
3400 p += scnprintf(p, end - p, "0x%02X\n", val8);
3401 break;
3402 case 2:
3403 val16 = rtw89_read16_mask(rtwdev,
3404 info->rd_addr, info->rd_msk);
3405 p += scnprintf(p, end - p, "0x%04X\n", val16);
3406 break;
3407 case 4:
3408 val32 = rtw89_read32_mask(rtwdev,
3409 info->rd_addr, info->rd_msk);
3410 p += scnprintf(p, end - p, "0x%08X\n", val32);
3411 break;
3412 }
3413 }
3414
3415 out:
3416 return p - buf;
3417 }
3418
rtw89_debug_mac_dump_dbg_port(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)3419 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,
3420 char *buf, size_t bufsz)
3421 {
3422 char *p = buf, *end = buf + bufsz;
3423 ssize_t n;
3424 u32 sel;
3425
3426 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0;
3427 sel < RTW89_DBG_PORT_SEL_LAST; sel++) {
3428 if (!is_dbg_port_valid(rtwdev, sel))
3429 continue;
3430 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel);
3431 if (n < 0) {
3432 rtw89_err(rtwdev,
3433 "failed to dump debug port %d\n", sel);
3434 break;
3435 }
3436 p += n;
3437 }
3438
3439 return p - buf;
3440 }
3441
3442 static ssize_t
rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)3443 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev,
3444 struct rtw89_debugfs_priv *debugfs_priv,
3445 char *buf, size_t bufsz)
3446 {
3447 char *p = buf, *end = buf + bufsz;
3448
3449 if (debugfs_priv->dbgpkg_en.ss_dbg)
3450 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p);
3451 if (debugfs_priv->dbgpkg_en.dle_dbg)
3452 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p);
3453 if (debugfs_priv->dbgpkg_en.dmac_dbg)
3454 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p);
3455 if (debugfs_priv->dbgpkg_en.cmac_dbg)
3456 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p);
3457 if (debugfs_priv->dbgpkg_en.dbg_port)
3458 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p);
3459
3460 return p - buf;
3461 };
3462
rtw89_hex2bin(struct rtw89_dev * rtwdev,const char * buf,size_t count)3463 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count)
3464 {
3465 u8 *bin;
3466 int num;
3467 int err = 0;
3468
3469 num = count / 2;
3470 bin = kmalloc(num, GFP_KERNEL);
3471 if (!bin) {
3472 err = -EFAULT;
3473 goto out;
3474 }
3475
3476 if (hex2bin(bin, buf, num)) {
3477 rtw89_info(rtwdev, "valid format: H1H2H3...\n");
3478 kfree(bin);
3479 err = -EINVAL;
3480 }
3481
3482 out:
3483 return err ? ERR_PTR(err) : bin;
3484 }
3485
rtw89_debug_priv_send_h2c_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)3486 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev,
3487 struct rtw89_debugfs_priv *debugfs_priv,
3488 const char *buf, size_t count)
3489 {
3490 u8 *h2c;
3491 int ret;
3492 u16 h2c_len = count / 2;
3493
3494 h2c = rtw89_hex2bin(rtwdev, buf, count);
3495 if (IS_ERR(h2c))
3496 return -EFAULT;
3497
3498 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len);
3499
3500 kfree(h2c);
3501
3502 return ret ? ret : count;
3503 }
3504
3505 static ssize_t
rtw89_debug_priv_early_h2c_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)3506 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev,
3507 struct rtw89_debugfs_priv *debugfs_priv,
3508 char *buf, size_t bufsz)
3509 {
3510 struct rtw89_early_h2c *early_h2c;
3511 char *p = buf, *end = buf + bufsz;
3512 int seq = 0;
3513
3514 lockdep_assert_wiphy(rtwdev->hw->wiphy);
3515
3516 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list)
3517 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq,
3518 early_h2c->h2c_len, early_h2c->h2c);
3519
3520 return p - buf;
3521 }
3522
3523 static ssize_t
rtw89_debug_priv_early_h2c_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)3524 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev,
3525 struct rtw89_debugfs_priv *debugfs_priv,
3526 const char *buf, size_t count)
3527 {
3528 struct rtw89_early_h2c *early_h2c;
3529 u8 *h2c;
3530 u16 h2c_len = count / 2;
3531
3532 lockdep_assert_wiphy(rtwdev->hw->wiphy);
3533
3534 h2c = rtw89_hex2bin(rtwdev, buf, count);
3535 if (IS_ERR(h2c))
3536 return -EFAULT;
3537
3538 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) {
3539 kfree(h2c);
3540 rtw89_fw_free_all_early_h2c(rtwdev);
3541 goto out;
3542 }
3543
3544 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL);
3545 if (!early_h2c) {
3546 kfree(h2c);
3547 return -EFAULT;
3548 }
3549
3550 early_h2c->h2c = h2c;
3551 early_h2c->h2c_len = h2c_len;
3552
3553 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list);
3554
3555 out:
3556 return count;
3557 }
3558
rtw89_dbg_trigger_ctrl_error(struct rtw89_dev * rtwdev)3559 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev)
3560 {
3561 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3562 struct rtw89_cpuio_ctrl ctrl_para = {0};
3563 u16 pkt_id;
3564 int ret;
3565
3566 rtw89_leave_ps_mode(rtwdev);
3567
3568 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3569 if (ret)
3570 return ret;
3571
3572 /* intentionally, enqueue two pkt, but has only one pkt id */
3573 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
3574 ctrl_para.start_pktid = pkt_id;
3575 ctrl_para.end_pktid = pkt_id;
3576 ctrl_para.pkt_num = 1; /* start from 0 */
3577 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
3578 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
3579
3580 if (mac->set_cpuio(rtwdev, &ctrl_para, true))
3581 return -EFAULT;
3582
3583 return 0;
3584 }
3585
3586 static ssize_t
rtw89_debug_priv_fw_crash_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)3587 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev,
3588 struct rtw89_debugfs_priv *debugfs_priv,
3589 char *buf, size_t bufsz)
3590 {
3591 char *p = buf, *end = buf + bufsz;
3592
3593 p += scnprintf(p, end - p, "%d\n",
3594 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags));
3595 return p - buf;
3596 }
3597
3598 enum rtw89_dbg_crash_simulation_type {
3599 RTW89_DBG_SIM_CPU_EXCEPTION = 1,
3600 RTW89_DBG_SIM_CTRL_ERROR = 2,
3601 };
3602
3603 static ssize_t
rtw89_debug_priv_fw_crash_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)3604 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev,
3605 struct rtw89_debugfs_priv *debugfs_priv,
3606 const char *buf, size_t count)
3607 {
3608 int (*sim)(struct rtw89_dev *rtwdev);
3609 u8 crash_type;
3610 int ret;
3611
3612 lockdep_assert_wiphy(rtwdev->hw->wiphy);
3613
3614 ret = kstrtou8(buf, 0, &crash_type);
3615 if (ret)
3616 return -EINVAL;
3617
3618 switch (crash_type) {
3619 case RTW89_DBG_SIM_CPU_EXCEPTION:
3620 if (!RTW89_CHK_FW_FEATURE_GROUP(CRASH_TRIGGER, &rtwdev->fw))
3621 return -EOPNOTSUPP;
3622 sim = rtw89_fw_h2c_trigger_cpu_exception;
3623 break;
3624 case RTW89_DBG_SIM_CTRL_ERROR:
3625 sim = rtw89_dbg_trigger_ctrl_error;
3626 break;
3627 default:
3628 return -EINVAL;
3629 }
3630
3631 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
3632 ret = sim(rtwdev);
3633
3634 if (ret)
3635 return ret;
3636
3637 return count;
3638 }
3639
rtw89_debug_priv_btc_info_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)3640 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev,
3641 struct rtw89_debugfs_priv *debugfs_priv,
3642 char *buf, size_t bufsz)
3643 {
3644 return rtw89_btc_dump_info(rtwdev, buf, bufsz);
3645 }
3646
rtw89_debug_priv_btc_manual_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)3647 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev,
3648 struct rtw89_debugfs_priv *debugfs_priv,
3649 const char *buf, size_t count)
3650 {
3651 struct rtw89_btc *btc = &rtwdev->btc;
3652 const struct rtw89_btc_ver *ver = btc->ver;
3653 int ret;
3654
3655 ret = kstrtobool(buf, &btc->manual_ctrl);
3656 if (ret)
3657 return ret;
3658
3659 if (ver->fcxctrl == 7)
3660 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl;
3661 else
3662 btc->ctrl.ctrl.manual = btc->manual_ctrl;
3663
3664 return count;
3665 }
3666
rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)3667 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev,
3668 struct rtw89_debugfs_priv *debugfs_priv,
3669 const char *buf, size_t count)
3670 {
3671 struct rtw89_fw_log *log = &rtwdev->fw.log;
3672 bool fw_log_manual;
3673
3674 lockdep_assert_wiphy(rtwdev->hw->wiphy);
3675
3676 if (kstrtobool(buf, &fw_log_manual))
3677 goto out;
3678
3679 log->enable = fw_log_manual;
3680 if (log->enable)
3681 rtw89_fw_log_prepare(rtwdev);
3682 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual);
3683 out:
3684 return count;
3685 }
3686
rtw89_sta_link_info_get_iter(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,struct rtw89_sta_link * rtwsta_link)3687 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev,
3688 char *buf, size_t bufsz,
3689 struct rtw89_sta_link *rtwsta_link)
3690 {
3691 static const char * const he_gi_str[] = {
3692 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8",
3693 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6",
3694 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2",
3695 };
3696 static const char * const eht_gi_str[] = {
3697 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8",
3698 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6",
3699 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2",
3700 };
3701 struct rate_info *rate = &rtwsta_link->ra_report.txrate;
3702 struct ieee80211_rx_status *status = &rtwsta_link->rx_status;
3703 struct rtw89_hal *hal = &rtwdev->hal;
3704 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3705 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity;
3706 struct ieee80211_link_sta *link_sta;
3707 char *p = buf, *end = buf + bufsz;
3708 u8 evm_min, evm_max, evm_1ss;
3709 u16 max_rc_amsdu_len;
3710 u8 rssi;
3711 u8 snr;
3712 int i;
3713
3714 rcu_read_lock();
3715
3716 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3717 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len;
3718
3719 rcu_read_unlock();
3720
3721 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id,
3722 rtwsta_link->link_id);
3723
3724 if (rate->flags & RATE_INFO_FLAGS_MCS)
3725 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs,
3726 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
3727 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
3728 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss,
3729 rate->mcs,
3730 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
3731 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
3732 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss,
3733 rate->mcs,
3734 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
3735 he_gi_str[rate->he_gi] : "N/A");
3736 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS)
3737 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss,
3738 rate->mcs,
3739 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ?
3740 eht_gi_str[rate->eht_gi] : "N/A");
3741 else
3742 p += scnprintf(p, end - p, "Legacy %d", rate->legacy);
3743 p += scnprintf(p, end - p, "%s",
3744 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : "");
3745 p += scnprintf(p, end - p, " BW:%u",
3746 rtw89_rate_info_bw_to_mhz(rate->bw));
3747 p += scnprintf(p, end - p, " (hw_rate=0x%x)",
3748 rtwsta_link->ra_report.hw_rate);
3749 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n",
3750 rtwsta_link->max_agg_wait,
3751 max_rc_amsdu_len);
3752
3753 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id,
3754 rtwsta_link->link_id);
3755
3756 switch (status->encoding) {
3757 case RX_ENC_LEGACY:
3758 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx +
3759 (status->band != NL80211_BAND_2GHZ ? 4 : 0));
3760 break;
3761 case RX_ENC_HT:
3762 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx,
3763 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
3764 break;
3765 case RX_ENC_VHT:
3766 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss,
3767 status->rate_idx,
3768 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
3769 break;
3770 case RX_ENC_HE:
3771 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s",
3772 status->nss, status->rate_idx,
3773 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
3774 he_gi_str[status->he_gi] : "N/A");
3775 break;
3776 case RX_ENC_EHT:
3777 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s",
3778 status->nss, status->rate_idx,
3779 status->eht.gi < ARRAY_SIZE(eht_gi_str) ?
3780 eht_gi_str[status->eht.gi] : "N/A");
3781 break;
3782 }
3783 p += scnprintf(p, end - p, " BW:%u",
3784 rtw89_rate_info_bw_to_mhz(status->bw));
3785 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n",
3786 rtwsta_link->rx_hw_rate);
3787
3788 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
3789 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [",
3790 RTW89_RSSI_RAW_TO_DBM(rssi), rssi,
3791 rtwsta_link->prev_rssi);
3792 for (i = 0; i < ant_num; i++) {
3793 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]);
3794 p += scnprintf(p, end - p, "%d%s%s",
3795 RTW89_RSSI_RAW_TO_DBM(rssi),
3796 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "",
3797 i + 1 == ant_num ? "" : ", ");
3798 }
3799 p += scnprintf(p, end - p, "]\n");
3800
3801 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss);
3802 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2,
3803 (evm_1ss & 0x3) * 25);
3804 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) {
3805 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]);
3806 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]);
3807
3808 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)",
3809 i == 0 ? "" : " ",
3810 evm_min >> 2, (evm_min & 0x3) * 25,
3811 evm_max >> 2, (evm_max & 0x3) * 25);
3812 }
3813 p += scnprintf(p, end - p, "]\t");
3814
3815 snr = ewma_snr_read(&rtwsta_link->avg_snr);
3816 p += scnprintf(p, end - p, "SNR: %u\n", snr);
3817
3818 return p - buf;
3819 }
3820
rtw89_sta_info_get_iter(void * data,struct ieee80211_sta * sta)3821 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
3822 {
3823 struct rtw89_debugfs_iter_data *iter_data =
3824 (struct rtw89_debugfs_iter_data *)data;
3825 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3826 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3827 struct rtw89_sta_link *rtwsta_link;
3828 size_t bufsz = iter_data->bufsz;
3829 char *buf = iter_data->buf;
3830 char *p = buf, *end = buf + bufsz;
3831 unsigned int link_id;
3832
3833 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
3834 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link);
3835
3836 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf);
3837 }
3838
3839 static int
rtw89_debug_append_rx_rate(char * buf,size_t bufsz,struct rtw89_pkt_stat * pkt_stat,enum rtw89_hw_rate first_rate,int len)3840 rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat,
3841 enum rtw89_hw_rate first_rate, int len)
3842 {
3843 char *p = buf, *end = buf + bufsz;
3844 int i;
3845
3846 for (i = 0; i < len; i++)
3847 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ",
3848 pkt_stat->rx_rate_cnt[first_rate + i]);
3849
3850 return p - buf;
3851 }
3852
3853 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate}
3854 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate}
3855 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate}
3856
3857 static const struct rtw89_rx_rate_cnt_info {
3858 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM];
3859 int len;
3860 int ext;
3861 const char *rate_mode;
3862 } rtw89_rx_rate_cnt_infos[] = {
3863 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"},
3864 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"},
3865 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"},
3866 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"},
3867 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"},
3868 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"},
3869 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"},
3870 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"},
3871 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"},
3872 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"},
3873 };
3874
rtw89_debug_priv_phy_info_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)3875 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev,
3876 struct rtw89_debugfs_priv *debugfs_priv,
3877 char *buf, size_t bufsz)
3878 {
3879 struct rtw89_traffic_stats *stats = &rtwdev->stats;
3880 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat;
3881 const struct rtw89_chip_info *chip = rtwdev->chip;
3882 struct rtw89_debugfs_iter_data iter_data;
3883 const struct rtw89_rx_rate_cnt_info *info;
3884 struct rtw89_hal *hal = &rtwdev->hal;
3885 char *p = buf, *end = buf + bufsz;
3886 enum rtw89_hw_rate first_rate;
3887 u8 rssi;
3888 int i;
3889
3890 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi);
3891
3892 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d",
3893 stats->tx_throughput, stats->tx_throughput_raw,
3894 stats->tx_tfc_lv);
3895 if (hal->thermal_prot_lv)
3896 p += scnprintf(p, end - p, ", duty: %d%%",
3897 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP);
3898 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n",
3899 stats->rx_throughput, stats->rx_throughput_raw,
3900 stats->rx_tfc_lv);
3901 p += scnprintf(p, end - p, "Beacon: %u (%d dBm), TF: %u\n",
3902 pkt_stat->beacon_nr,
3903 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic);
3904 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n",
3905 stats->tx_avg_len,
3906 stats->rx_avg_len);
3907
3908 p += scnprintf(p, end - p, "RX count:\n");
3909
3910 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) {
3911 info = &rtw89_rx_rate_cnt_infos[i];
3912 first_rate = info->first_rate[chip->chip_gen];
3913 if (first_rate >= RTW89_HW_RATE_NR)
3914 continue;
3915
3916 p += scnprintf(p, end - p, "%10s [", info->rate_mode);
3917 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat,
3918 first_rate, info->len);
3919 if (info->ext) {
3920 p += scnprintf(p, end - p, "][");
3921 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat,
3922 first_rate + info->len, info->ext);
3923 }
3924 p += scnprintf(p, end - p, "]\n");
3925 }
3926
3927 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p);
3928 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data);
3929 p += iter_data.written_sz;
3930
3931 return p - buf;
3932 }
3933
rtw89_dump_addr_cam(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,struct rtw89_addr_cam_entry * addr_cam)3934 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev,
3935 char *buf, size_t bufsz,
3936 struct rtw89_addr_cam_entry *addr_cam)
3937 {
3938 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3939 const struct rtw89_sec_cam_entry *sec_entry;
3940 char *p = buf, *end = buf + bufsz;
3941 u8 sec_cam_idx;
3942 int i;
3943
3944 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n",
3945 addr_cam->addr_cam_idx);
3946 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n",
3947 addr_cam->bssid_cam_idx);
3948 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n",
3949 (int)sizeof(addr_cam->sec_cam_map),
3950 addr_cam->sec_cam_map);
3951 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) {
3952 sec_cam_idx = addr_cam->sec_ent[i];
3953 sec_entry = cam_info->sec_entries[sec_cam_idx];
3954 if (!sec_entry)
3955 continue;
3956 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i,
3957 sec_entry->sec_cam_idx);
3958 if (sec_entry->ext_key)
3959 p += scnprintf(p, end - p, ", %u",
3960 sec_entry->sec_cam_idx + 1);
3961 p += scnprintf(p, end - p, "\n");
3962 }
3963
3964 return p - buf;
3965 }
3966
3967 __printf(4, 5)
rtw89_dump_pkt_offload(char * buf,size_t bufsz,struct list_head * pkt_list,const char * fmt,...)3968 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list,
3969 const char *fmt, ...)
3970 {
3971 char *p = buf, *end = buf + bufsz;
3972 struct rtw89_pktofld_info *info;
3973 struct va_format vaf;
3974 va_list args;
3975
3976 if (list_empty(pkt_list))
3977 return 0;
3978
3979 va_start(args, fmt);
3980 vaf.va = &args;
3981 vaf.fmt = fmt;
3982
3983 p += scnprintf(p, end - p, "%pV", &vaf);
3984
3985 va_end(args);
3986
3987 list_for_each_entry(info, pkt_list, list)
3988 p += scnprintf(p, end - p, "%d ", info->id);
3989
3990 p += scnprintf(p, end - p, "\n");
3991
3992 return p - buf;
3993 }
3994
rtw89_vif_link_ids_get(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,u8 * mac,struct rtw89_vif_link * rtwvif_link,bool designated)3995 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev,
3996 char *buf, size_t bufsz, u8 *mac,
3997 struct rtw89_vif_link *rtwvif_link,
3998 bool designated)
3999 {
4000 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam;
4001 char *p = buf, *end = buf + bufsz;
4002
4003 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id,
4004 rtwvif_link->mac_addr);
4005 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id,
4006 designated ? " (*)" : "");
4007 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n",
4008 bssid_cam->bssid_cam_idx);
4009 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam);
4010 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list,
4011 "\tpkt_ofld[GENERAL]: ");
4012
4013 return p - buf;
4014 }
4015
4016 static
rtw89_vif_ids_get_iter(void * data,u8 * mac,struct ieee80211_vif * vif)4017 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
4018 {
4019 struct rtw89_debugfs_iter_data *iter_data =
4020 (struct rtw89_debugfs_iter_data *)data;
4021 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
4022 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
4023 struct rtw89_vif_link *designated_link;
4024 struct rtw89_vif_link *rtwvif_link;
4025 size_t bufsz = iter_data->bufsz;
4026 char *buf = iter_data->buf;
4027 char *p = buf, *end = buf + bufsz;
4028 unsigned int link_id;
4029
4030 designated_link = rtw89_get_designated_link(rtwvif);
4031
4032 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr);
4033 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4034 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link,
4035 rtwvif_link == designated_link);
4036
4037 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf);
4038 }
4039
rtw89_dump_ba_cam(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,struct rtw89_sta_link * rtwsta_link)4040 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev,
4041 char *buf, size_t bufsz,
4042 struct rtw89_sta_link *rtwsta_link)
4043 {
4044 struct rtw89_ba_cam_entry *entry;
4045 char *p = buf, *end = buf + bufsz;
4046 bool first = true;
4047
4048 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) {
4049 if (first) {
4050 p += scnprintf(p, end - p, "\tba_cam ");
4051 first = false;
4052 } else {
4053 p += scnprintf(p, end - p, ", ");
4054 }
4055 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid,
4056 (int)(entry - rtwdev->cam_info.ba_cam_entry));
4057 }
4058 p += scnprintf(p, end - p, "\n");
4059
4060 return p - buf;
4061 }
4062
rtw89_sta_link_ids_get(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,struct rtw89_sta_link * rtwsta_link,bool designated)4063 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev,
4064 char *buf, size_t bufsz,
4065 struct rtw89_sta_link *rtwsta_link,
4066 bool designated)
4067 {
4068 struct ieee80211_link_sta *link_sta;
4069 char *p = buf, *end = buf + bufsz;
4070
4071 rcu_read_lock();
4072
4073 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
4074
4075 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id,
4076 link_sta->addr);
4077
4078 rcu_read_unlock();
4079
4080 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id,
4081 designated ? " (*)" : "");
4082 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam);
4083 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link);
4084
4085 return p - buf;
4086 }
4087
rtw89_sta_ids_get_iter(void * data,struct ieee80211_sta * sta)4088 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta)
4089 {
4090 struct rtw89_debugfs_iter_data *iter_data =
4091 (struct rtw89_debugfs_iter_data *)data;
4092 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4093 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
4094 struct rtw89_sta_link *designated_link;
4095 struct rtw89_sta_link *rtwsta_link;
4096 size_t bufsz = iter_data->bufsz;
4097 char *buf = iter_data->buf;
4098 char *p = buf, *end = buf + bufsz;
4099 unsigned int link_id;
4100
4101 designated_link = rtw89_get_designated_link(rtwsta);
4102
4103 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr,
4104 sta->tdls ? "(TDLS)" : "");
4105 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
4106 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link,
4107 rtwsta_link == designated_link);
4108
4109 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf);
4110 }
4111
rtw89_debug_priv_stations_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)4112 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev,
4113 struct rtw89_debugfs_priv *debugfs_priv,
4114 char *buf, size_t bufsz)
4115 {
4116 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
4117 struct rtw89_debugfs_iter_data iter_data;
4118 char *p = buf, *end = buf + bufsz;
4119 u8 idx;
4120
4121 lockdep_assert_wiphy(rtwdev->hw->wiphy);
4122
4123 p += scnprintf(p, end - p, "map:\n");
4124 p += scnprintf(p, end - p, "\tmac_id: %*ph\n",
4125 (int)sizeof(rtwdev->mac_id_map),
4126 rtwdev->mac_id_map);
4127 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n",
4128 (int)sizeof(cam_info->addr_cam_map),
4129 cam_info->addr_cam_map);
4130 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n",
4131 (int)sizeof(cam_info->bssid_cam_map),
4132 cam_info->bssid_cam_map);
4133 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n",
4134 (int)sizeof(cam_info->sec_cam_map),
4135 cam_info->sec_cam_map);
4136 p += scnprintf(p, end - p, "\tba_cam: %*ph\n",
4137 (int)sizeof(cam_info->ba_cam_map),
4138 cam_info->ba_cam_map);
4139 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n",
4140 (int)sizeof(rtwdev->pkt_offload),
4141 rtwdev->pkt_offload);
4142
4143 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) {
4144 if (!(rtwdev->chip->support_bands & BIT(idx)))
4145 continue;
4146 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx],
4147 "\t\t[SCAN %u]: ", idx);
4148 }
4149
4150 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p);
4151 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw,
4152 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data);
4153 p += iter_data.written_sz;
4154
4155 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p);
4156 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data);
4157 p += iter_data.written_sz;
4158
4159 return p - buf;
4160 }
4161
rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev * rtwdev,u32 new)4162 static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new)
4163 {
4164 struct rtw89_hal *hal = &rtwdev->hal;
4165 u32 old = hal->disabled_dm_bitmap;
4166
4167 if (new == old)
4168 return;
4169
4170 hal->disabled_dm_bitmap = new;
4171
4172 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new);
4173 }
4174
rtw89_debug_disable_dm_set_flag(struct rtw89_dev * rtwdev,u8 flag)4175 static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag)
4176 {
4177 struct rtw89_hal *hal = &rtwdev->hal;
4178 u32 cur = hal->disabled_dm_bitmap;
4179
4180 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag));
4181 }
4182
rtw89_debug_disable_dm_clr_flag(struct rtw89_dev * rtwdev,u8 flag)4183 static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag)
4184 {
4185 struct rtw89_hal *hal = &rtwdev->hal;
4186 u32 cur = hal->disabled_dm_bitmap;
4187
4188 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag));
4189 }
4190
4191 #define DM_INFO(type) {RTW89_DM_ ## type, #type}
4192
4193 static const struct rtw89_disabled_dm_info {
4194 enum rtw89_dm_type type;
4195 const char *name;
4196 } rtw89_disabled_dm_infos[] = {
4197 DM_INFO(DYNAMIC_EDCCA),
4198 DM_INFO(THERMAL_PROTECT),
4199 DM_INFO(TAS),
4200 DM_INFO(MLO),
4201 };
4202
4203 static ssize_t
rtw89_debug_priv_disable_dm_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)4204 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev,
4205 struct rtw89_debugfs_priv *debugfs_priv,
4206 char *buf, size_t bufsz)
4207 {
4208 const struct rtw89_disabled_dm_info *info;
4209 struct rtw89_hal *hal = &rtwdev->hal;
4210 char *p = buf, *end = buf + bufsz;
4211 u32 disabled;
4212 int i;
4213
4214 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n",
4215 hal->disabled_dm_bitmap);
4216
4217 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) {
4218 info = &rtw89_disabled_dm_infos[i];
4219 disabled = BIT(info->type) & hal->disabled_dm_bitmap;
4220
4221 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type,
4222 info->name,
4223 disabled ? 'X' : 'O');
4224 }
4225
4226 return p - buf;
4227 }
4228
4229 static ssize_t
rtw89_debug_priv_disable_dm_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)4230 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev,
4231 struct rtw89_debugfs_priv *debugfs_priv,
4232 const char *buf, size_t count)
4233 {
4234 u32 conf;
4235 int ret;
4236
4237 ret = kstrtou32(buf, 0, &conf);
4238 if (ret)
4239 return -EINVAL;
4240
4241 rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf);
4242
4243 return count;
4244 }
4245
rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev * rtwdev,unsigned int link_id)4246 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev,
4247 unsigned int link_id)
4248 {
4249 struct ieee80211_vif *vif;
4250 struct rtw89_vif *rtwvif;
4251
4252 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4253 vif = rtwvif_to_vif(rtwvif);
4254 if (!ieee80211_vif_is_mld(vif))
4255 continue;
4256
4257 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id);
4258 }
4259 }
4260
4261 static ssize_t
rtw89_debug_priv_mlo_mode_get(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,char * buf,size_t bufsz)4262 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev,
4263 struct rtw89_debugfs_priv *debugfs_priv,
4264 char *buf, size_t bufsz)
4265 {
4266 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO);
4267 char *p = buf, *end = buf + bufsz;
4268 struct ieee80211_vif *vif;
4269 struct rtw89_vif *rtwvif;
4270 int count = 0;
4271
4272 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n",
4273 str_disable_enable(mlo_dm_dis));
4274
4275 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4276 vif = rtwvif_to_vif(rtwvif);
4277 if (!ieee80211_vif_is_mld(vif))
4278 continue;
4279
4280 p += scnprintf(p, end - p,
4281 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n",
4282 count++, rtwvif->mlo_mode, vif->valid_links,
4283 vif->active_links);
4284 }
4285
4286 if (count == 0)
4287 p += scnprintf(p, end - p, "\t(None)\n");
4288
4289 return p - buf;
4290 }
4291
4292 static ssize_t
rtw89_debug_priv_mlo_mode_set(struct rtw89_dev * rtwdev,struct rtw89_debugfs_priv * debugfs_priv,const char * buf,size_t count)4293 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev,
4294 struct rtw89_debugfs_priv *debugfs_priv,
4295 const char *buf, size_t count)
4296 {
4297 u8 num, mlo_mode;
4298 u32 argv;
4299
4300 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv);
4301 if (num != 2)
4302 return -EINVAL;
4303
4304 rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO);
4305
4306 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode);
4307
4308 switch (mlo_mode) {
4309 case RTW89_MLO_MODE_MLSR:
4310 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv);
4311 break;
4312 default:
4313 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n");
4314 rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO);
4315
4316 return -EOPNOTSUPP;
4317 }
4318
4319 return count;
4320 }
4321
4322 #define rtw89_debug_priv_get(name, opts...) \
4323 { \
4324 .cb_read = rtw89_debug_priv_ ##name## _get, \
4325 .opt = { opts }, \
4326 }
4327
4328 #define rtw89_debug_priv_set(name, opts...) \
4329 { \
4330 .cb_write = rtw89_debug_priv_ ##name## _set, \
4331 .opt = { opts }, \
4332 }
4333
4334 #define rtw89_debug_priv_select_and_get(name, opts...) \
4335 { \
4336 .cb_write = rtw89_debug_priv_ ##name## _select, \
4337 .cb_read = rtw89_debug_priv_ ##name## _get, \
4338 .opt = { opts }, \
4339 }
4340
4341 #define rtw89_debug_priv_set_and_get(name, opts...) \
4342 { \
4343 .cb_write = rtw89_debug_priv_ ##name## _set, \
4344 .cb_read = rtw89_debug_priv_ ##name## _get, \
4345 .opt = { opts }, \
4346 }
4347
4348 #define RSIZE_8K .rsize = 0x2000
4349 #define RSIZE_12K .rsize = 0x3000
4350 #define RSIZE_16K .rsize = 0x4000
4351 #define RSIZE_20K .rsize = 0x5000
4352 #define RSIZE_32K .rsize = 0x8000
4353 #define RSIZE_64K .rsize = 0x10000
4354 #define RSIZE_128K .rsize = 0x20000
4355 #define RSIZE_1M .rsize = 0x100000
4356 #define RLOCK .rlock = 1
4357 #define WLOCK .wlock = 1
4358 #define RWLOCK RLOCK, WLOCK
4359
4360 static const struct rtw89_debugfs rtw89_debugfs_templ = {
4361 .read_reg = rtw89_debug_priv_select_and_get(read_reg),
4362 .write_reg = rtw89_debug_priv_set(write_reg),
4363 .read_rf = rtw89_debug_priv_select_and_get(read_rf),
4364 .write_rf = rtw89_debug_priv_set(write_rf),
4365 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K),
4366 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK),
4367 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K),
4368 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK),
4369 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M),
4370 .send_h2c = rtw89_debug_priv_set(send_h2c),
4371 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK),
4372 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK),
4373 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K),
4374 .btc_manual = rtw89_debug_priv_set(btc_manual),
4375 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK),
4376 .phy_info = rtw89_debug_priv_get(phy_info),
4377 .stations = rtw89_debug_priv_get(stations, RLOCK),
4378 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK),
4379 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK),
4380 };
4381
4382 #define rtw89_debugfs_add(name, mode, fopname, parent) \
4383 do { \
4384 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \
4385 priv->rtwdev = rtwdev; \
4386 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \
4387 &file_ops_ ##fopname))) \
4388 pr_debug("Unable to initialize debugfs:%s\n", #name); \
4389 } while (0)
4390
4391 #define rtw89_debugfs_add_w(name) \
4392 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir)
4393 #define rtw89_debugfs_add_rw(name) \
4394 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir)
4395 #define rtw89_debugfs_add_r(name) \
4396 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir)
4397
4398 static
rtw89_debugfs_add_sec0(struct rtw89_dev * rtwdev,struct dentry * debugfs_topdir)4399 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir)
4400 {
4401 rtw89_debugfs_add_rw(read_reg);
4402 rtw89_debugfs_add_w(write_reg);
4403 rtw89_debugfs_add_rw(read_rf);
4404 rtw89_debugfs_add_w(write_rf);
4405 rtw89_debugfs_add_r(rf_reg_dump);
4406 rtw89_debugfs_add_r(txpwr_table);
4407 rtw89_debugfs_add_rw(mac_reg_dump);
4408 rtw89_debugfs_add_rw(mac_mem_dump);
4409 rtw89_debugfs_add_rw(mac_dbg_port_dump);
4410 }
4411
4412 static
rtw89_debugfs_add_sec1(struct rtw89_dev * rtwdev,struct dentry * debugfs_topdir)4413 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir)
4414 {
4415 rtw89_debugfs_add_w(send_h2c);
4416 rtw89_debugfs_add_rw(early_h2c);
4417 rtw89_debugfs_add_rw(fw_crash);
4418 rtw89_debugfs_add_r(btc_info);
4419 rtw89_debugfs_add_w(btc_manual);
4420 rtw89_debugfs_add_w(fw_log_manual);
4421 rtw89_debugfs_add_r(phy_info);
4422 rtw89_debugfs_add_r(stations);
4423 rtw89_debugfs_add_rw(disable_dm);
4424 rtw89_debugfs_add_rw(mlo_mode);
4425 }
4426
rtw89_debugfs_init(struct rtw89_dev * rtwdev)4427 void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
4428 {
4429 struct dentry *debugfs_topdir;
4430
4431 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ,
4432 sizeof(rtw89_debugfs_templ), GFP_KERNEL);
4433 if (!rtwdev->debugfs)
4434 return;
4435
4436 #if defined(__linux__)
4437 debugfs_topdir = debugfs_create_dir("rtw89",
4438 #elif defined(__FreeBSD__)
4439 debugfs_topdir = debugfs_create_dir(dev_name(rtwdev->dev),
4440 #endif
4441 rtwdev->hw->wiphy->debugfsdir);
4442
4443 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir);
4444 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir);
4445 }
4446
rtw89_debugfs_deinit(struct rtw89_dev * rtwdev)4447 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev)
4448 {
4449 kfree(rtwdev->debugfs);
4450 }
4451 #endif
4452
4453 #ifdef CONFIG_RTW89_DEBUGMSG
rtw89_debug(struct rtw89_dev * rtwdev,enum rtw89_debug_mask mask,const char * fmt,...)4454 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask,
4455 const char *fmt, ...)
4456 {
4457 struct va_format vaf = {
4458 .fmt = fmt,
4459 };
4460
4461 va_list args;
4462
4463 va_start(args, fmt);
4464 vaf.va = &args;
4465
4466 if (rtw89_debug_mask & mask)
4467 #if defined(__linux__)
4468 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf);
4469 #elif defined(__FreeBSD__)
4470 {
4471 char *str;
4472 vasprintf(&str, M_KMALLOC, vaf.fmt, args);
4473 dev_printk(KERN_DEBUG, rtwdev->dev, "%s", str);
4474 free(str, M_KMALLOC);
4475 }
4476 #endif
4477
4478 va_end(args);
4479 }
4480 EXPORT_SYMBOL(rtw89_debug);
4481 #endif
4482