1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "chan.h"
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15 #include "txrx.h"
16 #include "util.h"
17
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
19 {
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
21
22 return phy->phy0_phy1_offset(rtwdev, addr);
23 }
24
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
26 const struct rtw89_ra_report *report)
27 {
28 u32 bit_rate = report->bit_rate;
29
30 /* lower than ofdm, do not aggregate */
31 if (bit_rate < 550)
32 return 1;
33
34 /* avoid AMSDU for legacy rate */
35 if (report->might_fallback_legacy)
36 return 1;
37
38 /* lower than 20M vht 2ss mcs8, make it small */
39 if (bit_rate < 1800)
40 return 1200;
41
42 /* lower than 40M vht 2ss mcs9, make it medium */
43 if (bit_rate < 4000)
44 return 2600;
45
46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
47 if (bit_rate < 7000)
48 return 3500;
49
50 return rtwdev->chip->max_amsdu_limit;
51 }
52
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
54 {
55 u64 ra_mask = 0;
56 u8 mcs_cap;
57 int i, nss;
58
59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
60 mcs_cap = mcs_map & 0x3;
61 switch (mcs_cap) {
62 case 2:
63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
64 break;
65 case 1:
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
67 break;
68 case 0:
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
70 break;
71 default:
72 break;
73 }
74 }
75
76 return ra_mask;
77 }
78
get_he_ra_mask(struct ieee80211_link_sta * link_sta)79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta)
80 {
81 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
82 u16 mcs_map;
83
84 switch (link_sta->bandwidth) {
85 case IEEE80211_STA_RX_BW_160:
86 if (cap.he_cap_elem.phy_cap_info[0] &
87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
89 else
90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
91 break;
92 default:
93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
94 }
95
96 /* MCS11, MCS9, MCS7 */
97 return get_mcs_ra_mask(mcs_map, 11, 2);
98 }
99
get_eht_mcs_ra_mask(u8 * max_nss,u8 start_mcs,u8 n_nss)100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)
101 {
102 u64 nss_mcs_shift;
103 u64 nss_mcs_val;
104 u64 mask = 0;
105 int i, j;
106 u8 nss;
107
108 for (i = 0; i < n_nss; i++) {
109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);
110 if (!nss)
111 continue;
112
113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);
114
115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)
116 mask |= nss_mcs_val << nss_mcs_shift;
117 }
118
119 return mask;
120 }
121
get_eht_ra_mask(struct rtw89_vif_link * rtwvif_link,struct ieee80211_link_sta * link_sta)122 static u64 get_eht_ra_mask(struct rtw89_vif_link *rtwvif_link,
123 struct ieee80211_link_sta *link_sta)
124 {
125 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
126 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;
127 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
128 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;
129 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
130
131 switch (link_sta->bandwidth) {
132 case IEEE80211_STA_RX_BW_320:
133 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
134 /* MCS 9, 11, 13 */
135 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
136 case IEEE80211_STA_RX_BW_160:
137 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
138 /* MCS 9, 11, 13 */
139 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
140 case IEEE80211_STA_RX_BW_20:
141 if (vif->type == NL80211_IFTYPE_AP &&
142 !(he_phy_cap[0] & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
143 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
144 /* MCS 7, 9, 11, 13 */
145 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
146 }
147 fallthrough;
148 case IEEE80211_STA_RX_BW_80:
149 default:
150 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
151 /* MCS 9, 11, 13 */
152 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
153 }
154 }
155
156 #define RA_FLOOR_TABLE_SIZE 7
157 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)158 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
159 u8 ratr_state)
160 {
161 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
162 u8 rssi_lv = 0;
163 u8 i;
164
165 rssi >>= 1;
166 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
167 if (i >= ratr_state)
168 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
169 if (rssi < rssi_lv_t[i]) {
170 rssi_lv = i;
171 break;
172 }
173 }
174 if (rssi_lv == 0)
175 return 0xffffffffffffffffULL;
176 else if (rssi_lv == 1)
177 return 0xfffffffffffffff0ULL;
178 else if (rssi_lv == 2)
179 return 0xffffffffffffefe0ULL;
180 else if (rssi_lv == 3)
181 return 0xffffffffffffcfc0ULL;
182 else if (rssi_lv == 4)
183 return 0xffffffffffff8f80ULL;
184 else if (rssi_lv >= 5)
185 return 0xffffffffffff0f00ULL;
186
187 return 0xffffffffffffffffULL;
188 }
189
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)190 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
191 {
192 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
193 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
194
195 if (ra_mask == 0)
196 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
197
198 return ra_mask;
199 }
200
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan)201 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev,
202 struct rtw89_sta_link *rtwsta_link,
203 struct ieee80211_link_sta *link_sta,
204 const struct rtw89_chan *chan)
205 {
206 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
207 enum nl80211_band band;
208 u64 cfg_mask;
209
210 if (!rtwsta_link->use_cfg_mask)
211 return -1;
212
213 switch (chan->band_type) {
214 case RTW89_BAND_2G:
215 band = NL80211_BAND_2GHZ;
216 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
217 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
218 break;
219 case RTW89_BAND_5G:
220 band = NL80211_BAND_5GHZ;
221 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
222 RA_MASK_OFDM_RATES);
223 break;
224 case RTW89_BAND_6G:
225 band = NL80211_BAND_6GHZ;
226 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
227 RA_MASK_OFDM_RATES);
228 break;
229 default:
230 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
231 return -1;
232 }
233
234 if (link_sta->he_cap.has_he) {
235 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
236 RA_MASK_HE_1SS_RATES);
237 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
238 RA_MASK_HE_2SS_RATES);
239 } else if (link_sta->vht_cap.vht_supported) {
240 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
241 RA_MASK_VHT_1SS_RATES);
242 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
243 RA_MASK_VHT_2SS_RATES);
244 } else if (link_sta->ht_cap.ht_supported) {
245 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
246 RA_MASK_HT_1SS_RATES);
247 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
248 RA_MASK_HT_2SS_RATES);
249 }
250
251 return cfg_mask;
252 }
253
254 static const u64
255 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
256 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
257 static const u64
258 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
259 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
260 static const u64
261 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
262 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
263 static const u64
264 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,
265 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};
266 static const u64
267 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11,
268 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11};
269
rtw89_phy_ra_gi_ltf(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan,bool * fix_giltf_en,u8 * fix_giltf)270 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
271 struct rtw89_sta_link *rtwsta_link,
272 struct ieee80211_link_sta *link_sta,
273 const struct rtw89_chan *chan,
274 bool *fix_giltf_en, u8 *fix_giltf)
275 {
276 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
277 u8 band = chan->band_type;
278 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
279 u8 he_ltf = mask->control[nl_band].he_ltf;
280 u8 he_gi = mask->control[nl_band].he_gi;
281
282 *fix_giltf_en = true;
283
284 if (rtwdev->chip->chip_id == RTL8852C &&
285 chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
286 rtw89_sta_link_has_su_mu_4xhe08(link_sta))
287 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
288 else
289 *fix_giltf = RTW89_GILTF_2XHE08;
290
291 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he))
292 return;
293
294 if (he_ltf == 2 && he_gi == 2) {
295 *fix_giltf = RTW89_GILTF_LGI_4XHE32;
296 } else if (he_ltf == 2 && he_gi == 0) {
297 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
298 } else if (he_ltf == 1 && he_gi == 1) {
299 *fix_giltf = RTW89_GILTF_2XHE16;
300 } else if (he_ltf == 1 && he_gi == 0) {
301 *fix_giltf = RTW89_GILTF_2XHE08;
302 } else if (he_ltf == 0 && he_gi == 1) {
303 *fix_giltf = RTW89_GILTF_1XHE16;
304 } else if (he_ltf == 0 && he_gi == 0) {
305 *fix_giltf = RTW89_GILTF_1XHE08;
306 }
307 }
308
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,bool p2p,bool csi)309 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
310 struct rtw89_vif_link *rtwvif_link,
311 struct rtw89_sta_link *rtwsta_link,
312 struct ieee80211_link_sta *link_sta,
313 bool p2p, bool csi)
314 {
315 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
316 struct rtw89_ra_info *ra = &rtwsta_link->ra;
317 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
318 rtwvif_link->chanctx_idx);
319 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
320 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
321 u64 ra_mask = 0;
322 u64 ra_mask_bak;
323 u8 mode = 0;
324 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
325 u8 bw_mode = 0;
326 u8 stbc_en = 0;
327 u8 ldpc_en = 0;
328 u8 fix_giltf = 0;
329 u8 i;
330 bool sgi = false;
331 bool fix_giltf_en = false;
332
333 memset(ra, 0, sizeof(*ra));
334 /* Set the ra mask from sta's capability */
335 if (link_sta->eht_cap.has_eht) {
336 mode |= RTW89_RA_MODE_EHT;
337 ra_mask |= get_eht_ra_mask(rtwvif_link, link_sta);
338
339 if (rtwdev->hal.no_mcs_12_13)
340 high_rate_masks = rtw89_ra_mask_eht_mcs0_11;
341 else
342 high_rate_masks = rtw89_ra_mask_eht_rates;
343
344 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
345 chan, &fix_giltf_en, &fix_giltf);
346 } else if (link_sta->he_cap.has_he) {
347 mode |= RTW89_RA_MODE_HE;
348 csi_mode = RTW89_RA_RPT_MODE_HE;
349 ra_mask |= get_he_ra_mask(link_sta);
350 high_rate_masks = rtw89_ra_mask_he_rates;
351 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
352 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
353 stbc_en = 1;
354 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
355 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
356 ldpc_en = 1;
357 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
358 chan, &fix_giltf_en, &fix_giltf);
359 } else if (link_sta->vht_cap.vht_supported) {
360 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
361
362 mode |= RTW89_RA_MODE_VHT;
363 csi_mode = RTW89_RA_RPT_MODE_VHT;
364 /* MCS9 (non-20MHz), MCS8, MCS7 */
365 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
366 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1);
367 else
368 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
369 high_rate_masks = rtw89_ra_mask_vht_rates;
370 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
371 stbc_en = 1;
372 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
373 ldpc_en = 1;
374 } else if (link_sta->ht_cap.ht_supported) {
375 mode |= RTW89_RA_MODE_HT;
376 csi_mode = RTW89_RA_RPT_MODE_HT;
377 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
378 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
379 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
380 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
381 high_rate_masks = rtw89_ra_mask_ht_rates;
382 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
383 stbc_en = 1;
384 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
385 ldpc_en = 1;
386 }
387
388 switch (chan->band_type) {
389 case RTW89_BAND_2G:
390 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
391 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
392 mode |= RTW89_RA_MODE_CCK;
393 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
394 mode |= RTW89_RA_MODE_OFDM;
395 break;
396 case RTW89_BAND_5G:
397 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
398 mode |= RTW89_RA_MODE_OFDM;
399 break;
400 case RTW89_BAND_6G:
401 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
402 mode |= RTW89_RA_MODE_OFDM;
403 break;
404 default:
405 rtw89_err(rtwdev, "Unknown band type\n");
406 break;
407 }
408
409 ra_mask_bak = ra_mask;
410
411 if (mode >= RTW89_RA_MODE_HT) {
412 u64 mask = 0;
413 for (i = 0; i < rtwdev->hal.tx_nss; i++)
414 mask |= high_rate_masks[i];
415 if (mode & RTW89_RA_MODE_OFDM)
416 mask |= RA_MASK_SUBOFDM_RATES;
417 if (mode & RTW89_RA_MODE_CCK)
418 mask |= RA_MASK_SUBCCK_RATES;
419 ra_mask &= mask;
420 } else if (mode & RTW89_RA_MODE_OFDM) {
421 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
422 }
423
424 if (mode != RTW89_RA_MODE_CCK)
425 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
426
427 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
428 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
429
430 switch (link_sta->bandwidth) {
431 case IEEE80211_STA_RX_BW_160:
432 bw_mode = RTW89_CHANNEL_WIDTH_160;
433 sgi = link_sta->vht_cap.vht_supported &&
434 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
435 break;
436 case IEEE80211_STA_RX_BW_80:
437 bw_mode = RTW89_CHANNEL_WIDTH_80;
438 sgi = link_sta->vht_cap.vht_supported &&
439 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
440 break;
441 case IEEE80211_STA_RX_BW_40:
442 bw_mode = RTW89_CHANNEL_WIDTH_40;
443 sgi = link_sta->ht_cap.ht_supported &&
444 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
445 break;
446 default:
447 bw_mode = RTW89_CHANNEL_WIDTH_20;
448 sgi = link_sta->ht_cap.ht_supported &&
449 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
450 break;
451 }
452
453 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
454 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
455 ra->dcm_cap = 1;
456
457 if (rate_pattern->enable && !p2p) {
458 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
459 ra_mask &= rate_pattern->ra_mask;
460 mode = rate_pattern->ra_mode;
461 }
462
463 ra->bw_cap = bw_mode;
464 ra->er_cap = rtwsta_link->er_cap;
465 ra->mode_ctrl = mode;
466 ra->macid = rtwsta_link->mac_id;
467 ra->stbc_cap = stbc_en;
468 ra->ldpc_cap = ldpc_en;
469 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
470 ra->en_sgi = sgi;
471 ra->ra_mask = ra_mask;
472 ra->fix_giltf_en = fix_giltf_en;
473 ra->fix_giltf = fix_giltf;
474
475 if (!csi)
476 return;
477
478 ra->fixed_csi_rate_en = false;
479 ra->ra_csi_rate_en = true;
480 ra->cr_tbl_sel = false;
481 ra->band_num = rtwvif_link->phy_idx;
482 ra->csi_bw = bw_mode;
483 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
484 ra->csi_mcs_ss_idx = 5;
485 ra->csi_mode = csi_mode;
486 }
487
rtw89_phy_ra_update_sta_link(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u32 changed)488 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
489 struct rtw89_sta_link *rtwsta_link,
490 u32 changed)
491 {
492 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
493 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
494 struct rtw89_ra_info *ra = &rtwsta_link->ra;
495 struct ieee80211_link_sta *link_sta;
496
497 rcu_read_lock();
498
499 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
500 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
501 link_sta, vif->p2p, false);
502
503 rcu_read_unlock();
504
505 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
506 ra->upd_mask = 1;
507 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
508 ra->upd_bw_nss_mask = 1;
509
510 rtw89_debug(rtwdev, RTW89_DBG_RA,
511 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
512 ra->macid,
513 ra->bw_cap,
514 ra->ss_num,
515 ra->en_sgi,
516 ra->giltf);
517
518 rtw89_fw_h2c_ra(rtwdev, ra, false);
519 }
520
rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)521 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
522 u32 changed)
523 {
524 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
525 struct rtw89_sta_link *rtwsta_link;
526 unsigned int link_id;
527
528 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
529 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed);
530 }
531
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)532 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
533 u16 rate_base, u64 ra_mask, u8 ra_mode,
534 u32 rate_ctrl, u32 ctrl_skip, bool force)
535 {
536 u8 n, c;
537
538 if (rate_ctrl == ctrl_skip)
539 return true;
540
541 n = hweight32(rate_ctrl);
542 if (n == 0)
543 return true;
544
545 if (force && n != 1)
546 return false;
547
548 if (next->enable)
549 return false;
550
551 c = __fls(rate_ctrl);
552 next->rate = rate_base + c;
553 next->ra_mode = ra_mode;
554 next->ra_mask = ra_mask;
555 next->enable = true;
556
557 return true;
558 }
559
560 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
561 { \
562 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
563 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \
564 }
565
566 static
__rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const struct cfg80211_bitrate_mask * mask)567 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
568 struct rtw89_vif_link *rtwvif_link,
569 const struct cfg80211_bitrate_mask *mask)
570 {
571 struct ieee80211_supported_band *sband;
572 struct rtw89_phy_rate_pattern next_pattern = {0};
573 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
574 rtwvif_link->chanctx_idx);
575 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
576 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
577 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
578 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0),
579 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0),
580 };
581 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = {
582 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0),
583 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0),
584 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0),
585 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0),
586 };
587 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = {
588 RTW89_HW_RATE_BY_CHIP_GEN(MCS0),
589 RTW89_HW_RATE_BY_CHIP_GEN(MCS8),
590 RTW89_HW_RATE_BY_CHIP_GEN(MCS16),
591 RTW89_HW_RATE_BY_CHIP_GEN(MCS24),
592 };
593 u8 band = chan->band_type;
594 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
595 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
596 u8 tx_nss = rtwdev->hal.tx_nss;
597 u8 i;
598
599 for (i = 0; i < tx_nss; i++)
600 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
601 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
602 mask->control[nl_band].he_mcs[i],
603 0, true))
604 goto out;
605
606 for (i = 0; i < tx_nss; i++)
607 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen],
608 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
609 mask->control[nl_band].vht_mcs[i],
610 0, true))
611 goto out;
612
613 for (i = 0; i < tx_nss; i++)
614 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen],
615 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
616 mask->control[nl_band].ht_mcs[i],
617 0, true))
618 goto out;
619
620 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
621 * require at least one basic rate for ieee80211_set_bitrate_mask,
622 * so the decision just depends on if all bitrates are set or not.
623 */
624 sband = rtwdev->hw->wiphy->bands[nl_band];
625 if (band == RTW89_BAND_2G) {
626 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
627 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
628 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
629 mask->control[nl_band].legacy,
630 BIT(sband->n_bitrates) - 1, false))
631 goto out;
632 } else {
633 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
634 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
635 mask->control[nl_band].legacy,
636 BIT(sband->n_bitrates) - 1, false))
637 goto out;
638 }
639
640 if (!next_pattern.enable)
641 goto out;
642
643 rtwvif_link->rate_pattern = next_pattern;
644 rtw89_debug(rtwdev, RTW89_DBG_RA,
645 #if defined(__linux__)
646 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
647 #elif defined(__FreeBSD__)
648 "configure pattern: rate 0x%x, mask 0x%jx, mode 0x%x\n",
649 #endif
650 next_pattern.rate,
651 #if defined(__FreeBSD__)
652 (uintmax_t)
653 #endif
654 next_pattern.ra_mask,
655 next_pattern.ra_mode);
656 return;
657
658 out:
659 rtwvif_link->rate_pattern.enable = false;
660 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
661 }
662
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)663 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
664 struct ieee80211_vif *vif,
665 const struct cfg80211_bitrate_mask *mask)
666 {
667 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
668 struct rtw89_vif_link *rtwvif_link;
669 unsigned int link_id;
670
671 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
672 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask);
673 }
674
rtw89_phy_ra_update_sta_iter(void * data,struct ieee80211_sta * sta)675 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta)
676 {
677 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
678
679 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
680 }
681
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)682 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
683 {
684 ieee80211_iterate_stations_atomic(rtwdev->hw,
685 rtw89_phy_ra_update_sta_iter,
686 rtwdev);
687 }
688
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)689 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link)
690 {
691 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
692 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
693 struct rtw89_ra_info *ra = &rtwsta_link->ra;
694 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
695 struct ieee80211_link_sta *link_sta;
696 bool csi;
697
698 rcu_read_lock();
699
700 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
701 csi = rtw89_sta_has_beamformer_cap(link_sta);
702
703 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
704 link_sta, vif->p2p, csi);
705
706 rcu_read_unlock();
707
708 if (rssi > 40)
709 ra->init_rate_lv = 1;
710 else if (rssi > 20)
711 ra->init_rate_lv = 2;
712 else if (rssi > 1)
713 ra->init_rate_lv = 3;
714 else
715 ra->init_rate_lv = 0;
716 ra->upd_all = 1;
717 rtw89_debug(rtwdev, RTW89_DBG_RA,
718 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
719 ra->macid,
720 ra->mode_ctrl,
721 ra->bw_cap,
722 ra->ss_num,
723 ra->init_rate_lv);
724 rtw89_debug(rtwdev, RTW89_DBG_RA,
725 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
726 ra->dcm_cap,
727 ra->er_cap,
728 ra->ldpc_cap,
729 ra->stbc_cap,
730 ra->en_sgi,
731 ra->giltf);
732
733 rtw89_fw_h2c_ra(rtwdev, ra, csi);
734 }
735
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)736 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
737 const struct rtw89_chan *chan,
738 enum rtw89_bandwidth dbw)
739 {
740 enum rtw89_bandwidth cbw = chan->band_width;
741 u8 pri_ch = chan->primary_channel;
742 u8 central_ch = chan->channel;
743 u8 txsc_idx = 0;
744 u8 tmp = 0;
745
746 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
747 return txsc_idx;
748
749 switch (cbw) {
750 case RTW89_CHANNEL_WIDTH_40:
751 txsc_idx = pri_ch > central_ch ? 1 : 2;
752 break;
753 case RTW89_CHANNEL_WIDTH_80:
754 if (dbw == RTW89_CHANNEL_WIDTH_20) {
755 if (pri_ch > central_ch)
756 txsc_idx = (pri_ch - central_ch) >> 1;
757 else
758 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
759 } else {
760 txsc_idx = pri_ch > central_ch ? 9 : 10;
761 }
762 break;
763 case RTW89_CHANNEL_WIDTH_160:
764 if (pri_ch > central_ch)
765 tmp = (pri_ch - central_ch) >> 1;
766 else
767 tmp = ((central_ch - pri_ch) >> 1) + 1;
768
769 if (dbw == RTW89_CHANNEL_WIDTH_20) {
770 txsc_idx = tmp;
771 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
772 if (tmp == 1 || tmp == 3)
773 txsc_idx = 9;
774 else if (tmp == 5 || tmp == 7)
775 txsc_idx = 11;
776 else if (tmp == 2 || tmp == 4)
777 txsc_idx = 10;
778 else if (tmp == 6 || tmp == 8)
779 txsc_idx = 12;
780 else
781 return 0xff;
782 } else {
783 txsc_idx = pri_ch > central_ch ? 13 : 14;
784 }
785 break;
786 case RTW89_CHANNEL_WIDTH_80_80:
787 if (dbw == RTW89_CHANNEL_WIDTH_20) {
788 if (pri_ch > central_ch)
789 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
790 else
791 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
792 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
793 txsc_idx = pri_ch > central_ch ? 10 : 12;
794 } else {
795 txsc_idx = 14;
796 }
797 break;
798 default:
799 break;
800 }
801
802 return txsc_idx;
803 }
804 EXPORT_SYMBOL(rtw89_phy_get_txsc);
805
rtw89_phy_get_txsb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)806 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
807 enum rtw89_bandwidth dbw)
808 {
809 enum rtw89_bandwidth cbw = chan->band_width;
810 u8 pri_ch = chan->primary_channel;
811 u8 central_ch = chan->channel;
812 u8 txsb_idx = 0;
813
814 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
815 return txsb_idx;
816
817 switch (cbw) {
818 case RTW89_CHANNEL_WIDTH_40:
819 txsb_idx = pri_ch > central_ch ? 1 : 0;
820 break;
821 case RTW89_CHANNEL_WIDTH_80:
822 if (dbw == RTW89_CHANNEL_WIDTH_20)
823 txsb_idx = (pri_ch - central_ch + 6) / 4;
824 else
825 txsb_idx = pri_ch > central_ch ? 1 : 0;
826 break;
827 case RTW89_CHANNEL_WIDTH_160:
828 if (dbw == RTW89_CHANNEL_WIDTH_20)
829 txsb_idx = (pri_ch - central_ch + 14) / 4;
830 else if (dbw == RTW89_CHANNEL_WIDTH_40)
831 txsb_idx = (pri_ch - central_ch + 12) / 8;
832 else
833 txsb_idx = pri_ch > central_ch ? 1 : 0;
834 break;
835 case RTW89_CHANNEL_WIDTH_320:
836 if (dbw == RTW89_CHANNEL_WIDTH_20)
837 txsb_idx = (pri_ch - central_ch + 30) / 4;
838 else if (dbw == RTW89_CHANNEL_WIDTH_40)
839 txsb_idx = (pri_ch - central_ch + 28) / 8;
840 else if (dbw == RTW89_CHANNEL_WIDTH_80)
841 txsb_idx = (pri_ch - central_ch + 24) / 16;
842 else
843 txsb_idx = pri_ch > central_ch ? 1 : 0;
844 break;
845 default:
846 break;
847 }
848
849 return txsb_idx;
850 }
851 EXPORT_SYMBOL(rtw89_phy_get_txsb);
852
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)853 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
854 {
855 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
856 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
857 }
858
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)859 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
860 u32 addr, u32 mask)
861 {
862 const struct rtw89_chip_info *chip = rtwdev->chip;
863 const u32 *base_addr = chip->rf_base_addr;
864 u32 val, direct_addr;
865
866 if (rf_path >= rtwdev->chip->rf_path_num) {
867 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
868 return INV_RF_DATA;
869 }
870
871 addr &= 0xff;
872 direct_addr = base_addr[rf_path] + (addr << 2);
873 mask &= RFREG_MASK;
874
875 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
876
877 return val;
878 }
879 EXPORT_SYMBOL(rtw89_phy_read_rf);
880
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)881 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
882 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
883 {
884 bool busy;
885 bool done;
886 u32 val;
887 int ret;
888
889 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
890 1, 30, false, rtwdev);
891 if (ret) {
892 rtw89_err(rtwdev, "read rf busy swsi\n");
893 return INV_RF_DATA;
894 }
895
896 mask &= RFREG_MASK;
897
898 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
899 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
900 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
901 udelay(2);
902
903 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
904 30, false, rtwdev, R_SWSI_V1,
905 B_SWSI_R_DATA_DONE_V1);
906 if (ret) {
907 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags))
908 rtw89_err(rtwdev, "read swsi busy\n");
909 return INV_RF_DATA;
910 }
911
912 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
913 }
914
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)915 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
916 u32 addr, u32 mask)
917 {
918 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
919
920 if (rf_path >= rtwdev->chip->rf_path_num) {
921 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
922 return INV_RF_DATA;
923 }
924
925 if (ad_sel)
926 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
927 else
928 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
929 }
930 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
931
rtw89_phy_read_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)932 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
933 enum rtw89_rf_path rf_path, u32 addr)
934 {
935 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24};
936 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC};
937 bool busy, done;
938 int ret;
939 u32 val;
940
941 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
942 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
943 1, 3800, false,
944 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
945 if (ret) {
946 rtw89_warn(rtwdev, "poll HWSI is busy\n");
947 return INV_RF_DATA;
948 }
949
950 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
951 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
952 udelay(2);
953
954 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
955 1, 3800, false,
956 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
957 if (ret) {
958 rtw89_warn(rtwdev, "read HWSI is busy\n");
959 val = INV_RF_DATA;
960 goto out;
961 }
962
963 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
964 out:
965 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
966
967 return val;
968 }
969
rtw89_phy_read_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)970 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
971 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
972 {
973 u32 val;
974
975 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
976
977 return (val & mask) >> __ffs(mask);
978 }
979
rtw89_phy_read_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)980 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
981 u32 addr, u32 mask)
982 {
983 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
984
985 if (rf_path >= rtwdev->chip->rf_path_num) {
986 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
987 return INV_RF_DATA;
988 }
989
990 if (ad_sel)
991 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
992 else
993 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
994 }
995 EXPORT_SYMBOL(rtw89_phy_read_rf_v2);
996
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)997 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
998 u32 addr, u32 mask, u32 data)
999 {
1000 const struct rtw89_chip_info *chip = rtwdev->chip;
1001 const u32 *base_addr = chip->rf_base_addr;
1002 u32 direct_addr;
1003
1004 if (rf_path >= rtwdev->chip->rf_path_num) {
1005 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1006 return false;
1007 }
1008
1009 addr &= 0xff;
1010 direct_addr = base_addr[rf_path] + (addr << 2);
1011 mask &= RFREG_MASK;
1012
1013 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
1014
1015 /* delay to ensure writing properly */
1016 udelay(1);
1017
1018 return true;
1019 }
1020 EXPORT_SYMBOL(rtw89_phy_write_rf);
1021
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1022 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
1023 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
1024 u32 data)
1025 {
1026 u8 bit_shift;
1027 u32 val;
1028 bool busy, b_msk_en = false;
1029 int ret;
1030
1031 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
1032 1, 30, false, rtwdev);
1033 if (ret) {
1034 rtw89_err(rtwdev, "write rf busy swsi\n");
1035 return false;
1036 }
1037
1038 data &= RFREG_MASK;
1039 mask &= RFREG_MASK;
1040
1041 if (mask != RFREG_MASK) {
1042 b_msk_en = true;
1043 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
1044 mask);
1045 bit_shift = __ffs(mask);
1046 data = (data << bit_shift) & RFREG_MASK;
1047 }
1048
1049 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
1050 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
1051 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
1052 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
1053
1054 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
1055
1056 return true;
1057 }
1058
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1059 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1060 u32 addr, u32 mask, u32 data)
1061 {
1062 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
1063
1064 if (rf_path >= rtwdev->chip->rf_path_num) {
1065 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1066 return false;
1067 }
1068
1069 if (ad_sel)
1070 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1071 else
1072 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1073 }
1074 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
1075
1076 static
rtw89_phy_write_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1077 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1078 u32 addr, u32 data)
1079 {
1080 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24};
1081 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0};
1082 bool busy;
1083 u32 val;
1084 int ret;
1085
1086 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1087 1, 3800, false,
1088 rtwdev, addr_is_idle[rf_path], BIT(29));
1089 if (ret) {
1090 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1091 return false;
1092 }
1093
1094 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) |
1095 u32_encode_bits(data, B_HWSI_DATA_VAL);
1096
1097 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1098
1099 return true;
1100 }
1101
1102 static
rtw89_phy_write_rf_a_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1103 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1104 u32 addr, u32 mask, u32 data)
1105 {
1106 u32 val;
1107
1108 if (mask == RFREG_MASK) {
1109 val = data;
1110 } else {
1111 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1112 val &= ~mask;
1113 val |= (data << __ffs(mask)) & mask;
1114 }
1115
1116 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1117 }
1118
rtw89_phy_write_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1119 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1120 u32 addr, u32 mask, u32 data)
1121 {
1122 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1123
1124 if (rf_path >= rtwdev->chip->rf_path_num) {
1125 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1126 return INV_RF_DATA;
1127 }
1128
1129 if (ad_sel)
1130 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1131 else
1132 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1133 }
1134 EXPORT_SYMBOL(rtw89_phy_write_rf_v2);
1135
rtw89_chip_rf_v1(struct rtw89_dev * rtwdev)1136 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1137 {
1138 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1139 }
1140
__rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1141 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1142 enum rtw89_phy_idx phy_idx)
1143 {
1144 const struct rtw89_chip_info *chip = rtwdev->chip;
1145
1146 chip->ops->bb_reset(rtwdev, phy_idx);
1147 }
1148
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev)1149 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev)
1150 {
1151 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1152 if (rtwdev->dbcc_en)
1153 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1);
1154 }
1155
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1156 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1157 const struct rtw89_reg2_def *reg,
1158 enum rtw89_rf_path rf_path,
1159 void *extra_data)
1160 {
1161 u32 addr;
1162
1163 if (reg->addr == 0xfe) {
1164 mdelay(50);
1165 } else if (reg->addr == 0xfd) {
1166 mdelay(5);
1167 } else if (reg->addr == 0xfc) {
1168 mdelay(1);
1169 } else if (reg->addr == 0xfb) {
1170 udelay(50);
1171 } else if (reg->addr == 0xfa) {
1172 udelay(5);
1173 } else if (reg->addr == 0xf9) {
1174 udelay(1);
1175 } else if (reg->data == BYPASS_CR_DATA) {
1176 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1177 } else {
1178 addr = reg->addr;
1179
1180 if ((uintptr_t)extra_data == RTW89_PHY_1)
1181 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1182
1183 rtw89_phy_write32(rtwdev, addr, reg->data);
1184 }
1185 }
1186
1187 union rtw89_phy_bb_gain_arg {
1188 u32 addr;
1189 struct {
1190 union {
1191 u8 type;
1192 struct {
1193 u8 rxsc_start:4;
1194 u8 bw:4;
1195 };
1196 };
1197 u8 path;
1198 u8 gain_band;
1199 u8 cfg_type;
1200 };
1201 } __packed;
1202
1203 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1204 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1205 union rtw89_phy_bb_gain_arg arg, u32 data)
1206 {
1207 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1208 u8 type = arg.type;
1209 u8 path = arg.path;
1210 u8 gband = arg.gain_band;
1211 int i;
1212
1213 switch (type) {
1214 case 0:
1215 for (i = 0; i < 4; i++, data >>= 8)
1216 gain->lna_gain[gband][path][i] = data & 0xff;
1217 break;
1218 case 1:
1219 for (i = 4; i < 7; i++, data >>= 8)
1220 gain->lna_gain[gband][path][i] = data & 0xff;
1221 break;
1222 case 2:
1223 for (i = 0; i < 2; i++, data >>= 8)
1224 gain->tia_gain[gband][path][i] = data & 0xff;
1225 break;
1226 default:
1227 rtw89_warn(rtwdev,
1228 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
1229 arg.addr, data, type);
1230 break;
1231 }
1232 }
1233
1234 enum rtw89_phy_bb_rxsc_start_idx {
1235 RTW89_BB_RXSC_START_IDX_FULL = 0,
1236 RTW89_BB_RXSC_START_IDX_20 = 1,
1237 RTW89_BB_RXSC_START_IDX_20_1 = 5,
1238 RTW89_BB_RXSC_START_IDX_40 = 9,
1239 RTW89_BB_RXSC_START_IDX_80 = 13,
1240 };
1241
1242 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1243 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1244 union rtw89_phy_bb_gain_arg arg, u32 data)
1245 {
1246 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1247 u8 rxsc_start = arg.rxsc_start;
1248 u8 bw = arg.bw;
1249 u8 path = arg.path;
1250 u8 gband = arg.gain_band;
1251 u8 rxsc;
1252 s8 ofst;
1253 int i;
1254
1255 switch (bw) {
1256 case RTW89_CHANNEL_WIDTH_20:
1257 gain->rpl_ofst_20[gband][path] = (s8)data;
1258 break;
1259 case RTW89_CHANNEL_WIDTH_40:
1260 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1261 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1262 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1263 for (i = 0; i < 2; i++, data >>= 8) {
1264 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1265 ofst = (s8)(data & 0xff);
1266 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1267 }
1268 }
1269 break;
1270 case RTW89_CHANNEL_WIDTH_80:
1271 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1272 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1273 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1274 for (i = 0; i < 4; i++, data >>= 8) {
1275 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1276 ofst = (s8)(data & 0xff);
1277 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1278 }
1279 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1280 for (i = 0; i < 2; i++, data >>= 8) {
1281 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1282 ofst = (s8)(data & 0xff);
1283 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1284 }
1285 }
1286 break;
1287 case RTW89_CHANNEL_WIDTH_160:
1288 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1289 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1290 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1291 for (i = 0; i < 4; i++, data >>= 8) {
1292 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1293 ofst = (s8)(data & 0xff);
1294 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1295 }
1296 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
1297 for (i = 0; i < 4; i++, data >>= 8) {
1298 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
1299 ofst = (s8)(data & 0xff);
1300 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1301 }
1302 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1303 for (i = 0; i < 4; i++, data >>= 8) {
1304 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1305 ofst = (s8)(data & 0xff);
1306 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1307 }
1308 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
1309 for (i = 0; i < 2; i++, data >>= 8) {
1310 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
1311 ofst = (s8)(data & 0xff);
1312 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1313 }
1314 }
1315 break;
1316 default:
1317 rtw89_warn(rtwdev,
1318 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1319 arg.addr, data, bw);
1320 break;
1321 }
1322 }
1323
1324 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1325 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1326 union rtw89_phy_bb_gain_arg arg, u32 data)
1327 {
1328 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1329 u8 type = arg.type;
1330 u8 path = arg.path;
1331 u8 gband = arg.gain_band;
1332 int i;
1333
1334 switch (type) {
1335 case 0:
1336 for (i = 0; i < 4; i++, data >>= 8)
1337 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1338 break;
1339 case 1:
1340 for (i = 4; i < 7; i++, data >>= 8)
1341 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1342 break;
1343 default:
1344 rtw89_warn(rtwdev,
1345 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
1346 arg.addr, data, type);
1347 break;
1348 }
1349 }
1350
1351 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1352 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1353 union rtw89_phy_bb_gain_arg arg, u32 data)
1354 {
1355 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1356 u8 type = arg.type;
1357 u8 path = arg.path;
1358 u8 gband = arg.gain_band;
1359 int i;
1360
1361 switch (type) {
1362 case 0:
1363 for (i = 0; i < 4; i++, data >>= 8)
1364 gain->lna_op1db[gband][path][i] = data & 0xff;
1365 break;
1366 case 1:
1367 for (i = 4; i < 7; i++, data >>= 8)
1368 gain->lna_op1db[gband][path][i] = data & 0xff;
1369 break;
1370 case 2:
1371 for (i = 0; i < 4; i++, data >>= 8)
1372 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1373 break;
1374 case 3:
1375 for (i = 4; i < 8; i++, data >>= 8)
1376 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1377 break;
1378 default:
1379 rtw89_warn(rtwdev,
1380 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
1381 arg.addr, data, type);
1382 break;
1383 }
1384 }
1385
rtw89_phy_config_bb_gain_ax(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1386 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1387 const struct rtw89_reg2_def *reg,
1388 enum rtw89_rf_path rf_path,
1389 void *extra_data)
1390 {
1391 const struct rtw89_chip_info *chip = rtwdev->chip;
1392 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1393 struct rtw89_efuse *efuse = &rtwdev->efuse;
1394
1395 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1396 return;
1397
1398 if (arg.path >= chip->rf_path_num)
1399 return;
1400
1401 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1402 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1403 return;
1404 }
1405
1406 switch (arg.cfg_type) {
1407 case 0:
1408 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1409 break;
1410 case 1:
1411 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1412 break;
1413 case 2:
1414 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1415 break;
1416 case 3:
1417 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1418 break;
1419 case 4:
1420 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
1421 if (efuse->rfe_type < 50)
1422 break;
1423 fallthrough;
1424 default:
1425 rtw89_warn(rtwdev,
1426 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1427 arg.addr, reg->data, arg.cfg_type);
1428 break;
1429 }
1430 }
1431
1432 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1433 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1434 const struct rtw89_reg2_def *reg,
1435 enum rtw89_rf_path rf_path,
1436 struct rtw89_fw_h2c_rf_reg_info *info)
1437 {
1438 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1439 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1440
1441 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1442 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1443 rf_path, info->curr_idx);
1444 return;
1445 }
1446
1447 info->rtw89_phy_config_rf_h2c[page][idx] =
1448 cpu_to_le32((reg->addr << 20) | reg->data);
1449 info->curr_idx++;
1450 }
1451
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1452 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1453 struct rtw89_fw_h2c_rf_reg_info *info)
1454 {
1455 u16 remain = info->curr_idx;
1456 u16 len = 0;
1457 u8 i;
1458 int ret = 0;
1459
1460 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1461 rtw89_warn(rtwdev,
1462 "rf reg h2c total len %d larger than %d\n",
1463 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1464 ret = -EINVAL;
1465 goto out;
1466 }
1467
1468 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1469 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1470 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1471 if (ret)
1472 goto out;
1473 }
1474 out:
1475 info->curr_idx = 0;
1476
1477 return ret;
1478 }
1479
rtw89_phy_config_rf_reg_noio(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1480 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1481 const struct rtw89_reg2_def *reg,
1482 enum rtw89_rf_path rf_path,
1483 void *extra_data)
1484 {
1485 u32 addr = reg->addr;
1486
1487 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1488 addr == 0xfa || addr == 0xf9)
1489 return;
1490
1491 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1492 return;
1493
1494 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1495 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1496 }
1497
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1498 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1499 const struct rtw89_reg2_def *reg,
1500 enum rtw89_rf_path rf_path,
1501 void *extra_data)
1502 {
1503 if (reg->addr == 0xfe) {
1504 mdelay(50);
1505 } else if (reg->addr == 0xfd) {
1506 mdelay(5);
1507 } else if (reg->addr == 0xfc) {
1508 mdelay(1);
1509 } else if (reg->addr == 0xfb) {
1510 udelay(50);
1511 } else if (reg->addr == 0xfa) {
1512 udelay(5);
1513 } else if (reg->addr == 0xf9) {
1514 udelay(1);
1515 } else {
1516 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1517 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1518 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1519 }
1520 }
1521
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1522 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1523 const struct rtw89_reg2_def *reg,
1524 enum rtw89_rf_path rf_path,
1525 void *extra_data)
1526 {
1527 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1528
1529 if (reg->addr < 0x100)
1530 return;
1531
1532 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1533 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1534 }
1535 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1536
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1537 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1538 const struct rtw89_phy_table *table,
1539 u32 *headline_size, u32 *headline_idx,
1540 u8 rfe, u8 cv)
1541 {
1542 const struct rtw89_reg2_def *reg;
1543 u32 headline;
1544 u32 compare, target;
1545 u8 rfe_para, cv_para;
1546 u8 cv_max = 0;
1547 bool case_matched = false;
1548 u32 i;
1549
1550 for (i = 0; i < table->n_regs; i++) {
1551 reg = &table->regs[i];
1552 headline = get_phy_headline(reg->addr);
1553 if (headline != PHY_HEADLINE_VALID)
1554 break;
1555 }
1556 *headline_size = i;
1557 if (*headline_size == 0)
1558 return 0;
1559
1560 /* case 1: RFE match, CV match */
1561 compare = get_phy_compare(rfe, cv);
1562 for (i = 0; i < *headline_size; i++) {
1563 reg = &table->regs[i];
1564 target = get_phy_target(reg->addr);
1565 if (target == compare) {
1566 *headline_idx = i;
1567 return 0;
1568 }
1569 }
1570
1571 /* case 2: RFE match, CV don't care */
1572 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1573 for (i = 0; i < *headline_size; i++) {
1574 reg = &table->regs[i];
1575 target = get_phy_target(reg->addr);
1576 if (target == compare) {
1577 *headline_idx = i;
1578 return 0;
1579 }
1580 }
1581
1582 /* case 3: RFE match, CV max in table */
1583 for (i = 0; i < *headline_size; i++) {
1584 reg = &table->regs[i];
1585 rfe_para = get_phy_cond_rfe(reg->addr);
1586 cv_para = get_phy_cond_cv(reg->addr);
1587 if (rfe_para == rfe) {
1588 if (cv_para >= cv_max) {
1589 cv_max = cv_para;
1590 *headline_idx = i;
1591 case_matched = true;
1592 }
1593 }
1594 }
1595
1596 if (case_matched)
1597 return 0;
1598
1599 /* case 4: RFE don't care, CV max in table */
1600 for (i = 0; i < *headline_size; i++) {
1601 reg = &table->regs[i];
1602 rfe_para = get_phy_cond_rfe(reg->addr);
1603 cv_para = get_phy_cond_cv(reg->addr);
1604 if (rfe_para == PHY_COND_DONT_CARE) {
1605 if (cv_para >= cv_max) {
1606 cv_max = cv_para;
1607 *headline_idx = i;
1608 case_matched = true;
1609 }
1610 }
1611 }
1612
1613 if (case_matched)
1614 return 0;
1615
1616 return -EINVAL;
1617 }
1618
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1619 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1620 const struct rtw89_phy_table *table,
1621 void (*config)(struct rtw89_dev *rtwdev,
1622 const struct rtw89_reg2_def *reg,
1623 enum rtw89_rf_path rf_path,
1624 void *data),
1625 void *extra_data)
1626 {
1627 const struct rtw89_reg2_def *reg;
1628 enum rtw89_rf_path rf_path = table->rf_path;
1629 u8 rfe = rtwdev->efuse.rfe_type;
1630 u8 cv = rtwdev->hal.cv;
1631 u32 i;
1632 u32 headline_size = 0, headline_idx = 0;
1633 u32 target = 0, cfg_target;
1634 u8 cond;
1635 bool is_matched = true;
1636 bool target_found = false;
1637 int ret;
1638
1639 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1640 &headline_idx, rfe, cv);
1641 if (ret) {
1642 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1643 return;
1644 }
1645
1646 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1647 for (i = headline_size; i < table->n_regs; i++) {
1648 reg = &table->regs[i];
1649 cond = get_phy_cond(reg->addr);
1650 switch (cond) {
1651 case PHY_COND_BRANCH_IF:
1652 case PHY_COND_BRANCH_ELIF:
1653 target = get_phy_target(reg->addr);
1654 break;
1655 case PHY_COND_BRANCH_ELSE:
1656 is_matched = false;
1657 if (!target_found) {
1658 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1659 reg->addr, reg->data);
1660 return;
1661 }
1662 break;
1663 case PHY_COND_BRANCH_END:
1664 is_matched = true;
1665 target_found = false;
1666 break;
1667 case PHY_COND_CHECK:
1668 if (target_found) {
1669 is_matched = false;
1670 break;
1671 }
1672
1673 if (target == cfg_target) {
1674 is_matched = true;
1675 target_found = true;
1676 } else {
1677 is_matched = false;
1678 target_found = false;
1679 }
1680 break;
1681 default:
1682 if (is_matched)
1683 config(rtwdev, reg, rf_path, extra_data);
1684 break;
1685 }
1686 }
1687 }
1688
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1689 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1690 {
1691 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1692 const struct rtw89_chip_info *chip = rtwdev->chip;
1693 const struct rtw89_phy_table *bb_table;
1694 const struct rtw89_phy_table *bb_gain_table;
1695
1696 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1697 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1698 if (rtwdev->dbcc_en)
1699 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1700 (void *)RTW89_PHY_1);
1701
1702 rtw89_chip_init_txpwr_unit(rtwdev);
1703
1704 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1705 if (bb_gain_table)
1706 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1707 chip->phy_def->config_bb_gain, NULL);
1708
1709 rtw89_phy_bb_reset(rtwdev);
1710 }
1711
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1712 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1713 {
1714 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1715 udelay(1);
1716 return rtw89_phy_read32(rtwdev, 0x8080);
1717 }
1718
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev,bool noio)1719 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1720 {
1721 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1722 enum rtw89_rf_path rf_path, void *data);
1723 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1724 const struct rtw89_chip_info *chip = rtwdev->chip;
1725 const struct rtw89_phy_table *rf_table;
1726 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1727 u8 path;
1728
1729 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1730 if (!rf_reg_info)
1731 return;
1732
1733 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1734 rf_table = elm_info->rf_radio[path] ?
1735 elm_info->rf_radio[path] : chip->rf_table[path];
1736 rf_reg_info->rf_path = rf_table->rf_path;
1737 if (noio)
1738 config = rtw89_phy_config_rf_reg_noio;
1739 else
1740 config = rf_table->config ? rf_table->config :
1741 rtw89_phy_config_rf_reg;
1742 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1743 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1744 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1745 rf_reg_info->rf_path);
1746 }
1747 kfree(rf_reg_info);
1748 }
1749
rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev * rtwdev)1750 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
1751 {
1752 const struct rtw89_chip_info *chip = rtwdev->chip;
1753 u32 val;
1754 int ret;
1755
1756 /* IQK/DPK clock & reset */
1757 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
1758 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
1759 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
1760 if (chip->chip_id != RTL8851B)
1761 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
1762 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
1763 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
1764
1765 /* check 0x8080 */
1766 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
1767
1768 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1769 1000, false, rtwdev);
1770 if (ret)
1771 #if defined(__linux__)
1772 rtw89_err(rtwdev, "failed to poll nctl block\n");
1773 #elif defined(__FreeBSD__)
1774 rtw89_err(rtwdev, "failed to poll nctl block: ret %d val %#06x\n", ret, val);
1775 #endif
1776 }
1777
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1778 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1779 {
1780 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1781 const struct rtw89_chip_info *chip = rtwdev->chip;
1782 const struct rtw89_phy_table *nctl_table;
1783
1784 rtw89_phy_preinit_rf_nctl(rtwdev);
1785
1786 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
1787 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1788
1789 if (chip->nctl_post_table)
1790 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1791 }
1792
rtw89_phy0_phy1_offset_ax(struct rtw89_dev * rtwdev,u32 addr)1793 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
1794 {
1795 u32 phy_page = addr >> 8;
1796 u32 ofst = 0;
1797
1798 switch (phy_page) {
1799 case 0x6:
1800 case 0x7:
1801 case 0x8:
1802 case 0x9:
1803 case 0xa:
1804 case 0xb:
1805 case 0xc:
1806 case 0xd:
1807 case 0x19:
1808 case 0x1a:
1809 case 0x1b:
1810 ofst = 0x2000;
1811 break;
1812 default:
1813 /* warning case */
1814 ofst = 0;
1815 break;
1816 }
1817
1818 if (phy_page >= 0x40 && phy_page <= 0x4f)
1819 ofst = 0x2000;
1820
1821 return ofst;
1822 }
1823
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1824 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1825 u32 data, enum rtw89_phy_idx phy_idx)
1826 {
1827 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1828 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1829 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1830 }
1831 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1832
rtw89_phy_write32_idx_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1833 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1834 enum rtw89_phy_idx phy_idx)
1835 {
1836 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1837 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1838 rtw89_phy_write32_set(rtwdev, addr, bits);
1839 }
1840 EXPORT_SYMBOL(rtw89_phy_write32_idx_set);
1841
rtw89_phy_write32_idx_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1842 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1843 enum rtw89_phy_idx phy_idx)
1844 {
1845 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1846 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1847 rtw89_phy_write32_clr(rtwdev, addr, bits);
1848 }
1849 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr);
1850
rtw89_phy_read32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,enum rtw89_phy_idx phy_idx)1851 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1852 enum rtw89_phy_idx phy_idx)
1853 {
1854 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1855 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1856 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1857 }
1858 EXPORT_SYMBOL(rtw89_phy_read32_idx);
1859
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1860 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1861 u32 val)
1862 {
1863 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1864
1865 if (!rtwdev->dbcc_en)
1866 return;
1867
1868 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1869 }
1870 EXPORT_SYMBOL(rtw89_phy_set_phy_regs);
1871
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1872 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1873 const struct rtw89_phy_reg3_tbl *tbl)
1874 {
1875 const struct rtw89_reg3_def *reg3;
1876 int i;
1877
1878 for (i = 0; i < tbl->size; i++) {
1879 reg3 = &tbl->reg3[i];
1880 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1881 }
1882 }
1883 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1884
rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev * rtwdev,u8 ant_gain_regd)1885 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd)
1886 {
1887 switch (ant_gain_regd) {
1888 case RTW89_ANT_GAIN_ETSI:
1889 return RTW89_ETSI;
1890 default:
1891 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1892 "unknown antenna gain domain: %d\n",
1893 ant_gain_regd);
1894 return RTW89_REGD_NUM;
1895 }
1896 }
1897
1898 /* antenna gain in unit of 0.25 dbm */
1899 #define RTW89_ANT_GAIN_2GHZ_MIN -8
1900 #define RTW89_ANT_GAIN_2GHZ_MAX 14
1901 #define RTW89_ANT_GAIN_5GHZ_MIN -8
1902 #define RTW89_ANT_GAIN_5GHZ_MAX 20
1903 #define RTW89_ANT_GAIN_6GHZ_MIN -8
1904 #define RTW89_ANT_GAIN_6GHZ_MAX 20
1905
1906 #define RTW89_ANT_GAIN_REF_2GHZ 14
1907 #define RTW89_ANT_GAIN_REF_5GHZ 20
1908 #define RTW89_ANT_GAIN_REF_6GHZ 20
1909
rtw89_phy_ant_gain_init(struct rtw89_dev * rtwdev)1910 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev)
1911 {
1912 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
1913 const struct rtw89_chip_info *chip = rtwdev->chip;
1914 struct rtw89_acpi_rtag_result res = {};
1915 u32 domain;
1916 int ret;
1917 u8 i, j;
1918 u8 regd;
1919 u8 val;
1920
1921 if (!chip->support_ant_gain)
1922 return;
1923
1924 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res);
1925 if (ret) {
1926 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1927 "acpi: cannot eval rtag: %d\n", ret);
1928 return;
1929 }
1930
1931 if (res.revision != 0) {
1932 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1933 "unknown rtag revision: %d\n", res.revision);
1934 return;
1935 }
1936
1937 domain = get_unaligned_le32(&res.domain);
1938
1939 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) {
1940 if (!(domain & BIT(i)))
1941 continue;
1942
1943 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i);
1944 if (regd >= RTW89_REGD_NUM)
1945 continue;
1946 ant_gain->regd_enabled |= BIT(regd);
1947 }
1948
1949 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) {
1950 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) {
1951 val = res.ant_gain_table[i][j];
1952 switch (j) {
1953 default:
1954 case RTW89_ANT_GAIN_2GHZ_SUBBAND:
1955 val = RTW89_ANT_GAIN_REF_2GHZ -
1956 clamp_t(s8, val,
1957 RTW89_ANT_GAIN_2GHZ_MIN,
1958 RTW89_ANT_GAIN_2GHZ_MAX);
1959 break;
1960 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1:
1961 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2:
1962 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E:
1963 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4:
1964 val = RTW89_ANT_GAIN_REF_5GHZ -
1965 clamp_t(s8, val,
1966 RTW89_ANT_GAIN_5GHZ_MIN,
1967 RTW89_ANT_GAIN_5GHZ_MAX);
1968 break;
1969 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L:
1970 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H:
1971 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6:
1972 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L:
1973 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H:
1974 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8:
1975 val = RTW89_ANT_GAIN_REF_6GHZ -
1976 clamp_t(s8, val,
1977 RTW89_ANT_GAIN_6GHZ_MIN,
1978 RTW89_ANT_GAIN_6GHZ_MAX);
1979 }
1980 ant_gain->offset[i][j] = val;
1981 }
1982 }
1983 }
1984
1985 static
rtw89_phy_ant_gain_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)1986 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev,
1987 u32 center_freq)
1988 {
1989 switch (center_freq) {
1990 default:
1991 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1992 "center freq: %u to antenna gain subband is unhandled\n",
1993 center_freq);
1994 fallthrough;
1995 case 2412 ... 2484:
1996 return RTW89_ANT_GAIN_2GHZ_SUBBAND;
1997 case 5180 ... 5240:
1998 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1;
1999 case 5250 ... 5320:
2000 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2;
2001 case 5500 ... 5720:
2002 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E;
2003 case 5745 ... 5885:
2004 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4;
2005 case 5955 ... 6155:
2006 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L;
2007 case 6175 ... 6415:
2008 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H;
2009 case 6435 ... 6515:
2010 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6;
2011 case 6535 ... 6695:
2012 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L;
2013 case 6715 ... 6855:
2014 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H;
2015
2016 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H
2017 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with
2018 * struct rtw89_6ghz_span.
2019 */
2020
2021 case 6895 ... 7115:
2022 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8;
2023 }
2024 }
2025
rtw89_phy_ant_gain_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u32 center_freq)2026 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev,
2027 enum rtw89_rf_path path, u32 center_freq)
2028 {
2029 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2030 enum rtw89_ant_gain_subband subband_l, subband_h;
2031 const struct rtw89_6ghz_span *span;
2032
2033 span = rtw89_get_6ghz_span(rtwdev, center_freq);
2034
2035 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) {
2036 subband_l = span->ant_gain_subband_low;
2037 subband_h = span->ant_gain_subband_high;
2038 } else {
2039 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq);
2040 subband_h = subband_l;
2041 }
2042
2043 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2044 "center_freq %u: antenna gain subband {%u, %u}\n",
2045 center_freq, subband_l, subband_h);
2046
2047 return min(ant_gain->offset[path][subband_l],
2048 ant_gain->offset[path][subband_h]);
2049 }
2050
rtw89_phy_ant_gain_offset(struct rtw89_dev * rtwdev,u32 center_freq)2051 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u32 center_freq)
2052 {
2053 s8 offset_patha, offset_pathb;
2054
2055 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq);
2056 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq);
2057
2058 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2059 return min(offset_patha, offset_pathb);
2060
2061 return max(offset_patha, offset_pathb);
2062 }
2063
rtw89_can_apply_ant_gain(struct rtw89_dev * rtwdev,u8 band)2064 static bool rtw89_can_apply_ant_gain(struct rtw89_dev *rtwdev, u8 band)
2065 {
2066 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2067 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2068 const struct rtw89_chip_info *chip = rtwdev->chip;
2069 u8 regd = rtw89_regd_get(rtwdev, band);
2070
2071 if (!chip->support_ant_gain)
2072 return false;
2073
2074 if (ant_gain->block_country || !(ant_gain->regd_enabled & BIT(regd)))
2075 return false;
2076
2077 if (!rfe_parms->has_da)
2078 return false;
2079
2080 return true;
2081 }
2082
rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2083 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
2084 const struct rtw89_chan *chan)
2085 {
2086 s8 offset_patha, offset_pathb;
2087
2088 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type))
2089 return 0;
2090
2091 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2092 return 0;
2093
2094 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2095 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2096
2097 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb);
2098 }
2099 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset);
2100
rtw89_print_ant_gain(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_chan * chan)2101 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
2102 const struct rtw89_chan *chan)
2103 {
2104 char *p = buf, *end = buf + bufsz;
2105 s8 offset_patha, offset_pathb;
2106
2107 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type)) {
2108 p += scnprintf(p, end - p, "no DAG is applied\n");
2109 goto out;
2110 }
2111
2112 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2113 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2114
2115 p += scnprintf(p, end - p, "ChainA offset: %d dBm\n", offset_patha);
2116 p += scnprintf(p, end - p, "ChainB offset: %d dBm\n", offset_pathb);
2117
2118 out:
2119 return p - buf;
2120 }
2121
2122 static const u8 rtw89_rs_idx_num_ax[] = {
2123 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
2124 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
2125 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
2126 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
2127 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
2128 };
2129
2130 static const u8 rtw89_rs_nss_num_ax[] = {
2131 [RTW89_RS_CCK] = 1,
2132 [RTW89_RS_OFDM] = 1,
2133 [RTW89_RS_MCS] = RTW89_NSS_NUM,
2134 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
2135 [RTW89_RS_OFFSET] = 1,
2136 };
2137
rtw89_phy_raw_byr_seek(struct rtw89_dev * rtwdev,struct rtw89_txpwr_byrate * head,const struct rtw89_rate_desc * desc)2138 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
2139 struct rtw89_txpwr_byrate *head,
2140 const struct rtw89_rate_desc *desc)
2141 {
2142 switch (desc->rs) {
2143 case RTW89_RS_CCK:
2144 return &head->cck[desc->idx];
2145 case RTW89_RS_OFDM:
2146 return &head->ofdm[desc->idx];
2147 case RTW89_RS_MCS:
2148 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
2149 case RTW89_RS_HEDCM:
2150 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
2151 case RTW89_RS_OFFSET:
2152 return &head->offset[desc->idx];
2153 default:
2154 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
2155 return &head->trap;
2156 }
2157 }
2158
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)2159 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
2160 const struct rtw89_txpwr_table *tbl)
2161 {
2162 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
2163 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
2164 struct rtw89_txpwr_byrate *byr_head;
2165 struct rtw89_rate_desc desc = {};
2166 s8 *byr;
2167 u32 data;
2168 u8 i;
2169
2170 for (; cfg < end; cfg++) {
2171 byr_head = &rtwdev->byr[cfg->band][0];
2172 desc.rs = cfg->rs;
2173 desc.nss = cfg->nss;
2174 data = cfg->data;
2175
2176 for (i = 0; i < cfg->len; i++, data >>= 8) {
2177 desc.idx = cfg->shf + i;
2178 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
2179 *byr = data & 0xff;
2180 }
2181 }
2182 }
2183 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
2184
rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)2185 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
2186 {
2187 const u8 tssi_deviation_point = 0;
2188 const u8 tssi_max_deviation = 2;
2189
2190 if (dbm <= tssi_deviation_point)
2191 dbm -= tssi_max_deviation;
2192
2193 return dbm;
2194 }
2195
rtw89_phy_get_tpe_constraint(struct rtw89_dev * rtwdev,u8 band)2196 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
2197 {
2198 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2199 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
2200 s8 cstr = S8_MAX;
2201
2202 if (band == RTW89_BAND_6G && tpe->valid)
2203 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
2204
2205 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
2206 }
2207
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,u8 bw,const struct rtw89_rate_desc * rate_desc)2208 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
2209 const struct rtw89_rate_desc *rate_desc)
2210 {
2211 struct rtw89_txpwr_byrate *byr_head;
2212 s8 *byr;
2213
2214 if (rate_desc->rs == RTW89_RS_CCK)
2215 band = RTW89_BAND_2G;
2216
2217 byr_head = &rtwdev->byr[band][bw];
2218 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
2219
2220 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
2221 }
2222
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)2223 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
2224 {
2225 switch (channel_6g) {
2226 case 1 ... 29:
2227 return (channel_6g - 1) / 2;
2228 case 33 ... 61:
2229 return (channel_6g - 3) / 2;
2230 case 65 ... 93:
2231 return (channel_6g - 5) / 2;
2232 case 97 ... 125:
2233 return (channel_6g - 7) / 2;
2234 case 129 ... 157:
2235 return (channel_6g - 9) / 2;
2236 case 161 ... 189:
2237 return (channel_6g - 11) / 2;
2238 case 193 ... 221:
2239 return (channel_6g - 13) / 2;
2240 case 225 ... 253:
2241 return (channel_6g - 15) / 2;
2242 default:
2243 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
2244 return 0;
2245 }
2246 }
2247
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)2248 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
2249 {
2250 if (band == RTW89_BAND_6G)
2251 return rtw89_channel_6g_to_idx(rtwdev, channel);
2252
2253 switch (channel) {
2254 case 1 ... 14:
2255 return channel - 1;
2256 case 36 ... 64:
2257 return (channel - 36) / 2;
2258 case 100 ... 144:
2259 return ((channel - 100) / 2) + 15;
2260 case 149 ... 177:
2261 return ((channel - 149) / 2) + 38;
2262 default:
2263 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
2264 return 0;
2265 }
2266 }
2267
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)2268 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2269 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
2270 {
2271 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2272 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz;
2273 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz;
2274 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz;
2275 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2276 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2277 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2278 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2279 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2280 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band);
2281 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2282 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2283 s8 lmt = 0, da_lmt = S8_MAX, sar, offset = 0;
2284 u8 regd = rtw89_regd_get(rtwdev, band);
2285 u8 reg6 = regulatory->reg_6ghz_power;
2286 struct rtw89_sar_parm sar_parm = {
2287 .center_freq = freq,
2288 .ntx = ntx,
2289 };
2290 s8 cstr;
2291
2292 switch (band) {
2293 case RTW89_BAND_2G:
2294 if (has_ant_gain)
2295 da_lmt = (*rule_da_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2296
2297 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2298 if (lmt)
2299 break;
2300
2301 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2302 break;
2303 case RTW89_BAND_5G:
2304 if (has_ant_gain)
2305 da_lmt = (*rule_da_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2306
2307 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2308 if (lmt)
2309 break;
2310
2311 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2312 break;
2313 case RTW89_BAND_6G:
2314 if (has_ant_gain)
2315 da_lmt = (*rule_da_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2316
2317 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2318 if (lmt)
2319 break;
2320
2321 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2322 [RTW89_REG_6GHZ_POWER_DFLT]
2323 [ch_idx];
2324 break;
2325 default:
2326 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2327 return 0;
2328 }
2329
2330 da_lmt = da_lmt ?: S8_MAX;
2331 if (da_lmt != S8_MAX)
2332 offset = rtw89_phy_ant_gain_offset(rtwdev, freq);
2333
2334 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt + offset, da_lmt));
2335 sar = rtw89_query_sar(rtwdev, &sar_parm);
2336 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2337
2338 return min3(lmt, sar, cstr);
2339 }
2340 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
2341
2342 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2343 do { \
2344 u8 __i; \
2345 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
2346 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2347 band, \
2348 bw, ntx, \
2349 rs, __i, \
2350 (ch)); \
2351 } while (0)
2352
rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch)2353 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2354 struct rtw89_txpwr_limit_ax *lmt,
2355 u8 band, u8 ntx, u8 ch)
2356 {
2357 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2358 ntx, RTW89_RS_CCK, ch);
2359 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2360 ntx, RTW89_RS_CCK, ch);
2361 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2362 ntx, RTW89_RS_OFDM, ch);
2363 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2364 RTW89_CHANNEL_WIDTH_20,
2365 ntx, RTW89_RS_MCS, ch);
2366 }
2367
rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2368 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2369 struct rtw89_txpwr_limit_ax *lmt,
2370 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2371 {
2372 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2373 ntx, RTW89_RS_CCK, ch - 2);
2374 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2375 ntx, RTW89_RS_CCK, ch);
2376 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2377 ntx, RTW89_RS_OFDM, pri_ch);
2378 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2379 RTW89_CHANNEL_WIDTH_20,
2380 ntx, RTW89_RS_MCS, ch - 2);
2381 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2382 RTW89_CHANNEL_WIDTH_20,
2383 ntx, RTW89_RS_MCS, ch + 2);
2384 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2385 RTW89_CHANNEL_WIDTH_40,
2386 ntx, RTW89_RS_MCS, ch);
2387 }
2388
rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2389 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2390 struct rtw89_txpwr_limit_ax *lmt,
2391 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2392 {
2393 s8 val_0p5_n[RTW89_BF_NUM];
2394 s8 val_0p5_p[RTW89_BF_NUM];
2395 u8 i;
2396
2397 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2398 ntx, RTW89_RS_OFDM, pri_ch);
2399 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2400 RTW89_CHANNEL_WIDTH_20,
2401 ntx, RTW89_RS_MCS, ch - 6);
2402 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2403 RTW89_CHANNEL_WIDTH_20,
2404 ntx, RTW89_RS_MCS, ch - 2);
2405 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2406 RTW89_CHANNEL_WIDTH_20,
2407 ntx, RTW89_RS_MCS, ch + 2);
2408 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2409 RTW89_CHANNEL_WIDTH_20,
2410 ntx, RTW89_RS_MCS, ch + 6);
2411 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2412 RTW89_CHANNEL_WIDTH_40,
2413 ntx, RTW89_RS_MCS, ch - 4);
2414 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2415 RTW89_CHANNEL_WIDTH_40,
2416 ntx, RTW89_RS_MCS, ch + 4);
2417 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2418 RTW89_CHANNEL_WIDTH_80,
2419 ntx, RTW89_RS_MCS, ch);
2420
2421 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2422 ntx, RTW89_RS_MCS, ch - 4);
2423 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2424 ntx, RTW89_RS_MCS, ch + 4);
2425
2426 for (i = 0; i < RTW89_BF_NUM; i++)
2427 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2428 }
2429
rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2430 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2431 struct rtw89_txpwr_limit_ax *lmt,
2432 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2433 {
2434 s8 val_0p5_n[RTW89_BF_NUM];
2435 s8 val_0p5_p[RTW89_BF_NUM];
2436 s8 val_2p5_n[RTW89_BF_NUM];
2437 s8 val_2p5_p[RTW89_BF_NUM];
2438 u8 i;
2439
2440 /* fill ofdm section */
2441 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2442 ntx, RTW89_RS_OFDM, pri_ch);
2443
2444 /* fill mcs 20m section */
2445 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2446 RTW89_CHANNEL_WIDTH_20,
2447 ntx, RTW89_RS_MCS, ch - 14);
2448 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2449 RTW89_CHANNEL_WIDTH_20,
2450 ntx, RTW89_RS_MCS, ch - 10);
2451 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2452 RTW89_CHANNEL_WIDTH_20,
2453 ntx, RTW89_RS_MCS, ch - 6);
2454 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2455 RTW89_CHANNEL_WIDTH_20,
2456 ntx, RTW89_RS_MCS, ch - 2);
2457 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2458 RTW89_CHANNEL_WIDTH_20,
2459 ntx, RTW89_RS_MCS, ch + 2);
2460 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2461 RTW89_CHANNEL_WIDTH_20,
2462 ntx, RTW89_RS_MCS, ch + 6);
2463 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2464 RTW89_CHANNEL_WIDTH_20,
2465 ntx, RTW89_RS_MCS, ch + 10);
2466 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2467 RTW89_CHANNEL_WIDTH_20,
2468 ntx, RTW89_RS_MCS, ch + 14);
2469
2470 /* fill mcs 40m section */
2471 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2472 RTW89_CHANNEL_WIDTH_40,
2473 ntx, RTW89_RS_MCS, ch - 12);
2474 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2475 RTW89_CHANNEL_WIDTH_40,
2476 ntx, RTW89_RS_MCS, ch - 4);
2477 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2478 RTW89_CHANNEL_WIDTH_40,
2479 ntx, RTW89_RS_MCS, ch + 4);
2480 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2481 RTW89_CHANNEL_WIDTH_40,
2482 ntx, RTW89_RS_MCS, ch + 12);
2483
2484 /* fill mcs 80m section */
2485 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2486 RTW89_CHANNEL_WIDTH_80,
2487 ntx, RTW89_RS_MCS, ch - 8);
2488 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2489 RTW89_CHANNEL_WIDTH_80,
2490 ntx, RTW89_RS_MCS, ch + 8);
2491
2492 /* fill mcs 160m section */
2493 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2494 RTW89_CHANNEL_WIDTH_160,
2495 ntx, RTW89_RS_MCS, ch);
2496
2497 /* fill mcs 40m 0p5 section */
2498 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2499 ntx, RTW89_RS_MCS, ch - 4);
2500 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2501 ntx, RTW89_RS_MCS, ch + 4);
2502
2503 for (i = 0; i < RTW89_BF_NUM; i++)
2504 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2505
2506 /* fill mcs 40m 2p5 section */
2507 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2508 ntx, RTW89_RS_MCS, ch - 8);
2509 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2510 ntx, RTW89_RS_MCS, ch + 8);
2511
2512 for (i = 0; i < RTW89_BF_NUM; i++)
2513 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2514 }
2515
2516 static
rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ax * lmt,u8 ntx)2517 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2518 const struct rtw89_chan *chan,
2519 struct rtw89_txpwr_limit_ax *lmt,
2520 u8 ntx)
2521 {
2522 u8 band = chan->band_type;
2523 u8 pri_ch = chan->primary_channel;
2524 u8 ch = chan->channel;
2525 u8 bw = chan->band_width;
2526
2527 memset(lmt, 0, sizeof(*lmt));
2528
2529 switch (bw) {
2530 case RTW89_CHANNEL_WIDTH_20:
2531 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2532 break;
2533 case RTW89_CHANNEL_WIDTH_40:
2534 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2535 pri_ch);
2536 break;
2537 case RTW89_CHANNEL_WIDTH_80:
2538 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2539 pri_ch);
2540 break;
2541 case RTW89_CHANNEL_WIDTH_160:
2542 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2543 pri_ch);
2544 break;
2545 }
2546 }
2547
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)2548 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2549 u8 ru, u8 ntx, u8 ch)
2550 {
2551 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2552 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz;
2553 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz;
2554 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz;
2555 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2556 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2557 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2558 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2559 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2560 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band);
2561 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2562 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2563 s8 lmt_ru = 0, da_lmt_ru = S8_MAX, sar, offset = 0;
2564 u8 regd = rtw89_regd_get(rtwdev, band);
2565 u8 reg6 = regulatory->reg_6ghz_power;
2566 struct rtw89_sar_parm sar_parm = {
2567 .center_freq = freq,
2568 .ntx = ntx,
2569 };
2570 s8 cstr;
2571
2572 switch (band) {
2573 case RTW89_BAND_2G:
2574 if (has_ant_gain)
2575 da_lmt_ru = (*rule_da_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2576
2577 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2578 if (lmt_ru)
2579 break;
2580
2581 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2582 break;
2583 case RTW89_BAND_5G:
2584 if (has_ant_gain)
2585 da_lmt_ru = (*rule_da_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2586
2587 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2588 if (lmt_ru)
2589 break;
2590
2591 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2592 break;
2593 case RTW89_BAND_6G:
2594 if (has_ant_gain)
2595 da_lmt_ru = (*rule_da_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2596
2597 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2598 if (lmt_ru)
2599 break;
2600
2601 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2602 [RTW89_REG_6GHZ_POWER_DFLT]
2603 [ch_idx];
2604 break;
2605 default:
2606 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2607 return 0;
2608 }
2609
2610 da_lmt_ru = da_lmt_ru ?: S8_MAX;
2611 if (da_lmt_ru != S8_MAX)
2612 offset = rtw89_phy_ant_gain_offset(rtwdev, freq);
2613
2614 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt_ru + offset, da_lmt_ru));
2615 sar = rtw89_query_sar(rtwdev, &sar_parm);
2616 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2617
2618 return min3(lmt_ru, sar, cstr);
2619 }
2620
2621 static void
rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2622 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2623 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2624 u8 band, u8 ntx, u8 ch)
2625 {
2626 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2627 RTW89_RU26,
2628 ntx, ch);
2629 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2630 RTW89_RU52,
2631 ntx, ch);
2632 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2633 RTW89_RU106,
2634 ntx, ch);
2635 }
2636
2637 static void
rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2638 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2639 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2640 u8 band, u8 ntx, u8 ch)
2641 {
2642 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2643 RTW89_RU26,
2644 ntx, ch - 2);
2645 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2646 RTW89_RU26,
2647 ntx, ch + 2);
2648 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2649 RTW89_RU52,
2650 ntx, ch - 2);
2651 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2652 RTW89_RU52,
2653 ntx, ch + 2);
2654 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2655 RTW89_RU106,
2656 ntx, ch - 2);
2657 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2658 RTW89_RU106,
2659 ntx, ch + 2);
2660 }
2661
2662 static void
rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2663 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2664 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2665 u8 band, u8 ntx, u8 ch)
2666 {
2667 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2668 RTW89_RU26,
2669 ntx, ch - 6);
2670 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2671 RTW89_RU26,
2672 ntx, ch - 2);
2673 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2674 RTW89_RU26,
2675 ntx, ch + 2);
2676 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2677 RTW89_RU26,
2678 ntx, ch + 6);
2679 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2680 RTW89_RU52,
2681 ntx, ch - 6);
2682 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2683 RTW89_RU52,
2684 ntx, ch - 2);
2685 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2686 RTW89_RU52,
2687 ntx, ch + 2);
2688 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2689 RTW89_RU52,
2690 ntx, ch + 6);
2691 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2692 RTW89_RU106,
2693 ntx, ch - 6);
2694 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2695 RTW89_RU106,
2696 ntx, ch - 2);
2697 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2698 RTW89_RU106,
2699 ntx, ch + 2);
2700 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2701 RTW89_RU106,
2702 ntx, ch + 6);
2703 }
2704
2705 static void
rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2706 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2707 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2708 u8 band, u8 ntx, u8 ch)
2709 {
2710 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2711 int i;
2712
2713 #if defined(__linux__)
2714 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2715 #elif defined(__FreeBSD__)
2716 rtw89_static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2717 #endif
2718 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) {
2719 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2720 RTW89_RU26,
2721 ntx,
2722 ch + ofst[i]);
2723 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2724 RTW89_RU52,
2725 ntx,
2726 ch + ofst[i]);
2727 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2728 RTW89_RU106,
2729 ntx,
2730 ch + ofst[i]);
2731 }
2732 }
2733
2734 static
rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 ntx)2735 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2736 const struct rtw89_chan *chan,
2737 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2738 u8 ntx)
2739 {
2740 u8 band = chan->band_type;
2741 u8 ch = chan->channel;
2742 u8 bw = chan->band_width;
2743
2744 memset(lmt_ru, 0, sizeof(*lmt_ru));
2745
2746 switch (bw) {
2747 case RTW89_CHANNEL_WIDTH_20:
2748 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2749 ch);
2750 break;
2751 case RTW89_CHANNEL_WIDTH_40:
2752 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2753 ch);
2754 break;
2755 case RTW89_CHANNEL_WIDTH_80:
2756 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2757 ch);
2758 break;
2759 case RTW89_CHANNEL_WIDTH_160:
2760 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2761 ch);
2762 break;
2763 }
2764 }
2765
rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2766 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
2767 const struct rtw89_chan *chan,
2768 enum rtw89_phy_idx phy_idx)
2769 {
2770 u8 max_nss_num = rtwdev->chip->rf_path_num;
2771 static const u8 rs[] = {
2772 RTW89_RS_CCK,
2773 RTW89_RS_OFDM,
2774 RTW89_RS_MCS,
2775 RTW89_RS_HEDCM,
2776 };
2777 struct rtw89_rate_desc cur = {};
2778 u8 band = chan->band_type;
2779 u8 ch = chan->channel;
2780 u32 addr, val;
2781 s8 v[4] = {};
2782 u8 i;
2783
2784 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2785 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
2786
2787 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
2788 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
2789 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
2790 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
2791
2792 addr = R_AX_PWR_BY_RATE;
2793 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
2794 for (i = 0; i < ARRAY_SIZE(rs); i++) {
2795 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
2796 continue;
2797
2798 cur.rs = rs[i];
2799 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
2800 cur.idx++) {
2801 v[cur.idx % 4] =
2802 rtw89_phy_read_txpwr_byrate(rtwdev,
2803 band, 0,
2804 &cur);
2805
2806 if ((cur.idx + 1) % 4)
2807 continue;
2808
2809 val = FIELD_PREP(GENMASK(7, 0), v[0]) |
2810 FIELD_PREP(GENMASK(15, 8), v[1]) |
2811 FIELD_PREP(GENMASK(23, 16), v[2]) |
2812 FIELD_PREP(GENMASK(31, 24), v[3]);
2813
2814 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2815 val);
2816 addr += 4;
2817 }
2818 }
2819 }
2820 }
2821
2822 static
rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2823 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
2824 const struct rtw89_chan *chan,
2825 enum rtw89_phy_idx phy_idx)
2826 {
2827 struct rtw89_rate_desc desc = {
2828 .nss = RTW89_NSS_1,
2829 .rs = RTW89_RS_OFFSET,
2830 };
2831 u8 band = chan->band_type;
2832 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
2833 u32 val;
2834
2835 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2836
2837 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++)
2838 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2839
2840 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5);
2841 val = FIELD_PREP(GENMASK(3, 0), v[0]) |
2842 FIELD_PREP(GENMASK(7, 4), v[1]) |
2843 FIELD_PREP(GENMASK(11, 8), v[2]) |
2844 FIELD_PREP(GENMASK(15, 12), v[3]) |
2845 FIELD_PREP(GENMASK(19, 16), v[4]);
2846
2847 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2848 GENMASK(19, 0), val);
2849 }
2850
rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2851 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2852 const struct rtw89_chan *chan,
2853 enum rtw89_phy_idx phy_idx)
2854 {
2855 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2856 struct rtw89_txpwr_limit_ax lmt;
2857 u8 ch = chan->channel;
2858 u8 bw = chan->band_width;
2859 const s8 *ptr;
2860 u32 addr, val;
2861 u8 i, j;
2862
2863 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2864 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
2865
2866 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) !=
2867 RTW89_TXPWR_LMT_PAGE_SIZE_AX);
2868
2869 addr = R_AX_PWR_LMT;
2870 for (i = 0; i < max_ntx_num; i++) {
2871 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
2872
2873 ptr = (s8 *)&lmt;
2874 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX;
2875 j += 4, addr += 4, ptr += 4) {
2876 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2877 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2878 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2879 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2880
2881 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2882 }
2883 }
2884 }
2885
rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2886 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2887 const struct rtw89_chan *chan,
2888 enum rtw89_phy_idx phy_idx)
2889 {
2890 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2891 struct rtw89_txpwr_limit_ru_ax lmt_ru;
2892 u8 ch = chan->channel;
2893 u8 bw = chan->band_width;
2894 const s8 *ptr;
2895 u32 addr, val;
2896 u8 i, j;
2897
2898 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2899 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
2900
2901 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) !=
2902 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX);
2903
2904 addr = R_AX_PWR_RU_LMT;
2905 for (i = 0; i < max_ntx_num; i++) {
2906 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
2907
2908 ptr = (s8 *)&lmt_ru;
2909 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX;
2910 j += 4, addr += 4, ptr += 4) {
2911 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2912 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2913 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2914 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2915
2916 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2917 }
2918 }
2919 }
2920
2921 struct rtw89_phy_iter_ra_data {
2922 struct rtw89_dev *rtwdev;
2923 struct sk_buff *c2h;
2924 };
2925
__rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,struct rtw89_phy_iter_ra_data * ra_data)2926 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
2927 struct ieee80211_link_sta *link_sta,
2928 struct rtw89_phy_iter_ra_data *ra_data)
2929 {
2930 struct rtw89_dev *rtwdev = ra_data->rtwdev;
2931 const struct rtw89_c2h_ra_rpt *c2h =
2932 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
2933 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
2934 const struct rtw89_chip_info *chip = rtwdev->chip;
2935 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
2936 u8 mode, rate, bw, giltf, mac_id;
2937 u16 legacy_bitrate;
2938 bool valid;
2939 u8 mcs = 0;
2940 u8 t;
2941
2942 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
2943 if (mac_id != rtwsta_link->mac_id)
2944 return;
2945
2946 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
2947 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
2948 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
2949 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
2950
2951 if (format_v1) {
2952 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
2953 rate |= u8_encode_bits(t, BIT(7));
2954 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
2955 bw |= u8_encode_bits(t, BIT(2));
2956 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
2957 mode |= u8_encode_bits(t, BIT(2));
2958 }
2959
2960 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
2961 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
2962 if (!valid)
2963 return;
2964 }
2965
2966 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
2967
2968 switch (mode) {
2969 case RTW89_RA_RPT_MODE_LEGACY:
2970 ra_report->txrate.legacy = legacy_bitrate;
2971 break;
2972 case RTW89_RA_RPT_MODE_HT:
2973 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
2974 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2975 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
2976 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
2977 else
2978 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
2979 ra_report->txrate.mcs = rate;
2980 if (giltf)
2981 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2982 mcs = ra_report->txrate.mcs & 0x07;
2983 break;
2984 case RTW89_RA_RPT_MODE_VHT:
2985 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
2986 ra_report->txrate.mcs = format_v1 ?
2987 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2988 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2989 ra_report->txrate.nss = format_v1 ?
2990 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2991 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2992 if (giltf)
2993 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2994 mcs = ra_report->txrate.mcs;
2995 break;
2996 case RTW89_RA_RPT_MODE_HE:
2997 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
2998 ra_report->txrate.mcs = format_v1 ?
2999 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
3000 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
3001 ra_report->txrate.nss = format_v1 ?
3002 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
3003 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
3004 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
3005 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
3006 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
3007 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
3008 else
3009 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
3010 mcs = ra_report->txrate.mcs;
3011 break;
3012 case RTW89_RA_RPT_MODE_EHT:
3013 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
3014 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
3015 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
3016 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
3017 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
3018 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
3019 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
3020 else
3021 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
3022 mcs = ra_report->txrate.mcs;
3023 break;
3024 }
3025
3026 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
3027 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
3028 ra_report->hw_rate = format_v1 ?
3029 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
3030 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
3031 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
3032 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
3033 ra_report->might_fallback_legacy = mcs <= 2;
3034 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
3035 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
3036 }
3037
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)3038 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
3039 {
3040 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
3041 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3042 struct rtw89_sta_link *rtwsta_link;
3043 struct ieee80211_link_sta *link_sta;
3044 unsigned int link_id;
3045
3046 rcu_read_lock();
3047
3048 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
3049 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
3050 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
3051 }
3052
3053 rcu_read_unlock();
3054 }
3055
3056 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3057 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3058 {
3059 struct rtw89_phy_iter_ra_data ra_data;
3060
3061 ra_data.rtwdev = rtwdev;
3062 ra_data.c2h = c2h;
3063 ieee80211_iterate_stations_atomic(rtwdev->hw,
3064 rtw89_phy_c2h_ra_rpt_iter,
3065 &ra_data);
3066 }
3067
3068 static
3069 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
3070 struct sk_buff *c2h, u32 len) = {
3071 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
3072 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
3073 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
3074 };
3075
3076 static void
rtw89_phy_c2h_lowrt_rty(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3077 rtw89_phy_c2h_lowrt_rty(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3078 {
3079 }
3080
3081 static void
rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3082 rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3083 {
3084 const struct rtw89_c2h_fw_scan_rpt *c2h_rpt =
3085 (const struct rtw89_c2h_fw_scan_rpt *)c2h->data;
3086
3087 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3088 "%s: band: %u, op_chan: %u, PD_low_bd(ofdm, cck): (-%d, %d), phy_idx: %u\n",
3089 __func__, c2h_rpt->band, c2h_rpt->center_ch,
3090 PD_LOWER_BOUND_BASE - (c2h_rpt->ofdm_pd_idx << 1),
3091 c2h_rpt->cck_pd_idx, c2h_rpt->phy_idx);
3092 }
3093
3094 static
3095 void (* const rtw89_phy_c2h_dm_handler[])(struct rtw89_dev *rtwdev,
3096 struct sk_buff *c2h, u32 len) = {
3097 [RTW89_PHY_C2H_DM_FUNC_FW_TEST] = NULL,
3098 [RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT] = NULL,
3099 [RTW89_PHY_C2H_DM_FUNC_SIGB] = NULL,
3100 [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty,
3101 [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL,
3102 [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt,
3103 };
3104
rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3105 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
3106 enum rtw89_phy_c2h_rfk_log_func func,
3107 void *content, u16 len)
3108 {
3109 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk;
3110 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck;
3111 struct rtw89_c2h_rf_dack_rpt_log *dack;
3112 struct rtw89_c2h_rf_tssi_rpt_log *tssi;
3113 struct rtw89_c2h_rf_dpk_rpt_log *dpk;
3114 struct rtw89_c2h_rf_iqk_rpt_log *iqk;
3115 int i, j, k;
3116
3117 switch (func) {
3118 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3119 if (len != sizeof(*iqk))
3120 goto out;
3121
3122 iqk = content;
3123 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3124 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init);
3125 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3126 "[IQK] iqk->is_reload = %x\n", iqk->is_reload);
3127 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3128 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk);
3129 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3130 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en);
3131 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3132 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en);
3133 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3134 "[IQK] iqk->lok_en = %x\n", iqk->lok_en);
3135 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3136 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en);
3137 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3138 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en);
3139 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3140 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en);
3141 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3142 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk);
3143 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3144 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable);
3145 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3146 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en);
3147 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3148 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en);
3149 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3150 "[IQK] iqk->version = %x\n", iqk->version);
3151 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3152 "[IQK] iqk->phy = %x\n", iqk->phy);
3153 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3154 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status);
3155
3156 for (i = 0; i < 2; i++) {
3157 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3158 "[IQK] ======== Path %x ========\n", i);
3159 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n",
3160 i, iqk->iqk_band[i]);
3161 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n",
3162 i, iqk->iqk_ch[i]);
3163 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n",
3164 i, iqk->iqk_bw[i]);
3165 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n",
3166 i, le32_to_cpu(iqk->lok_idac[i]));
3167 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n",
3168 i, le32_to_cpu(iqk->lok_vbuf[i]));
3169 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n",
3170 i, iqk->iqk_tx_fail[i]);
3171 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n",
3172 i, iqk->iqk_rx_fail[i]);
3173 for (j = 0; j < 4; j++)
3174 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3175 "[IQK] iqk->rftxgain[%d][%d] = %x\n",
3176 i, j, le32_to_cpu(iqk->rftxgain[i][j]));
3177 for (j = 0; j < 4; j++)
3178 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3179 "[IQK] iqk->tx_xym[%d][%d] = %x\n",
3180 i, j, le32_to_cpu(iqk->tx_xym[i][j]));
3181 for (j = 0; j < 4; j++)
3182 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3183 "[IQK] iqk->rfrxgain[%d][%d] = %x\n",
3184 i, j, le32_to_cpu(iqk->rfrxgain[i][j]));
3185 for (j = 0; j < 4; j++)
3186 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3187 "[IQK] iqk->rx_xym[%d][%d] = %x\n",
3188 i, j, le32_to_cpu(iqk->rx_xym[i][j]));
3189 }
3190 return;
3191 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3192 if (len != sizeof(*dpk))
3193 goto out;
3194
3195 dpk = content;
3196 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3197 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
3198 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
3199 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3200 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n",
3201 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
3202 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3203 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n",
3204 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
3205 return;
3206 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3207 if (len != sizeof(*dack))
3208 goto out;
3209
3210 dack = content;
3211
3212 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n");
3213 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3214 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n",
3215 dack->fwdack_ver, dack->fwdack_info_ver, 0x2);
3216
3217 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3218 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n",
3219 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout,
3220 dack->adgaink_timeout, dack->msbk_timeout);
3221 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3222 "[DACK]DACK fail = 0x%x\n", dack->dack_fail);
3223 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3224 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]);
3225 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3226 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]);
3227 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3228 "[DACK]DRCK = [0x%x]\n", dack->rck_d);
3229 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
3230 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
3231 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
3232 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
3233 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
3234 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
3235 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
3236 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
3237
3238 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
3239 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0],
3240 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]);
3241 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
3242 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0],
3243 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]);
3244 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
3245 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0],
3246 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]);
3247 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
3248 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0],
3249 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]);
3250
3251 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3252 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
3253 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3254 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
3255
3256 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3257 dack->dadck_d[0][0], dack->dadck_d[0][1]);
3258 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3259 dack->dadck_d[1][0], dack->dadck_d[1][1]);
3260
3261 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
3262 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]);
3263 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
3264 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]);
3265
3266 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
3267 for (i = 0; i < 0x10; i++)
3268 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3269 dack->msbk_d[0][0][i]);
3270
3271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
3272 for (i = 0; i < 0x10; i++)
3273 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3274 dack->msbk_d[0][1][i]);
3275
3276 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
3277 for (i = 0; i < 0x10; i++)
3278 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3279 dack->msbk_d[1][0][i]);
3280
3281 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
3282 for (i = 0; i < 0x10; i++)
3283 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3284 dack->msbk_d[1][1][i]);
3285 return;
3286 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3287 if (len != sizeof(*rxdck))
3288 goto out;
3289
3290 rxdck = content;
3291 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3292 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
3293 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
3294 rxdck->timeout);
3295 return;
3296 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3297 if (len != sizeof(*tssi))
3298 goto out;
3299
3300 tssi = content;
3301 for (i = 0; i < 2; i++) {
3302 for (j = 0; j < 2; j++) {
3303 for (k = 0; k < 4; k++) {
3304 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3305 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n",
3306 i, j, k, tssi->alignment_power_cw_h[i][j][k]);
3307 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3308 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n",
3309 i, j, k, tssi->alignment_power_cw_l[i][j][k]);
3310 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3311 "[TSSI] alignment_power[%d][%d][%d]=%d\n",
3312 i, j, k, tssi->alignment_power[i][j][k]);
3313 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3314 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n",
3315 i, j, k,
3316 (tssi->alignment_power_cw_h[i][j][k] << 8) +
3317 tssi->alignment_power_cw_l[i][j][k]);
3318 }
3319
3320 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3321 "[TSSI] tssi_alimk_state[%d][%d]=%d\n",
3322 i, j, tssi->tssi_alimk_state[i][j]);
3323 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3324 "[TSSI] default_txagc_offset[%d]=%d\n",
3325 j, tssi->default_txagc_offset[0][j]);
3326 }
3327 }
3328 return;
3329 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3330 if (len != sizeof(*txgapk))
3331 goto out;
3332
3333 txgapk = content;
3334 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3335 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n",
3336 le32_to_cpu(txgapk->r0x8010[0]),
3337 le32_to_cpu(txgapk->r0x8010[1]));
3338 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
3339 txgapk->chk_id);
3340 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
3341 le32_to_cpu(txgapk->chk_cnt));
3342 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
3343 txgapk->ver);
3344 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n",
3345 txgapk->rsv1);
3346
3347 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
3348 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
3349 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
3350 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
3351 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
3352 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
3353 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
3354 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
3355 return;
3356 default:
3357 break;
3358 }
3359
3360 out:
3361 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3362 "unexpected RFK func %d report log with length %d\n", func, len);
3363 }
3364
rtw89_phy_c2h_rfk_run_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3365 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
3366 enum rtw89_phy_c2h_rfk_log_func func,
3367 void *content, u16 len)
3368 {
3369 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
3370 const struct rtw89_c2h_rf_run_log *log = content;
3371 const struct rtw89_fw_element_hdr *elm;
3372 u32 fmt_idx;
3373 u16 offset;
3374
3375 if (sizeof(*log) != len)
3376 return false;
3377
3378 if (!elm_info->rfk_log_fmt)
3379 return false;
3380
3381 elm = elm_info->rfk_log_fmt->elm[func];
3382 fmt_idx = le32_to_cpu(log->fmt_idx);
3383 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
3384 return false;
3385
3386 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
3387 if (offset == 0)
3388 return false;
3389
3390 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
3391 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
3392 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
3393
3394 return true;
3395 }
3396
rtw89_phy_c2h_rfk_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len,enum rtw89_phy_c2h_rfk_log_func func,const char * rfk_name)3397 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3398 u32 len, enum rtw89_phy_c2h_rfk_log_func func,
3399 const char *rfk_name)
3400 {
3401 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
3402 struct rtw89_c2h_rf_log_hdr *log_hdr;
3403 #if defined(__linux__)
3404 void *log_ptr = c2h_hdr;
3405 #elif defined(__FreeBSD__)
3406 u8 *log_ptr = (void *)c2h_hdr;
3407 #endif
3408 u16 content_len;
3409 u16 chunk_len;
3410 bool handled;
3411
3412 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK))
3413 return;
3414
3415 log_ptr += sizeof(*c2h_hdr);
3416 len -= sizeof(*c2h_hdr);
3417
3418 while (len > sizeof(*log_hdr)) {
3419 #if defined(__linux__)
3420 log_hdr = log_ptr;
3421 #elif defined(__FreeBSD__)
3422 log_hdr = (void *)log_ptr;
3423 #endif
3424 content_len = le16_to_cpu(log_hdr->len);
3425 chunk_len = content_len + sizeof(*log_hdr);
3426
3427 if (chunk_len > len)
3428 break;
3429
3430 switch (log_hdr->type) {
3431 case RTW89_RF_RUN_LOG:
3432 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
3433 log_hdr->content, content_len);
3434 if (handled)
3435 break;
3436
3437 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
3438 rfk_name, content_len, log_hdr->content);
3439 break;
3440 case RTW89_RF_RPT_LOG:
3441 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
3442 log_hdr->content, content_len);
3443 break;
3444 default:
3445 return;
3446 }
3447
3448 log_ptr += chunk_len;
3449 len -= chunk_len;
3450 }
3451 }
3452
3453 static void
rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3454 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3455 {
3456 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3457 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK");
3458 }
3459
3460 static void
rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3461 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3462 {
3463 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3464 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK");
3465 }
3466
3467 static void
rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3468 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3469 {
3470 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3471 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK");
3472 }
3473
3474 static void
rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3475 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3476 {
3477 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3478 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK");
3479 }
3480
3481 static void
rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3482 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3483 {
3484 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3485 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI");
3486 }
3487
3488 static void
rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3489 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3490 {
3491 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3492 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK");
3493 }
3494
3495 static
3496 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
3497 struct sk_buff *c2h, u32 len) = {
3498 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk,
3499 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk,
3500 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack,
3501 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck,
3502 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi,
3503 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk,
3504 };
3505
3506 static
rtw89_phy_rfk_report_prep(struct rtw89_dev * rtwdev)3507 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
3508 {
3509 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3510
3511 wait->state = RTW89_RFK_STATE_START;
3512 wait->start_time = ktime_get();
3513 reinit_completion(&wait->completion);
3514 }
3515
3516 static
rtw89_phy_rfk_report_wait(struct rtw89_dev * rtwdev,const char * rfk_name,unsigned int ms)3517 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
3518 unsigned int ms)
3519 {
3520 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3521 unsigned long time_left;
3522
3523 /* Since we can't receive C2H event during SER, use a fixed delay. */
3524 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3525 fsleep(1000 * ms / 2);
3526 goto out;
3527 }
3528
3529 time_left = wait_for_completion_timeout(&wait->completion,
3530 msecs_to_jiffies(ms));
3531 if (time_left == 0) {
3532 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
3533 return -ETIMEDOUT;
3534 } else if (wait->state != RTW89_RFK_STATE_OK) {
3535 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
3536 rfk_name, wait->state);
3537 return -EFAULT;
3538 }
3539
3540 out:
3541 #if defined(__linux__)
3542 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3543 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3544 #elif defined(__FreeBSD__)
3545 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %jd ms to complete\n",
3546 rfk_name, ktime_ms_delta(ktime_get(), (intmax_t)wait->start_time));
3547 #endif
3548
3549 return 0;
3550 }
3551
3552 static void
rtw89_phy_c2h_rfk_report_state(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3553 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3554 {
3555 const struct rtw89_c2h_rfk_report *report =
3556 (const struct rtw89_c2h_rfk_report *)c2h->data;
3557 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3558
3559 wait->state = report->state;
3560 wait->version = report->version;
3561
3562 complete(&wait->completion);
3563
3564 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3565 "RFK report state %d with version %d (%*ph)\n",
3566 wait->state, wait->version,
3567 (int)(len - sizeof(report->hdr)), &report->state);
3568 }
3569
3570 static void
rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3571 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3572 {
3573 const struct rtw89_c2h_rf_tas_info *rf_tas =
3574 (const struct rtw89_c2h_rf_tas_info *)c2h->data;
3575 const enum rtw89_sar_sources src = rtwdev->sar.src;
3576 struct rtw89_tas_info *tas = &rtwdev->tas;
3577 u64 linear = 0;
3578 u32 i, cur_idx;
3579 s16 txpwr;
3580
3581 if (!tas->enable || src == RTW89_SAR_SOURCE_NONE)
3582 return;
3583
3584 cur_idx = le32_to_cpu(rf_tas->cur_idx);
3585 for (i = 0; i < cur_idx; i++) {
3586 txpwr = (s16)le16_to_cpu(rf_tas->txpwr_history[i]);
3587 linear += rtw89_db_quarter_to_linear(txpwr);
3588
3589 rtw89_debug(rtwdev, RTW89_DBG_SAR,
3590 "tas: index: %u, txpwr: %d\n", i, txpwr);
3591 }
3592
3593 if (cur_idx == 0)
3594 tas->instant_txpwr = rtw89_db_to_linear(0);
3595 else
3596 tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx);
3597 }
3598
3599 static
3600 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3601 struct sk_buff *c2h, u32 len) = {
3602 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state,
3603 [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr,
3604 };
3605
rtw89_phy_c2h_chk_atomic(struct rtw89_dev * rtwdev,u8 class,u8 func)3606 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
3607 {
3608 switch (class) {
3609 case RTW89_PHY_C2H_RFK_LOG:
3610 switch (func) {
3611 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3612 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3613 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3614 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3615 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3616 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3617 return true;
3618 default:
3619 return false;
3620 }
3621 case RTW89_PHY_C2H_RFK_REPORT:
3622 switch (func) {
3623 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE:
3624 return true;
3625 default:
3626 return false;
3627 }
3628 default:
3629 return false;
3630 }
3631 }
3632
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3633 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3634 u32 len, u8 class, u8 func)
3635 {
3636 void (*handler)(struct rtw89_dev *rtwdev,
3637 struct sk_buff *c2h, u32 len) = NULL;
3638
3639 switch (class) {
3640 case RTW89_PHY_C2H_CLASS_RA:
3641 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
3642 handler = rtw89_phy_c2h_ra_handler[func];
3643 break;
3644 case RTW89_PHY_C2H_RFK_LOG:
3645 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler))
3646 handler = rtw89_phy_c2h_rfk_log_handler[func];
3647 break;
3648 case RTW89_PHY_C2H_RFK_REPORT:
3649 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler))
3650 handler = rtw89_phy_c2h_rfk_report_handler[func];
3651 break;
3652 case RTW89_PHY_C2H_CLASS_DM:
3653 if (func < ARRAY_SIZE(rtw89_phy_c2h_dm_handler))
3654 handler = rtw89_phy_c2h_dm_handler[func];
3655 break;
3656 default:
3657 rtw89_info(rtwdev, "PHY c2h class %d not support\n", class);
3658 return;
3659 }
3660 if (!handler) {
3661 rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class,
3662 func);
3663 return;
3664 }
3665 handler(rtwdev, skb, len);
3666 }
3667
rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,unsigned int ms)3668 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
3669 enum rtw89_phy_idx phy_idx,
3670 unsigned int ms)
3671 {
3672 int ret;
3673
3674 rtw89_phy_rfk_report_prep(rtwdev);
3675
3676 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3677 if (ret)
3678 return ret;
3679
3680 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3681 }
3682 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
3683
rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)3684 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
3685 enum rtw89_phy_idx phy_idx,
3686 const struct rtw89_chan *chan,
3687 enum rtw89_tssi_mode tssi_mode,
3688 unsigned int ms)
3689 {
3690 int ret;
3691
3692 rtw89_phy_rfk_report_prep(rtwdev);
3693
3694 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
3695 if (ret)
3696 return ret;
3697
3698 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
3699 }
3700 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait);
3701
rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3702 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
3703 enum rtw89_phy_idx phy_idx,
3704 const struct rtw89_chan *chan,
3705 unsigned int ms)
3706 {
3707 int ret;
3708
3709 rtw89_phy_rfk_report_prep(rtwdev);
3710
3711 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
3712 if (ret)
3713 return ret;
3714
3715 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
3716 }
3717 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait);
3718
rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3719 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
3720 enum rtw89_phy_idx phy_idx,
3721 const struct rtw89_chan *chan,
3722 unsigned int ms)
3723 {
3724 int ret;
3725
3726 rtw89_phy_rfk_report_prep(rtwdev);
3727
3728 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
3729 if (ret)
3730 return ret;
3731
3732 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
3733 }
3734 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait);
3735
rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3736 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
3737 enum rtw89_phy_idx phy_idx,
3738 const struct rtw89_chan *chan,
3739 unsigned int ms)
3740 {
3741 int ret;
3742
3743 rtw89_phy_rfk_report_prep(rtwdev);
3744
3745 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
3746 if (ret)
3747 return ret;
3748
3749 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
3750 }
3751 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait);
3752
rtw89_phy_rfk_dack_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3753 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
3754 enum rtw89_phy_idx phy_idx,
3755 const struct rtw89_chan *chan,
3756 unsigned int ms)
3757 {
3758 int ret;
3759
3760 rtw89_phy_rfk_report_prep(rtwdev);
3761
3762 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
3763 if (ret)
3764 return ret;
3765
3766 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
3767 }
3768 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait);
3769
rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,bool is_chl_k,unsigned int ms)3770 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
3771 enum rtw89_phy_idx phy_idx,
3772 const struct rtw89_chan *chan,
3773 bool is_chl_k, unsigned int ms)
3774 {
3775 int ret;
3776
3777 rtw89_phy_rfk_report_prep(rtwdev);
3778
3779 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k);
3780 if (ret)
3781 return ret;
3782
3783 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
3784 }
3785 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait);
3786
phy_tssi_get_cck_group(u8 ch)3787 static u32 phy_tssi_get_cck_group(u8 ch)
3788 {
3789 switch (ch) {
3790 case 1 ... 2:
3791 return 0;
3792 case 3 ... 5:
3793 return 1;
3794 case 6 ... 8:
3795 return 2;
3796 case 9 ... 11:
3797 return 3;
3798 case 12 ... 13:
3799 return 4;
3800 case 14:
3801 return 5;
3802 }
3803
3804 return 0;
3805 }
3806
3807 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31)
3808 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx))
3809 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT)
3810 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \
3811 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT)
3812 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \
3813 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
3814
phy_tssi_get_ofdm_group(u8 ch)3815 static u32 phy_tssi_get_ofdm_group(u8 ch)
3816 {
3817 switch (ch) {
3818 case 1 ... 2:
3819 return 0;
3820 case 3 ... 5:
3821 return 1;
3822 case 6 ... 8:
3823 return 2;
3824 case 9 ... 11:
3825 return 3;
3826 case 12 ... 14:
3827 return 4;
3828 case 36 ... 40:
3829 return 5;
3830 case 41 ... 43:
3831 return PHY_TSSI_EXTRA_GROUP(5);
3832 case 44 ... 48:
3833 return 6;
3834 case 49 ... 51:
3835 return PHY_TSSI_EXTRA_GROUP(6);
3836 case 52 ... 56:
3837 return 7;
3838 case 57 ... 59:
3839 return PHY_TSSI_EXTRA_GROUP(7);
3840 case 60 ... 64:
3841 return 8;
3842 case 100 ... 104:
3843 return 9;
3844 case 105 ... 107:
3845 return PHY_TSSI_EXTRA_GROUP(9);
3846 case 108 ... 112:
3847 return 10;
3848 case 113 ... 115:
3849 return PHY_TSSI_EXTRA_GROUP(10);
3850 case 116 ... 120:
3851 return 11;
3852 case 121 ... 123:
3853 return PHY_TSSI_EXTRA_GROUP(11);
3854 case 124 ... 128:
3855 return 12;
3856 case 129 ... 131:
3857 return PHY_TSSI_EXTRA_GROUP(12);
3858 case 132 ... 136:
3859 return 13;
3860 case 137 ... 139:
3861 return PHY_TSSI_EXTRA_GROUP(13);
3862 case 140 ... 144:
3863 return 14;
3864 case 149 ... 153:
3865 return 15;
3866 case 154 ... 156:
3867 return PHY_TSSI_EXTRA_GROUP(15);
3868 case 157 ... 161:
3869 return 16;
3870 case 162 ... 164:
3871 return PHY_TSSI_EXTRA_GROUP(16);
3872 case 165 ... 169:
3873 return 17;
3874 case 170 ... 172:
3875 return PHY_TSSI_EXTRA_GROUP(17);
3876 case 173 ... 177:
3877 return 18;
3878 }
3879
3880 return 0;
3881 }
3882
phy_tssi_get_6g_ofdm_group(u8 ch)3883 static u32 phy_tssi_get_6g_ofdm_group(u8 ch)
3884 {
3885 switch (ch) {
3886 case 1 ... 5:
3887 return 0;
3888 case 6 ... 8:
3889 return PHY_TSSI_EXTRA_GROUP(0);
3890 case 9 ... 13:
3891 return 1;
3892 case 14 ... 16:
3893 return PHY_TSSI_EXTRA_GROUP(1);
3894 case 17 ... 21:
3895 return 2;
3896 case 22 ... 24:
3897 return PHY_TSSI_EXTRA_GROUP(2);
3898 case 25 ... 29:
3899 return 3;
3900 case 33 ... 37:
3901 return 4;
3902 case 38 ... 40:
3903 return PHY_TSSI_EXTRA_GROUP(4);
3904 case 41 ... 45:
3905 return 5;
3906 case 46 ... 48:
3907 return PHY_TSSI_EXTRA_GROUP(5);
3908 case 49 ... 53:
3909 return 6;
3910 case 54 ... 56:
3911 return PHY_TSSI_EXTRA_GROUP(6);
3912 case 57 ... 61:
3913 return 7;
3914 case 65 ... 69:
3915 return 8;
3916 case 70 ... 72:
3917 return PHY_TSSI_EXTRA_GROUP(8);
3918 case 73 ... 77:
3919 return 9;
3920 case 78 ... 80:
3921 return PHY_TSSI_EXTRA_GROUP(9);
3922 case 81 ... 85:
3923 return 10;
3924 case 86 ... 88:
3925 return PHY_TSSI_EXTRA_GROUP(10);
3926 case 89 ... 93:
3927 return 11;
3928 case 97 ... 101:
3929 return 12;
3930 case 102 ... 104:
3931 return PHY_TSSI_EXTRA_GROUP(12);
3932 case 105 ... 109:
3933 return 13;
3934 case 110 ... 112:
3935 return PHY_TSSI_EXTRA_GROUP(13);
3936 case 113 ... 117:
3937 return 14;
3938 case 118 ... 120:
3939 return PHY_TSSI_EXTRA_GROUP(14);
3940 case 121 ... 125:
3941 return 15;
3942 case 129 ... 133:
3943 return 16;
3944 case 134 ... 136:
3945 return PHY_TSSI_EXTRA_GROUP(16);
3946 case 137 ... 141:
3947 return 17;
3948 case 142 ... 144:
3949 return PHY_TSSI_EXTRA_GROUP(17);
3950 case 145 ... 149:
3951 return 18;
3952 case 150 ... 152:
3953 return PHY_TSSI_EXTRA_GROUP(18);
3954 case 153 ... 157:
3955 return 19;
3956 case 161 ... 165:
3957 return 20;
3958 case 166 ... 168:
3959 return PHY_TSSI_EXTRA_GROUP(20);
3960 case 169 ... 173:
3961 return 21;
3962 case 174 ... 176:
3963 return PHY_TSSI_EXTRA_GROUP(21);
3964 case 177 ... 181:
3965 return 22;
3966 case 182 ... 184:
3967 return PHY_TSSI_EXTRA_GROUP(22);
3968 case 185 ... 189:
3969 return 23;
3970 case 193 ... 197:
3971 return 24;
3972 case 198 ... 200:
3973 return PHY_TSSI_EXTRA_GROUP(24);
3974 case 201 ... 205:
3975 return 25;
3976 case 206 ... 208:
3977 return PHY_TSSI_EXTRA_GROUP(25);
3978 case 209 ... 213:
3979 return 26;
3980 case 214 ... 216:
3981 return PHY_TSSI_EXTRA_GROUP(26);
3982 case 217 ... 221:
3983 return 27;
3984 case 225 ... 229:
3985 return 28;
3986 case 230 ... 232:
3987 return PHY_TSSI_EXTRA_GROUP(28);
3988 case 233 ... 237:
3989 return 29;
3990 case 238 ... 240:
3991 return PHY_TSSI_EXTRA_GROUP(29);
3992 case 241 ... 245:
3993 return 30;
3994 case 246 ... 248:
3995 return PHY_TSSI_EXTRA_GROUP(30);
3996 case 249 ... 253:
3997 return 31;
3998 }
3999
4000 return 0;
4001 }
4002
phy_tssi_get_trim_group(u8 ch)4003 static u32 phy_tssi_get_trim_group(u8 ch)
4004 {
4005 switch (ch) {
4006 case 1 ... 8:
4007 return 0;
4008 case 9 ... 14:
4009 return 1;
4010 case 36 ... 48:
4011 return 2;
4012 case 49 ... 51:
4013 return PHY_TSSI_EXTRA_GROUP(2);
4014 case 52 ... 64:
4015 return 3;
4016 case 100 ... 112:
4017 return 4;
4018 case 113 ... 115:
4019 return PHY_TSSI_EXTRA_GROUP(4);
4020 case 116 ... 128:
4021 return 5;
4022 case 132 ... 144:
4023 return 6;
4024 case 149 ... 177:
4025 return 7;
4026 }
4027
4028 return 0;
4029 }
4030
phy_tssi_get_6g_trim_group(u8 ch)4031 static u32 phy_tssi_get_6g_trim_group(u8 ch)
4032 {
4033 switch (ch) {
4034 case 1 ... 13:
4035 return 0;
4036 case 14 ... 16:
4037 return PHY_TSSI_EXTRA_GROUP(0);
4038 case 17 ... 29:
4039 return 1;
4040 case 33 ... 45:
4041 return 2;
4042 case 46 ... 48:
4043 return PHY_TSSI_EXTRA_GROUP(2);
4044 case 49 ... 61:
4045 return 3;
4046 case 65 ... 77:
4047 return 4;
4048 case 78 ... 80:
4049 return PHY_TSSI_EXTRA_GROUP(4);
4050 case 81 ... 93:
4051 return 5;
4052 case 97 ... 109:
4053 return 6;
4054 case 110 ... 112:
4055 return PHY_TSSI_EXTRA_GROUP(6);
4056 case 113 ... 125:
4057 return 7;
4058 case 129 ... 141:
4059 return 8;
4060 case 142 ... 144:
4061 return PHY_TSSI_EXTRA_GROUP(8);
4062 case 145 ... 157:
4063 return 9;
4064 case 161 ... 173:
4065 return 10;
4066 case 174 ... 176:
4067 return PHY_TSSI_EXTRA_GROUP(10);
4068 case 177 ... 189:
4069 return 11;
4070 case 193 ... 205:
4071 return 12;
4072 case 206 ... 208:
4073 return PHY_TSSI_EXTRA_GROUP(12);
4074 case 209 ... 221:
4075 return 13;
4076 case 225 ... 237:
4077 return 14;
4078 case 238 ... 240:
4079 return PHY_TSSI_EXTRA_GROUP(14);
4080 case 241 ... 253:
4081 return 15;
4082 }
4083
4084 return 0;
4085 }
4086
phy_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4087 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
4088 enum rtw89_phy_idx phy,
4089 const struct rtw89_chan *chan,
4090 enum rtw89_rf_path path)
4091 {
4092 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4093 enum rtw89_band band = chan->band_type;
4094 u8 ch = chan->channel;
4095 u32 gidx_1st;
4096 u32 gidx_2nd;
4097 s8 de_1st;
4098 s8 de_2nd;
4099 u32 gidx;
4100 s8 val;
4101
4102 if (band == RTW89_BAND_6G)
4103 goto calc_6g;
4104
4105 gidx = phy_tssi_get_ofdm_group(ch);
4106
4107 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4108 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4109 path, gidx);
4110
4111 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4112 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4113 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4114 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
4115 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
4116 val = (de_1st + de_2nd) / 2;
4117
4118 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4119 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4120 path, val, de_1st, de_2nd);
4121 } else {
4122 val = tssi_info->tssi_mcs[path][gidx];
4123
4124 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4125 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4126 }
4127
4128 return val;
4129
4130 calc_6g:
4131 gidx = phy_tssi_get_6g_ofdm_group(ch);
4132
4133 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4134 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4135 path, gidx);
4136
4137 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4138 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4139 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4140 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
4141 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
4142 val = (de_1st + de_2nd) / 2;
4143
4144 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4145 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4146 path, val, de_1st, de_2nd);
4147 } else {
4148 val = tssi_info->tssi_6g_mcs[path][gidx];
4149
4150 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4151 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4152 }
4153
4154 return val;
4155 }
4156
phy_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4157 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
4158 enum rtw89_phy_idx phy,
4159 const struct rtw89_chan *chan,
4160 enum rtw89_rf_path path)
4161 {
4162 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4163 enum rtw89_band band = chan->band_type;
4164 u8 ch = chan->channel;
4165 u32 tgidx_1st;
4166 u32 tgidx_2nd;
4167 s8 tde_1st;
4168 s8 tde_2nd;
4169 u32 tgidx;
4170 s8 val;
4171
4172 if (band == RTW89_BAND_6G)
4173 goto calc_6g;
4174
4175 tgidx = phy_tssi_get_trim_group(ch);
4176
4177 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4178 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4179 path, tgidx);
4180
4181 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4182 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4183 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4184 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
4185 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
4186 val = (tde_1st + tde_2nd) / 2;
4187
4188 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4189 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4190 path, val, tde_1st, tde_2nd);
4191 } else {
4192 val = tssi_info->tssi_trim[path][tgidx];
4193
4194 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4195 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4196 path, val);
4197 }
4198
4199 return val;
4200
4201 calc_6g:
4202 tgidx = phy_tssi_get_6g_trim_group(ch);
4203
4204 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4205 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4206 path, tgidx);
4207
4208 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4209 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4210 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4211 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
4212 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
4213 val = (tde_1st + tde_2nd) / 2;
4214
4215 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4216 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4217 path, val, tde_1st, tde_2nd);
4218 } else {
4219 val = tssi_info->tssi_trim_6g[path][tgidx];
4220
4221 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4222 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4223 path, val);
4224 }
4225
4226 return val;
4227 }
4228
rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4229 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
4230 enum rtw89_phy_idx phy,
4231 const struct rtw89_chan *chan,
4232 struct rtw89_h2c_rf_tssi *h2c)
4233 {
4234 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4235 u8 ch = chan->channel;
4236 s8 trim_de;
4237 s8 ofdm_de;
4238 s8 cck_de;
4239 u8 gidx;
4240 s8 val;
4241 int i;
4242
4243 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
4244 phy, ch);
4245
4246 for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
4247 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
4248 h2c->curr_tssi_trim_de[i] = trim_de;
4249
4250 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4251 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de);
4252
4253 gidx = phy_tssi_get_cck_group(ch);
4254 cck_de = tssi_info->tssi_cck[i][gidx];
4255 val = u32_get_bits(cck_de + trim_de, 0xff);
4256
4257 h2c->curr_tssi_cck_de[i] = 0x0;
4258 h2c->curr_tssi_cck_de_20m[i] = val;
4259 h2c->curr_tssi_cck_de_40m[i] = val;
4260 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
4261
4262 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4263 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de);
4264
4265 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
4266 val = u32_get_bits(ofdm_de + trim_de, 0xff);
4267
4268 h2c->curr_tssi_ofdm_de[i] = 0x0;
4269 h2c->curr_tssi_ofdm_de_20m[i] = val;
4270 h2c->curr_tssi_ofdm_de_40m[i] = val;
4271 h2c->curr_tssi_ofdm_de_80m[i] = val;
4272 h2c->curr_tssi_ofdm_de_160m[i] = val;
4273 h2c->curr_tssi_ofdm_de_320m[i] = val;
4274 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
4275
4276 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4277 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de);
4278 }
4279 }
4280
rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4281 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
4282 enum rtw89_phy_idx phy,
4283 const struct rtw89_chan *chan,
4284 struct rtw89_h2c_rf_tssi *h2c)
4285 {
4286 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
4287 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4288 const s8 *thm_up[RF_PATH_B + 1] = {};
4289 const s8 *thm_down[RF_PATH_B + 1] = {};
4290 u8 subband = chan->subband_type;
4291 s8 thm_ofst[128] = {0};
4292 u8 thermal;
4293 u8 path;
4294 u8 i, j;
4295
4296 switch (subband) {
4297 default:
4298 case RTW89_CH_2G:
4299 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
4300 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
4301 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
4302 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
4303 break;
4304 case RTW89_CH_5G_BAND_1:
4305 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
4306 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
4307 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
4308 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
4309 break;
4310 case RTW89_CH_5G_BAND_3:
4311 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
4312 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
4313 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
4314 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
4315 break;
4316 case RTW89_CH_5G_BAND_4:
4317 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
4318 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
4319 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
4320 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
4321 break;
4322 case RTW89_CH_6G_BAND_IDX0:
4323 case RTW89_CH_6G_BAND_IDX1:
4324 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
4325 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
4326 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
4327 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
4328 break;
4329 case RTW89_CH_6G_BAND_IDX2:
4330 case RTW89_CH_6G_BAND_IDX3:
4331 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
4332 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
4333 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
4334 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
4335 break;
4336 case RTW89_CH_6G_BAND_IDX4:
4337 case RTW89_CH_6G_BAND_IDX5:
4338 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
4339 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
4340 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
4341 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
4342 break;
4343 case RTW89_CH_6G_BAND_IDX6:
4344 case RTW89_CH_6G_BAND_IDX7:
4345 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
4346 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
4347 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
4348 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
4349 break;
4350 }
4351
4352 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4353 "[TSSI] tmeter tbl on subband: %u\n", subband);
4354
4355 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
4356 thermal = tssi_info->thermal[path];
4357 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4358 "path: %u, pg thermal: 0x%x\n", path, thermal);
4359
4360 if (thermal == 0xff) {
4361 h2c->pg_thermal[path] = 0x38;
4362 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
4363 continue;
4364 }
4365
4366 h2c->pg_thermal[path] = thermal;
4367
4368 i = 0;
4369 for (j = 0; j < 64; j++)
4370 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4371 thm_up[path][i++] :
4372 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
4373
4374 i = 1;
4375 for (j = 127; j >= 64; j--)
4376 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4377 -thm_down[path][i++] :
4378 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
4379
4380 for (i = 0; i < 128; i += 4) {
4381 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
4382 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
4383 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
4384 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
4385
4386 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4387 "thm ofst [%x]: %02x %02x %02x %02x\n",
4388 i, thm_ofst[i], thm_ofst[i + 1],
4389 thm_ofst[i + 2], thm_ofst[i + 3]);
4390 }
4391 }
4392 }
4393
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)4394 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
4395 {
4396 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4397 u32 reg_mask;
4398
4399 if (sc_xo)
4400 reg_mask = xtal->sc_xo_mask;
4401 else
4402 reg_mask = xtal->sc_xi_mask;
4403
4404 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
4405 }
4406
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)4407 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
4408 u8 val)
4409 {
4410 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4411 u32 reg_mask;
4412
4413 if (sc_xo)
4414 reg_mask = xtal->sc_xo_mask;
4415 else
4416 reg_mask = xtal->sc_xi_mask;
4417
4418 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
4419 }
4420
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)4421 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
4422 u8 crystal_cap, bool force)
4423 {
4424 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4425 const struct rtw89_chip_info *chip = rtwdev->chip;
4426 u8 sc_xi_val, sc_xo_val;
4427
4428 if (!force && cfo->crystal_cap == crystal_cap)
4429 return;
4430 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
4431 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
4432 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
4433 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
4434 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
4435 } else {
4436 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
4437 crystal_cap, XTAL_SC_XO_MASK);
4438 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
4439 crystal_cap, XTAL_SC_XI_MASK);
4440 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
4441 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
4442 }
4443 cfo->crystal_cap = sc_xi_val;
4444 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
4445
4446 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
4447 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
4448 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
4449 cfo->x_cap_ofst);
4450 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
4451 }
4452
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)4453 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
4454 {
4455 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4456 u8 cap;
4457
4458 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
4459 cfo->is_adjust = false;
4460 if (cfo->crystal_cap == cfo->def_x_cap)
4461 return;
4462 cap = cfo->crystal_cap;
4463 cap += (cap > cfo->def_x_cap ? -1 : 1);
4464 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
4465 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4466 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
4467 cfo->def_x_cap);
4468 }
4469
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)4470 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
4471 {
4472 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
4473 bool is_linked = rtwdev->total_sta_assoc > 0;
4474 s32 cfo_avg_312;
4475 s32 dcfo_comp_val;
4476 int sign;
4477
4478 if (rtwdev->chip->chip_id == RTL8922A)
4479 return;
4480
4481 if (!is_linked) {
4482 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
4483 is_linked);
4484 return;
4485 }
4486 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
4487 if (curr_cfo == 0)
4488 return;
4489 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
4490 sign = curr_cfo > 0 ? 1 : -1;
4491 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val;
4492 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
4493 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
4494 cfo_avg_312 = -cfo_avg_312;
4495 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
4496 cfo_avg_312);
4497 }
4498
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)4499 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
4500 {
4501 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4502 const struct rtw89_chip_info *chip = rtwdev->chip;
4503 const struct rtw89_cfo_regs *cfo = phy->cfo;
4504
4505 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
4506 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
4507
4508 if (chip->chip_gen == RTW89_CHIP_AX) {
4509 if (chip->cfo_hw_comp) {
4510 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
4511 B_AX_PWR_UL_CFO_MASK, 0x6);
4512 } else {
4513 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
4514 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
4515 B_AX_PWR_UL_CFO_MASK);
4516 }
4517 }
4518 }
4519
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)4520 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
4521 {
4522 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4523 struct rtw89_efuse *efuse = &rtwdev->efuse;
4524
4525 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
4526 cfo->crystal_cap = cfo->crystal_cap_default;
4527 cfo->def_x_cap = cfo->crystal_cap;
4528 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4529 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4530 cfo->is_adjust = false;
4531 cfo->divergence_lock_en = false;
4532 cfo->x_cap_ofst = 0;
4533 cfo->lock_cnt = 0;
4534 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4535 cfo->apply_compensation = false;
4536 cfo->residual_cfo_acc = 0;
4537 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
4538 cfo->crystal_cap_default);
4539 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
4540 rtw89_dcfo_comp_init(rtwdev);
4541 cfo->cfo_timer_ms = 2000;
4542 cfo->cfo_trig_by_timer_en = false;
4543 cfo->phy_cfo_trk_cnt = 0;
4544 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4545 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
4546 }
4547
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)4548 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
4549 s32 curr_cfo)
4550 {
4551 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4552 int crystal_cap = cfo->crystal_cap;
4553 s32 cfo_abs = abs(curr_cfo);
4554 int sign;
4555
4556 if (curr_cfo == 0) {
4557 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
4558 return;
4559 }
4560 if (!cfo->is_adjust) {
4561 if (cfo_abs > CFO_TRK_ENABLE_TH)
4562 cfo->is_adjust = true;
4563 } else {
4564 if (cfo_abs <= CFO_TRK_STOP_TH)
4565 cfo->is_adjust = false;
4566 }
4567 if (!cfo->is_adjust) {
4568 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
4569 return;
4570 }
4571 sign = curr_cfo > 0 ? 1 : -1;
4572 if (cfo_abs > CFO_TRK_STOP_TH_4)
4573 crystal_cap += 3 * sign;
4574 else if (cfo_abs > CFO_TRK_STOP_TH_3)
4575 crystal_cap += 3 * sign;
4576 else if (cfo_abs > CFO_TRK_STOP_TH_2)
4577 crystal_cap += 1 * sign;
4578 else if (cfo_abs > CFO_TRK_STOP_TH_1)
4579 crystal_cap += 1 * sign;
4580 else
4581 return;
4582
4583 crystal_cap = clamp(crystal_cap, 0, 127);
4584 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
4585 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4586 "X_cap{Curr,Default}={0x%x,0x%x}\n",
4587 cfo->crystal_cap, cfo->def_x_cap);
4588 }
4589
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)4590 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
4591 {
4592 const struct rtw89_chip_info *chip = rtwdev->chip;
4593 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4594 s32 cfo_khz_all = 0;
4595 s32 cfo_cnt_all = 0;
4596 s32 cfo_all_avg = 0;
4597 u8 i;
4598
4599 if (rtwdev->total_sta_assoc != 1)
4600 return 0;
4601 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
4602 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4603 if (cfo->cfo_cnt[i] == 0)
4604 continue;
4605 cfo_khz_all += cfo->cfo_tail[i];
4606 cfo_cnt_all += cfo->cfo_cnt[i];
4607 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
4608 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4609 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
4610 cfo_cnt_all);
4611 }
4612 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4613 "CFO track for macid = %d\n", i);
4614 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4615 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
4616 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
4617 return cfo_all_avg;
4618 }
4619
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)4620 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
4621 {
4622 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4623 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4624 s32 target_cfo = 0;
4625 s32 cfo_khz_all = 0;
4626 s32 cfo_khz_all_tp_wgt = 0;
4627 s32 cfo_avg = 0;
4628 s32 max_cfo_lb = BIT(31);
4629 s32 min_cfo_ub = GENMASK(30, 0);
4630 u16 cfo_cnt_all = 0;
4631 u8 active_entry_cnt = 0;
4632 u8 sta_cnt = 0;
4633 u32 tp_all = 0;
4634 u8 i;
4635 u8 cfo_tol = 0;
4636
4637 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
4638 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
4639 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
4640 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4641 if (cfo->cfo_cnt[i] == 0)
4642 continue;
4643 cfo_khz_all += cfo->cfo_tail[i];
4644 cfo_cnt_all += cfo->cfo_cnt[i];
4645 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
4646 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4647 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
4648 cfo_khz_all, cfo_cnt_all, cfo_avg);
4649 target_cfo = cfo_avg;
4650 }
4651 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
4652 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
4653 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4654 if (cfo->cfo_cnt[i] == 0)
4655 continue;
4656 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4657 (s32)cfo->cfo_cnt[i]);
4658 cfo_khz_all += cfo->cfo_avg[i];
4659 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4660 "Macid=%d, cfo_avg=%d\n", i,
4661 cfo->cfo_avg[i]);
4662 }
4663 sta_cnt = rtwdev->total_sta_assoc;
4664 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
4665 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4666 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
4667 cfo_khz_all, sta_cnt, cfo_avg);
4668 target_cfo = cfo_avg;
4669 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
4670 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
4671 cfo_tol = cfo->sta_cfo_tolerance;
4672 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4673 sta_cnt++;
4674 if (cfo->cfo_cnt[i] != 0) {
4675 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4676 (s32)cfo->cfo_cnt[i]);
4677 active_entry_cnt++;
4678 } else {
4679 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
4680 }
4681 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
4682 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
4683 cfo_khz_all += cfo->cfo_avg[i];
4684 /* need tp for each entry */
4685 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4686 "[%d] cfo_avg=%d, tp=tbd\n",
4687 i, cfo->cfo_avg[i]);
4688 if (sta_cnt >= rtwdev->total_sta_assoc)
4689 break;
4690 }
4691 tp_all = stats->rx_throughput; /* need tp for each entry */
4692 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
4693
4694 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
4695 sta_cnt);
4696 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
4697 active_entry_cnt);
4698 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4699 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
4700 cfo_khz_all_tp_wgt, cfo_avg);
4701 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
4702 max_cfo_lb, min_cfo_ub);
4703 if (max_cfo_lb <= min_cfo_ub) {
4704 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4705 "cfo win_size=%d\n",
4706 min_cfo_ub - max_cfo_lb);
4707 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
4708 } else {
4709 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4710 "No intersection of cfo tolerance windows\n");
4711 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
4712 }
4713 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
4714 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4715 }
4716 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
4717 return target_cfo;
4718 }
4719
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)4720 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
4721 {
4722 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4723
4724 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
4725 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
4726 cfo->packet_count = 0;
4727 cfo->packet_count_pre = 0;
4728 cfo->cfo_avg_pre = 0;
4729 }
4730
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)4731 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
4732 {
4733 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4734 s32 new_cfo = 0;
4735 bool x_cap_update = false;
4736 u8 pre_x_cap = cfo->crystal_cap;
4737 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4738
4739 cfo->dcfo_avg = 0;
4740 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
4741 rtwdev->total_sta_assoc);
4742 if (rtwdev->total_sta_assoc == 0 || rtw89_is_mlo_1_1(rtwdev)) {
4743 rtw89_phy_cfo_reset(rtwdev);
4744 return;
4745 }
4746 if (cfo->packet_count == 0) {
4747 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
4748 return;
4749 }
4750 if (cfo->packet_count == cfo->packet_count_pre) {
4751 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
4752 return;
4753 }
4754 if (rtwdev->total_sta_assoc == 1)
4755 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
4756 else
4757 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
4758 if (cfo->divergence_lock_en) {
4759 cfo->lock_cnt++;
4760 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
4761 cfo->divergence_lock_en = false;
4762 cfo->lock_cnt = 0;
4763 } else {
4764 rtw89_phy_cfo_reset(rtwdev);
4765 }
4766 return;
4767 }
4768 if (cfo->crystal_cap >= cfo->x_cap_ub ||
4769 cfo->crystal_cap <= cfo->x_cap_lb) {
4770 cfo->divergence_lock_en = true;
4771 rtw89_phy_cfo_reset(rtwdev);
4772 return;
4773 }
4774
4775 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
4776 cfo->cfo_avg_pre = new_cfo;
4777 cfo->dcfo_avg_pre = cfo->dcfo_avg;
4778 x_cap_update = cfo->crystal_cap != pre_x_cap;
4779 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
4780 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4781 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
4782 cfo->x_cap_ofst);
4783 if (x_cap_update) {
4784 if (cfo->dcfo_avg > 0)
4785 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4786 else
4787 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4788 }
4789 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4790 rtw89_phy_cfo_statistics_reset(rtwdev);
4791 }
4792
rtw89_phy_cfo_track_work(struct wiphy * wiphy,struct wiphy_work * work)4793 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work)
4794 {
4795 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4796 cfo_track_work.work);
4797 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4798
4799 lockdep_assert_wiphy(wiphy);
4800
4801 if (!cfo->cfo_trig_by_timer_en)
4802 return;
4803 rtw89_leave_ps_mode(rtwdev);
4804 rtw89_phy_cfo_dm(rtwdev);
4805 wiphy_delayed_work_queue(wiphy, &rtwdev->cfo_track_work,
4806 msecs_to_jiffies(cfo->cfo_timer_ms));
4807 }
4808
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)4809 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
4810 {
4811 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4812
4813 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->cfo_track_work,
4814 msecs_to_jiffies(cfo->cfo_timer_ms));
4815 }
4816
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)4817 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
4818 {
4819 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4820 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4821 bool is_ul_ofdma = false, ofdma_acc_en = false;
4822
4823 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
4824 is_ul_ofdma = true;
4825 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
4826 is_ul_ofdma)
4827 ofdma_acc_en = true;
4828
4829 switch (cfo->phy_cfo_status) {
4830 case RTW89_PHY_DCFO_STATE_NORMAL:
4831 if (stats->tx_throughput >= CFO_TP_UPPER) {
4832 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
4833 cfo->cfo_trig_by_timer_en = true;
4834 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
4835 rtw89_phy_cfo_start_work(rtwdev);
4836 }
4837 break;
4838 case RTW89_PHY_DCFO_STATE_ENHANCE:
4839 if (stats->tx_throughput <= CFO_TP_LOWER)
4840 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4841 else if (ofdma_acc_en &&
4842 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
4843 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
4844 else
4845 cfo->phy_cfo_trk_cnt++;
4846
4847 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
4848 cfo->phy_cfo_trk_cnt = 0;
4849 cfo->cfo_trig_by_timer_en = false;
4850 }
4851 break;
4852 case RTW89_PHY_DCFO_STATE_HOLD:
4853 if (stats->tx_throughput <= CFO_TP_LOWER) {
4854 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4855 cfo->phy_cfo_trk_cnt = 0;
4856 cfo->cfo_trig_by_timer_en = false;
4857 } else {
4858 cfo->phy_cfo_trk_cnt++;
4859 }
4860 break;
4861 default:
4862 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4863 cfo->phy_cfo_trk_cnt = 0;
4864 break;
4865 }
4866 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4867 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
4868 stats->tx_throughput, cfo->phy_cfo_status,
4869 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
4870 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
4871 if (cfo->cfo_trig_by_timer_en)
4872 return;
4873 rtw89_phy_cfo_dm(rtwdev);
4874 }
4875
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)4876 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
4877 struct rtw89_rx_phy_ppdu *phy_ppdu)
4878 {
4879 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4880 u8 macid = phy_ppdu->mac_id;
4881
4882 if (macid >= CFO_TRACK_MAX_USER) {
4883 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
4884 return;
4885 }
4886
4887 cfo->cfo_tail[macid] += cfo_val;
4888 cfo->cfo_cnt[macid]++;
4889 cfo->packet_count++;
4890 }
4891
rtw89_phy_ul_tb_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4892 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4893 {
4894 const struct rtw89_chip_info *chip = rtwdev->chip;
4895 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4896 rtwvif_link->chanctx_idx);
4897 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4898
4899 if (!chip->ul_tb_waveform_ctrl)
4900 return;
4901
4902 rtwvif_link->def_tri_idx =
4903 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
4904
4905 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
4906 rtwvif_link->dyn_tb_bedge_en = false;
4907 else if (chan->band_type >= RTW89_BAND_5G &&
4908 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
4909 rtwvif_link->dyn_tb_bedge_en = true;
4910 else
4911 rtwvif_link->dyn_tb_bedge_en = false;
4912
4913 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4914 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
4915 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
4916 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4917 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
4918 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
4919 }
4920
4921 struct rtw89_phy_ul_tb_check_data {
4922 bool valid;
4923 bool high_tf_client;
4924 bool low_tf_client;
4925 bool dyn_tb_bedge_en;
4926 u8 def_tri_idx;
4927 };
4928
4929 struct rtw89_phy_power_diff {
4930 u32 q_00;
4931 u32 q_11;
4932 u32 q_matrix_en;
4933 u32 ultb_1t_norm_160;
4934 u32 ultb_2t_norm_160;
4935 u32 com1_norm_1sts;
4936 u32 com2_resp_1sts_path;
4937 };
4938
rtw89_phy_ofdma_power_diff(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4939 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
4940 struct rtw89_vif_link *rtwvif_link)
4941 {
4942 static const struct rtw89_phy_power_diff table[2] = {
4943 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3},
4944 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1},
4945 };
4946 const struct rtw89_phy_power_diff *param;
4947 u32 reg;
4948
4949 if (!rtwdev->chip->ul_tb_pwr_diff)
4950 return;
4951
4952 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
4953 rtwvif_link->pwr_diff_en = false;
4954 return;
4955 }
4956
4957 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
4958 param = &table[rtwvif_link->pwr_diff_en];
4959
4960 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
4961 param->q_00);
4962 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
4963 param->q_11);
4964 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
4965 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
4966
4967 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
4968 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
4969 param->ultb_1t_norm_160);
4970
4971 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
4972 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
4973 param->ultb_2t_norm_160);
4974
4975 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
4976 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
4977 param->com1_norm_1sts);
4978
4979 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
4980 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
4981 param->com2_resp_1sts_path);
4982 }
4983
4984 static
rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4985 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
4986 struct rtw89_vif_link *rtwvif_link,
4987 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4988 {
4989 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4990 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4991
4992 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
4993 return;
4994
4995 if (!vif->cfg.assoc)
4996 return;
4997
4998 if (rtwdev->chip->ul_tb_waveform_ctrl) {
4999 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
5000 ul_tb_data->high_tf_client = true;
5001 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
5002 ul_tb_data->low_tf_client = true;
5003
5004 ul_tb_data->valid = true;
5005 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
5006 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
5007 }
5008
5009 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link);
5010 }
5011
rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev * rtwdev,struct rtw89_phy_ul_tb_check_data * ul_tb_data)5012 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
5013 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
5014 {
5015 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5016
5017 if (!rtwdev->chip->ul_tb_waveform_ctrl)
5018 return;
5019
5020 if (ul_tb_data->dyn_tb_bedge_en) {
5021 if (ul_tb_data->high_tf_client) {
5022 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
5023 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5024 "[ULTB] Turn off if_bandedge\n");
5025 } else if (ul_tb_data->low_tf_client) {
5026 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
5027 ul_tb_info->def_if_bandedge);
5028 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5029 "[ULTB] Set to default if_bandedge = %d\n",
5030 ul_tb_info->def_if_bandedge);
5031 }
5032 }
5033
5034 if (ul_tb_info->dyn_tb_tri_en) {
5035 if (ul_tb_data->high_tf_client) {
5036 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
5037 B_TXSHAPE_TRIANGULAR_CFG, 0);
5038 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5039 "[ULTB] Turn off Tx triangle\n");
5040 } else if (ul_tb_data->low_tf_client) {
5041 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
5042 B_TXSHAPE_TRIANGULAR_CFG,
5043 ul_tb_data->def_tri_idx);
5044 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5045 "[ULTB] Set to default tx_shap_idx = %d\n",
5046 ul_tb_data->def_tri_idx);
5047 }
5048 }
5049 }
5050
rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev * rtwdev)5051 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
5052 {
5053 const struct rtw89_chip_info *chip = rtwdev->chip;
5054 struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
5055 struct rtw89_vif_link *rtwvif_link;
5056 struct rtw89_vif *rtwvif;
5057 unsigned int link_id;
5058
5059 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
5060 return;
5061
5062 if (rtwdev->total_sta_assoc != 1)
5063 return;
5064
5065 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5066 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
5067 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data);
5068
5069 if (!ul_tb_data.valid)
5070 return;
5071
5072 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
5073 }
5074
rtw89_phy_ul_tb_info_init(struct rtw89_dev * rtwdev)5075 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
5076 {
5077 const struct rtw89_chip_info *chip = rtwdev->chip;
5078 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5079
5080 if (!chip->ul_tb_waveform_ctrl)
5081 return;
5082
5083 ul_tb_info->dyn_tb_tri_en = true;
5084 ul_tb_info->def_if_bandedge =
5085 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
5086 }
5087
5088 static
rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats * antdiv_sts)5089 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
5090 {
5091 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
5092 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
5093 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
5094 antdiv_sts->pkt_cnt_cck = 0;
5095 antdiv_sts->pkt_cnt_ofdm = 0;
5096 antdiv_sts->pkt_cnt_non_legacy = 0;
5097 antdiv_sts->evm = 0;
5098 }
5099
rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_antdiv_stats * stats)5100 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
5101 struct rtw89_rx_phy_ppdu *phy_ppdu,
5102 struct rtw89_antdiv_stats *stats)
5103 {
5104 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
5105 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
5106 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
5107 stats->pkt_cnt_cck++;
5108 } else {
5109 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
5110 stats->pkt_cnt_ofdm++;
5111 stats->evm += phy_ppdu->ofdm.evm_min;
5112 }
5113 } else {
5114 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
5115 stats->pkt_cnt_non_legacy++;
5116 stats->evm += phy_ppdu->ofdm.evm_min;
5117 }
5118 }
5119
rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats * stats)5120 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
5121 {
5122 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
5123 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
5124 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
5125 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
5126 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
5127 return ewma_rssi_read(&stats->ofdm_rssi_avg);
5128 else
5129 return ewma_rssi_read(&stats->cck_rssi_avg);
5130 }
5131
rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats * stats)5132 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
5133 {
5134 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
5135 }
5136
rtw89_phy_antdiv_parse(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)5137 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
5138 struct rtw89_rx_phy_ppdu *phy_ppdu)
5139 {
5140 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5141 struct rtw89_hal *hal = &rtwdev->hal;
5142
5143 if (!hal->ant_diversity || hal->ant_diversity_fixed)
5144 return;
5145
5146 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
5147
5148 if (!antdiv->get_stats)
5149 return;
5150
5151 if (hal->antenna_rx == RF_A)
5152 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
5153 else if (hal->antenna_rx == RF_B)
5154 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
5155 }
5156
rtw89_phy_antdiv_reg_init(struct rtw89_dev * rtwdev)5157 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
5158 {
5159 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
5160 0x0, RTW89_PHY_0);
5161 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
5162 0x0, RTW89_PHY_0);
5163
5164 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
5165 0x0, RTW89_PHY_0);
5166 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
5167 0x0, RTW89_PHY_0);
5168
5169 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
5170 0x0, RTW89_PHY_0);
5171
5172 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
5173 0x0100, RTW89_PHY_0);
5174
5175 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
5176 0x1, RTW89_PHY_0);
5177 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
5178 0x0, RTW89_PHY_0);
5179 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
5180 0x0, RTW89_PHY_0);
5181 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
5182 0x0, RTW89_PHY_0);
5183 }
5184
rtw89_phy_antdiv_sts_reset(struct rtw89_dev * rtwdev)5185 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
5186 {
5187 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5188
5189 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
5190 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
5191 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
5192 }
5193
rtw89_phy_antdiv_init(struct rtw89_dev * rtwdev)5194 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
5195 {
5196 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5197 struct rtw89_hal *hal = &rtwdev->hal;
5198
5199 if (!hal->ant_diversity)
5200 return;
5201
5202 antdiv->get_stats = false;
5203 antdiv->rssi_pre = 0;
5204 rtw89_phy_antdiv_sts_reset(rtwdev);
5205 rtw89_phy_antdiv_reg_init(rtwdev);
5206 }
5207
rtw89_phy_thermal_protect(struct rtw89_dev * rtwdev)5208 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev)
5209 {
5210 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5211 struct rtw89_hal *hal = &rtwdev->hal;
5212 u8 th_max = phystat->last_thermal_max;
5213 u8 lv = hal->thermal_prot_lv;
5214
5215 if (!hal->thermal_prot_th ||
5216 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT)))
5217 return;
5218
5219 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX)
5220 lv++;
5221 else if (th_max < hal->thermal_prot_th - 2 && lv > 0)
5222 lv--;
5223 else
5224 return;
5225
5226 hal->thermal_prot_lv = lv;
5227
5228 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv);
5229
5230 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv);
5231 }
5232
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)5233 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
5234 {
5235 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5236 u8 th, th_max = 0;
5237 int i;
5238
5239 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
5240 th = rtw89_chip_get_thermal(rtwdev, i);
5241 if (th)
5242 ewma_thermal_add(&phystat->avg_thermal[i], th);
5243
5244 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
5245 "path(%d) thermal cur=%u avg=%ld", i, th,
5246 ewma_thermal_read(&phystat->avg_thermal[i]));
5247
5248 th_max = max(th_max, th);
5249 }
5250
5251 phystat->last_thermal_max = th_max;
5252 }
5253
5254 struct rtw89_phy_iter_rssi_data {
5255 struct rtw89_dev *rtwdev;
5256 bool rssi_changed;
5257 };
5258
5259 static
__rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link * rtwsta_link,struct rtw89_phy_iter_rssi_data * rssi_data)5260 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link,
5261 struct rtw89_phy_iter_rssi_data *rssi_data)
5262 {
5263 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
5264 struct rtw89_dev *rtwdev = rssi_data->rtwdev;
5265 struct rtw89_phy_ch_info *ch_info;
5266 struct rtw89_bb_ctx *bb;
5267 unsigned long rssi_curr;
5268
5269 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
5270 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
5271 ch_info = &bb->ch_info;
5272
5273 if (rssi_curr < ch_info->rssi_min) {
5274 ch_info->rssi_min = rssi_curr;
5275 ch_info->rssi_min_macid = rtwsta_link->mac_id;
5276 }
5277
5278 if (rtwsta_link->prev_rssi == 0) {
5279 rtwsta_link->prev_rssi = rssi_curr;
5280 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
5281 (3 << RSSI_FACTOR)) {
5282 rtwsta_link->prev_rssi = rssi_curr;
5283 rssi_data->rssi_changed = true;
5284 }
5285 }
5286
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)5287 static void rtw89_phy_stat_rssi_update_iter(void *data,
5288 struct ieee80211_sta *sta)
5289 {
5290 struct rtw89_phy_iter_rssi_data *rssi_data =
5291 (struct rtw89_phy_iter_rssi_data *)data;
5292 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
5293 struct rtw89_sta_link *rtwsta_link;
5294 unsigned int link_id;
5295
5296 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
5297 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data);
5298 }
5299
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)5300 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
5301 {
5302 struct rtw89_phy_iter_rssi_data rssi_data = {};
5303 struct rtw89_bb_ctx *bb;
5304
5305 rssi_data.rtwdev = rtwdev;
5306 rtw89_for_each_active_bb(rtwdev, bb)
5307 bb->ch_info.rssi_min = U8_MAX;
5308
5309 ieee80211_iterate_stations_atomic(rtwdev->hw,
5310 rtw89_phy_stat_rssi_update_iter,
5311 &rssi_data);
5312 if (rssi_data.rssi_changed)
5313 rtw89_btc_ntfy_wl_sta(rtwdev);
5314 }
5315
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)5316 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
5317 {
5318 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5319 int i;
5320
5321 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
5322 ewma_thermal_init(&phystat->avg_thermal[i]);
5323
5324 rtw89_phy_stat_thermal_update(rtwdev);
5325
5326 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5327 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
5328
5329 ewma_rssi_init(&phystat->bcn_rssi);
5330
5331 rtwdev->hal.thermal_prot_lv = 0;
5332 }
5333
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)5334 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
5335 {
5336 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5337
5338 rtw89_phy_stat_thermal_update(rtwdev);
5339 rtw89_phy_thermal_protect(rtwdev);
5340 rtw89_phy_stat_rssi_update(rtwdev);
5341
5342 phystat->last_pkt_stat = phystat->cur_pkt_stat;
5343 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5344 }
5345
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u32 time_us)5346 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev,
5347 struct rtw89_bb_ctx *bb, u32 time_us)
5348 {
5349 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5350
5351 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5352 }
5353
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 idx)5354 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev,
5355 struct rtw89_bb_ctx *bb, u16 idx)
5356 {
5357 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5358
5359 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5360 }
5361
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5362 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev,
5363 struct rtw89_bb_ctx *bb)
5364 {
5365 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5366 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5367 const struct rtw89_ccx_regs *ccx = phy->ccx;
5368
5369 env->ccx_manual_ctrl = false;
5370 env->ccx_ongoing = false;
5371 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5372 env->ccx_period = 0;
5373 env->ccx_unit_idx = RTW89_CCX_32_US;
5374
5375 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->en_mask, 1, bb->phy_idx);
5376 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1,
5377 bb->phy_idx);
5378 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5379 bb->phy_idx);
5380 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
5381 RTW89_CCX_EDCCA_BW20_0, bb->phy_idx);
5382 }
5383
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 report,u16 score)5384 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev,
5385 struct rtw89_bb_ctx *bb,
5386 u16 report, u16 score)
5387 {
5388 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5389 u32 numer = 0;
5390 u16 ret = 0;
5391
5392 numer = report * score + (env->ccx_period >> 1);
5393 if (env->ccx_period)
5394 ret = numer / env->ccx_period;
5395
5396 return ret >= score ? score - 1 : ret;
5397 }
5398
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)5399 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
5400 u16 time_ms, u32 *period,
5401 u32 *unit_idx)
5402 {
5403 u32 idx;
5404 u8 quotient;
5405
5406 if (time_ms >= CCX_MAX_PERIOD)
5407 time_ms = CCX_MAX_PERIOD;
5408
5409 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
5410
5411 if (quotient < 4)
5412 idx = RTW89_CCX_4_US;
5413 else if (quotient < 8)
5414 idx = RTW89_CCX_8_US;
5415 else if (quotient < 16)
5416 idx = RTW89_CCX_16_US;
5417 else
5418 idx = RTW89_CCX_32_US;
5419
5420 *unit_idx = idx;
5421 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
5422
5423 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5424 "[Trigger Time] period:%d, unit_idx:%d\n",
5425 *period, *unit_idx);
5426 }
5427
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5428 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev,
5429 struct rtw89_bb_ctx *bb)
5430 {
5431 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5432
5433 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5434 "lv:(%d)->(0)\n", env->ccx_rac_lv);
5435
5436 env->ccx_ongoing = false;
5437 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5438 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5439 }
5440
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)5441 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
5442 struct rtw89_bb_ctx *bb,
5443 struct rtw89_ccx_para_info *para)
5444 {
5445 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5446 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
5447 u8 i = 0;
5448 u16 *ifs_th_l = env->ifs_clm_th_l;
5449 u16 *ifs_th_h = env->ifs_clm_th_h;
5450 u32 ifs_th0_us = 0, ifs_th_times = 0;
5451 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
5452
5453 if (!is_update)
5454 goto ifs_update_finished;
5455
5456 switch (para->ifs_clm_app) {
5457 case RTW89_IFS_CLM_INIT:
5458 case RTW89_IFS_CLM_BACKGROUND:
5459 case RTW89_IFS_CLM_ACS:
5460 case RTW89_IFS_CLM_DBG:
5461 case RTW89_IFS_CLM_DIG:
5462 case RTW89_IFS_CLM_TDMA_DIG:
5463 ifs_th0_us = IFS_CLM_TH0_UPPER;
5464 ifs_th_times = IFS_CLM_TH_MUL;
5465 break;
5466 case RTW89_IFS_CLM_DBG_MANUAL:
5467 ifs_th0_us = para->ifs_clm_manual_th0;
5468 ifs_th_times = para->ifs_clm_manual_th_times;
5469 break;
5470 default:
5471 break;
5472 }
5473
5474 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
5475 * low[i] = high[i-1] + 1
5476 * high[i] = high[i-1] * ifs_th_times
5477 */
5478 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
5479 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
5480 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, bb,
5481 ifs_th0_us);
5482 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
5483 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
5484 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
5485 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, ifs_th_h_us[i]);
5486 }
5487
5488 ifs_update_finished:
5489 if (!is_update)
5490 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5491 "No need to update IFS_TH\n");
5492
5493 return is_update;
5494 }
5495
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5496 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev,
5497 struct rtw89_bb_ctx *bb)
5498 {
5499 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5500 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5501 const struct rtw89_ccx_regs *ccx = phy->ccx;
5502 u8 i = 0;
5503
5504 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
5505 env->ifs_clm_th_l[0], bb->phy_idx);
5506 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
5507 env->ifs_clm_th_l[1], bb->phy_idx);
5508 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
5509 env->ifs_clm_th_l[2], bb->phy_idx);
5510 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
5511 env->ifs_clm_th_l[3], bb->phy_idx);
5512
5513 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
5514 env->ifs_clm_th_h[0], bb->phy_idx);
5515 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
5516 env->ifs_clm_th_h[1], bb->phy_idx);
5517 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
5518 env->ifs_clm_th_h[2], bb->phy_idx);
5519 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
5520 env->ifs_clm_th_h[3], bb->phy_idx);
5521
5522 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5523 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5524 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
5525 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
5526 }
5527
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5528 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev,
5529 struct rtw89_bb_ctx *bb)
5530 {
5531 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5532 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5533 const struct rtw89_ccx_regs *ccx = phy->ccx;
5534 struct rtw89_ccx_para_info para = {};
5535
5536 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5537 env->ifs_clm_mntr_time = 0;
5538
5539 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
5540 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, ¶))
5541 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
5542
5543 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true,
5544 bb->phy_idx);
5545 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true,
5546 bb->phy_idx);
5547 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true,
5548 bb->phy_idx);
5549 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true,
5550 bb->phy_idx);
5551 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true,
5552 bb->phy_idx);
5553 }
5554
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,enum rtw89_env_racing_lv level)5555 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
5556 struct rtw89_bb_ctx *bb,
5557 enum rtw89_env_racing_lv level)
5558 {
5559 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5560 int ret = 0;
5561
5562 if (level >= RTW89_RAC_MAX_NUM) {
5563 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5564 "[WARNING] Wrong LV=%d\n", level);
5565 return -EINVAL;
5566 }
5567
5568 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5569 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
5570 env->ccx_rac_lv, level);
5571
5572 if (env->ccx_ongoing) {
5573 if (level <= env->ccx_rac_lv)
5574 ret = -EINVAL;
5575 else
5576 env->ccx_ongoing = false;
5577 }
5578
5579 if (ret == 0)
5580 env->ccx_rac_lv = level;
5581
5582 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
5583 !ret);
5584
5585 return ret;
5586 }
5587
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5588 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev,
5589 struct rtw89_bb_ctx *bb)
5590 {
5591 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5592 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5593 const struct rtw89_ccx_regs *ccx = phy->ccx;
5594
5595 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0,
5596 bb->phy_idx);
5597 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0,
5598 bb->phy_idx);
5599 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1,
5600 bb->phy_idx);
5601 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5602 bb->phy_idx);
5603
5604 env->ccx_ongoing = true;
5605 }
5606
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5607 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev,
5608 struct rtw89_bb_ctx *bb)
5609 {
5610 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5611 u8 i = 0;
5612 u32 res = 0;
5613
5614 env->ifs_clm_tx_ratio =
5615 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_tx, PERCENT);
5616 env->ifs_clm_edcca_excl_cca_ratio =
5617 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_edcca_excl_cca,
5618 PERCENT);
5619 env->ifs_clm_cck_fa_ratio =
5620 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERCENT);
5621 env->ifs_clm_ofdm_fa_ratio =
5622 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERCENT);
5623 env->ifs_clm_cck_cca_excl_fa_ratio =
5624 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckcca_excl_fa,
5625 PERCENT);
5626 env->ifs_clm_ofdm_cca_excl_fa_ratio =
5627 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmcca_excl_fa,
5628 PERCENT);
5629 env->ifs_clm_cck_fa_permil =
5630 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERMIL);
5631 env->ifs_clm_ofdm_fa_permil =
5632 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERMIL);
5633
5634 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
5635 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
5636 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
5637 } else {
5638 env->ifs_clm_ifs_avg[i] =
5639 rtw89_phy_ccx_idx_to_us(rtwdev, bb,
5640 env->ifs_clm_avg[i]);
5641 }
5642
5643 res = rtw89_phy_ccx_idx_to_us(rtwdev, bb, env->ifs_clm_cca[i]);
5644 res += env->ifs_clm_his[i] >> 1;
5645 if (env->ifs_clm_his[i])
5646 res /= env->ifs_clm_his[i];
5647 else
5648 res = 0;
5649 env->ifs_clm_cca_avg[i] = res;
5650 }
5651
5652 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5653 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5654 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
5655 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5656 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
5657 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
5658 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5659 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
5660 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
5661 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5662 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
5663 env->ifs_clm_cck_cca_excl_fa_ratio,
5664 env->ifs_clm_ofdm_cca_excl_fa_ratio);
5665 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5666 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
5667 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5668 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
5669 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
5670 env->ifs_clm_cca_avg[i]);
5671 }
5672
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5673 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev,
5674 struct rtw89_bb_ctx *bb)
5675 {
5676 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5677 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5678 const struct rtw89_ccx_regs *ccx = phy->ccx;
5679 u8 i = 0;
5680
5681 if (rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
5682 ccx->ifs_cnt_done_mask, bb->phy_idx) == 0) {
5683 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5684 "Get IFS_CLM report Fail\n");
5685 return false;
5686 }
5687
5688 env->ifs_clm_tx =
5689 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5690 ccx->ifs_clm_tx_cnt_msk, bb->phy_idx);
5691 env->ifs_clm_edcca_excl_cca =
5692 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5693 ccx->ifs_clm_edcca_excl_cca_fa_mask, bb->phy_idx);
5694 env->ifs_clm_cckcca_excl_fa =
5695 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
5696 ccx->ifs_clm_cckcca_excl_fa_mask, bb->phy_idx);
5697 env->ifs_clm_ofdmcca_excl_fa =
5698 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
5699 ccx->ifs_clm_ofdmcca_excl_fa_mask, bb->phy_idx);
5700 env->ifs_clm_cckfa =
5701 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
5702 ccx->ifs_clm_cck_fa_mask, bb->phy_idx);
5703 env->ifs_clm_ofdmfa =
5704 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
5705 ccx->ifs_clm_ofdm_fa_mask, bb->phy_idx);
5706
5707 env->ifs_clm_his[0] =
5708 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5709 ccx->ifs_t1_his_mask, bb->phy_idx);
5710 env->ifs_clm_his[1] =
5711 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5712 ccx->ifs_t2_his_mask, bb->phy_idx);
5713 env->ifs_clm_his[2] =
5714 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5715 ccx->ifs_t3_his_mask, bb->phy_idx);
5716 env->ifs_clm_his[3] =
5717 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5718 ccx->ifs_t4_his_mask, bb->phy_idx);
5719
5720 env->ifs_clm_avg[0] =
5721 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
5722 ccx->ifs_t1_avg_mask, bb->phy_idx);
5723 env->ifs_clm_avg[1] =
5724 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
5725 ccx->ifs_t2_avg_mask, bb->phy_idx);
5726 env->ifs_clm_avg[2] =
5727 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
5728 ccx->ifs_t3_avg_mask, bb->phy_idx);
5729 env->ifs_clm_avg[3] =
5730 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
5731 ccx->ifs_t4_avg_mask, bb->phy_idx);
5732
5733 env->ifs_clm_cca[0] =
5734 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
5735 ccx->ifs_t1_cca_mask, bb->phy_idx);
5736 env->ifs_clm_cca[1] =
5737 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
5738 ccx->ifs_t2_cca_mask, bb->phy_idx);
5739 env->ifs_clm_cca[2] =
5740 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
5741 ccx->ifs_t3_cca_mask, bb->phy_idx);
5742 env->ifs_clm_cca[3] =
5743 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
5744 ccx->ifs_t4_cca_mask, bb->phy_idx);
5745
5746 env->ifs_clm_total_ifs =
5747 rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
5748 ccx->ifs_total_mask, bb->phy_idx);
5749
5750 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
5751 env->ifs_clm_total_ifs);
5752 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5753 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5754 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
5755 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5756 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
5757 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
5758 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5759 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
5760 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
5761
5762 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
5763 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5764 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5765 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
5766 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
5767
5768 rtw89_phy_ifs_clm_get_utility(rtwdev, bb);
5769
5770 return true;
5771 }
5772
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)5773 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
5774 struct rtw89_bb_ctx *bb,
5775 struct rtw89_ccx_para_info *para)
5776 {
5777 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5778 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5779 const struct rtw89_ccx_regs *ccx = phy->ccx;
5780 u32 period = 0;
5781 u32 unit_idx = 0;
5782
5783 if (para->mntr_time == 0) {
5784 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5785 "[WARN] MNTR_TIME is 0\n");
5786 return -EINVAL;
5787 }
5788
5789 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv))
5790 return -EINVAL;
5791
5792 if (para->mntr_time != env->ifs_clm_mntr_time) {
5793 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
5794 &period, &unit_idx);
5795 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
5796 ccx->ifs_clm_period_mask, period, bb->phy_idx);
5797 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
5798 ccx->ifs_clm_cnt_unit_mask,
5799 unit_idx, bb->phy_idx);
5800
5801 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5802 "Update IFS-CLM time ((%d)) -> ((%d))\n",
5803 env->ifs_clm_mntr_time, para->mntr_time);
5804
5805 env->ifs_clm_mntr_time = para->mntr_time;
5806 env->ccx_period = (u16)period;
5807 env->ccx_unit_idx = (u8)unit_idx;
5808 }
5809
5810 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, para)) {
5811 env->ifs_clm_app = para->ifs_clm_app;
5812 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
5813 }
5814
5815 return 0;
5816 }
5817
__rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5818 static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev,
5819 struct rtw89_bb_ctx *bb)
5820 {
5821 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5822 struct rtw89_ccx_para_info para = {};
5823 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5824
5825 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5826 if (env->ccx_manual_ctrl) {
5827 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5828 "CCX in manual ctrl\n");
5829 return;
5830 }
5831
5832 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5833 "BB-%d env_monitor track\n", bb->phy_idx);
5834
5835 /* only ifs_clm for now */
5836 if (rtw89_phy_ifs_clm_get_result(rtwdev, bb))
5837 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5838
5839 rtw89_phy_ccx_racing_release(rtwdev, bb);
5840 para.mntr_time = 1900;
5841 para.rac_lv = RTW89_RAC_LV_1;
5842 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5843
5844 if (rtw89_phy_ifs_clm_set(rtwdev, bb, ¶) == 0)
5845 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5846 if (chk_result)
5847 rtw89_phy_ccx_trigger(rtwdev, bb);
5848
5849 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5850 "get_result=0x%x, chk_result:0x%x\n",
5851 env->ccx_watchdog_result, chk_result);
5852 }
5853
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)5854 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
5855 {
5856 struct rtw89_bb_ctx *bb;
5857
5858 rtw89_for_each_active_bb(rtwdev, bb)
5859 __rtw89_phy_env_monitor_track(rtwdev, bb);
5860 }
5861
rtw89_physts_ie_page_valid(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap * ie_page)5862 static bool rtw89_physts_ie_page_valid(struct rtw89_dev *rtwdev,
5863 enum rtw89_phy_status_bitmap *ie_page)
5864 {
5865 const struct rtw89_chip_info *chip = rtwdev->chip;
5866
5867 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM ||
5868 *ie_page == RTW89_RSVD_9)
5869 return false;
5870 else if (*ie_page > RTW89_RSVD_9 && *ie_page < RTW89_EHT_PKT)
5871 *ie_page -= 1;
5872
5873 if (*ie_page == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX)
5874 return false;
5875
5876 return true;
5877 }
5878
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)5879 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
5880 {
5881 static const u8 ie_page_shift = 2;
5882
5883 if (ie_page == RTW89_EHT_PKT)
5884 return R_PHY_STS_BITMAP_EHT;
5885
5886 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
5887 }
5888
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,enum rtw89_phy_idx phy_idx)5889 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
5890 enum rtw89_phy_status_bitmap ie_page,
5891 enum rtw89_phy_idx phy_idx)
5892 {
5893 u32 addr;
5894
5895 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page))
5896 return 0;
5897
5898 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5899
5900 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx);
5901 }
5902
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val,enum rtw89_phy_idx phy_idx)5903 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
5904 enum rtw89_phy_status_bitmap ie_page,
5905 u32 val, enum rtw89_phy_idx phy_idx)
5906 {
5907 const struct rtw89_chip_info *chip = rtwdev->chip;
5908 u32 addr;
5909
5910 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page))
5911 return;
5912
5913 if (chip->chip_id == RTL8852A)
5914 val &= B_PHY_STS_BITMAP_MSK_52A;
5915
5916 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5917 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
5918 }
5919
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)5920 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
5921 bool enable,
5922 enum rtw89_phy_idx phy_idx)
5923 {
5924 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5925 const struct rtw89_physts_regs *physts = phy->physts;
5926
5927 if (enable) {
5928 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5929 physts->dis_trigger_fail_mask, phy_idx);
5930 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5931 physts->dis_trigger_brk_mask, phy_idx);
5932 } else {
5933 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5934 physts->dis_trigger_fail_mask, phy_idx);
5935 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5936 physts->dis_trigger_brk_mask, phy_idx);
5937 }
5938 }
5939
__rtw89_physts_parsing_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5940 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
5941 enum rtw89_phy_idx phy_idx)
5942 {
5943 const struct rtw89_chip_info *chip = rtwdev->chip;
5944 u32 val;
5945 u8 i;
5946
5947 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
5948
5949 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
5950 if (i == RTW89_RSVD_9 ||
5951 (i == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX))
5952 continue;
5953
5954 val = rtw89_physts_get_ie_bitmap(rtwdev, i, phy_idx);
5955 if (i == RTW89_HE_MU || i == RTW89_VHT_MU) {
5956 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF);
5957 } else if (i == RTW89_TRIG_BASE_PPDU) {
5958 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF) |
5959 BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
5960 } else if (i >= RTW89_CCK_PKT) {
5961 val |= BIT(RTW89_PHYSTS_IE09_FTR_0);
5962
5963 val &= ~(GENMASK(RTW89_PHYSTS_IE07_CMN_EXT_PATH_D,
5964 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A));
5965
5966 if (i == RTW89_CCK_PKT)
5967 val |= BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
5968 else if (i >= RTW89_HT_PKT)
5969 val |= BIT(RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0);
5970 }
5971
5972 rtw89_physts_set_ie_bitmap(rtwdev, i, val, phy_idx);
5973 }
5974 }
5975
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)5976 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
5977 {
5978 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0);
5979 if (rtwdev->dbcc_en)
5980 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1);
5981 }
5982
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,int type)5983 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev,
5984 struct rtw89_bb_ctx *bb, int type)
5985 {
5986 const struct rtw89_chip_info *chip = rtwdev->chip;
5987 const struct rtw89_phy_dig_gain_cfg *cfg;
5988 struct rtw89_dig_info *dig = &bb->dig;
5989 const char *msg;
5990 u8 i;
5991 s8 gain_base;
5992 s8 *gain_arr;
5993 u32 tmp;
5994
5995 switch (type) {
5996 case RTW89_DIG_GAIN_LNA_G:
5997 gain_arr = dig->lna_gain_g;
5998 gain_base = LNA0_GAIN;
5999 cfg = chip->dig_table->cfg_lna_g;
6000 msg = "lna_gain_g";
6001 break;
6002 case RTW89_DIG_GAIN_TIA_G:
6003 gain_arr = dig->tia_gain_g;
6004 gain_base = TIA0_GAIN_G;
6005 cfg = chip->dig_table->cfg_tia_g;
6006 msg = "tia_gain_g";
6007 break;
6008 case RTW89_DIG_GAIN_LNA_A:
6009 gain_arr = dig->lna_gain_a;
6010 gain_base = LNA0_GAIN;
6011 cfg = chip->dig_table->cfg_lna_a;
6012 msg = "lna_gain_a";
6013 break;
6014 case RTW89_DIG_GAIN_TIA_A:
6015 gain_arr = dig->tia_gain_a;
6016 gain_base = TIA0_GAIN_A;
6017 cfg = chip->dig_table->cfg_tia_a;
6018 msg = "tia_gain_a";
6019 break;
6020 default:
6021 return;
6022 }
6023
6024 for (i = 0; i < cfg->size; i++) {
6025 tmp = rtw89_phy_read32_idx(rtwdev, cfg->table[i].addr,
6026 cfg->table[i].mask, bb->phy_idx);
6027 tmp >>= DIG_GAIN_SHIFT;
6028 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
6029 gain_base += DIG_GAIN;
6030
6031 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
6032 msg, i, gain_arr[i]);
6033 }
6034 }
6035
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6036 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev,
6037 struct rtw89_bb_ctx *bb)
6038 {
6039 struct rtw89_dig_info *dig = &bb->dig;
6040 u32 tmp;
6041 u8 i;
6042
6043 if (!rtwdev->hal.support_igi)
6044 return;
6045
6046 tmp = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PKPW,
6047 B_PATH0_IB_PKPW_MSK, bb->phy_idx);
6048 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
6049 dig->ib_pbk = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PBK,
6050 B_PATH0_IB_PBK_MSK, bb->phy_idx);
6051 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
6052 dig->ib_pkpwr, dig->ib_pbk);
6053
6054 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
6055 rtw89_phy_dig_read_gain_table(rtwdev, bb, i);
6056 }
6057
6058 static const u8 rssi_nolink = 22;
6059 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
6060 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
6061 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
6062 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
6063
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6064 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev,
6065 struct rtw89_bb_ctx *bb)
6066 {
6067 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
6068 struct rtw89_dig_info *dig = &bb->dig;
6069 bool is_linked = rtwdev->total_sta_assoc > 0;
6070
6071 if (is_linked) {
6072 dig->igi_rssi = ch_info->rssi_min >> 1;
6073 } else {
6074 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
6075 dig->igi_rssi = rssi_nolink;
6076 }
6077 }
6078
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6079 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev,
6080 struct rtw89_bb_ctx *bb)
6081 {
6082 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
6083 struct rtw89_dig_info *dig = &bb->dig;
6084 bool is_linked = rtwdev->total_sta_assoc > 0;
6085 const u16 *fa_th_src = NULL;
6086
6087 switch (chan->band_type) {
6088 case RTW89_BAND_2G:
6089 dig->lna_gain = dig->lna_gain_g;
6090 dig->tia_gain = dig->tia_gain_g;
6091 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
6092 dig->force_gaincode_idx_en = false;
6093 dig->dyn_pd_th_en = true;
6094 break;
6095 case RTW89_BAND_5G:
6096 default:
6097 dig->lna_gain = dig->lna_gain_a;
6098 dig->tia_gain = dig->tia_gain_a;
6099 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
6100 dig->force_gaincode_idx_en = true;
6101 dig->dyn_pd_th_en = true;
6102 break;
6103 }
6104 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
6105 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
6106 }
6107
6108 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20;
6109 static const u8 igi_max_performance_mode = 0x5a;
6110 static const u8 dynamic_pd_threshold_max;
6111
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6112 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev,
6113 struct rtw89_bb_ctx *bb)
6114 {
6115 struct rtw89_dig_info *dig = &bb->dig;
6116
6117 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
6118 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
6119 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
6120 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
6121 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
6122 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
6123
6124 dig->dyn_igi_max = igi_max_performance_mode;
6125 dig->dyn_igi_min = dynamic_igi_min;
6126 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
6127 dig->pd_low_th_ofst = pd_low_th_offset;
6128 dig->is_linked_pre = false;
6129 }
6130
__rtw89_phy_dig_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6131 static void __rtw89_phy_dig_init(struct rtw89_dev *rtwdev,
6132 struct rtw89_bb_ctx *bb)
6133 {
6134 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig_init\n", bb->phy_idx);
6135
6136 rtw89_phy_dig_update_gain_para(rtwdev, bb);
6137 rtw89_phy_dig_reset(rtwdev, bb);
6138 }
6139
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)6140 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
6141 {
6142 struct rtw89_bb_ctx *bb;
6143
6144 rtw89_for_each_capab_bb(rtwdev, bb)
6145 __rtw89_phy_dig_init(rtwdev, bb);
6146 }
6147
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6148 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev,
6149 struct rtw89_bb_ctx *bb, u8 rssi)
6150 {
6151 struct rtw89_dig_info *dig = &bb->dig;
6152 u8 lna_idx;
6153
6154 if (rssi < dig->igi_rssi_th[0])
6155 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
6156 else if (rssi < dig->igi_rssi_th[1])
6157 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
6158 else if (rssi < dig->igi_rssi_th[2])
6159 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
6160 else if (rssi < dig->igi_rssi_th[3])
6161 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
6162 else if (rssi < dig->igi_rssi_th[4])
6163 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
6164 else
6165 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
6166
6167 return lna_idx;
6168 }
6169
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6170 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev,
6171 struct rtw89_bb_ctx *bb, u8 rssi)
6172 {
6173 struct rtw89_dig_info *dig = &bb->dig;
6174 u8 tia_idx;
6175
6176 if (rssi < dig->igi_rssi_th[0])
6177 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
6178 else
6179 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
6180
6181 return tia_idx;
6182 }
6183
6184 #define IB_PBK_BASE 110
6185 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6186 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev,
6187 struct rtw89_bb_ctx *bb, u8 rssi,
6188 struct rtw89_agc_gaincode_set *set)
6189 {
6190 struct rtw89_dig_info *dig = &bb->dig;
6191 s8 lna_gain = dig->lna_gain[set->lna_idx];
6192 s8 tia_gain = dig->tia_gain[set->tia_idx];
6193 s32 wb_rssi = rssi + lna_gain + tia_gain;
6194 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
6195 u8 rxb_idx;
6196
6197 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
6198 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
6199
6200 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
6201 wb_rssi, rxb_idx_tmp);
6202
6203 return rxb_idx;
6204 }
6205
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6206 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev,
6207 struct rtw89_bb_ctx *bb, u8 rssi,
6208 struct rtw89_agc_gaincode_set *set)
6209 {
6210 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, bb, rssi);
6211 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, bb, rssi);
6212 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, bb, rssi, set);
6213
6214 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6215 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
6216 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
6217 }
6218
6219 #define IGI_OFFSET_MAX 25
6220 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6221 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev,
6222 struct rtw89_bb_ctx *bb)
6223 {
6224 struct rtw89_dig_info *dig = &bb->dig;
6225 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6226 enum rtw89_dig_noisy_level noisy_lv;
6227 u8 igi_offset = dig->fa_rssi_ofst;
6228 u16 fa_ratio = 0;
6229
6230 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
6231
6232 if (fa_ratio < dig->fa_th[0])
6233 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
6234 else if (fa_ratio < dig->fa_th[1])
6235 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
6236 else if (fa_ratio < dig->fa_th[2])
6237 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
6238 else if (fa_ratio < dig->fa_th[3])
6239 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
6240 else
6241 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
6242
6243 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
6244 igi_offset = 0;
6245 else
6246 igi_offset += noisy_lv * IGI_OFFSET_MUL;
6247
6248 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
6249 dig->fa_rssi_ofst = igi_offset;
6250
6251 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6252 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
6253 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
6254
6255 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6256 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
6257 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
6258 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
6259 noisy_lv, igi_offset);
6260 }
6261
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 lna_idx)6262 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev,
6263 struct rtw89_bb_ctx *bb, u8 lna_idx)
6264 {
6265 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6266
6267 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_lna_init.addr,
6268 dig_regs->p0_lna_init.mask, lna_idx, bb->phy_idx);
6269 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_lna_init.addr,
6270 dig_regs->p1_lna_init.mask, lna_idx, bb->phy_idx);
6271 }
6272
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 tia_idx)6273 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev,
6274 struct rtw89_bb_ctx *bb, u8 tia_idx)
6275 {
6276 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6277
6278 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_tia_init.addr,
6279 dig_regs->p0_tia_init.mask, tia_idx, bb->phy_idx);
6280 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_tia_init.addr,
6281 dig_regs->p1_tia_init.mask, tia_idx, bb->phy_idx);
6282 }
6283
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rxb_idx)6284 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev,
6285 struct rtw89_bb_ctx *bb, u8 rxb_idx)
6286 {
6287 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6288
6289 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_rxb_init.addr,
6290 dig_regs->p0_rxb_init.mask, rxb_idx, bb->phy_idx);
6291 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_rxb_init.addr,
6292 dig_regs->p1_rxb_init.mask, rxb_idx, bb->phy_idx);
6293 }
6294
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_agc_gaincode_set set)6295 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
6296 struct rtw89_bb_ctx *bb,
6297 const struct rtw89_agc_gaincode_set set)
6298 {
6299 if (!rtwdev->hal.support_igi)
6300 return;
6301
6302 rtw89_phy_dig_set_lna_idx(rtwdev, bb, set.lna_idx);
6303 rtw89_phy_dig_set_tia_idx(rtwdev, bb, set.tia_idx);
6304 rtw89_phy_dig_set_rxb_idx(rtwdev, bb, set.rxb_idx);
6305
6306 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
6307 set.lna_idx, set.tia_idx, set.rxb_idx);
6308 }
6309
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool enable)6310 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
6311 struct rtw89_bb_ctx *bb,
6312 bool enable)
6313 {
6314 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6315
6316 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
6317 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx);
6318 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
6319 dig_regs->p0_s20_pagcugc_en.mask, enable, bb->phy_idx);
6320 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
6321 dig_regs->p1_p20_pagcugc_en.mask, enable, bb->phy_idx);
6322 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
6323 dig_regs->p1_s20_pagcugc_en.mask, enable, bb->phy_idx);
6324
6325 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
6326 }
6327
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6328 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev,
6329 struct rtw89_bb_ctx *bb)
6330 {
6331 struct rtw89_dig_info *dig = &bb->dig;
6332
6333 if (!rtwdev->hal.support_igi)
6334 return;
6335
6336 if (dig->force_gaincode_idx_en) {
6337 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
6338 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6339 "Force gaincode index enabled.\n");
6340 } else {
6341 rtw89_phy_dig_gaincode_by_rssi(rtwdev, bb, dig->igi_fa_rssi,
6342 &dig->cur_gaincode);
6343 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->cur_gaincode);
6344 }
6345 }
6346
rtw89_phy_dig_cal_under_region(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_chan * chan)6347 static u8 rtw89_phy_dig_cal_under_region(struct rtw89_dev *rtwdev,
6348 struct rtw89_bb_ctx *bb,
6349 const struct rtw89_chan *chan)
6350 {
6351 enum rtw89_bandwidth cbw = chan->band_width;
6352 struct rtw89_dig_info *dig = &bb->dig;
6353 u8 under_region = dig->pd_low_th_ofst;
6354
6355 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
6356 under_region += PD_TH_SB_FLTR_CMP_VAL;
6357
6358 switch (cbw) {
6359 case RTW89_CHANNEL_WIDTH_40:
6360 under_region += PD_TH_BW40_CMP_VAL;
6361 break;
6362 case RTW89_CHANNEL_WIDTH_80:
6363 under_region += PD_TH_BW80_CMP_VAL;
6364 break;
6365 case RTW89_CHANNEL_WIDTH_160:
6366 under_region += PD_TH_BW160_CMP_VAL;
6367 break;
6368 case RTW89_CHANNEL_WIDTH_20:
6369 fallthrough;
6370 default:
6371 under_region += PD_TH_BW20_CMP_VAL;
6372 break;
6373 }
6374
6375 return under_region;
6376 }
6377
__rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable,const struct rtw89_chan * chan)6378 static u32 __rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
6379 struct rtw89_bb_ctx *bb,
6380 u8 rssi, bool enable,
6381 const struct rtw89_chan *chan)
6382 {
6383 struct rtw89_dig_info *dig = &bb->dig;
6384 u8 ofdm_cca_th, under_region;
6385 u8 final_rssi;
6386 u32 pd_val;
6387
6388 under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
6389 dig->dyn_pd_th_max = dig->igi_rssi;
6390
6391 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6392 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
6393 PD_TH_MAX_RSSI + under_region);
6394
6395 if (enable) {
6396 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
6397 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6398 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
6399 final_rssi, ofdm_cca_th, under_region, pd_val);
6400 } else {
6401 pd_val = 0;
6402 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6403 "Dynamic PD th disabled, Set PD_low_bd=0\n");
6404 }
6405
6406 return pd_val;
6407 }
6408
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable)6409 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
6410 struct rtw89_bb_ctx *bb,
6411 u8 rssi, bool enable)
6412 {
6413 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
6414 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6415 struct rtw89_dig_info *dig = &bb->dig;
6416 u8 final_rssi, under_region = dig->pd_low_th_ofst;
6417 s8 cck_cca_th;
6418 u32 pd_val;
6419
6420 pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi, enable, chan);
6421 dig->bak_dig = pd_val;
6422
6423 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6424 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
6425 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6426 dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx);
6427
6428 if (!rtwdev->hal.support_cckpd)
6429 return;
6430
6431 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6432 under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
6433 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
6434 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
6435
6436 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6437 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
6438 final_rssi, cck_cca_th, under_region, pd_val);
6439
6440 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg,
6441 dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx);
6442 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
6443 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val, bb->phy_idx);
6444 }
6445
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6446 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6447 {
6448 struct rtw89_dig_info *dig = &bb->dig;
6449
6450 dig->bypass_dig = false;
6451 rtw89_phy_dig_para_reset(rtwdev, bb);
6452 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
6453 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi_nolink, false);
6454 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
6455 rtw89_phy_dig_update_para(rtwdev, bb);
6456 }
6457
6458 #define IGI_RSSI_MIN 10
6459 #define ABS_IGI_MIN 0xc
6460 static
rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6461 void rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6462 {
6463 struct rtw89_dig_info *dig = &bb->dig;
6464 u8 igi_min;
6465
6466 rtw89_phy_dig_igi_offset_by_env(rtwdev, bb);
6467
6468 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
6469 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
6470 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
6471
6472 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
6473 dig->igi_fa_rssi += dig->fa_rssi_ofst;
6474 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
6475 dig->dyn_igi_max);
6476 } else {
6477 dig->igi_fa_rssi = dig->dyn_igi_max;
6478 }
6479 }
6480
6481 struct rtw89_phy_iter_mcc_dig {
6482 struct rtw89_vif_link *rtwvif_link;
6483 bool has_sta;
6484 u8 rssi_min;
6485 };
6486
rtw89_phy_set_mcc_dig(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_bb_ctx * bb,u8 rssi_min,u8 mcc_role_idx,bool is_linked)6487 static void rtw89_phy_set_mcc_dig(struct rtw89_dev *rtwdev,
6488 struct rtw89_vif_link *rtwvif_link,
6489 struct rtw89_bb_ctx *bb,
6490 u8 rssi_min, u8 mcc_role_idx,
6491 bool is_linked)
6492 {
6493 struct rtw89_dig_info *dig = &bb->dig;
6494 const struct rtw89_chan *chan;
6495 u8 pd_val;
6496
6497 if (is_linked) {
6498 dig->igi_rssi = rssi_min >> 1;
6499 dig->igi_fa_rssi = dig->igi_rssi;
6500 } else {
6501 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
6502 dig->igi_rssi = rssi_nolink;
6503 dig->igi_fa_rssi = dig->igi_rssi;
6504 }
6505
6506 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
6507 rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
6508 pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi,
6509 is_linked, chan);
6510 rtw89_fw_h2c_mcc_dig(rtwdev, rtwvif_link->chanctx_idx,
6511 mcc_role_idx, pd_val, true);
6512
6513 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6514 "MCC chanctx_idx %d chan %d rssi %d pd_val %d",
6515 rtwvif_link->chanctx_idx, chan->primary_channel,
6516 dig->igi_rssi, pd_val);
6517 }
6518
rtw89_phy_set_mcc_dig_iter(void * data,struct ieee80211_sta * sta)6519 static void rtw89_phy_set_mcc_dig_iter(void *data, struct ieee80211_sta *sta)
6520 {
6521 struct rtw89_phy_iter_mcc_dig *mcc_dig = (struct rtw89_phy_iter_mcc_dig *)data;
6522 unsigned int link_id = mcc_dig->rtwvif_link->link_id;
6523 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
6524 struct rtw89_sta_link *rtwsta_link;
6525
6526 if (rtwsta->rtwvif != mcc_dig->rtwvif_link->rtwvif)
6527 return;
6528
6529 rtwsta_link = rtwsta->links[link_id];
6530 if (!rtwsta_link)
6531 return;
6532
6533 mcc_dig->has_sta = true;
6534 if (ewma_rssi_read(&rtwsta_link->avg_rssi) < mcc_dig->rssi_min)
6535 mcc_dig->rssi_min = ewma_rssi_read(&rtwsta_link->avg_rssi);
6536 }
6537
rtw89_phy_dig_mcc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6538 static void rtw89_phy_dig_mcc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6539 {
6540 struct rtw89_phy_iter_mcc_dig mcc_dig;
6541 struct rtw89_vif_link *rtwvif_link;
6542 struct rtw89_mcc_links_info info;
6543 int i;
6544
6545 rtw89_mcc_get_links(rtwdev, &info);
6546 for (i = 0; i < ARRAY_SIZE(info.links); i++) {
6547 rtwvif_link = info.links[i];
6548 if (!rtwvif_link)
6549 continue;
6550
6551 memset(&mcc_dig, 0, sizeof(mcc_dig));
6552 mcc_dig.rtwvif_link = rtwvif_link;
6553 mcc_dig.has_sta = false;
6554 mcc_dig.rssi_min = U8_MAX;
6555 ieee80211_iterate_stations_atomic(rtwdev->hw,
6556 rtw89_phy_set_mcc_dig_iter,
6557 &mcc_dig);
6558
6559 rtw89_phy_set_mcc_dig(rtwdev, rtwvif_link, bb,
6560 mcc_dig.rssi_min, i, mcc_dig.has_sta);
6561 }
6562 }
6563
rtw89_phy_dig_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool pause_dig,bool restore)6564 static void rtw89_phy_dig_ctrl(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb,
6565 bool pause_dig, bool restore)
6566 {
6567 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6568 struct rtw89_dig_info *dig = &bb->dig;
6569 bool en_dig;
6570 u32 pd_val;
6571
6572 if (dig->pause_dig == pause_dig)
6573 return;
6574
6575 if (pause_dig) {
6576 en_dig = false;
6577 pd_val = 0;
6578 } else {
6579 en_dig = rtwdev->total_sta_assoc > 0;
6580 pd_val = restore ? dig->bak_dig : 0;
6581 }
6582
6583 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s <%s> PD_low=%d", __func__,
6584 pause_dig ? "suspend" : "resume", pd_val);
6585
6586 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6587 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
6588 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6589 dig_regs->pd_spatial_reuse_en, en_dig, bb->phy_idx);
6590
6591 dig->pause_dig = pause_dig;
6592 }
6593
rtw89_phy_dig_suspend(struct rtw89_dev * rtwdev)6594 void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev)
6595 {
6596 struct rtw89_bb_ctx *bb;
6597
6598 rtw89_for_each_active_bb(rtwdev, bb)
6599 rtw89_phy_dig_ctrl(rtwdev, bb, true, false);
6600 }
6601
rtw89_phy_dig_resume(struct rtw89_dev * rtwdev,bool restore)6602 void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore)
6603 {
6604 struct rtw89_bb_ctx *bb;
6605
6606 rtw89_for_each_active_bb(rtwdev, bb)
6607 rtw89_phy_dig_ctrl(rtwdev, bb, false, restore);
6608 }
6609
__rtw89_phy_dig(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6610 static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6611 {
6612 struct rtw89_dig_info *dig = &bb->dig;
6613 bool is_linked = rtwdev->total_sta_assoc > 0;
6614 enum rtw89_entity_mode mode;
6615
6616 if (unlikely(dig->bypass_dig)) {
6617 dig->bypass_dig = false;
6618 return;
6619 }
6620
6621 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig track\n", bb->phy_idx);
6622
6623 rtw89_phy_dig_update_rssi_info(rtwdev, bb);
6624
6625 mode = rtw89_get_entity_mode(rtwdev);
6626 if (mode == RTW89_ENTITY_MODE_MCC) {
6627 rtw89_phy_dig_mcc(rtwdev, bb);
6628 return;
6629 }
6630
6631 if (unlikely(dig->pause_dig))
6632 return;
6633
6634 if (!dig->is_linked_pre && is_linked) {
6635 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
6636 rtw89_phy_dig_update_para(rtwdev, bb);
6637 dig->igi_fa_rssi = dig->igi_rssi;
6638 } else if (dig->is_linked_pre && !is_linked) {
6639 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
6640 rtw89_phy_dig_update_para(rtwdev, bb);
6641 dig->igi_fa_rssi = dig->igi_rssi;
6642 }
6643 dig->is_linked_pre = is_linked;
6644
6645 rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
6646
6647 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6648 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
6649 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
6650 dig->igi_fa_rssi);
6651
6652 rtw89_phy_dig_config_igi(rtwdev, bb);
6653
6654 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi, dig->dyn_pd_th_en);
6655
6656 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
6657 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, true);
6658 else
6659 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
6660 }
6661
rtw89_phy_dig(struct rtw89_dev * rtwdev)6662 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
6663 {
6664 struct rtw89_bb_ctx *bb;
6665
6666 rtw89_for_each_active_bb(rtwdev, bb)
6667 __rtw89_phy_dig(rtwdev, bb);
6668 }
6669
__rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)6670 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev,
6671 struct rtw89_sta_link *rtwsta_link)
6672 {
6673 struct rtw89_hal *hal = &rtwdev->hal;
6674 u8 rssi_a, rssi_b;
6675 u32 candidate;
6676
6677 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
6678 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
6679
6680 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
6681 candidate = RF_A;
6682 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
6683 candidate = RF_B;
6684 else
6685 return;
6686
6687 if (hal->antenna_tx == candidate)
6688 return;
6689
6690 hal->antenna_tx = candidate;
6691 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link);
6692
6693 if (hal->antenna_tx == RF_A) {
6694 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
6695 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
6696 } else if (hal->antenna_tx == RF_B) {
6697 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
6698 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
6699 }
6700 }
6701
rtw89_phy_tx_path_div_sta_iter(void * data,struct ieee80211_sta * sta)6702 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
6703 {
6704 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
6705 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6706 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6707 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6708 struct rtw89_vif_link *rtwvif_link;
6709 struct rtw89_sta_link *rtwsta_link;
6710 unsigned int link_id;
6711 bool *done = data;
6712
6713 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n"))
6714 return;
6715
6716 if (sta->tdls)
6717 return;
6718
6719 if (*done)
6720 return;
6721
6722 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
6723 rtwvif_link = rtwsta_link->rtwvif_link;
6724 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
6725 continue;
6726
6727 *done = true;
6728 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link);
6729 return;
6730 }
6731 }
6732
rtw89_phy_tx_path_div_track(struct rtw89_dev * rtwdev)6733 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
6734 {
6735 struct rtw89_hal *hal = &rtwdev->hal;
6736 bool done = false;
6737
6738 if (!hal->tx_path_diversity)
6739 return;
6740
6741 ieee80211_iterate_stations_atomic(rtwdev->hw,
6742 rtw89_phy_tx_path_div_sta_iter,
6743 &done);
6744 }
6745
6746 #define ANTDIV_MAIN 0
6747 #define ANTDIV_AUX 1
6748
rtw89_phy_antdiv_set_ant(struct rtw89_dev * rtwdev)6749 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
6750 {
6751 struct rtw89_hal *hal = &rtwdev->hal;
6752 u8 default_ant, optional_ant;
6753
6754 if (!hal->ant_diversity || hal->antenna_tx == 0)
6755 return;
6756
6757 if (hal->antenna_tx == RF_B) {
6758 default_ant = ANTDIV_AUX;
6759 optional_ant = ANTDIV_MAIN;
6760 } else {
6761 default_ant = ANTDIV_MAIN;
6762 optional_ant = ANTDIV_AUX;
6763 }
6764
6765 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
6766 default_ant, RTW89_PHY_0);
6767 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
6768 default_ant, RTW89_PHY_0);
6769 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
6770 optional_ant, RTW89_PHY_0);
6771 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
6772 default_ant, RTW89_PHY_0);
6773 }
6774
rtw89_phy_swap_hal_antenna(struct rtw89_dev * rtwdev)6775 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
6776 {
6777 struct rtw89_hal *hal = &rtwdev->hal;
6778
6779 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
6780 hal->antenna_tx = hal->antenna_rx;
6781 }
6782
rtw89_phy_antdiv_decision_state(struct rtw89_dev * rtwdev)6783 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
6784 {
6785 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6786 struct rtw89_hal *hal = &rtwdev->hal;
6787 bool no_change = false;
6788 u8 main_rssi, aux_rssi;
6789 u8 main_evm, aux_evm;
6790 u32 candidate;
6791
6792 antdiv->get_stats = false;
6793 antdiv->training_count = 0;
6794
6795 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
6796 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
6797 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
6798 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
6799
6800 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
6801 candidate = RF_A;
6802 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
6803 candidate = RF_B;
6804 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
6805 candidate = RF_A;
6806 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
6807 candidate = RF_B;
6808 else
6809 no_change = true;
6810
6811 if (no_change) {
6812 /* swap back from training antenna to original */
6813 rtw89_phy_swap_hal_antenna(rtwdev);
6814 return;
6815 }
6816
6817 hal->antenna_tx = candidate;
6818 hal->antenna_rx = candidate;
6819 }
6820
rtw89_phy_antdiv_training_state(struct rtw89_dev * rtwdev)6821 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
6822 {
6823 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6824 u64 state_period;
6825
6826 if (antdiv->training_count % 2 == 0) {
6827 if (antdiv->training_count == 0)
6828 rtw89_phy_antdiv_sts_reset(rtwdev);
6829
6830 antdiv->get_stats = true;
6831 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
6832 } else {
6833 antdiv->get_stats = false;
6834 state_period = msecs_to_jiffies(ANTDIV_DELAY);
6835
6836 rtw89_phy_swap_hal_antenna(rtwdev);
6837 rtw89_phy_antdiv_set_ant(rtwdev);
6838 }
6839
6840 antdiv->training_count++;
6841 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work,
6842 state_period);
6843 }
6844
rtw89_phy_antdiv_work(struct wiphy * wiphy,struct wiphy_work * work)6845 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work)
6846 {
6847 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
6848 antdiv_work.work);
6849 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6850
6851 lockdep_assert_wiphy(wiphy);
6852
6853 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
6854 rtw89_phy_antdiv_training_state(rtwdev);
6855 } else {
6856 rtw89_phy_antdiv_decision_state(rtwdev);
6857 rtw89_phy_antdiv_set_ant(rtwdev);
6858 }
6859 }
6860
rtw89_phy_antdiv_track(struct rtw89_dev * rtwdev)6861 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
6862 {
6863 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6864 struct rtw89_hal *hal = &rtwdev->hal;
6865 u8 rssi, rssi_pre;
6866
6867 if (!hal->ant_diversity || hal->ant_diversity_fixed)
6868 return;
6869
6870 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
6871 rssi_pre = antdiv->rssi_pre;
6872 antdiv->rssi_pre = rssi;
6873 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
6874
6875 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
6876 return;
6877
6878 antdiv->training_count = 0;
6879 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 0);
6880 }
6881
__rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6882 static void __rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev,
6883 struct rtw89_bb_ctx *bb)
6884 {
6885 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6886 "BB-%d env_monitor init\n", bb->phy_idx);
6887
6888 rtw89_phy_ccx_top_setting_init(rtwdev, bb);
6889 rtw89_phy_ifs_clm_setting_init(rtwdev, bb);
6890 }
6891
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)6892 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
6893 {
6894 struct rtw89_bb_ctx *bb;
6895
6896 rtw89_for_each_capab_bb(rtwdev, bb)
6897 __rtw89_phy_env_monitor_init(rtwdev, bb);
6898 }
6899
__rtw89_phy_edcca_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6900 static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev,
6901 struct rtw89_bb_ctx *bb)
6902 {
6903 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6904 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
6905
6906 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca init\n", bb->phy_idx);
6907
6908 memset(edcca_bak, 0, sizeof(*edcca_bak));
6909
6910 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
6911 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
6912 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
6913 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
6914 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
6915 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
6916 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
6917 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
6918 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
6919 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
6920 }
6921
6922 rtw89_phy_write32_idx(rtwdev, edcca_regs->tx_collision_t2r_st,
6923 edcca_regs->tx_collision_t2r_st_mask, 0x29, bb->phy_idx);
6924 }
6925
rtw89_phy_edcca_init(struct rtw89_dev * rtwdev)6926 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
6927 {
6928 struct rtw89_bb_ctx *bb;
6929
6930 rtw89_for_each_capab_bb(rtwdev, bb)
6931 __rtw89_phy_edcca_init(rtwdev, bb);
6932 }
6933
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)6934 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
6935 {
6936 rtw89_phy_stat_init(rtwdev);
6937
6938 rtw89_chip_bb_sethw(rtwdev);
6939
6940 rtw89_phy_env_monitor_init(rtwdev);
6941 rtw89_physts_parsing_init(rtwdev);
6942 rtw89_phy_dig_init(rtwdev);
6943 rtw89_phy_cfo_init(rtwdev);
6944 rtw89_phy_bb_wrap_init(rtwdev);
6945 rtw89_phy_edcca_init(rtwdev);
6946 rtw89_phy_ch_info_init(rtwdev);
6947 rtw89_phy_ul_tb_info_init(rtwdev);
6948 rtw89_phy_antdiv_init(rtwdev);
6949 rtw89_chip_rfe_gpio(rtwdev);
6950 rtw89_phy_antdiv_set_ant(rtwdev);
6951
6952 rtw89_chip_rfk_hw_init(rtwdev);
6953 rtw89_phy_init_rf_nctl(rtwdev);
6954 rtw89_chip_rfk_init(rtwdev);
6955 rtw89_chip_set_txpwr_ctrl(rtwdev);
6956 rtw89_chip_power_trim(rtwdev);
6957 rtw89_chip_cfg_txrx_path(rtwdev);
6958 }
6959
rtw89_phy_dm_reinit(struct rtw89_dev * rtwdev)6960 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev)
6961 {
6962 rtw89_phy_env_monitor_init(rtwdev);
6963 rtw89_physts_parsing_init(rtwdev);
6964 }
6965
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6966 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
6967 struct rtw89_vif_link *rtwvif_link)
6968 {
6969 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6970 const struct rtw89_chip_info *chip = rtwdev->chip;
6971 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
6972 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
6973 struct ieee80211_bss_conf *bss_conf;
6974 u8 bss_color;
6975
6976 rcu_read_lock();
6977
6978 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6979 if (!bss_conf->he_support || !vif->cfg.assoc) {
6980 rcu_read_unlock();
6981 return;
6982 }
6983
6984 bss_color = bss_conf->he_bss_color.color;
6985
6986 rcu_read_unlock();
6987
6988 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
6989 phy_idx);
6990 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
6991 bss_color, phy_idx);
6992 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
6993 vif->cfg.aid, phy_idx);
6994 }
6995
rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc * desc)6996 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
6997 {
6998 return desc->ch != 0;
6999 }
7000
rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc * desc,const struct rtw89_chan * chan)7001 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
7002 const struct rtw89_chan *chan)
7003 {
7004 if (!rfk_chan_validate_desc(desc))
7005 return false;
7006
7007 if (desc->ch != chan->channel)
7008 return false;
7009
7010 if (desc->has_band && desc->band != chan->band_type)
7011 return false;
7012
7013 if (desc->has_bw && desc->bw != chan->band_width)
7014 return false;
7015
7016 return true;
7017 }
7018
7019 struct rfk_chan_iter_data {
7020 const struct rtw89_rfk_chan_desc desc;
7021 unsigned int found;
7022 };
7023
rfk_chan_iter_search(const struct rtw89_chan * chan,void * data)7024 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
7025 {
7026 struct rfk_chan_iter_data *iter_data = data;
7027
7028 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
7029 iter_data->found++;
7030
7031 return 0;
7032 }
7033
rtw89_rfk_chan_lookup(struct rtw89_dev * rtwdev,const struct rtw89_rfk_chan_desc * desc,u8 desc_nr,const struct rtw89_chan * target_chan)7034 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
7035 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
7036 const struct rtw89_chan *target_chan)
7037 {
7038 int sel = -1;
7039 u8 i;
7040
7041 for (i = 0; i < desc_nr; i++) {
7042 struct rfk_chan_iter_data iter_data = {
7043 .desc = desc[i],
7044 };
7045
7046 if (rfk_chan_is_equivalent(&desc[i], target_chan))
7047 return i;
7048
7049 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
7050 if (!iter_data.found && sel == -1)
7051 sel = i;
7052 }
7053
7054 if (sel == -1) {
7055 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7056 "no idle rfk entry; force replace the first\n");
7057 sel = 0;
7058 }
7059
7060 return sel;
7061 }
7062 EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
7063
7064 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7065 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7066 {
7067 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
7068 }
7069
7070 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7071 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7072 {
7073 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
7074 }
7075
7076 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7077 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7078 {
7079 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
7080 }
7081
7082 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7083 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7084 {
7085 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
7086 }
7087
7088 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7089 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7090 {
7091 udelay(def->data);
7092 }
7093
7094 static void
7095 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
7096 [RTW89_RFK_F_WRF] = _rfk_write_rf,
7097 [RTW89_RFK_F_WM] = _rfk_write32_mask,
7098 [RTW89_RFK_F_WS] = _rfk_write32_set,
7099 [RTW89_RFK_F_WC] = _rfk_write32_clr,
7100 [RTW89_RFK_F_DELAY] = _rfk_delay,
7101 };
7102
7103 #if defined(__linux__)
7104 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
7105 #elif defined(__FreeBSD__)
7106 rtw89_static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
7107 #endif
7108
7109 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)7110 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
7111 {
7112 const struct rtw89_reg5_def *p = tbl->defs;
7113 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
7114
7115 for (; p < end; p++)
7116 _rfk_handler[p->flag](rtwdev, p);
7117 }
7118 EXPORT_SYMBOL(rtw89_rfk_parser);
7119
7120 #define RTW89_TSSI_FAST_MODE_NUM 4
7121
7122 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
7123 {0xD934, 0xff0000},
7124 {0xD934, 0xff000000},
7125 {0xD938, 0xff},
7126 {0xD934, 0xff00},
7127 };
7128
7129 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
7130 {0xD930, 0xff0000},
7131 {0xD930, 0xff000000},
7132 {0xD934, 0xff},
7133 {0xD930, 0xff00},
7134 };
7135
7136 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)7137 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
7138 enum rtw89_mac_idx mac_idx,
7139 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
7140 u32 val)
7141 {
7142 const struct rtw89_reg_def *regs;
7143 u32 reg;
7144 int i;
7145
7146 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
7147 regs = rtw89_tssi_fastmode_regs_flat;
7148 else
7149 regs = rtw89_tssi_fastmode_regs_level;
7150
7151 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
7152 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
7153 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
7154 }
7155 }
7156
7157 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
7158 {0xD91C, 0xff000000},
7159 {0xD920, 0xff},
7160 {0xD920, 0xff00},
7161 {0xD920, 0xff0000},
7162 {0xD920, 0xff000000},
7163 {0xD924, 0xff},
7164 {0xD924, 0xff00},
7165 {0xD914, 0xff000000},
7166 {0xD918, 0xff},
7167 {0xD918, 0xff00},
7168 {0xD918, 0xff0000},
7169 {0xD918, 0xff000000},
7170 {0xD91C, 0xff},
7171 {0xD91C, 0xff00},
7172 {0xD91C, 0xff0000},
7173 };
7174
7175 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
7176 {0xD910, 0xff},
7177 {0xD910, 0xff00},
7178 {0xD910, 0xff0000},
7179 {0xD910, 0xff000000},
7180 {0xD914, 0xff},
7181 {0xD914, 0xff00},
7182 {0xD914, 0xff0000},
7183 {0xD908, 0xff},
7184 {0xD908, 0xff00},
7185 {0xD908, 0xff0000},
7186 {0xD908, 0xff000000},
7187 {0xD90C, 0xff},
7188 {0xD90C, 0xff00},
7189 {0xD90C, 0xff0000},
7190 {0xD90C, 0xff000000},
7191 };
7192
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)7193 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
7194 enum rtw89_mac_idx mac_idx,
7195 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
7196 {
7197 const struct rtw89_chip_info *chip = rtwdev->chip;
7198 const struct rtw89_reg_def *regs;
7199 const u32 *data;
7200 u32 reg;
7201 int i;
7202
7203 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
7204 return;
7205
7206 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
7207 regs = rtw89_tssi_bandedge_regs_flat;
7208 else
7209 regs = rtw89_tssi_bandedge_regs_level;
7210
7211 data = chip->tssi_dbw_table->data[bandedge_cfg];
7212
7213 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
7214 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
7215 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
7216 }
7217
7218 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
7219 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
7220
7221 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
7222 data[RTW89_TSSI_SBW20]);
7223 }
7224 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
7225
7226 static
7227 const u8 rtw89_ch_base_table[16] = {1, 0xff,
7228 36, 100, 132, 149, 0xff,
7229 1, 33, 65, 97, 129, 161, 193, 225, 0xff};
7230 #define RTW89_CH_BASE_IDX_2G 0
7231 #define RTW89_CH_BASE_IDX_5G_FIRST 2
7232 #define RTW89_CH_BASE_IDX_5G_LAST 5
7233 #define RTW89_CH_BASE_IDX_6G_FIRST 7
7234 #define RTW89_CH_BASE_IDX_6G_LAST 14
7235
7236 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)
7237 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0)
7238
rtw89_encode_chan_idx(struct rtw89_dev * rtwdev,u8 central_ch,u8 band)7239 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
7240 {
7241 u8 chan_idx;
7242 u8 last, first;
7243 u8 idx;
7244
7245 switch (band) {
7246 case RTW89_BAND_2G:
7247 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) |
7248 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch);
7249 return chan_idx;
7250 case RTW89_BAND_5G:
7251 first = RTW89_CH_BASE_IDX_5G_FIRST;
7252 last = RTW89_CH_BASE_IDX_5G_LAST;
7253 break;
7254 case RTW89_BAND_6G:
7255 first = RTW89_CH_BASE_IDX_6G_FIRST;
7256 last = RTW89_CH_BASE_IDX_6G_LAST;
7257 break;
7258 default:
7259 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
7260 return 0;
7261 }
7262
7263 for (idx = last; idx >= first; idx--)
7264 if (central_ch >= rtw89_ch_base_table[idx])
7265 break;
7266
7267 if (idx < first) {
7268 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
7269 return 0;
7270 }
7271
7272 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) |
7273 FIELD_PREP(RTW89_CH_OFFSET_MASK,
7274 (central_ch - rtw89_ch_base_table[idx]) >> 1);
7275 return chan_idx;
7276 }
7277 EXPORT_SYMBOL(rtw89_encode_chan_idx);
7278
rtw89_decode_chan_idx(struct rtw89_dev * rtwdev,u8 chan_idx,u8 * ch,enum nl80211_band * band)7279 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
7280 u8 *ch, enum nl80211_band *band)
7281 {
7282 u8 idx, offset;
7283
7284 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx);
7285 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx);
7286
7287 if (idx == RTW89_CH_BASE_IDX_2G) {
7288 *band = NL80211_BAND_2GHZ;
7289 *ch = offset;
7290 return;
7291 }
7292
7293 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
7294 *ch = rtw89_ch_base_table[idx] + (offset << 1);
7295 }
7296 EXPORT_SYMBOL(rtw89_decode_chan_idx);
7297
rtw89_phy_config_edcca(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool scan)7298 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
7299 struct rtw89_bb_ctx *bb, bool scan)
7300 {
7301 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7302 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7303
7304 if (scan) {
7305 edcca_bak->a =
7306 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
7307 edcca_regs->edcca_mask, bb->phy_idx);
7308 edcca_bak->p =
7309 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
7310 edcca_regs->edcca_p_mask, bb->phy_idx);
7311 edcca_bak->ppdu =
7312 rtw89_phy_read32_idx(rtwdev, edcca_regs->ppdu_level,
7313 edcca_regs->ppdu_mask, bb->phy_idx);
7314
7315 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7316 edcca_regs->edcca_mask, EDCCA_MAX, bb->phy_idx);
7317 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7318 edcca_regs->edcca_p_mask, EDCCA_MAX, bb->phy_idx);
7319 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7320 edcca_regs->ppdu_mask, EDCCA_MAX, bb->phy_idx);
7321 } else {
7322 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7323 edcca_regs->edcca_mask,
7324 edcca_bak->a, bb->phy_idx);
7325 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7326 edcca_regs->edcca_p_mask,
7327 edcca_bak->p, bb->phy_idx);
7328 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7329 edcca_regs->ppdu_mask,
7330 edcca_bak->ppdu, bb->phy_idx);
7331 }
7332 }
7333
rtw89_phy_edcca_log(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7334 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7335 {
7336 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7337 const struct rtw89_edcca_p_regs *edcca_p_regs;
7338 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
7339 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
7340 u8 path, per20_bitmap = 0;
7341 u8 pwdb[8];
7342 u32 tmp;
7343
7344 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
7345 return;
7346
7347 if (bb->phy_idx == RTW89_PHY_1)
7348 edcca_p_regs = &edcca_regs->p[RTW89_PHY_1];
7349 else
7350 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0];
7351
7352 if (rtwdev->chip->chip_id == RTL8922A)
7353 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7354 edcca_regs->rpt_sel_be_mask, 0);
7355
7356 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7357 edcca_p_regs->rpt_sel_mask, 0);
7358 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7359 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
7360 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
7361 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
7362 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20);
7363 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20);
7364 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB);
7365 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1);
7366 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
7367 pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
7368
7369 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7370 edcca_p_regs->rpt_sel_mask, 5);
7371 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7372 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
7373 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
7374
7375 if (rtwdev->chip->chip_id == RTL8922A) {
7376 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7377 edcca_regs->rpt_sel_be_mask, 4);
7378 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7379 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
7380 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
7381 pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
7382 pwdb[3] = u32_get_bits(tmp, MASKBYTE0);
7383 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a,
7384 MASKBYTE0);
7385
7386 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7387 edcca_regs->rpt_sel_be_mask, 5);
7388 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7389 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
7390 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
7391 pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
7392 pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
7393 } else {
7394 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7395 edcca_p_regs->rpt_sel_mask, 0);
7396 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7397 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
7398 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
7399
7400 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7401 edcca_p_regs->rpt_sel_mask, 5);
7402 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7403 pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
7404 pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
7405
7406 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7407 edcca_p_regs->rpt_sel_mask, 2);
7408 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7409 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
7410 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
7411
7412 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7413 edcca_p_regs->rpt_sel_mask, 3);
7414 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7415 pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
7416 pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
7417 }
7418
7419 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7420 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap);
7421
7422 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7423 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
7424 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5],
7425 pwdb[6], pwdb[7]);
7426
7427 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7428 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n",
7429 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80);
7430
7431 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7432 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n",
7433 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80);
7434 }
7435
rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7436 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev,
7437 struct rtw89_bb_ctx *bb)
7438 {
7439 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
7440 bool is_linked = rtwdev->total_sta_assoc > 0;
7441 u8 rssi_min = ch_info->rssi_min >> 1;
7442 u8 edcca_thre;
7443
7444 if (!is_linked) {
7445 edcca_thre = EDCCA_MAX;
7446 } else {
7447 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
7448 EDCCA_TH_REF;
7449 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB);
7450 }
7451
7452 return edcca_thre;
7453 }
7454
rtw89_phy_edcca_thre_calc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7455 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7456 {
7457 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7458 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7459 u8 th;
7460
7461 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev, bb);
7462 if (th == edcca_bak->th_old)
7463 return;
7464
7465 edcca_bak->th_old = th;
7466
7467 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7468 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th);
7469
7470 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7471 edcca_regs->edcca_mask, th, bb->phy_idx);
7472 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7473 edcca_regs->edcca_p_mask, th, bb->phy_idx);
7474 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7475 edcca_regs->ppdu_mask, th, bb->phy_idx);
7476 }
7477
7478 static
__rtw89_phy_edcca_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7479 void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7480 {
7481 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca track\n", bb->phy_idx);
7482
7483 rtw89_phy_edcca_thre_calc(rtwdev, bb);
7484 rtw89_phy_edcca_log(rtwdev, bb);
7485 }
7486
rtw89_phy_edcca_track(struct rtw89_dev * rtwdev)7487 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
7488 {
7489 struct rtw89_hal *hal = &rtwdev->hal;
7490 struct rtw89_bb_ctx *bb;
7491
7492 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
7493 return;
7494
7495 rtw89_for_each_active_bb(rtwdev, bb)
7496 __rtw89_phy_edcca_track(rtwdev, bb);
7497 }
7498
rtw89_phy_get_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7499 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
7500 enum rtw89_phy_idx phy_idx)
7501 {
7502 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7503 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7504 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7505
7506 switch (rtwdev->mlo_dbcc_mode) {
7507 case MLO_1_PLUS_1_1RF:
7508 if (phy_idx == RTW89_PHY_0)
7509 return RF_A;
7510 else
7511 return RF_B;
7512 case MLO_1_PLUS_1_2RF:
7513 if (phy_idx == RTW89_PHY_0)
7514 return RF_A;
7515 else
7516 return RF_D;
7517 case MLO_0_PLUS_2_1RF:
7518 case MLO_2_PLUS_0_1RF:
7519 /* for both PHY 0/1 */
7520 return RF_AB;
7521 case MLO_0_PLUS_2_2RF:
7522 case MLO_2_PLUS_0_2RF:
7523 case MLO_2_PLUS_2_2RF:
7524 default:
7525 if (phy_idx == RTW89_PHY_0)
7526 return RF_AB;
7527 else
7528 return RF_CD;
7529 }
7530 }
7531 EXPORT_SYMBOL(rtw89_phy_get_kpath);
7532
rtw89_phy_get_syn_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7533 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
7534 enum rtw89_phy_idx phy_idx)
7535 {
7536 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7537 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7538 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7539
7540 switch (rtwdev->mlo_dbcc_mode) {
7541 case MLO_1_PLUS_1_1RF:
7542 if (phy_idx == RTW89_PHY_0)
7543 return RF_PATH_A;
7544 else
7545 return RF_PATH_B;
7546 case MLO_1_PLUS_1_2RF:
7547 if (phy_idx == RTW89_PHY_0)
7548 return RF_PATH_A;
7549 else
7550 return RF_PATH_D;
7551 case MLO_0_PLUS_2_1RF:
7552 case MLO_2_PLUS_0_1RF:
7553 if (phy_idx == RTW89_PHY_0)
7554 return RF_PATH_A;
7555 else
7556 return RF_PATH_B;
7557 case MLO_0_PLUS_2_2RF:
7558 case MLO_2_PLUS_0_2RF:
7559 case MLO_2_PLUS_2_2RF:
7560 default:
7561 if (phy_idx == RTW89_PHY_0)
7562 return RF_PATH_A;
7563 else
7564 return RF_PATH_C;
7565 }
7566 }
7567 EXPORT_SYMBOL(rtw89_phy_get_syn_sel);
7568
7569 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
7570 .setting_addr = R_CCX,
7571 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
7572 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
7573 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
7574 .en_mask = B_CCX_EN_MSK,
7575 .ifs_cnt_addr = R_IFS_COUNTER,
7576 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
7577 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
7578 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
7579 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
7580 .ifs_t1_addr = R_IFS_T1,
7581 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
7582 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
7583 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
7584 .ifs_t2_addr = R_IFS_T2,
7585 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
7586 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
7587 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
7588 .ifs_t3_addr = R_IFS_T3,
7589 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
7590 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
7591 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
7592 .ifs_t4_addr = R_IFS_T4,
7593 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
7594 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
7595 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
7596 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
7597 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
7598 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
7599 .ifs_clm_cca_addr = R_IFS_CLM_CCA,
7600 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
7601 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
7602 .ifs_clm_fa_addr = R_IFS_CLM_FA,
7603 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
7604 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
7605 .ifs_his_addr = R_IFS_HIS,
7606 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
7607 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
7608 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
7609 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
7610 .ifs_avg_l_addr = R_IFS_AVG_L,
7611 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
7612 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
7613 .ifs_avg_h_addr = R_IFS_AVG_H,
7614 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
7615 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
7616 .ifs_cca_l_addr = R_IFS_CCA_L,
7617 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
7618 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
7619 .ifs_cca_h_addr = R_IFS_CCA_H,
7620 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
7621 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
7622 .ifs_total_addr = R_IFSCNT,
7623 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
7624 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
7625 };
7626
7627 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
7628 .setting_addr = R_PLCP_HISTOGRAM,
7629 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
7630 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
7631 };
7632
7633 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
7634 .comp = R_DCFO_WEIGHT,
7635 .weighting_mask = B_DCFO_WEIGHT_MSK,
7636 .comp_seg0 = R_DCFO_OPT,
7637 .valid_0_mask = B_DCFO_OPT_EN,
7638 };
7639
7640 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
7641 .cr_base = 0x10000,
7642 .ccx = &rtw89_ccx_regs_ax,
7643 .physts = &rtw89_physts_regs_ax,
7644 .cfo = &rtw89_cfo_regs_ax,
7645 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
7646 .config_bb_gain = rtw89_phy_config_bb_gain_ax,
7647 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
7648 .bb_wrap_init = NULL,
7649 .ch_info_init = NULL,
7650
7651 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
7652 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
7653 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax,
7654 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax,
7655 };
7656 EXPORT_SYMBOL(rtw89_phy_gen_ax);
7657