1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "chan.h"
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15 #include "txrx.h"
16 #include "util.h"
17
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
19 {
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
21
22 return phy->phy0_phy1_offset(rtwdev, addr);
23 }
24
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
26 const struct rtw89_ra_report *report)
27 {
28 u32 bit_rate = report->bit_rate;
29
30 /* lower than ofdm, do not aggregate */
31 if (bit_rate < 550)
32 return 1;
33
34 /* avoid AMSDU for legacy rate */
35 if (report->might_fallback_legacy)
36 return 1;
37
38 /* lower than 20M vht 2ss mcs8, make it small */
39 if (bit_rate < 1800)
40 return 1200;
41
42 /* lower than 40M vht 2ss mcs9, make it medium */
43 if (bit_rate < 4000)
44 return 2600;
45
46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
47 if (bit_rate < 7000)
48 return 3500;
49
50 return rtwdev->chip->max_amsdu_limit;
51 }
52
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
54 {
55 u64 ra_mask = 0;
56 u8 mcs_cap;
57 int i, nss;
58
59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
60 mcs_cap = mcs_map & 0x3;
61 switch (mcs_cap) {
62 case 2:
63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
64 break;
65 case 1:
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
67 break;
68 case 0:
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
70 break;
71 default:
72 break;
73 }
74 }
75
76 return ra_mask;
77 }
78
get_he_ra_mask(struct ieee80211_link_sta * link_sta)79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta)
80 {
81 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
82 u16 mcs_map;
83
84 switch (link_sta->bandwidth) {
85 case IEEE80211_STA_RX_BW_160:
86 if (cap.he_cap_elem.phy_cap_info[0] &
87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
89 else
90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
91 break;
92 default:
93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
94 }
95
96 /* MCS11, MCS9, MCS7 */
97 return get_mcs_ra_mask(mcs_map, 11, 2);
98 }
99
get_eht_mcs_ra_mask(u8 * max_nss,u8 start_mcs,u8 n_nss)100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)
101 {
102 u64 nss_mcs_shift;
103 u64 nss_mcs_val;
104 u64 mask = 0;
105 int i, j;
106 u8 nss;
107
108 for (i = 0; i < n_nss; i++) {
109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);
110 if (!nss)
111 continue;
112
113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);
114
115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)
116 mask |= nss_mcs_val << nss_mcs_shift;
117 }
118
119 return mask;
120 }
121
get_eht_ra_mask(struct rtw89_vif_link * rtwvif_link,struct ieee80211_link_sta * link_sta)122 static u64 get_eht_ra_mask(struct rtw89_vif_link *rtwvif_link,
123 struct ieee80211_link_sta *link_sta)
124 {
125 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
126 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;
127 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
128 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;
129 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
130
131 switch (link_sta->bandwidth) {
132 case IEEE80211_STA_RX_BW_320:
133 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
134 /* MCS 9, 11, 13 */
135 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
136 case IEEE80211_STA_RX_BW_160:
137 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
138 /* MCS 9, 11, 13 */
139 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
140 case IEEE80211_STA_RX_BW_20:
141 if (vif->type == NL80211_IFTYPE_AP &&
142 !(he_phy_cap[0] & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
143 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
144 /* MCS 7, 9, 11, 13 */
145 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
146 }
147 fallthrough;
148 case IEEE80211_STA_RX_BW_80:
149 default:
150 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
151 /* MCS 9, 11, 13 */
152 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
153 }
154 }
155
156 #define RA_FLOOR_TABLE_SIZE 7
157 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)158 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
159 u8 ratr_state)
160 {
161 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
162 u8 rssi_lv = 0;
163 u8 i;
164
165 rssi >>= 1;
166 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
167 if (i >= ratr_state)
168 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
169 if (rssi < rssi_lv_t[i]) {
170 rssi_lv = i;
171 break;
172 }
173 }
174 if (rssi_lv == 0)
175 return 0xffffffffffffffffULL;
176 else if (rssi_lv == 1)
177 return 0xfffffffffffffff0ULL;
178 else if (rssi_lv == 2)
179 return 0xffffffffffffefe0ULL;
180 else if (rssi_lv == 3)
181 return 0xffffffffffffcfc0ULL;
182 else if (rssi_lv == 4)
183 return 0xffffffffffff8f80ULL;
184 else if (rssi_lv >= 5)
185 return 0xffffffffffff0f00ULL;
186
187 return 0xffffffffffffffffULL;
188 }
189
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)190 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
191 {
192 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
193 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
194
195 if (ra_mask == 0)
196 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
197
198 return ra_mask;
199 }
200
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan)201 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev,
202 struct rtw89_sta_link *rtwsta_link,
203 struct ieee80211_link_sta *link_sta,
204 const struct rtw89_chan *chan)
205 {
206 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
207 enum nl80211_band band;
208 u64 cfg_mask;
209
210 if (!rtwsta_link->use_cfg_mask)
211 return -1;
212
213 switch (chan->band_type) {
214 case RTW89_BAND_2G:
215 band = NL80211_BAND_2GHZ;
216 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
217 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
218 break;
219 case RTW89_BAND_5G:
220 band = NL80211_BAND_5GHZ;
221 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
222 RA_MASK_OFDM_RATES);
223 break;
224 case RTW89_BAND_6G:
225 band = NL80211_BAND_6GHZ;
226 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
227 RA_MASK_OFDM_RATES);
228 break;
229 default:
230 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
231 return -1;
232 }
233
234 if (link_sta->eht_cap.has_eht) {
235 cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[0],
236 RA_MASK_EHT_1SS_RATES);
237 cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[1],
238 RA_MASK_EHT_2SS_RATES);
239 } else if (link_sta->he_cap.has_he) {
240 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
241 RA_MASK_HE_1SS_RATES);
242 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
243 RA_MASK_HE_2SS_RATES);
244 } else if (link_sta->vht_cap.vht_supported) {
245 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
246 RA_MASK_VHT_1SS_RATES);
247 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
248 RA_MASK_VHT_2SS_RATES);
249 } else if (link_sta->ht_cap.ht_supported) {
250 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
251 RA_MASK_HT_1SS_RATES);
252 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
253 RA_MASK_HT_2SS_RATES);
254 }
255
256 return cfg_mask;
257 }
258
259 static const u64
260 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
261 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
262 static const u64
263 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
264 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
265 static const u64
266 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
267 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
268 static const u64
269 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,
270 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};
271 static const u64
272 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11,
273 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11};
274
rtw89_phy_ra_gi_ltf(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan,bool * fix_giltf_en,u8 * fix_giltf)275 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
276 struct rtw89_sta_link *rtwsta_link,
277 struct ieee80211_link_sta *link_sta,
278 const struct rtw89_chan *chan,
279 bool *fix_giltf_en, u8 *fix_giltf)
280 {
281 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
282 u8 band = chan->band_type;
283 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
284 u8 he_ltf = mask->control[nl_band].he_ltf;
285 u8 he_gi = mask->control[nl_band].he_gi;
286
287 *fix_giltf_en = true;
288
289 if (rtwdev->chip->chip_id == RTL8852C &&
290 chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
291 rtw89_sta_link_has_su_mu_4xhe08(link_sta))
292 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
293 else
294 *fix_giltf = RTW89_GILTF_2XHE08;
295
296 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he))
297 return;
298
299 if (he_ltf == 2 && he_gi == 2) {
300 *fix_giltf = RTW89_GILTF_LGI_4XHE32;
301 } else if (he_ltf == 2 && he_gi == 0) {
302 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
303 } else if (he_ltf == 1 && he_gi == 1) {
304 *fix_giltf = RTW89_GILTF_2XHE16;
305 } else if (he_ltf == 1 && he_gi == 0) {
306 *fix_giltf = RTW89_GILTF_2XHE08;
307 } else if (he_ltf == 0 && he_gi == 1) {
308 *fix_giltf = RTW89_GILTF_1XHE16;
309 } else if (he_ltf == 0 && he_gi == 0) {
310 *fix_giltf = RTW89_GILTF_1XHE08;
311 }
312 }
313
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,bool p2p,bool csi)314 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
315 struct rtw89_vif_link *rtwvif_link,
316 struct rtw89_sta_link *rtwsta_link,
317 struct ieee80211_link_sta *link_sta,
318 bool p2p, bool csi)
319 {
320 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
321 struct rtw89_ra_info *ra = &rtwsta_link->ra;
322 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
323 rtwvif_link->chanctx_idx);
324 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
325 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
326 u64 ra_mask = 0;
327 u64 ra_mask_bak;
328 u8 mode = 0;
329 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
330 u8 bw_mode = 0;
331 u8 stbc_en = 0;
332 u8 ldpc_en = 0;
333 u8 fix_giltf = 0;
334 u8 i;
335 bool sgi = false;
336 bool fix_giltf_en = false;
337
338 memset(ra, 0, sizeof(*ra));
339 /* Set the ra mask from sta's capability */
340 if (link_sta->eht_cap.has_eht) {
341 mode |= RTW89_RA_MODE_EHT;
342 ra_mask |= get_eht_ra_mask(rtwvif_link, link_sta);
343
344 if (rtwdev->hal.no_mcs_12_13)
345 high_rate_masks = rtw89_ra_mask_eht_mcs0_11;
346 else
347 high_rate_masks = rtw89_ra_mask_eht_rates;
348
349 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
350 chan, &fix_giltf_en, &fix_giltf);
351 } else if (link_sta->he_cap.has_he) {
352 mode |= RTW89_RA_MODE_HE;
353 csi_mode = RTW89_RA_RPT_MODE_HE;
354 ra_mask |= get_he_ra_mask(link_sta);
355 high_rate_masks = rtw89_ra_mask_he_rates;
356 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
357 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
358 stbc_en = 1;
359 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
360 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
361 ldpc_en = 1;
362 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
363 chan, &fix_giltf_en, &fix_giltf);
364 } else if (link_sta->vht_cap.vht_supported) {
365 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
366
367 mode |= RTW89_RA_MODE_VHT;
368 csi_mode = RTW89_RA_RPT_MODE_VHT;
369 /* MCS9 (non-20MHz), MCS8, MCS7 */
370 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
371 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1);
372 else
373 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
374 high_rate_masks = rtw89_ra_mask_vht_rates;
375 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
376 stbc_en = 1;
377 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
378 ldpc_en = 1;
379 } else if (link_sta->ht_cap.ht_supported) {
380 mode |= RTW89_RA_MODE_HT;
381 csi_mode = RTW89_RA_RPT_MODE_HT;
382 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
383 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
384 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
385 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
386 high_rate_masks = rtw89_ra_mask_ht_rates;
387 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
388 stbc_en = 1;
389 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
390 ldpc_en = 1;
391 }
392
393 switch (chan->band_type) {
394 case RTW89_BAND_2G:
395 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
396 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
397 mode |= RTW89_RA_MODE_CCK;
398 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
399 mode |= RTW89_RA_MODE_OFDM;
400 break;
401 case RTW89_BAND_5G:
402 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
403 mode |= RTW89_RA_MODE_OFDM;
404 break;
405 case RTW89_BAND_6G:
406 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
407 mode |= RTW89_RA_MODE_OFDM;
408 break;
409 default:
410 rtw89_err(rtwdev, "Unknown band type\n");
411 break;
412 }
413
414 ra_mask_bak = ra_mask;
415
416 if (mode >= RTW89_RA_MODE_HT) {
417 u64 mask = 0;
418 for (i = 0; i < rtwdev->hal.tx_nss; i++)
419 mask |= high_rate_masks[i];
420 if (mode & RTW89_RA_MODE_OFDM)
421 mask |= RA_MASK_SUBOFDM_RATES;
422 if (mode & RTW89_RA_MODE_CCK)
423 mask |= RA_MASK_SUBCCK_RATES;
424 ra_mask &= mask;
425 } else if (mode & RTW89_RA_MODE_OFDM) {
426 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
427 }
428
429 if (mode != RTW89_RA_MODE_CCK)
430 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
431
432 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
433 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
434
435 switch (link_sta->bandwidth) {
436 case IEEE80211_STA_RX_BW_160:
437 bw_mode = RTW89_CHANNEL_WIDTH_160;
438 sgi = link_sta->vht_cap.vht_supported &&
439 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
440 break;
441 case IEEE80211_STA_RX_BW_80:
442 bw_mode = RTW89_CHANNEL_WIDTH_80;
443 sgi = link_sta->vht_cap.vht_supported &&
444 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
445 break;
446 case IEEE80211_STA_RX_BW_40:
447 bw_mode = RTW89_CHANNEL_WIDTH_40;
448 sgi = link_sta->ht_cap.ht_supported &&
449 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
450 break;
451 default:
452 bw_mode = RTW89_CHANNEL_WIDTH_20;
453 sgi = link_sta->ht_cap.ht_supported &&
454 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
455 break;
456 }
457
458 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
459 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
460 ra->dcm_cap = 1;
461
462 if (rate_pattern->enable && !p2p) {
463 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
464 ra_mask &= rate_pattern->ra_mask;
465 mode = rate_pattern->ra_mode;
466 }
467
468 ra->bw_cap = bw_mode;
469 ra->er_cap = rtwsta_link->er_cap;
470 ra->mode_ctrl = mode;
471 ra->macid = rtwsta_link->mac_id;
472 ra->stbc_cap = stbc_en;
473 ra->ldpc_cap = ldpc_en;
474 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
475 ra->en_sgi = sgi;
476 ra->ra_mask = ra_mask;
477 ra->fix_giltf_en = fix_giltf_en;
478 ra->fix_giltf = fix_giltf;
479 ra->partial_bw_er = link_sta->he_cap.has_he ?
480 !!(link_sta->he_cap.he_cap_elem.phy_cap_info[6] &
481 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE) : 0;
482 ra->band = chan->band_type;
483
484 if (!csi)
485 return;
486
487 ra->fixed_csi_rate_en = false;
488 ra->ra_csi_rate_en = true;
489 ra->cr_tbl_sel = false;
490 ra->band_num = rtwvif_link->phy_idx;
491 ra->csi_bw = bw_mode;
492 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
493 ra->csi_mcs_ss_idx = 5;
494 ra->csi_mode = csi_mode;
495 }
496
rtw89_phy_ra_update_sta_link(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u32 changed)497 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
498 struct rtw89_sta_link *rtwsta_link,
499 u32 changed)
500 {
501 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
502 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
503 struct rtw89_ra_info *ra = &rtwsta_link->ra;
504 struct ieee80211_link_sta *link_sta;
505
506 rcu_read_lock();
507
508 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
509 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
510 link_sta, vif->p2p, false);
511
512 rcu_read_unlock();
513
514 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
515 ra->upd_mask = 1;
516 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
517 ra->upd_bw_nss_mask = 1;
518
519 rtw89_debug(rtwdev, RTW89_DBG_RA,
520 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
521 ra->macid,
522 ra->bw_cap,
523 ra->ss_num,
524 ra->en_sgi,
525 ra->giltf);
526
527 rtw89_fw_h2c_ra(rtwdev, ra, false);
528 }
529
rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)530 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
531 u32 changed)
532 {
533 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
534 struct rtw89_sta_link *rtwsta_link;
535 unsigned int link_id;
536
537 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
538 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed);
539 }
540
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)541 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
542 u16 rate_base, u64 ra_mask, u8 ra_mode,
543 u32 rate_ctrl, u32 ctrl_skip, bool force)
544 {
545 u8 n, c;
546
547 if (rate_ctrl == ctrl_skip)
548 return true;
549
550 n = hweight32(rate_ctrl);
551 if (n == 0)
552 return true;
553
554 if (force && n != 1)
555 return false;
556
557 if (next->enable)
558 return false;
559
560 c = __fls(rate_ctrl);
561 next->rate = rate_base + c;
562 next->ra_mode = ra_mode;
563 next->ra_mask = ra_mask;
564 next->enable = true;
565
566 return true;
567 }
568
569 enum __rtw89_hw_rate_invalid_bases {
570 /* no EHT rate for ax chip */
571 RTW89_HW_RATE_EHT_NSS1_MCS0 = RTW89_HW_RATE_INVAL,
572 RTW89_HW_RATE_EHT_NSS2_MCS0 = RTW89_HW_RATE_INVAL,
573 RTW89_HW_RATE_EHT_NSS3_MCS0 = RTW89_HW_RATE_INVAL,
574 RTW89_HW_RATE_EHT_NSS4_MCS0 = RTW89_HW_RATE_INVAL,
575 };
576
577 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
578 { \
579 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
580 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \
581 }
582
583 static
__rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const struct cfg80211_bitrate_mask * mask)584 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
585 struct rtw89_vif_link *rtwvif_link,
586 const struct cfg80211_bitrate_mask *mask)
587 {
588 struct ieee80211_supported_band *sband;
589 struct rtw89_phy_rate_pattern next_pattern = {0};
590 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
591 rtwvif_link->chanctx_idx);
592 static const u16 hw_rate_eht[][RTW89_CHIP_GEN_NUM] = {
593 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS1_MCS0),
594 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS2_MCS0),
595 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS3_MCS0),
596 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS4_MCS0),
597 };
598 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
599 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
600 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
601 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0),
602 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0),
603 };
604 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = {
605 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0),
606 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0),
607 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0),
608 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0),
609 };
610 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = {
611 RTW89_HW_RATE_BY_CHIP_GEN(MCS0),
612 RTW89_HW_RATE_BY_CHIP_GEN(MCS8),
613 RTW89_HW_RATE_BY_CHIP_GEN(MCS16),
614 RTW89_HW_RATE_BY_CHIP_GEN(MCS24),
615 };
616 u8 band = chan->band_type;
617 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
618 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
619 u8 tx_nss = rtwdev->hal.tx_nss;
620 u8 i;
621
622 if (chip_gen == RTW89_CHIP_AX)
623 goto rs_11ax;
624
625 for (i = 0; i < tx_nss; i++)
626 if (!__check_rate_pattern(&next_pattern, hw_rate_eht[i][chip_gen],
627 RA_MASK_EHT_RATES, RTW89_RA_MODE_EHT,
628 mask->control[nl_band].eht_mcs[i],
629 0, true))
630 goto out;
631
632 rs_11ax:
633 for (i = 0; i < tx_nss; i++)
634 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
635 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
636 mask->control[nl_band].he_mcs[i],
637 0, true))
638 goto out;
639
640 for (i = 0; i < tx_nss; i++)
641 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen],
642 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
643 mask->control[nl_band].vht_mcs[i],
644 0, true))
645 goto out;
646
647 for (i = 0; i < tx_nss; i++)
648 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen],
649 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
650 mask->control[nl_band].ht_mcs[i],
651 0, true))
652 goto out;
653
654 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
655 * require at least one basic rate for ieee80211_set_bitrate_mask,
656 * so the decision just depends on if all bitrates are set or not.
657 */
658 sband = rtwdev->hw->wiphy->bands[nl_band];
659 if (band == RTW89_BAND_2G) {
660 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
661 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
662 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
663 mask->control[nl_band].legacy,
664 BIT(sband->n_bitrates) - 1, false))
665 goto out;
666 } else {
667 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
668 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
669 mask->control[nl_band].legacy,
670 BIT(sband->n_bitrates) - 1, false))
671 goto out;
672 }
673
674 if (!next_pattern.enable)
675 goto out;
676
677 if (unlikely(next_pattern.rate >= RTW89_HW_RATE_INVAL)) {
678 rtw89_debug(rtwdev, RTW89_DBG_RA,
679 "pattern invalid target: chip_gen %d, mode 0x%x\n",
680 chip_gen, next_pattern.ra_mode);
681 goto out;
682 }
683
684 rtwvif_link->rate_pattern = next_pattern;
685 rtw89_debug(rtwdev, RTW89_DBG_RA,
686 #if defined(__linux__)
687 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
688 #elif defined(__FreeBSD__)
689 "configure pattern: rate 0x%x, mask 0x%jx, mode 0x%x\n",
690 #endif
691 next_pattern.rate,
692 #if defined(__FreeBSD__)
693 (uintmax_t)
694 #endif
695 next_pattern.ra_mask,
696 next_pattern.ra_mode);
697 return;
698
699 out:
700 rtwvif_link->rate_pattern.enable = false;
701 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
702 }
703
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)704 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
705 struct ieee80211_vif *vif,
706 const struct cfg80211_bitrate_mask *mask)
707 {
708 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
709 struct rtw89_vif_link *rtwvif_link;
710 unsigned int link_id;
711
712 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
713 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask);
714 }
715
rtw89_phy_ra_update_sta_iter(void * data,struct ieee80211_sta * sta)716 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta)
717 {
718 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
719
720 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
721 }
722
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)723 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
724 {
725 ieee80211_iterate_stations_atomic(rtwdev->hw,
726 rtw89_phy_ra_update_sta_iter,
727 rtwdev);
728 }
729
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)730 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link)
731 {
732 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
733 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
734 struct rtw89_ra_info *ra = &rtwsta_link->ra;
735 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
736 struct ieee80211_link_sta *link_sta;
737 bool csi;
738
739 rcu_read_lock();
740
741 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
742 csi = rtw89_sta_has_beamformer_cap(link_sta);
743
744 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
745 link_sta, vif->p2p, csi);
746
747 rcu_read_unlock();
748
749 if (rssi > 40)
750 ra->init_rate_lv = 1;
751 else if (rssi > 20)
752 ra->init_rate_lv = 2;
753 else if (rssi > 1)
754 ra->init_rate_lv = 3;
755 else
756 ra->init_rate_lv = 0;
757 ra->upd_all = 1;
758 rtw89_debug(rtwdev, RTW89_DBG_RA,
759 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
760 ra->macid,
761 ra->mode_ctrl,
762 ra->bw_cap,
763 ra->ss_num,
764 ra->init_rate_lv);
765 rtw89_debug(rtwdev, RTW89_DBG_RA,
766 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
767 ra->dcm_cap,
768 ra->er_cap,
769 ra->ldpc_cap,
770 ra->stbc_cap,
771 ra->en_sgi,
772 ra->giltf);
773
774 rtw89_fw_h2c_ra(rtwdev, ra, csi);
775 }
776
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)777 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
778 const struct rtw89_chan *chan,
779 enum rtw89_bandwidth dbw)
780 {
781 enum rtw89_bandwidth cbw = chan->band_width;
782 u8 pri_ch = chan->primary_channel;
783 u8 central_ch = chan->channel;
784 u8 txsc_idx = 0;
785 u8 tmp = 0;
786
787 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
788 return txsc_idx;
789
790 switch (cbw) {
791 case RTW89_CHANNEL_WIDTH_40:
792 txsc_idx = pri_ch > central_ch ? 1 : 2;
793 break;
794 case RTW89_CHANNEL_WIDTH_80:
795 if (dbw == RTW89_CHANNEL_WIDTH_20) {
796 if (pri_ch > central_ch)
797 txsc_idx = (pri_ch - central_ch) >> 1;
798 else
799 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
800 } else {
801 txsc_idx = pri_ch > central_ch ? 9 : 10;
802 }
803 break;
804 case RTW89_CHANNEL_WIDTH_160:
805 if (pri_ch > central_ch)
806 tmp = (pri_ch - central_ch) >> 1;
807 else
808 tmp = ((central_ch - pri_ch) >> 1) + 1;
809
810 if (dbw == RTW89_CHANNEL_WIDTH_20) {
811 txsc_idx = tmp;
812 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
813 if (tmp == 1 || tmp == 3)
814 txsc_idx = 9;
815 else if (tmp == 5 || tmp == 7)
816 txsc_idx = 11;
817 else if (tmp == 2 || tmp == 4)
818 txsc_idx = 10;
819 else if (tmp == 6 || tmp == 8)
820 txsc_idx = 12;
821 else
822 return 0xff;
823 } else {
824 txsc_idx = pri_ch > central_ch ? 13 : 14;
825 }
826 break;
827 case RTW89_CHANNEL_WIDTH_80_80:
828 if (dbw == RTW89_CHANNEL_WIDTH_20) {
829 if (pri_ch > central_ch)
830 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
831 else
832 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
833 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
834 txsc_idx = pri_ch > central_ch ? 10 : 12;
835 } else {
836 txsc_idx = 14;
837 }
838 break;
839 default:
840 break;
841 }
842
843 return txsc_idx;
844 }
845 EXPORT_SYMBOL(rtw89_phy_get_txsc);
846
rtw89_phy_get_txsb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)847 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
848 enum rtw89_bandwidth dbw)
849 {
850 enum rtw89_bandwidth cbw = chan->band_width;
851 u8 pri_ch = chan->primary_channel;
852 u8 central_ch = chan->channel;
853 u8 txsb_idx = 0;
854
855 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
856 return txsb_idx;
857
858 switch (cbw) {
859 case RTW89_CHANNEL_WIDTH_40:
860 txsb_idx = pri_ch > central_ch ? 1 : 0;
861 break;
862 case RTW89_CHANNEL_WIDTH_80:
863 if (dbw == RTW89_CHANNEL_WIDTH_20)
864 txsb_idx = (pri_ch - central_ch + 6) / 4;
865 else
866 txsb_idx = pri_ch > central_ch ? 1 : 0;
867 break;
868 case RTW89_CHANNEL_WIDTH_160:
869 if (dbw == RTW89_CHANNEL_WIDTH_20)
870 txsb_idx = (pri_ch - central_ch + 14) / 4;
871 else if (dbw == RTW89_CHANNEL_WIDTH_40)
872 txsb_idx = (pri_ch - central_ch + 12) / 8;
873 else
874 txsb_idx = pri_ch > central_ch ? 1 : 0;
875 break;
876 case RTW89_CHANNEL_WIDTH_320:
877 if (dbw == RTW89_CHANNEL_WIDTH_20)
878 txsb_idx = (pri_ch - central_ch + 30) / 4;
879 else if (dbw == RTW89_CHANNEL_WIDTH_40)
880 txsb_idx = (pri_ch - central_ch + 28) / 8;
881 else if (dbw == RTW89_CHANNEL_WIDTH_80)
882 txsb_idx = (pri_ch - central_ch + 24) / 16;
883 else
884 txsb_idx = pri_ch > central_ch ? 1 : 0;
885 break;
886 default:
887 break;
888 }
889
890 return txsb_idx;
891 }
892 EXPORT_SYMBOL(rtw89_phy_get_txsb);
893
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)894 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
895 {
896 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
897 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
898 }
899
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)900 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
901 u32 addr, u32 mask)
902 {
903 const struct rtw89_chip_info *chip = rtwdev->chip;
904 const u32 *base_addr = chip->rf_base_addr;
905 u32 val, direct_addr;
906
907 if (rf_path >= rtwdev->chip->rf_path_num) {
908 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
909 return INV_RF_DATA;
910 }
911
912 addr &= 0xff;
913 direct_addr = base_addr[rf_path] + (addr << 2);
914 mask &= RFREG_MASK;
915
916 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
917
918 return val;
919 }
920 EXPORT_SYMBOL(rtw89_phy_read_rf);
921
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)922 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
923 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
924 {
925 bool busy;
926 bool done;
927 u32 val;
928 int ret;
929
930 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
931 1, 30, false, rtwdev);
932 if (ret) {
933 rtw89_err(rtwdev, "read rf busy swsi\n");
934 return INV_RF_DATA;
935 }
936
937 mask &= RFREG_MASK;
938
939 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
940 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
941 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
942 udelay(2);
943
944 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
945 30, false, rtwdev, R_SWSI_V1,
946 B_SWSI_R_DATA_DONE_V1);
947 if (ret) {
948 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags))
949 rtw89_err(rtwdev, "read swsi busy\n");
950 return INV_RF_DATA;
951 }
952
953 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
954 }
955
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)956 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
957 u32 addr, u32 mask)
958 {
959 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
960
961 if (rf_path >= rtwdev->chip->rf_path_num) {
962 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
963 return INV_RF_DATA;
964 }
965
966 if (ad_sel)
967 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
968 else
969 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
970 }
971 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
972
rtw89_phy_read_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)973 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
974 enum rtw89_rf_path rf_path, u32 addr)
975 {
976 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24};
977 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC};
978 bool busy, done;
979 int ret;
980 u32 val;
981
982 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
983 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
984 1, 3800, false,
985 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
986 if (ret) {
987 rtw89_warn(rtwdev, "poll HWSI is busy\n");
988 return INV_RF_DATA;
989 }
990
991 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
992 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
993 udelay(2);
994
995 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
996 1, 3800, false,
997 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
998 if (ret) {
999 rtw89_warn(rtwdev, "read HWSI is busy\n");
1000 val = INV_RF_DATA;
1001 goto out;
1002 }
1003
1004 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
1005 out:
1006 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
1007
1008 return val;
1009 }
1010
rtw89_phy_read_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)1011 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
1012 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
1013 {
1014 u32 val;
1015
1016 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1017
1018 return (val & mask) >> __ffs(mask);
1019 }
1020
rtw89_phy_read_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)1021 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1022 u32 addr, u32 mask)
1023 {
1024 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1025
1026 if (rf_path >= rtwdev->chip->rf_path_num) {
1027 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1028 return INV_RF_DATA;
1029 }
1030
1031 if (ad_sel)
1032 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
1033 else
1034 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
1035 }
1036 EXPORT_SYMBOL(rtw89_phy_read_rf_v2);
1037
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1038 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1039 u32 addr, u32 mask, u32 data)
1040 {
1041 const struct rtw89_chip_info *chip = rtwdev->chip;
1042 const u32 *base_addr = chip->rf_base_addr;
1043 u32 direct_addr;
1044
1045 if (rf_path >= rtwdev->chip->rf_path_num) {
1046 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1047 return false;
1048 }
1049
1050 addr &= 0xff;
1051 direct_addr = base_addr[rf_path] + (addr << 2);
1052 mask &= RFREG_MASK;
1053
1054 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
1055
1056 /* delay to ensure writing properly */
1057 udelay(1);
1058
1059 return true;
1060 }
1061 EXPORT_SYMBOL(rtw89_phy_write_rf);
1062
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1063 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
1064 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
1065 u32 data)
1066 {
1067 u8 bit_shift;
1068 u32 val;
1069 bool busy, b_msk_en = false;
1070 int ret;
1071
1072 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
1073 1, 30, false, rtwdev);
1074 if (ret) {
1075 rtw89_err(rtwdev, "write rf busy swsi\n");
1076 return false;
1077 }
1078
1079 data &= RFREG_MASK;
1080 mask &= RFREG_MASK;
1081
1082 if (mask != RFREG_MASK) {
1083 b_msk_en = true;
1084 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
1085 mask);
1086 bit_shift = __ffs(mask);
1087 data = (data << bit_shift) & RFREG_MASK;
1088 }
1089
1090 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
1091 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
1092 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
1093 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
1094
1095 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
1096
1097 return true;
1098 }
1099
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1100 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1101 u32 addr, u32 mask, u32 data)
1102 {
1103 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
1104
1105 if (rf_path >= rtwdev->chip->rf_path_num) {
1106 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1107 return false;
1108 }
1109
1110 if (ad_sel)
1111 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1112 else
1113 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1114 }
1115 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
1116
1117 static
rtw89_phy_write_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1118 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1119 u32 addr, u32 data)
1120 {
1121 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24};
1122 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0};
1123 bool busy;
1124 u32 val;
1125 int ret;
1126
1127 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1128 1, 3800, false,
1129 rtwdev, addr_is_idle[rf_path], BIT(29));
1130 if (ret) {
1131 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1132 return false;
1133 }
1134
1135 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) |
1136 u32_encode_bits(data, B_HWSI_DATA_VAL);
1137
1138 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1139
1140 return true;
1141 }
1142
1143 static
rtw89_phy_write_rf_a_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1144 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1145 u32 addr, u32 mask, u32 data)
1146 {
1147 u32 val;
1148
1149 if (mask == RFREG_MASK) {
1150 val = data;
1151 } else {
1152 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1153 val &= ~mask;
1154 val |= (data << __ffs(mask)) & mask;
1155 }
1156
1157 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1158 }
1159
rtw89_phy_write_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1160 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1161 u32 addr, u32 mask, u32 data)
1162 {
1163 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1164
1165 if (rf_path >= rtwdev->chip->rf_path_num) {
1166 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1167 return INV_RF_DATA;
1168 }
1169
1170 if (ad_sel)
1171 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1172 else
1173 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1174 }
1175 EXPORT_SYMBOL(rtw89_phy_write_rf_v2);
1176
rtw89_chip_rf_v1(struct rtw89_dev * rtwdev)1177 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1178 {
1179 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1180 }
1181
__rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1182 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1183 enum rtw89_phy_idx phy_idx)
1184 {
1185 const struct rtw89_chip_info *chip = rtwdev->chip;
1186
1187 chip->ops->bb_reset(rtwdev, phy_idx);
1188 }
1189
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev)1190 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev)
1191 {
1192 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1193 if (rtwdev->dbcc_en)
1194 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1);
1195 }
1196
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1197 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1198 const struct rtw89_reg2_def *reg,
1199 enum rtw89_rf_path rf_path,
1200 void *extra_data)
1201 {
1202 u32 addr;
1203
1204 if (reg->addr == 0xfe) {
1205 mdelay(50);
1206 } else if (reg->addr == 0xfd) {
1207 mdelay(5);
1208 } else if (reg->addr == 0xfc) {
1209 mdelay(1);
1210 } else if (reg->addr == 0xfb) {
1211 udelay(50);
1212 } else if (reg->addr == 0xfa) {
1213 udelay(5);
1214 } else if (reg->addr == 0xf9) {
1215 udelay(1);
1216 } else if (reg->data == BYPASS_CR_DATA) {
1217 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1218 } else {
1219 addr = reg->addr;
1220
1221 if ((uintptr_t)extra_data == RTW89_PHY_1)
1222 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1223
1224 rtw89_phy_write32(rtwdev, addr, reg->data);
1225 }
1226 }
1227
1228 union rtw89_phy_bb_gain_arg {
1229 u32 addr;
1230 struct {
1231 union {
1232 u8 type;
1233 struct {
1234 u8 rxsc_start:4;
1235 u8 bw:4;
1236 };
1237 };
1238 u8 path;
1239 u8 gain_band;
1240 u8 cfg_type;
1241 };
1242 } __packed;
1243
1244 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1245 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1246 union rtw89_phy_bb_gain_arg arg, u32 data)
1247 {
1248 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1249 u8 type = arg.type;
1250 u8 path = arg.path;
1251 u8 gband = arg.gain_band;
1252 int i;
1253
1254 switch (type) {
1255 case 0:
1256 for (i = 0; i < 4; i++, data >>= 8)
1257 gain->lna_gain[gband][path][i] = data & 0xff;
1258 break;
1259 case 1:
1260 for (i = 4; i < 7; i++, data >>= 8)
1261 gain->lna_gain[gband][path][i] = data & 0xff;
1262 break;
1263 case 2:
1264 for (i = 0; i < 2; i++, data >>= 8)
1265 gain->tia_gain[gband][path][i] = data & 0xff;
1266 break;
1267 default:
1268 rtw89_warn(rtwdev,
1269 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
1270 arg.addr, data, type);
1271 break;
1272 }
1273 }
1274
1275 enum rtw89_phy_bb_rxsc_start_idx {
1276 RTW89_BB_RXSC_START_IDX_FULL = 0,
1277 RTW89_BB_RXSC_START_IDX_20 = 1,
1278 RTW89_BB_RXSC_START_IDX_20_1 = 5,
1279 RTW89_BB_RXSC_START_IDX_40 = 9,
1280 RTW89_BB_RXSC_START_IDX_80 = 13,
1281 };
1282
1283 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1284 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1285 union rtw89_phy_bb_gain_arg arg, u32 data)
1286 {
1287 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1288 u8 rxsc_start = arg.rxsc_start;
1289 u8 bw = arg.bw;
1290 u8 path = arg.path;
1291 u8 gband = arg.gain_band;
1292 u8 rxsc;
1293 s8 ofst;
1294 int i;
1295
1296 switch (bw) {
1297 case RTW89_CHANNEL_WIDTH_20:
1298 gain->rpl_ofst_20[gband][path] = (s8)data;
1299 break;
1300 case RTW89_CHANNEL_WIDTH_40:
1301 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1302 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1303 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1304 for (i = 0; i < 2; i++, data >>= 8) {
1305 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1306 ofst = (s8)(data & 0xff);
1307 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1308 }
1309 }
1310 break;
1311 case RTW89_CHANNEL_WIDTH_80:
1312 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1313 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1314 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1315 for (i = 0; i < 4; i++, data >>= 8) {
1316 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1317 ofst = (s8)(data & 0xff);
1318 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1319 }
1320 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1321 for (i = 0; i < 2; i++, data >>= 8) {
1322 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1323 ofst = (s8)(data & 0xff);
1324 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1325 }
1326 }
1327 break;
1328 case RTW89_CHANNEL_WIDTH_160:
1329 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1330 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1331 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1332 for (i = 0; i < 4; i++, data >>= 8) {
1333 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1334 ofst = (s8)(data & 0xff);
1335 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1336 }
1337 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
1338 for (i = 0; i < 4; i++, data >>= 8) {
1339 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
1340 ofst = (s8)(data & 0xff);
1341 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1342 }
1343 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1344 for (i = 0; i < 4; i++, data >>= 8) {
1345 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1346 ofst = (s8)(data & 0xff);
1347 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1348 }
1349 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
1350 for (i = 0; i < 2; i++, data >>= 8) {
1351 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
1352 ofst = (s8)(data & 0xff);
1353 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1354 }
1355 }
1356 break;
1357 default:
1358 rtw89_warn(rtwdev,
1359 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1360 arg.addr, data, bw);
1361 break;
1362 }
1363 }
1364
1365 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1366 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1367 union rtw89_phy_bb_gain_arg arg, u32 data)
1368 {
1369 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1370 u8 type = arg.type;
1371 u8 path = arg.path;
1372 u8 gband = arg.gain_band;
1373 int i;
1374
1375 switch (type) {
1376 case 0:
1377 for (i = 0; i < 4; i++, data >>= 8)
1378 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1379 break;
1380 case 1:
1381 for (i = 4; i < 7; i++, data >>= 8)
1382 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1383 break;
1384 default:
1385 rtw89_warn(rtwdev,
1386 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
1387 arg.addr, data, type);
1388 break;
1389 }
1390 }
1391
1392 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1393 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1394 union rtw89_phy_bb_gain_arg arg, u32 data)
1395 {
1396 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1397 u8 type = arg.type;
1398 u8 path = arg.path;
1399 u8 gband = arg.gain_band;
1400 int i;
1401
1402 switch (type) {
1403 case 0:
1404 for (i = 0; i < 4; i++, data >>= 8)
1405 gain->lna_op1db[gband][path][i] = data & 0xff;
1406 break;
1407 case 1:
1408 for (i = 4; i < 7; i++, data >>= 8)
1409 gain->lna_op1db[gband][path][i] = data & 0xff;
1410 break;
1411 case 2:
1412 for (i = 0; i < 4; i++, data >>= 8)
1413 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1414 break;
1415 case 3:
1416 for (i = 4; i < 8; i++, data >>= 8)
1417 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1418 break;
1419 default:
1420 rtw89_warn(rtwdev,
1421 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
1422 arg.addr, data, type);
1423 break;
1424 }
1425 }
1426
rtw89_phy_config_bb_gain_ax(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1427 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1428 const struct rtw89_reg2_def *reg,
1429 enum rtw89_rf_path rf_path,
1430 void *extra_data)
1431 {
1432 const struct rtw89_chip_info *chip = rtwdev->chip;
1433 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1434 struct rtw89_efuse *efuse = &rtwdev->efuse;
1435
1436 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1437 return;
1438
1439 if (arg.path >= chip->rf_path_num)
1440 return;
1441
1442 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1443 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1444 return;
1445 }
1446
1447 switch (arg.cfg_type) {
1448 case 0:
1449 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1450 break;
1451 case 1:
1452 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1453 break;
1454 case 2:
1455 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1456 break;
1457 case 3:
1458 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1459 break;
1460 case 4:
1461 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
1462 if (efuse->rfe_type < 50)
1463 break;
1464 fallthrough;
1465 default:
1466 rtw89_warn(rtwdev,
1467 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1468 arg.addr, reg->data, arg.cfg_type);
1469 break;
1470 }
1471 }
1472
1473 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1474 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1475 const struct rtw89_reg2_def *reg,
1476 enum rtw89_rf_path rf_path,
1477 struct rtw89_fw_h2c_rf_reg_info *info)
1478 {
1479 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1480 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1481
1482 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1483 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1484 rf_path, info->curr_idx);
1485 return;
1486 }
1487
1488 info->rtw89_phy_config_rf_h2c[page][idx] =
1489 cpu_to_le32((reg->addr << 20) | reg->data);
1490 info->curr_idx++;
1491 }
1492
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1493 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1494 struct rtw89_fw_h2c_rf_reg_info *info)
1495 {
1496 u16 remain = info->curr_idx;
1497 u16 len = 0;
1498 u8 i;
1499 int ret = 0;
1500
1501 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1502 rtw89_warn(rtwdev,
1503 "rf reg h2c total len %d larger than %d\n",
1504 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1505 ret = -EINVAL;
1506 goto out;
1507 }
1508
1509 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1510 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1511 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1512 if (ret)
1513 goto out;
1514 }
1515 out:
1516 info->curr_idx = 0;
1517
1518 return ret;
1519 }
1520
rtw89_phy_config_rf_reg_noio(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1521 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1522 const struct rtw89_reg2_def *reg,
1523 enum rtw89_rf_path rf_path,
1524 void *extra_data)
1525 {
1526 u32 addr = reg->addr;
1527
1528 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1529 addr == 0xfa || addr == 0xf9)
1530 return;
1531
1532 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1533 return;
1534
1535 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1536 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1537 }
1538
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1539 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1540 const struct rtw89_reg2_def *reg,
1541 enum rtw89_rf_path rf_path,
1542 void *extra_data)
1543 {
1544 if (reg->addr == 0xfe) {
1545 mdelay(50);
1546 } else if (reg->addr == 0xfd) {
1547 mdelay(5);
1548 } else if (reg->addr == 0xfc) {
1549 mdelay(1);
1550 } else if (reg->addr == 0xfb) {
1551 udelay(50);
1552 } else if (reg->addr == 0xfa) {
1553 udelay(5);
1554 } else if (reg->addr == 0xf9) {
1555 udelay(1);
1556 } else {
1557 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1558 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1559 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1560 }
1561 }
1562
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1563 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1564 const struct rtw89_reg2_def *reg,
1565 enum rtw89_rf_path rf_path,
1566 void *extra_data)
1567 {
1568 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1569
1570 if (reg->addr < 0x100)
1571 return;
1572
1573 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1574 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1575 }
1576 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1577
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1578 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1579 const struct rtw89_phy_table *table,
1580 u32 *headline_size, u32 *headline_idx,
1581 u8 rfe, u8 cv)
1582 {
1583 const struct rtw89_reg2_def *reg;
1584 u32 headline;
1585 u32 compare, target;
1586 u8 rfe_para, cv_para;
1587 u8 cv_max = 0;
1588 bool case_matched = false;
1589 u32 i;
1590
1591 for (i = 0; i < table->n_regs; i++) {
1592 reg = &table->regs[i];
1593 headline = get_phy_headline(reg->addr);
1594 if (headline != PHY_HEADLINE_VALID)
1595 break;
1596 }
1597 *headline_size = i;
1598 if (*headline_size == 0)
1599 return 0;
1600
1601 /* case 1: RFE match, CV match */
1602 compare = get_phy_compare(rfe, cv);
1603 for (i = 0; i < *headline_size; i++) {
1604 reg = &table->regs[i];
1605 target = get_phy_target(reg->addr);
1606 if (target == compare) {
1607 *headline_idx = i;
1608 return 0;
1609 }
1610 }
1611
1612 /* case 2: RFE match, CV don't care */
1613 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1614 for (i = 0; i < *headline_size; i++) {
1615 reg = &table->regs[i];
1616 target = get_phy_target(reg->addr);
1617 if (target == compare) {
1618 *headline_idx = i;
1619 return 0;
1620 }
1621 }
1622
1623 /* case 3: RFE match, CV max in table */
1624 for (i = 0; i < *headline_size; i++) {
1625 reg = &table->regs[i];
1626 rfe_para = get_phy_cond_rfe(reg->addr);
1627 cv_para = get_phy_cond_cv(reg->addr);
1628 if (rfe_para == rfe) {
1629 if (cv_para >= cv_max) {
1630 cv_max = cv_para;
1631 *headline_idx = i;
1632 case_matched = true;
1633 }
1634 }
1635 }
1636
1637 if (case_matched)
1638 return 0;
1639
1640 /* case 4: RFE don't care, CV max in table */
1641 for (i = 0; i < *headline_size; i++) {
1642 reg = &table->regs[i];
1643 rfe_para = get_phy_cond_rfe(reg->addr);
1644 cv_para = get_phy_cond_cv(reg->addr);
1645 if (rfe_para == PHY_COND_DONT_CARE) {
1646 if (cv_para >= cv_max) {
1647 cv_max = cv_para;
1648 *headline_idx = i;
1649 case_matched = true;
1650 }
1651 }
1652 }
1653
1654 if (case_matched)
1655 return 0;
1656
1657 return -EINVAL;
1658 }
1659
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1660 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1661 const struct rtw89_phy_table *table,
1662 void (*config)(struct rtw89_dev *rtwdev,
1663 const struct rtw89_reg2_def *reg,
1664 enum rtw89_rf_path rf_path,
1665 void *data),
1666 void *extra_data)
1667 {
1668 const struct rtw89_reg2_def *reg;
1669 enum rtw89_rf_path rf_path = table->rf_path;
1670 u8 rfe = rtwdev->efuse.rfe_type;
1671 u8 cv = rtwdev->hal.cv;
1672 u32 i;
1673 u32 headline_size = 0, headline_idx = 0;
1674 u32 target = 0, cfg_target;
1675 u8 cond;
1676 bool is_matched = true;
1677 bool target_found = false;
1678 int ret;
1679
1680 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1681 &headline_idx, rfe, cv);
1682 if (ret) {
1683 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1684 return;
1685 }
1686
1687 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1688 for (i = headline_size; i < table->n_regs; i++) {
1689 reg = &table->regs[i];
1690 cond = get_phy_cond(reg->addr);
1691 switch (cond) {
1692 case PHY_COND_BRANCH_IF:
1693 case PHY_COND_BRANCH_ELIF:
1694 target = get_phy_target(reg->addr);
1695 break;
1696 case PHY_COND_BRANCH_ELSE:
1697 is_matched = false;
1698 if (!target_found) {
1699 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1700 reg->addr, reg->data);
1701 return;
1702 }
1703 break;
1704 case PHY_COND_BRANCH_END:
1705 is_matched = true;
1706 target_found = false;
1707 break;
1708 case PHY_COND_CHECK:
1709 if (target_found) {
1710 is_matched = false;
1711 break;
1712 }
1713
1714 if (target == cfg_target) {
1715 is_matched = true;
1716 target_found = true;
1717 } else {
1718 is_matched = false;
1719 target_found = false;
1720 }
1721 break;
1722 default:
1723 if (is_matched)
1724 config(rtwdev, reg, rf_path, extra_data);
1725 break;
1726 }
1727 }
1728 }
1729
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1730 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1731 {
1732 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1733 const struct rtw89_chip_info *chip = rtwdev->chip;
1734 const struct rtw89_phy_table *bb_table;
1735 const struct rtw89_phy_table *bb_gain_table;
1736
1737 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1738 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1739 if (rtwdev->dbcc_en)
1740 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1741 (void *)RTW89_PHY_1);
1742
1743 rtw89_chip_init_txpwr_unit(rtwdev);
1744
1745 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1746 if (bb_gain_table)
1747 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1748 chip->phy_def->config_bb_gain, NULL);
1749
1750 rtw89_phy_bb_reset(rtwdev);
1751 }
1752
rtw89_phy_init_bb_afe(struct rtw89_dev * rtwdev)1753 void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev)
1754 {
1755 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1756 const struct rtw89_fw_element_hdr *afe_elm = elm_info->afe;
1757 const struct rtw89_phy_afe_info *info;
1758 u32 action, cat, class;
1759 u32 addr, mask, val;
1760 u32 poll, rpt;
1761 u32 n, i;
1762
1763 if (!afe_elm)
1764 return;
1765
1766 n = le32_to_cpu(afe_elm->size) / sizeof(*info);
1767
1768 for (i = 0; i < n; i++) {
1769 info = &afe_elm->u.afe.infos[i];
1770
1771 class = le32_to_cpu(info->class);
1772 switch (class) {
1773 case RTW89_FW_AFE_CLASS_P0:
1774 case RTW89_FW_AFE_CLASS_P1:
1775 case RTW89_FW_AFE_CLASS_CMN:
1776 /* Currently support two paths */
1777 break;
1778 case RTW89_FW_AFE_CLASS_P2:
1779 case RTW89_FW_AFE_CLASS_P3:
1780 case RTW89_FW_AFE_CLASS_P4:
1781 default:
1782 rtw89_warn(rtwdev, "unexpected AFE class %u\n", class);
1783 continue;
1784 }
1785
1786 addr = le32_to_cpu(info->addr);
1787 mask = le32_to_cpu(info->mask);
1788 val = le32_to_cpu(info->val);
1789 cat = le32_to_cpu(info->cat);
1790 action = le32_to_cpu(info->action);
1791
1792 switch (action) {
1793 case RTW89_FW_AFE_ACTION_WRITE:
1794 switch (cat) {
1795 case RTW89_FW_AFE_CAT_MAC:
1796 case RTW89_FW_AFE_CAT_MAC1:
1797 rtw89_write32_mask(rtwdev, addr, mask, val);
1798 break;
1799 case RTW89_FW_AFE_CAT_AFEDIG:
1800 case RTW89_FW_AFE_CAT_AFEDIG1:
1801 rtw89_write32_mask(rtwdev, addr, mask, val);
1802 break;
1803 case RTW89_FW_AFE_CAT_BB:
1804 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1805 break;
1806 case RTW89_FW_AFE_CAT_BB1:
1807 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1808 break;
1809 default:
1810 rtw89_warn(rtwdev,
1811 "unexpected AFE writing action %u\n", action);
1812 break;
1813 }
1814 break;
1815 case RTW89_FW_AFE_ACTION_POLL:
1816 for (poll = 0; poll <= 10; poll++) {
1817 /*
1818 * For CAT_BB, AFE reads register with mcu_offset 0,
1819 * so both CAT_MAC and CAT_BB use the same method.
1820 */
1821 rpt = rtw89_read32_mask(rtwdev, addr, mask);
1822 if (rpt == val)
1823 goto poll_done;
1824
1825 fsleep(1);
1826 }
1827 rtw89_warn(rtwdev, "failed to poll AFE cat=%u addr=0x%x mask=0x%x\n",
1828 cat, addr, mask);
1829 poll_done:
1830 break;
1831 case RTW89_FW_AFE_ACTION_DELAY:
1832 fsleep(addr);
1833 break;
1834 }
1835 }
1836 }
1837
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1838 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1839 {
1840 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1841 udelay(1);
1842 return rtw89_phy_read32(rtwdev, 0x8080);
1843 }
1844
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev,bool noio)1845 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1846 {
1847 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1848 enum rtw89_rf_path rf_path, void *data);
1849 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1850 const struct rtw89_chip_info *chip = rtwdev->chip;
1851 const struct rtw89_phy_table *rf_table;
1852 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1853 u8 path;
1854
1855 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1856 if (!rf_reg_info)
1857 return;
1858
1859 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1860 rf_table = elm_info->rf_radio[path] ?
1861 elm_info->rf_radio[path] : chip->rf_table[path];
1862 rf_reg_info->rf_path = rf_table->rf_path;
1863 if (noio)
1864 config = rtw89_phy_config_rf_reg_noio;
1865 else
1866 config = rf_table->config ? rf_table->config :
1867 rtw89_phy_config_rf_reg;
1868 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1869 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1870 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1871 rf_reg_info->rf_path);
1872 }
1873 kfree(rf_reg_info);
1874 }
1875
rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev * rtwdev)1876 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
1877 {
1878 const struct rtw89_chip_info *chip = rtwdev->chip;
1879 u32 val;
1880 int ret;
1881
1882 /* IQK/DPK clock & reset */
1883 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
1884 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
1885 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
1886 if (chip->chip_id != RTL8851B)
1887 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
1888 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
1889 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
1890
1891 /* check 0x8080 */
1892 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
1893
1894 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1895 1000, false, rtwdev);
1896 if (ret)
1897 #if defined(__linux__)
1898 rtw89_err(rtwdev, "failed to poll nctl block\n");
1899 #elif defined(__FreeBSD__)
1900 rtw89_err(rtwdev, "failed to poll nctl block: ret %d val %#06x\n", ret, val);
1901 #endif
1902 }
1903
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1904 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1905 {
1906 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1907 const struct rtw89_chip_info *chip = rtwdev->chip;
1908 const struct rtw89_phy_table *nctl_table;
1909
1910 rtw89_phy_preinit_rf_nctl(rtwdev);
1911
1912 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
1913 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1914
1915 if (chip->nctl_post_table)
1916 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1917 }
1918
rtw89_phy0_phy1_offset_ax(struct rtw89_dev * rtwdev,u32 addr)1919 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
1920 {
1921 u32 phy_page = addr >> 8;
1922 u32 ofst = 0;
1923
1924 switch (phy_page) {
1925 case 0x6:
1926 case 0x7:
1927 case 0x8:
1928 case 0x9:
1929 case 0xa:
1930 case 0xb:
1931 case 0xc:
1932 case 0xd:
1933 case 0x19:
1934 case 0x1a:
1935 case 0x1b:
1936 ofst = 0x2000;
1937 break;
1938 default:
1939 /* warning case */
1940 ofst = 0;
1941 break;
1942 }
1943
1944 if (phy_page >= 0x40 && phy_page <= 0x4f)
1945 ofst = 0x2000;
1946
1947 return ofst;
1948 }
1949
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1950 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1951 u32 data, enum rtw89_phy_idx phy_idx)
1952 {
1953 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1954 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1955 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1956 }
1957 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1958
rtw89_phy_write32_idx_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1959 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1960 enum rtw89_phy_idx phy_idx)
1961 {
1962 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1963 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1964 rtw89_phy_write32_set(rtwdev, addr, bits);
1965 }
1966 EXPORT_SYMBOL(rtw89_phy_write32_idx_set);
1967
rtw89_phy_write32_idx_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1968 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1969 enum rtw89_phy_idx phy_idx)
1970 {
1971 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1972 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1973 rtw89_phy_write32_clr(rtwdev, addr, bits);
1974 }
1975 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr);
1976
rtw89_phy_read32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,enum rtw89_phy_idx phy_idx)1977 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1978 enum rtw89_phy_idx phy_idx)
1979 {
1980 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1981 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1982 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1983 }
1984 EXPORT_SYMBOL(rtw89_phy_read32_idx);
1985
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1986 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1987 u32 val)
1988 {
1989 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1990
1991 if (!rtwdev->dbcc_en)
1992 return;
1993
1994 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1995 }
1996 EXPORT_SYMBOL(rtw89_phy_set_phy_regs);
1997
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1998 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1999 const struct rtw89_phy_reg3_tbl *tbl)
2000 {
2001 const struct rtw89_reg3_def *reg3;
2002 int i;
2003
2004 for (i = 0; i < tbl->size; i++) {
2005 reg3 = &tbl->reg3[i];
2006 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
2007 }
2008 }
2009 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
2010
rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev * rtwdev,u8 ant_gain_regd)2011 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd)
2012 {
2013 switch (ant_gain_regd) {
2014 case RTW89_ANT_GAIN_ETSI:
2015 return RTW89_ETSI;
2016 default:
2017 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2018 "unknown antenna gain domain: %d\n",
2019 ant_gain_regd);
2020 return RTW89_REGD_NUM;
2021 }
2022 }
2023
2024 /* antenna gain in unit of 0.25 dbm */
2025 #define RTW89_ANT_GAIN_2GHZ_MIN -8
2026 #define RTW89_ANT_GAIN_2GHZ_MAX 14
2027 #define RTW89_ANT_GAIN_5GHZ_MIN -8
2028 #define RTW89_ANT_GAIN_5GHZ_MAX 20
2029 #define RTW89_ANT_GAIN_6GHZ_MIN -8
2030 #define RTW89_ANT_GAIN_6GHZ_MAX 20
2031
2032 #define RTW89_ANT_GAIN_REF_2GHZ 14
2033 #define RTW89_ANT_GAIN_REF_5GHZ 20
2034 #define RTW89_ANT_GAIN_REF_6GHZ 20
2035
rtw89_phy_ant_gain_init(struct rtw89_dev * rtwdev)2036 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev)
2037 {
2038 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2039 const struct rtw89_chip_info *chip = rtwdev->chip;
2040 struct rtw89_acpi_rtag_result res = {};
2041 u32 domain;
2042 int ret;
2043 u8 i, j;
2044 u8 regd;
2045 u8 val;
2046
2047 if (!chip->support_ant_gain)
2048 return;
2049
2050 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res);
2051 if (ret) {
2052 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2053 "acpi: cannot eval rtag: %d\n", ret);
2054 return;
2055 }
2056
2057 if (res.revision != 0) {
2058 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2059 "unknown rtag revision: %d\n", res.revision);
2060 return;
2061 }
2062
2063 domain = get_unaligned_le32(&res.domain);
2064
2065 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) {
2066 if (!(domain & BIT(i)))
2067 continue;
2068
2069 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i);
2070 if (regd >= RTW89_REGD_NUM)
2071 continue;
2072 ant_gain->regd_enabled |= BIT(regd);
2073 }
2074
2075 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) {
2076 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) {
2077 val = res.ant_gain_table[i][j];
2078 switch (j) {
2079 default:
2080 case RTW89_ANT_GAIN_2GHZ_SUBBAND:
2081 val = RTW89_ANT_GAIN_REF_2GHZ -
2082 clamp_t(s8, val,
2083 RTW89_ANT_GAIN_2GHZ_MIN,
2084 RTW89_ANT_GAIN_2GHZ_MAX);
2085 break;
2086 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1:
2087 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2:
2088 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E:
2089 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4:
2090 val = RTW89_ANT_GAIN_REF_5GHZ -
2091 clamp_t(s8, val,
2092 RTW89_ANT_GAIN_5GHZ_MIN,
2093 RTW89_ANT_GAIN_5GHZ_MAX);
2094 break;
2095 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L:
2096 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H:
2097 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6:
2098 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L:
2099 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H:
2100 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8:
2101 val = RTW89_ANT_GAIN_REF_6GHZ -
2102 clamp_t(s8, val,
2103 RTW89_ANT_GAIN_6GHZ_MIN,
2104 RTW89_ANT_GAIN_6GHZ_MAX);
2105 }
2106 ant_gain->offset[i][j] = val;
2107 }
2108 }
2109 }
2110
2111 static
rtw89_phy_ant_gain_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)2112 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev,
2113 u32 center_freq)
2114 {
2115 switch (center_freq) {
2116 default:
2117 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2118 "center freq: %u to antenna gain subband is unhandled\n",
2119 center_freq);
2120 fallthrough;
2121 case 2412 ... 2484:
2122 return RTW89_ANT_GAIN_2GHZ_SUBBAND;
2123 case 5180 ... 5240:
2124 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1;
2125 case 5250 ... 5320:
2126 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2;
2127 case 5500 ... 5720:
2128 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E;
2129 case 5745 ... 5885:
2130 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4;
2131 case 5955 ... 6155:
2132 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L;
2133 case 6175 ... 6415:
2134 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H;
2135 case 6435 ... 6515:
2136 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6;
2137 case 6535 ... 6695:
2138 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L;
2139 case 6715 ... 6855:
2140 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H;
2141
2142 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H
2143 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with
2144 * struct rtw89_6ghz_span.
2145 */
2146
2147 case 6895 ... 7115:
2148 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8;
2149 }
2150 }
2151
rtw89_phy_ant_gain_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u32 center_freq)2152 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev,
2153 enum rtw89_rf_path path, u32 center_freq)
2154 {
2155 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2156 enum rtw89_ant_gain_subband subband_l, subband_h;
2157 const struct rtw89_6ghz_span *span;
2158
2159 span = rtw89_get_6ghz_span(rtwdev, center_freq);
2160
2161 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) {
2162 subband_l = span->ant_gain_subband_low;
2163 subband_h = span->ant_gain_subband_high;
2164 } else {
2165 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq);
2166 subband_h = subband_l;
2167 }
2168
2169 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2170 "center_freq %u: antenna gain subband {%u, %u}\n",
2171 center_freq, subband_l, subband_h);
2172
2173 return min(ant_gain->offset[path][subband_l],
2174 ant_gain->offset[path][subband_h]);
2175 }
2176
rtw89_phy_ant_gain_offset(struct rtw89_dev * rtwdev,u32 center_freq)2177 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u32 center_freq)
2178 {
2179 s8 offset_patha, offset_pathb;
2180
2181 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq);
2182 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq);
2183
2184 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2185 return min(offset_patha, offset_pathb);
2186
2187 return max(offset_patha, offset_pathb);
2188 }
2189
rtw89_can_apply_ant_gain(struct rtw89_dev * rtwdev,u8 band)2190 static bool rtw89_can_apply_ant_gain(struct rtw89_dev *rtwdev, u8 band)
2191 {
2192 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2193 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2194 const struct rtw89_chip_info *chip = rtwdev->chip;
2195 u8 regd = rtw89_regd_get(rtwdev, band);
2196
2197 if (!chip->support_ant_gain)
2198 return false;
2199
2200 if (ant_gain->block_country || !(ant_gain->regd_enabled & BIT(regd)))
2201 return false;
2202
2203 if (!rfe_parms->has_da)
2204 return false;
2205
2206 return true;
2207 }
2208
rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2209 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
2210 const struct rtw89_chan *chan)
2211 {
2212 s8 offset_patha, offset_pathb;
2213
2214 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type))
2215 return 0;
2216
2217 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2218 return 0;
2219
2220 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2221 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2222
2223 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb);
2224 }
2225 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset);
2226
rtw89_print_ant_gain(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_chan * chan)2227 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
2228 const struct rtw89_chan *chan)
2229 {
2230 char *p = buf, *end = buf + bufsz;
2231 s8 offset_patha, offset_pathb;
2232
2233 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type)) {
2234 p += scnprintf(p, end - p, "no DAG is applied\n");
2235 goto out;
2236 }
2237
2238 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2239 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2240
2241 p += scnprintf(p, end - p, "ChainA offset: %d dBm\n", offset_patha);
2242 p += scnprintf(p, end - p, "ChainB offset: %d dBm\n", offset_pathb);
2243
2244 out:
2245 return p - buf;
2246 }
2247
2248 static const u8 rtw89_rs_idx_num_ax[] = {
2249 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
2250 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
2251 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
2252 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
2253 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
2254 };
2255
2256 static const u8 rtw89_rs_nss_num_ax[] = {
2257 [RTW89_RS_CCK] = 1,
2258 [RTW89_RS_OFDM] = 1,
2259 [RTW89_RS_MCS] = RTW89_NSS_NUM,
2260 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
2261 [RTW89_RS_OFFSET] = 1,
2262 };
2263
rtw89_phy_raw_byr_seek(struct rtw89_dev * rtwdev,struct rtw89_txpwr_byrate * head,const struct rtw89_rate_desc * desc)2264 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
2265 struct rtw89_txpwr_byrate *head,
2266 const struct rtw89_rate_desc *desc)
2267 {
2268 switch (desc->rs) {
2269 case RTW89_RS_CCK:
2270 return &head->cck[desc->idx];
2271 case RTW89_RS_OFDM:
2272 return &head->ofdm[desc->idx];
2273 case RTW89_RS_MCS:
2274 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
2275 case RTW89_RS_HEDCM:
2276 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
2277 case RTW89_RS_OFFSET:
2278 return &head->offset[desc->idx];
2279 default:
2280 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
2281 return &head->trap;
2282 }
2283 }
2284
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)2285 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
2286 const struct rtw89_txpwr_table *tbl)
2287 {
2288 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
2289 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
2290 struct rtw89_txpwr_byrate *byr_head;
2291 struct rtw89_rate_desc desc = {};
2292 s8 *byr;
2293 u32 data;
2294 u8 i;
2295
2296 for (; cfg < end; cfg++) {
2297 byr_head = &rtwdev->byr[cfg->band][0];
2298 desc.rs = cfg->rs;
2299 desc.nss = cfg->nss;
2300 data = cfg->data;
2301
2302 for (i = 0; i < cfg->len; i++, data >>= 8) {
2303 desc.idx = cfg->shf + i;
2304 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
2305 *byr = data & 0xff;
2306 }
2307 }
2308 }
2309 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
2310
rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)2311 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
2312 {
2313 const u8 tssi_deviation_point = 0;
2314 const u8 tssi_max_deviation = 2;
2315
2316 if (dbm <= tssi_deviation_point)
2317 dbm -= tssi_max_deviation;
2318
2319 return dbm;
2320 }
2321
rtw89_phy_get_tpe_constraint(struct rtw89_dev * rtwdev,u8 band)2322 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
2323 {
2324 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2325 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
2326 s8 cstr = S8_MAX;
2327
2328 if (band == RTW89_BAND_6G && tpe->valid)
2329 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
2330
2331 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
2332 }
2333
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,u8 bw,const struct rtw89_rate_desc * rate_desc)2334 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
2335 const struct rtw89_rate_desc *rate_desc)
2336 {
2337 struct rtw89_txpwr_byrate *byr_head;
2338 s8 *byr;
2339
2340 if (rate_desc->rs == RTW89_RS_CCK)
2341 band = RTW89_BAND_2G;
2342
2343 byr_head = &rtwdev->byr[band][bw];
2344 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
2345
2346 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
2347 }
2348
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)2349 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
2350 {
2351 switch (channel_6g) {
2352 case 1 ... 29:
2353 return (channel_6g - 1) / 2;
2354 case 33 ... 61:
2355 return (channel_6g - 3) / 2;
2356 case 65 ... 93:
2357 return (channel_6g - 5) / 2;
2358 case 97 ... 125:
2359 return (channel_6g - 7) / 2;
2360 case 129 ... 157:
2361 return (channel_6g - 9) / 2;
2362 case 161 ... 189:
2363 return (channel_6g - 11) / 2;
2364 case 193 ... 221:
2365 return (channel_6g - 13) / 2;
2366 case 225 ... 253:
2367 return (channel_6g - 15) / 2;
2368 default:
2369 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
2370 return 0;
2371 }
2372 }
2373
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)2374 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
2375 {
2376 if (band == RTW89_BAND_6G)
2377 return rtw89_channel_6g_to_idx(rtwdev, channel);
2378
2379 switch (channel) {
2380 case 1 ... 14:
2381 return channel - 1;
2382 case 36 ... 64:
2383 return (channel - 36) / 2;
2384 case 100 ... 144:
2385 return ((channel - 100) / 2) + 15;
2386 case 149 ... 177:
2387 return ((channel - 149) / 2) + 38;
2388 default:
2389 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
2390 return 0;
2391 }
2392 }
2393
rtw89_phy_validate_txpwr_limit_bw(struct rtw89_dev * rtwdev,u8 band,u8 bw)2394 static bool rtw89_phy_validate_txpwr_limit_bw(struct rtw89_dev *rtwdev,
2395 u8 band, u8 bw)
2396 {
2397 switch (band) {
2398 case RTW89_BAND_2G:
2399 return bw < RTW89_2G_BW_NUM;
2400 case RTW89_BAND_5G:
2401 return bw < RTW89_5G_BW_NUM;
2402 case RTW89_BAND_6G:
2403 return bw < RTW89_6G_BW_NUM;
2404 default:
2405 return false;
2406 }
2407 }
2408
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)2409 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2410 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
2411 {
2412 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2413 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz;
2414 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz;
2415 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz;
2416 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2417 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2418 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2419 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2420 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2421 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band);
2422 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2423 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2424 s8 lmt = 0, da_lmt = S8_MAX, sar, offset = 0;
2425 u8 regd = rtw89_regd_get(rtwdev, band);
2426 u8 reg6 = regulatory->reg_6ghz_power;
2427 struct rtw89_sar_parm sar_parm = {
2428 .center_freq = freq,
2429 .ntx = ntx,
2430 };
2431 s8 cstr;
2432
2433 if (!rtw89_phy_validate_txpwr_limit_bw(rtwdev, band, bw)) {
2434 rtw89_warn(rtwdev, "invalid band %u bandwidth %u\n", band, bw);
2435 return 0;
2436 }
2437
2438 switch (band) {
2439 case RTW89_BAND_2G:
2440 if (has_ant_gain)
2441 da_lmt = (*rule_da_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2442
2443 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2444 if (lmt)
2445 break;
2446
2447 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2448 break;
2449 case RTW89_BAND_5G:
2450 if (has_ant_gain)
2451 da_lmt = (*rule_da_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2452
2453 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2454 if (lmt)
2455 break;
2456
2457 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2458 break;
2459 case RTW89_BAND_6G:
2460 if (has_ant_gain)
2461 da_lmt = (*rule_da_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2462
2463 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2464 if (lmt)
2465 break;
2466
2467 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2468 [RTW89_REG_6GHZ_POWER_DFLT]
2469 [ch_idx];
2470 break;
2471 default:
2472 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2473 return 0;
2474 }
2475
2476 da_lmt = da_lmt ?: S8_MAX;
2477 if (da_lmt != S8_MAX)
2478 offset = rtw89_phy_ant_gain_offset(rtwdev, freq);
2479
2480 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt + offset, da_lmt));
2481 sar = rtw89_query_sar(rtwdev, &sar_parm);
2482 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2483
2484 return min3(lmt, sar, cstr);
2485 }
2486 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
2487
2488 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2489 do { \
2490 u8 __i; \
2491 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
2492 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2493 band, \
2494 bw, ntx, \
2495 rs, __i, \
2496 (ch)); \
2497 } while (0)
2498
rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch)2499 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2500 struct rtw89_txpwr_limit_ax *lmt,
2501 u8 band, u8 ntx, u8 ch)
2502 {
2503 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2504 ntx, RTW89_RS_CCK, ch);
2505 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2506 ntx, RTW89_RS_CCK, ch);
2507 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2508 ntx, RTW89_RS_OFDM, ch);
2509 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2510 RTW89_CHANNEL_WIDTH_20,
2511 ntx, RTW89_RS_MCS, ch);
2512 }
2513
rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2514 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2515 struct rtw89_txpwr_limit_ax *lmt,
2516 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2517 {
2518 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2519 ntx, RTW89_RS_CCK, ch - 2);
2520 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2521 ntx, RTW89_RS_CCK, ch);
2522 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2523 ntx, RTW89_RS_OFDM, pri_ch);
2524 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2525 RTW89_CHANNEL_WIDTH_20,
2526 ntx, RTW89_RS_MCS, ch - 2);
2527 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2528 RTW89_CHANNEL_WIDTH_20,
2529 ntx, RTW89_RS_MCS, ch + 2);
2530 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2531 RTW89_CHANNEL_WIDTH_40,
2532 ntx, RTW89_RS_MCS, ch);
2533 }
2534
rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2535 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2536 struct rtw89_txpwr_limit_ax *lmt,
2537 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2538 {
2539 s8 val_0p5_n[RTW89_BF_NUM];
2540 s8 val_0p5_p[RTW89_BF_NUM];
2541 u8 i;
2542
2543 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2544 ntx, RTW89_RS_OFDM, pri_ch);
2545 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2546 RTW89_CHANNEL_WIDTH_20,
2547 ntx, RTW89_RS_MCS, ch - 6);
2548 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2549 RTW89_CHANNEL_WIDTH_20,
2550 ntx, RTW89_RS_MCS, ch - 2);
2551 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2552 RTW89_CHANNEL_WIDTH_20,
2553 ntx, RTW89_RS_MCS, ch + 2);
2554 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2555 RTW89_CHANNEL_WIDTH_20,
2556 ntx, RTW89_RS_MCS, ch + 6);
2557 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2558 RTW89_CHANNEL_WIDTH_40,
2559 ntx, RTW89_RS_MCS, ch - 4);
2560 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2561 RTW89_CHANNEL_WIDTH_40,
2562 ntx, RTW89_RS_MCS, ch + 4);
2563 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2564 RTW89_CHANNEL_WIDTH_80,
2565 ntx, RTW89_RS_MCS, ch);
2566
2567 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2568 ntx, RTW89_RS_MCS, ch - 4);
2569 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2570 ntx, RTW89_RS_MCS, ch + 4);
2571
2572 for (i = 0; i < RTW89_BF_NUM; i++)
2573 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2574 }
2575
rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2576 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2577 struct rtw89_txpwr_limit_ax *lmt,
2578 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2579 {
2580 s8 val_0p5_n[RTW89_BF_NUM];
2581 s8 val_0p5_p[RTW89_BF_NUM];
2582 s8 val_2p5_n[RTW89_BF_NUM];
2583 s8 val_2p5_p[RTW89_BF_NUM];
2584 u8 i;
2585
2586 /* fill ofdm section */
2587 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2588 ntx, RTW89_RS_OFDM, pri_ch);
2589
2590 /* fill mcs 20m section */
2591 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2592 RTW89_CHANNEL_WIDTH_20,
2593 ntx, RTW89_RS_MCS, ch - 14);
2594 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2595 RTW89_CHANNEL_WIDTH_20,
2596 ntx, RTW89_RS_MCS, ch - 10);
2597 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2598 RTW89_CHANNEL_WIDTH_20,
2599 ntx, RTW89_RS_MCS, ch - 6);
2600 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2601 RTW89_CHANNEL_WIDTH_20,
2602 ntx, RTW89_RS_MCS, ch - 2);
2603 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2604 RTW89_CHANNEL_WIDTH_20,
2605 ntx, RTW89_RS_MCS, ch + 2);
2606 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2607 RTW89_CHANNEL_WIDTH_20,
2608 ntx, RTW89_RS_MCS, ch + 6);
2609 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2610 RTW89_CHANNEL_WIDTH_20,
2611 ntx, RTW89_RS_MCS, ch + 10);
2612 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2613 RTW89_CHANNEL_WIDTH_20,
2614 ntx, RTW89_RS_MCS, ch + 14);
2615
2616 /* fill mcs 40m section */
2617 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2618 RTW89_CHANNEL_WIDTH_40,
2619 ntx, RTW89_RS_MCS, ch - 12);
2620 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2621 RTW89_CHANNEL_WIDTH_40,
2622 ntx, RTW89_RS_MCS, ch - 4);
2623 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2624 RTW89_CHANNEL_WIDTH_40,
2625 ntx, RTW89_RS_MCS, ch + 4);
2626 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2627 RTW89_CHANNEL_WIDTH_40,
2628 ntx, RTW89_RS_MCS, ch + 12);
2629
2630 /* fill mcs 80m section */
2631 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2632 RTW89_CHANNEL_WIDTH_80,
2633 ntx, RTW89_RS_MCS, ch - 8);
2634 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2635 RTW89_CHANNEL_WIDTH_80,
2636 ntx, RTW89_RS_MCS, ch + 8);
2637
2638 /* fill mcs 160m section */
2639 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2640 RTW89_CHANNEL_WIDTH_160,
2641 ntx, RTW89_RS_MCS, ch);
2642
2643 /* fill mcs 40m 0p5 section */
2644 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2645 ntx, RTW89_RS_MCS, ch - 4);
2646 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2647 ntx, RTW89_RS_MCS, ch + 4);
2648
2649 for (i = 0; i < RTW89_BF_NUM; i++)
2650 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2651
2652 /* fill mcs 40m 2p5 section */
2653 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2654 ntx, RTW89_RS_MCS, ch - 8);
2655 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2656 ntx, RTW89_RS_MCS, ch + 8);
2657
2658 for (i = 0; i < RTW89_BF_NUM; i++)
2659 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2660 }
2661
2662 static
rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ax * lmt,u8 ntx)2663 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2664 const struct rtw89_chan *chan,
2665 struct rtw89_txpwr_limit_ax *lmt,
2666 u8 ntx)
2667 {
2668 u8 band = chan->band_type;
2669 u8 pri_ch = chan->primary_channel;
2670 u8 ch = chan->channel;
2671 u8 bw = chan->band_width;
2672
2673 memset(lmt, 0, sizeof(*lmt));
2674
2675 switch (bw) {
2676 case RTW89_CHANNEL_WIDTH_20:
2677 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2678 break;
2679 case RTW89_CHANNEL_WIDTH_40:
2680 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2681 pri_ch);
2682 break;
2683 case RTW89_CHANNEL_WIDTH_80:
2684 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2685 pri_ch);
2686 break;
2687 case RTW89_CHANNEL_WIDTH_160:
2688 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2689 pri_ch);
2690 break;
2691 }
2692 }
2693
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)2694 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2695 u8 ru, u8 ntx, u8 ch)
2696 {
2697 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2698 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz;
2699 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz;
2700 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz;
2701 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2702 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2703 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2704 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2705 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2706 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band);
2707 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2708 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2709 s8 lmt_ru = 0, da_lmt_ru = S8_MAX, sar, offset = 0;
2710 u8 regd = rtw89_regd_get(rtwdev, band);
2711 u8 reg6 = regulatory->reg_6ghz_power;
2712 struct rtw89_sar_parm sar_parm = {
2713 .center_freq = freq,
2714 .ntx = ntx,
2715 };
2716 s8 cstr;
2717
2718 switch (band) {
2719 case RTW89_BAND_2G:
2720 if (has_ant_gain)
2721 da_lmt_ru = (*rule_da_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2722
2723 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2724 if (lmt_ru)
2725 break;
2726
2727 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2728 break;
2729 case RTW89_BAND_5G:
2730 if (has_ant_gain)
2731 da_lmt_ru = (*rule_da_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2732
2733 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2734 if (lmt_ru)
2735 break;
2736
2737 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2738 break;
2739 case RTW89_BAND_6G:
2740 if (has_ant_gain)
2741 da_lmt_ru = (*rule_da_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2742
2743 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2744 if (lmt_ru)
2745 break;
2746
2747 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2748 [RTW89_REG_6GHZ_POWER_DFLT]
2749 [ch_idx];
2750 break;
2751 default:
2752 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2753 return 0;
2754 }
2755
2756 da_lmt_ru = da_lmt_ru ?: S8_MAX;
2757 if (da_lmt_ru != S8_MAX)
2758 offset = rtw89_phy_ant_gain_offset(rtwdev, freq);
2759
2760 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt_ru + offset, da_lmt_ru));
2761 sar = rtw89_query_sar(rtwdev, &sar_parm);
2762 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2763
2764 return min3(lmt_ru, sar, cstr);
2765 }
2766
2767 static void
rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2768 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2769 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2770 u8 band, u8 ntx, u8 ch)
2771 {
2772 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2773 RTW89_RU26,
2774 ntx, ch);
2775 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2776 RTW89_RU52,
2777 ntx, ch);
2778 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2779 RTW89_RU106,
2780 ntx, ch);
2781 }
2782
2783 static void
rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2784 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2785 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2786 u8 band, u8 ntx, u8 ch)
2787 {
2788 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2789 RTW89_RU26,
2790 ntx, ch - 2);
2791 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2792 RTW89_RU26,
2793 ntx, ch + 2);
2794 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2795 RTW89_RU52,
2796 ntx, ch - 2);
2797 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2798 RTW89_RU52,
2799 ntx, ch + 2);
2800 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2801 RTW89_RU106,
2802 ntx, ch - 2);
2803 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2804 RTW89_RU106,
2805 ntx, ch + 2);
2806 }
2807
2808 static void
rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2809 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2810 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2811 u8 band, u8 ntx, u8 ch)
2812 {
2813 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2814 RTW89_RU26,
2815 ntx, ch - 6);
2816 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2817 RTW89_RU26,
2818 ntx, ch - 2);
2819 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2820 RTW89_RU26,
2821 ntx, ch + 2);
2822 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2823 RTW89_RU26,
2824 ntx, ch + 6);
2825 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2826 RTW89_RU52,
2827 ntx, ch - 6);
2828 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2829 RTW89_RU52,
2830 ntx, ch - 2);
2831 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2832 RTW89_RU52,
2833 ntx, ch + 2);
2834 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2835 RTW89_RU52,
2836 ntx, ch + 6);
2837 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2838 RTW89_RU106,
2839 ntx, ch - 6);
2840 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2841 RTW89_RU106,
2842 ntx, ch - 2);
2843 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2844 RTW89_RU106,
2845 ntx, ch + 2);
2846 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2847 RTW89_RU106,
2848 ntx, ch + 6);
2849 }
2850
2851 static void
rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2852 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2853 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2854 u8 band, u8 ntx, u8 ch)
2855 {
2856 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2857 int i;
2858
2859 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2860 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) {
2861 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2862 RTW89_RU26,
2863 ntx,
2864 ch + ofst[i]);
2865 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2866 RTW89_RU52,
2867 ntx,
2868 ch + ofst[i]);
2869 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2870 RTW89_RU106,
2871 ntx,
2872 ch + ofst[i]);
2873 }
2874 }
2875
2876 static
rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 ntx)2877 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2878 const struct rtw89_chan *chan,
2879 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2880 u8 ntx)
2881 {
2882 u8 band = chan->band_type;
2883 u8 ch = chan->channel;
2884 u8 bw = chan->band_width;
2885
2886 memset(lmt_ru, 0, sizeof(*lmt_ru));
2887
2888 switch (bw) {
2889 case RTW89_CHANNEL_WIDTH_20:
2890 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2891 ch);
2892 break;
2893 case RTW89_CHANNEL_WIDTH_40:
2894 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2895 ch);
2896 break;
2897 case RTW89_CHANNEL_WIDTH_80:
2898 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2899 ch);
2900 break;
2901 case RTW89_CHANNEL_WIDTH_160:
2902 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2903 ch);
2904 break;
2905 }
2906 }
2907
rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2908 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
2909 const struct rtw89_chan *chan,
2910 enum rtw89_phy_idx phy_idx)
2911 {
2912 u8 max_nss_num = rtwdev->chip->rf_path_num;
2913 static const u8 rs[] = {
2914 RTW89_RS_CCK,
2915 RTW89_RS_OFDM,
2916 RTW89_RS_MCS,
2917 RTW89_RS_HEDCM,
2918 };
2919 struct rtw89_rate_desc cur = {};
2920 u8 band = chan->band_type;
2921 u8 ch = chan->channel;
2922 u32 addr, val;
2923 s8 v[4] = {};
2924 u8 i;
2925
2926 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2927 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
2928
2929 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
2930 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
2931 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
2932 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
2933
2934 addr = R_AX_PWR_BY_RATE;
2935 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
2936 for (i = 0; i < ARRAY_SIZE(rs); i++) {
2937 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
2938 continue;
2939
2940 cur.rs = rs[i];
2941 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
2942 cur.idx++) {
2943 v[cur.idx % 4] =
2944 rtw89_phy_read_txpwr_byrate(rtwdev,
2945 band, 0,
2946 &cur);
2947
2948 if ((cur.idx + 1) % 4)
2949 continue;
2950
2951 val = FIELD_PREP(GENMASK(7, 0), v[0]) |
2952 FIELD_PREP(GENMASK(15, 8), v[1]) |
2953 FIELD_PREP(GENMASK(23, 16), v[2]) |
2954 FIELD_PREP(GENMASK(31, 24), v[3]);
2955
2956 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2957 val);
2958 addr += 4;
2959 }
2960 }
2961 }
2962 }
2963
2964 static
rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2965 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
2966 const struct rtw89_chan *chan,
2967 enum rtw89_phy_idx phy_idx)
2968 {
2969 struct rtw89_rate_desc desc = {
2970 .nss = RTW89_NSS_1,
2971 .rs = RTW89_RS_OFFSET,
2972 };
2973 u8 band = chan->band_type;
2974 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
2975 u32 val;
2976
2977 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2978
2979 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++)
2980 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2981
2982 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5);
2983 val = FIELD_PREP(GENMASK(3, 0), v[0]) |
2984 FIELD_PREP(GENMASK(7, 4), v[1]) |
2985 FIELD_PREP(GENMASK(11, 8), v[2]) |
2986 FIELD_PREP(GENMASK(15, 12), v[3]) |
2987 FIELD_PREP(GENMASK(19, 16), v[4]);
2988
2989 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2990 GENMASK(19, 0), val);
2991 }
2992
rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2993 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2994 const struct rtw89_chan *chan,
2995 enum rtw89_phy_idx phy_idx)
2996 {
2997 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2998 struct rtw89_txpwr_limit_ax lmt;
2999 u8 ch = chan->channel;
3000 u8 bw = chan->band_width;
3001 const s8 *ptr;
3002 u32 addr, val;
3003 u8 i, j;
3004
3005 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
3006 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
3007
3008 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) !=
3009 RTW89_TXPWR_LMT_PAGE_SIZE_AX);
3010
3011 addr = R_AX_PWR_LMT;
3012 for (i = 0; i < max_ntx_num; i++) {
3013 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
3014
3015 ptr = (s8 *)&lmt;
3016 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX;
3017 j += 4, addr += 4, ptr += 4) {
3018 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
3019 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
3020 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
3021 FIELD_PREP(GENMASK(31, 24), ptr[3]);
3022
3023 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
3024 }
3025 }
3026 }
3027
rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)3028 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
3029 const struct rtw89_chan *chan,
3030 enum rtw89_phy_idx phy_idx)
3031 {
3032 u8 max_ntx_num = rtwdev->chip->rf_path_num;
3033 struct rtw89_txpwr_limit_ru_ax lmt_ru;
3034 u8 ch = chan->channel;
3035 u8 bw = chan->band_width;
3036 const s8 *ptr;
3037 u32 addr, val;
3038 u8 i, j;
3039
3040 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
3041 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
3042
3043 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) !=
3044 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX);
3045
3046 addr = R_AX_PWR_RU_LMT;
3047 for (i = 0; i < max_ntx_num; i++) {
3048 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
3049
3050 ptr = (s8 *)&lmt_ru;
3051 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX;
3052 j += 4, addr += 4, ptr += 4) {
3053 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
3054 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
3055 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
3056 FIELD_PREP(GENMASK(31, 24), ptr[3]);
3057
3058 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
3059 }
3060 }
3061 }
3062
3063 struct rtw89_phy_iter_ra_data {
3064 struct rtw89_dev *rtwdev;
3065 struct sk_buff *c2h;
3066 };
3067
__rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,struct rtw89_phy_iter_ra_data * ra_data)3068 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
3069 struct ieee80211_link_sta *link_sta,
3070 struct rtw89_phy_iter_ra_data *ra_data)
3071 {
3072 struct rtw89_dev *rtwdev = ra_data->rtwdev;
3073 const struct rtw89_c2h_ra_rpt *c2h =
3074 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
3075 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
3076 const struct rtw89_chip_info *chip = rtwdev->chip;
3077 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
3078 u8 mode, rate, bw, giltf, mac_id;
3079 u16 legacy_bitrate;
3080 bool valid;
3081 u8 mcs = 0;
3082 u8 t;
3083
3084 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
3085 if (mac_id != rtwsta_link->mac_id)
3086 return;
3087
3088 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
3089 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
3090 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
3091 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
3092
3093 if (format_v1) {
3094 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
3095 rate |= u8_encode_bits(t, BIT(7));
3096 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
3097 bw |= u8_encode_bits(t, BIT(2));
3098 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
3099 mode |= u8_encode_bits(t, BIT(2));
3100 }
3101
3102 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
3103 valid = rtw89_legacy_rate_to_bitrate(rtwdev, rate, &legacy_bitrate);
3104 if (!valid)
3105 return;
3106 }
3107
3108 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
3109
3110 switch (mode) {
3111 case RTW89_RA_RPT_MODE_LEGACY:
3112 ra_report->txrate.legacy = legacy_bitrate;
3113 break;
3114 case RTW89_RA_RPT_MODE_HT:
3115 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
3116 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
3117 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
3118 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
3119 else
3120 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
3121 ra_report->txrate.mcs = rate;
3122 if (giltf)
3123 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
3124 mcs = ra_report->txrate.mcs & 0x07;
3125 break;
3126 case RTW89_RA_RPT_MODE_VHT:
3127 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
3128 ra_report->txrate.mcs = format_v1 ?
3129 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
3130 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
3131 ra_report->txrate.nss = format_v1 ?
3132 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
3133 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
3134 if (giltf)
3135 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
3136 mcs = ra_report->txrate.mcs;
3137 break;
3138 case RTW89_RA_RPT_MODE_HE:
3139 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
3140 ra_report->txrate.mcs = format_v1 ?
3141 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
3142 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
3143 ra_report->txrate.nss = format_v1 ?
3144 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
3145 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
3146 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
3147 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
3148 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
3149 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
3150 else
3151 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
3152 mcs = ra_report->txrate.mcs;
3153 break;
3154 case RTW89_RA_RPT_MODE_EHT:
3155 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
3156 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
3157 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
3158 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
3159 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
3160 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
3161 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
3162 else
3163 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
3164 mcs = ra_report->txrate.mcs;
3165 break;
3166 }
3167
3168 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
3169 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
3170 ra_report->hw_rate = format_v1 ?
3171 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
3172 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
3173 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
3174 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
3175 ra_report->might_fallback_legacy = mcs <= 2;
3176 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
3177 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
3178 }
3179
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)3180 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
3181 {
3182 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
3183 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3184 struct rtw89_sta_link *rtwsta_link;
3185 struct ieee80211_link_sta *link_sta;
3186 unsigned int link_id;
3187
3188 rcu_read_lock();
3189
3190 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
3191 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
3192 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
3193 }
3194
3195 rcu_read_unlock();
3196 }
3197
3198 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3199 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3200 {
3201 struct rtw89_phy_iter_ra_data ra_data;
3202
3203 ra_data.rtwdev = rtwdev;
3204 ra_data.c2h = c2h;
3205 ieee80211_iterate_stations_atomic(rtwdev->hw,
3206 rtw89_phy_c2h_ra_rpt_iter,
3207 &ra_data);
3208 }
3209
3210 static
3211 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
3212 struct sk_buff *c2h, u32 len) = {
3213 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
3214 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
3215 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
3216 };
3217
3218 static void
rtw89_phy_c2h_lowrt_rty(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3219 rtw89_phy_c2h_lowrt_rty(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3220 {
3221 }
3222
3223 static void
rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3224 rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3225 {
3226 const struct rtw89_c2h_fw_scan_rpt *c2h_rpt =
3227 (const struct rtw89_c2h_fw_scan_rpt *)c2h->data;
3228
3229 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3230 "%s: band: %u, op_chan: %u, PD_low_bd(ofdm, cck): (-%d, %d), phy_idx: %u\n",
3231 __func__, c2h_rpt->band, c2h_rpt->center_ch,
3232 PD_LOWER_BOUND_BASE - (c2h_rpt->ofdm_pd_idx << 1),
3233 c2h_rpt->cck_pd_idx, c2h_rpt->phy_idx);
3234 }
3235
3236 static
3237 void (* const rtw89_phy_c2h_dm_handler[])(struct rtw89_dev *rtwdev,
3238 struct sk_buff *c2h, u32 len) = {
3239 [RTW89_PHY_C2H_DM_FUNC_FW_TEST] = NULL,
3240 [RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT] = NULL,
3241 [RTW89_PHY_C2H_DM_FUNC_SIGB] = NULL,
3242 [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty,
3243 [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL,
3244 [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt,
3245 };
3246
3247 static
rtw89_phy_c2h_rfk_tas_pwr(struct rtw89_dev * rtwdev,const struct rtw89_c2h_rf_tas_rpt_log * content)3248 void rtw89_phy_c2h_rfk_tas_pwr(struct rtw89_dev *rtwdev,
3249 const struct rtw89_c2h_rf_tas_rpt_log *content)
3250 {
3251 const enum rtw89_sar_sources src = rtwdev->sar.src;
3252 struct rtw89_tas_info *tas = &rtwdev->tas;
3253 u64 linear = 0;
3254 u32 i, cur_idx;
3255 s16 txpwr;
3256
3257 if (!tas->enable || src == RTW89_SAR_SOURCE_NONE)
3258 return;
3259
3260 cur_idx = le32_to_cpu(content->cur_idx);
3261 for (i = 0; i < cur_idx; i++) {
3262 txpwr = le16_to_cpu(content->txpwr_history[i]);
3263 linear += rtw89_db_quarter_to_linear(txpwr);
3264
3265 rtw89_debug(rtwdev, RTW89_DBG_SAR,
3266 "tas: index: %u, txpwr: %d\n", i, txpwr);
3267 }
3268
3269 if (cur_idx == 0)
3270 tas->instant_txpwr = rtw89_db_to_linear(0);
3271 else
3272 tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx);
3273 }
3274
rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3275 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
3276 enum rtw89_phy_c2h_rfk_log_func func,
3277 void *content, u16 len)
3278 {
3279 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk;
3280 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck;
3281 struct rtw89_c2h_rf_dack_rpt_log *dack;
3282 struct rtw89_c2h_rf_tssi_rpt_log *tssi;
3283 struct rtw89_c2h_rf_dpk_rpt_log *dpk;
3284 struct rtw89_c2h_rf_iqk_rpt_log *iqk;
3285 int i, j, k;
3286
3287 switch (func) {
3288 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3289 if (len != sizeof(*iqk))
3290 goto out;
3291
3292 iqk = content;
3293 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3294 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init);
3295 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3296 "[IQK] iqk->is_reload = %x\n", iqk->is_reload);
3297 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3298 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk);
3299 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3300 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en);
3301 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3302 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en);
3303 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3304 "[IQK] iqk->lok_en = %x\n", iqk->lok_en);
3305 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3306 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en);
3307 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3308 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en);
3309 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3310 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en);
3311 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3312 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk);
3313 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3314 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable);
3315 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3316 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en);
3317 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3318 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en);
3319 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3320 "[IQK] iqk->version = %x\n", iqk->version);
3321 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3322 "[IQK] iqk->phy = %x\n", iqk->phy);
3323 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3324 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status);
3325
3326 for (i = 0; i < 2; i++) {
3327 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3328 "[IQK] ======== Path %x ========\n", i);
3329 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n",
3330 i, iqk->iqk_band[i]);
3331 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n",
3332 i, iqk->iqk_ch[i]);
3333 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n",
3334 i, iqk->iqk_bw[i]);
3335 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n",
3336 i, le32_to_cpu(iqk->lok_idac[i]));
3337 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n",
3338 i, le32_to_cpu(iqk->lok_vbuf[i]));
3339 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n",
3340 i, iqk->iqk_tx_fail[i]);
3341 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n",
3342 i, iqk->iqk_rx_fail[i]);
3343 for (j = 0; j < 4; j++)
3344 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3345 "[IQK] iqk->rftxgain[%d][%d] = %x\n",
3346 i, j, le32_to_cpu(iqk->rftxgain[i][j]));
3347 for (j = 0; j < 4; j++)
3348 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3349 "[IQK] iqk->tx_xym[%d][%d] = %x\n",
3350 i, j, le32_to_cpu(iqk->tx_xym[i][j]));
3351 for (j = 0; j < 4; j++)
3352 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3353 "[IQK] iqk->rfrxgain[%d][%d] = %x\n",
3354 i, j, le32_to_cpu(iqk->rfrxgain[i][j]));
3355 for (j = 0; j < 4; j++)
3356 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3357 "[IQK] iqk->rx_xym[%d][%d] = %x\n",
3358 i, j, le32_to_cpu(iqk->rx_xym[i][j]));
3359 }
3360 return;
3361 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3362 if (len != sizeof(*dpk))
3363 goto out;
3364
3365 dpk = content;
3366 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3367 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
3368 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
3369 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3370 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n",
3371 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
3372 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3373 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n",
3374 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
3375 return;
3376 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3377 if (len != sizeof(*dack))
3378 goto out;
3379
3380 dack = content;
3381
3382 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n");
3383 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3384 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n",
3385 dack->fwdack_ver, dack->fwdack_info_ver, 0x2);
3386
3387 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3388 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n",
3389 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout,
3390 dack->adgaink_timeout, dack->msbk_timeout);
3391 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3392 "[DACK]DACK fail = 0x%x\n", dack->dack_fail);
3393 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3394 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]);
3395 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3396 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]);
3397 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3398 "[DACK]DRCK = [0x%x]\n", dack->rck_d);
3399 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
3400 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
3401 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
3402 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
3403 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
3404 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
3405 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
3406 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
3407
3408 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
3409 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0],
3410 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]);
3411 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
3412 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0],
3413 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]);
3414 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
3415 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0],
3416 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]);
3417 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
3418 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0],
3419 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]);
3420
3421 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3422 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
3423 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3424 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
3425
3426 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3427 dack->dadck_d[0][0], dack->dadck_d[0][1]);
3428 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3429 dack->dadck_d[1][0], dack->dadck_d[1][1]);
3430
3431 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
3432 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]);
3433 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
3434 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]);
3435
3436 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
3437 for (i = 0; i < 0x10; i++)
3438 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3439 dack->msbk_d[0][0][i]);
3440
3441 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
3442 for (i = 0; i < 0x10; i++)
3443 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3444 dack->msbk_d[0][1][i]);
3445
3446 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
3447 for (i = 0; i < 0x10; i++)
3448 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3449 dack->msbk_d[1][0][i]);
3450
3451 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
3452 for (i = 0; i < 0x10; i++)
3453 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3454 dack->msbk_d[1][1][i]);
3455 return;
3456 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3457 if (len != sizeof(*rxdck))
3458 goto out;
3459
3460 rxdck = content;
3461 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3462 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
3463 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
3464 rxdck->timeout);
3465 return;
3466 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3467 if (len != sizeof(*tssi))
3468 goto out;
3469
3470 tssi = content;
3471 for (i = 0; i < 2; i++) {
3472 for (j = 0; j < 2; j++) {
3473 for (k = 0; k < 4; k++) {
3474 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3475 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n",
3476 i, j, k, tssi->alignment_power_cw_h[i][j][k]);
3477 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3478 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n",
3479 i, j, k, tssi->alignment_power_cw_l[i][j][k]);
3480 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3481 "[TSSI] alignment_power[%d][%d][%d]=%d\n",
3482 i, j, k, tssi->alignment_power[i][j][k]);
3483 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3484 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n",
3485 i, j, k,
3486 (tssi->alignment_power_cw_h[i][j][k] << 8) +
3487 tssi->alignment_power_cw_l[i][j][k]);
3488 }
3489
3490 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3491 "[TSSI] tssi_alimk_state[%d][%d]=%d\n",
3492 i, j, tssi->tssi_alimk_state[i][j]);
3493 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3494 "[TSSI] default_txagc_offset[%d]=%d\n",
3495 j, tssi->default_txagc_offset[0][j]);
3496 }
3497 }
3498 return;
3499 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3500 if (len != sizeof(*txgapk))
3501 goto out;
3502
3503 txgapk = content;
3504 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3505 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n",
3506 le32_to_cpu(txgapk->r0x8010[0]),
3507 le32_to_cpu(txgapk->r0x8010[1]));
3508 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
3509 txgapk->chk_id);
3510 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
3511 le32_to_cpu(txgapk->chk_cnt));
3512 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
3513 txgapk->ver);
3514 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n",
3515 txgapk->rsv1);
3516
3517 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
3518 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
3519 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
3520 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
3521 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
3522 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
3523 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
3524 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
3525 return;
3526 case RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR:
3527 if (len != sizeof(struct rtw89_c2h_rf_tas_rpt_log))
3528 goto out;
3529
3530 rtw89_phy_c2h_rfk_tas_pwr(rtwdev, content);
3531
3532 return;
3533 default:
3534 break;
3535 }
3536
3537 out:
3538 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3539 "unexpected RFK func %d report log with length %d\n", func, len);
3540 }
3541
rtw89_phy_c2h_rfk_run_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3542 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
3543 enum rtw89_phy_c2h_rfk_log_func func,
3544 void *content, u16 len)
3545 {
3546 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
3547 const struct rtw89_c2h_rf_run_log *log = content;
3548 const struct rtw89_fw_element_hdr *elm;
3549 u32 fmt_idx;
3550 u16 offset;
3551
3552 if (sizeof(*log) != len)
3553 return false;
3554
3555 if (!elm_info->rfk_log_fmt)
3556 return false;
3557
3558 elm = elm_info->rfk_log_fmt->elm[func];
3559 fmt_idx = le32_to_cpu(log->fmt_idx);
3560 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
3561 return false;
3562
3563 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
3564 if (offset == 0)
3565 return false;
3566
3567 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
3568 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
3569 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
3570
3571 return true;
3572 }
3573
rtw89_phy_c2h_rfk_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len,enum rtw89_phy_c2h_rfk_log_func func,const char * rfk_name)3574 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3575 u32 len, enum rtw89_phy_c2h_rfk_log_func func,
3576 const char *rfk_name)
3577 {
3578 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
3579 struct rtw89_c2h_rf_log_hdr *log_hdr;
3580 #if defined(__linux__)
3581 void *log_ptr = c2h_hdr;
3582 #elif defined(__FreeBSD__)
3583 u8 *log_ptr = (void *)c2h_hdr;
3584 #endif
3585 u16 content_len;
3586 u16 chunk_len;
3587 bool handled;
3588
3589 log_ptr += sizeof(*c2h_hdr);
3590 len -= sizeof(*c2h_hdr);
3591
3592 while (len > sizeof(*log_hdr)) {
3593 #if defined(__linux__)
3594 log_hdr = log_ptr;
3595 #elif defined(__FreeBSD__)
3596 log_hdr = (void *)log_ptr;
3597 #endif
3598 content_len = le16_to_cpu(log_hdr->len);
3599 chunk_len = content_len + sizeof(*log_hdr);
3600
3601 if (chunk_len > len)
3602 break;
3603
3604 switch (log_hdr->type) {
3605 case RTW89_RF_RUN_LOG:
3606 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
3607 log_hdr->content, content_len);
3608 if (handled)
3609 break;
3610
3611 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
3612 rfk_name, content_len, log_hdr->content);
3613 break;
3614 case RTW89_RF_RPT_LOG:
3615 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
3616 log_hdr->content, content_len);
3617 break;
3618 default:
3619 return;
3620 }
3621
3622 log_ptr += chunk_len;
3623 len -= chunk_len;
3624 }
3625 }
3626
3627 static void
rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3628 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3629 {
3630 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3631 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK");
3632 }
3633
3634 static void
rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3635 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3636 {
3637 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3638 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK");
3639 }
3640
3641 static void
rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3642 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3643 {
3644 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3645 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK");
3646 }
3647
3648 static void
rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3649 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3650 {
3651 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3652 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK");
3653 }
3654
3655 static void
rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3656 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3657 {
3658 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3659 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI");
3660 }
3661
3662 static void
rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3663 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3664 {
3665 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3666 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK");
3667 }
3668
3669 static void
rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3670 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3671 {
3672 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3673 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR, "TAS");
3674 }
3675
3676 static
3677 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
3678 struct sk_buff *c2h, u32 len) = {
3679 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk,
3680 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk,
3681 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack,
3682 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck,
3683 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi,
3684 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk,
3685 [RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr,
3686 };
3687
3688 static
rtw89_phy_rfk_report_prep(struct rtw89_dev * rtwdev)3689 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
3690 {
3691 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3692
3693 wait->state = RTW89_RFK_STATE_START;
3694 wait->start_time = ktime_get();
3695 reinit_completion(&wait->completion);
3696 }
3697
3698 static
rtw89_phy_rfk_report_wait(struct rtw89_dev * rtwdev,const char * rfk_name,unsigned int ms)3699 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
3700 unsigned int ms)
3701 {
3702 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3703 unsigned long time_left;
3704
3705 /* Since we can't receive C2H event during SER, use a fixed delay. */
3706 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3707 fsleep(1000 * ms / 2);
3708 goto out;
3709 }
3710
3711 time_left = wait_for_completion_timeout(&wait->completion,
3712 msecs_to_jiffies(ms));
3713 if (time_left == 0) {
3714 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
3715 return -ETIMEDOUT;
3716 } else if (wait->state != RTW89_RFK_STATE_OK) {
3717 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
3718 rfk_name, wait->state);
3719 return -EFAULT;
3720 }
3721
3722 out:
3723 #if defined(__linux__)
3724 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3725 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3726 #elif defined(__FreeBSD__)
3727 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %jd ms to complete\n",
3728 rfk_name, ktime_ms_delta(ktime_get(), (intmax_t)wait->start_time));
3729 #endif
3730
3731 return 0;
3732 }
3733
3734 static void
rtw89_phy_c2h_rfk_report_state(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3735 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3736 {
3737 const struct rtw89_c2h_rfk_report *report =
3738 (const struct rtw89_c2h_rfk_report *)c2h->data;
3739 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3740
3741 wait->state = report->state;
3742 wait->version = report->version;
3743
3744 complete(&wait->completion);
3745
3746 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3747 "RFK report state %d with version %d (%*ph)\n",
3748 wait->state, wait->version,
3749 (int)(len - sizeof(report->hdr)), &report->state);
3750 }
3751
3752 static void
rtw89_phy_c2h_rfk_report_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3753 rtw89_phy_c2h_rfk_report_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3754 {
3755 const struct rtw89_c2h_rf_tas_info *report =
3756 (const struct rtw89_c2h_rf_tas_info *)c2h->data;
3757
3758 rtw89_phy_c2h_rfk_tas_pwr(rtwdev, &report->content);
3759 }
3760
3761 static
3762 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3763 struct sk_buff *c2h, u32 len) = {
3764 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state,
3765 [RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_report_tas_pwr,
3766 };
3767
rtw89_phy_c2h_chk_atomic(struct rtw89_dev * rtwdev,u8 class,u8 func)3768 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
3769 {
3770 switch (class) {
3771 case RTW89_PHY_C2H_RFK_LOG:
3772 switch (func) {
3773 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3774 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3775 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3776 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3777 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3778 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3779 return true;
3780 default:
3781 return false;
3782 }
3783 case RTW89_PHY_C2H_RFK_REPORT:
3784 switch (func) {
3785 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE:
3786 return true;
3787 default:
3788 return false;
3789 }
3790 default:
3791 return false;
3792 }
3793 }
3794
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3795 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3796 u32 len, u8 class, u8 func)
3797 {
3798 void (*handler)(struct rtw89_dev *rtwdev,
3799 struct sk_buff *c2h, u32 len) = NULL;
3800
3801 switch (class) {
3802 case RTW89_PHY_C2H_CLASS_RA:
3803 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
3804 handler = rtw89_phy_c2h_ra_handler[func];
3805 break;
3806 case RTW89_PHY_C2H_RFK_LOG:
3807 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler))
3808 handler = rtw89_phy_c2h_rfk_log_handler[func];
3809 break;
3810 case RTW89_PHY_C2H_RFK_REPORT:
3811 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler))
3812 handler = rtw89_phy_c2h_rfk_report_handler[func];
3813 break;
3814 case RTW89_PHY_C2H_CLASS_DM:
3815 if (func < ARRAY_SIZE(rtw89_phy_c2h_dm_handler))
3816 handler = rtw89_phy_c2h_dm_handler[func];
3817 break;
3818 default:
3819 break;
3820 }
3821 if (!handler) {
3822 rtw89_info_once(rtwdev, "PHY c2h class %d func %d not support\n",
3823 class, func);
3824 return;
3825 }
3826 handler(rtwdev, skb, len);
3827 }
3828
rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,unsigned int ms)3829 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
3830 enum rtw89_phy_idx phy_idx,
3831 unsigned int ms)
3832 {
3833 int ret;
3834
3835 rtw89_phy_rfk_report_prep(rtwdev);
3836
3837 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3838 if (ret)
3839 return ret;
3840
3841 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3842 }
3843 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
3844
rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)3845 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
3846 enum rtw89_phy_idx phy_idx,
3847 const struct rtw89_chan *chan,
3848 enum rtw89_tssi_mode tssi_mode,
3849 unsigned int ms)
3850 {
3851 int ret;
3852
3853 rtw89_phy_rfk_report_prep(rtwdev);
3854
3855 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
3856 if (ret)
3857 return ret;
3858
3859 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
3860 }
3861 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait);
3862
rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3863 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
3864 enum rtw89_phy_idx phy_idx,
3865 const struct rtw89_chan *chan,
3866 unsigned int ms)
3867 {
3868 int ret;
3869
3870 rtw89_phy_rfk_report_prep(rtwdev);
3871
3872 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
3873 if (ret)
3874 return ret;
3875
3876 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
3877 }
3878 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait);
3879
rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3880 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
3881 enum rtw89_phy_idx phy_idx,
3882 const struct rtw89_chan *chan,
3883 unsigned int ms)
3884 {
3885 int ret;
3886
3887 rtw89_phy_rfk_report_prep(rtwdev);
3888
3889 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
3890 if (ret)
3891 return ret;
3892
3893 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
3894 }
3895 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait);
3896
rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3897 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
3898 enum rtw89_phy_idx phy_idx,
3899 const struct rtw89_chan *chan,
3900 unsigned int ms)
3901 {
3902 int ret;
3903
3904 rtw89_phy_rfk_report_prep(rtwdev);
3905
3906 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
3907 if (ret)
3908 return ret;
3909
3910 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
3911 }
3912 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait);
3913
rtw89_phy_rfk_dack_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3914 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
3915 enum rtw89_phy_idx phy_idx,
3916 const struct rtw89_chan *chan,
3917 unsigned int ms)
3918 {
3919 int ret;
3920
3921 rtw89_phy_rfk_report_prep(rtwdev);
3922
3923 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
3924 if (ret)
3925 return ret;
3926
3927 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
3928 }
3929 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait);
3930
rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,bool is_chl_k,unsigned int ms)3931 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
3932 enum rtw89_phy_idx phy_idx,
3933 const struct rtw89_chan *chan,
3934 bool is_chl_k, unsigned int ms)
3935 {
3936 int ret;
3937
3938 rtw89_phy_rfk_report_prep(rtwdev);
3939
3940 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k);
3941 if (ret)
3942 return ret;
3943
3944 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
3945 }
3946 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait);
3947
phy_tssi_get_cck_group(u8 ch)3948 static u32 phy_tssi_get_cck_group(u8 ch)
3949 {
3950 switch (ch) {
3951 case 1 ... 2:
3952 return 0;
3953 case 3 ... 5:
3954 return 1;
3955 case 6 ... 8:
3956 return 2;
3957 case 9 ... 11:
3958 return 3;
3959 case 12 ... 13:
3960 return 4;
3961 case 14:
3962 return 5;
3963 }
3964
3965 return 0;
3966 }
3967
3968 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31)
3969 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx))
3970 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT)
3971 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \
3972 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT)
3973 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \
3974 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
3975
phy_tssi_get_ofdm_group(u8 ch)3976 static u32 phy_tssi_get_ofdm_group(u8 ch)
3977 {
3978 switch (ch) {
3979 case 1 ... 2:
3980 return 0;
3981 case 3 ... 5:
3982 return 1;
3983 case 6 ... 8:
3984 return 2;
3985 case 9 ... 11:
3986 return 3;
3987 case 12 ... 14:
3988 return 4;
3989 case 36 ... 40:
3990 return 5;
3991 case 41 ... 43:
3992 return PHY_TSSI_EXTRA_GROUP(5);
3993 case 44 ... 48:
3994 return 6;
3995 case 49 ... 51:
3996 return PHY_TSSI_EXTRA_GROUP(6);
3997 case 52 ... 56:
3998 return 7;
3999 case 57 ... 59:
4000 return PHY_TSSI_EXTRA_GROUP(7);
4001 case 60 ... 64:
4002 return 8;
4003 case 100 ... 104:
4004 return 9;
4005 case 105 ... 107:
4006 return PHY_TSSI_EXTRA_GROUP(9);
4007 case 108 ... 112:
4008 return 10;
4009 case 113 ... 115:
4010 return PHY_TSSI_EXTRA_GROUP(10);
4011 case 116 ... 120:
4012 return 11;
4013 case 121 ... 123:
4014 return PHY_TSSI_EXTRA_GROUP(11);
4015 case 124 ... 128:
4016 return 12;
4017 case 129 ... 131:
4018 return PHY_TSSI_EXTRA_GROUP(12);
4019 case 132 ... 136:
4020 return 13;
4021 case 137 ... 139:
4022 return PHY_TSSI_EXTRA_GROUP(13);
4023 case 140 ... 144:
4024 return 14;
4025 case 149 ... 153:
4026 return 15;
4027 case 154 ... 156:
4028 return PHY_TSSI_EXTRA_GROUP(15);
4029 case 157 ... 161:
4030 return 16;
4031 case 162 ... 164:
4032 return PHY_TSSI_EXTRA_GROUP(16);
4033 case 165 ... 169:
4034 return 17;
4035 case 170 ... 172:
4036 return PHY_TSSI_EXTRA_GROUP(17);
4037 case 173 ... 177:
4038 return 18;
4039 }
4040
4041 return 0;
4042 }
4043
phy_tssi_get_6g_ofdm_group(u8 ch)4044 static u32 phy_tssi_get_6g_ofdm_group(u8 ch)
4045 {
4046 switch (ch) {
4047 case 1 ... 5:
4048 return 0;
4049 case 6 ... 8:
4050 return PHY_TSSI_EXTRA_GROUP(0);
4051 case 9 ... 13:
4052 return 1;
4053 case 14 ... 16:
4054 return PHY_TSSI_EXTRA_GROUP(1);
4055 case 17 ... 21:
4056 return 2;
4057 case 22 ... 24:
4058 return PHY_TSSI_EXTRA_GROUP(2);
4059 case 25 ... 29:
4060 return 3;
4061 case 33 ... 37:
4062 return 4;
4063 case 38 ... 40:
4064 return PHY_TSSI_EXTRA_GROUP(4);
4065 case 41 ... 45:
4066 return 5;
4067 case 46 ... 48:
4068 return PHY_TSSI_EXTRA_GROUP(5);
4069 case 49 ... 53:
4070 return 6;
4071 case 54 ... 56:
4072 return PHY_TSSI_EXTRA_GROUP(6);
4073 case 57 ... 61:
4074 return 7;
4075 case 65 ... 69:
4076 return 8;
4077 case 70 ... 72:
4078 return PHY_TSSI_EXTRA_GROUP(8);
4079 case 73 ... 77:
4080 return 9;
4081 case 78 ... 80:
4082 return PHY_TSSI_EXTRA_GROUP(9);
4083 case 81 ... 85:
4084 return 10;
4085 case 86 ... 88:
4086 return PHY_TSSI_EXTRA_GROUP(10);
4087 case 89 ... 93:
4088 return 11;
4089 case 97 ... 101:
4090 return 12;
4091 case 102 ... 104:
4092 return PHY_TSSI_EXTRA_GROUP(12);
4093 case 105 ... 109:
4094 return 13;
4095 case 110 ... 112:
4096 return PHY_TSSI_EXTRA_GROUP(13);
4097 case 113 ... 117:
4098 return 14;
4099 case 118 ... 120:
4100 return PHY_TSSI_EXTRA_GROUP(14);
4101 case 121 ... 125:
4102 return 15;
4103 case 129 ... 133:
4104 return 16;
4105 case 134 ... 136:
4106 return PHY_TSSI_EXTRA_GROUP(16);
4107 case 137 ... 141:
4108 return 17;
4109 case 142 ... 144:
4110 return PHY_TSSI_EXTRA_GROUP(17);
4111 case 145 ... 149:
4112 return 18;
4113 case 150 ... 152:
4114 return PHY_TSSI_EXTRA_GROUP(18);
4115 case 153 ... 157:
4116 return 19;
4117 case 161 ... 165:
4118 return 20;
4119 case 166 ... 168:
4120 return PHY_TSSI_EXTRA_GROUP(20);
4121 case 169 ... 173:
4122 return 21;
4123 case 174 ... 176:
4124 return PHY_TSSI_EXTRA_GROUP(21);
4125 case 177 ... 181:
4126 return 22;
4127 case 182 ... 184:
4128 return PHY_TSSI_EXTRA_GROUP(22);
4129 case 185 ... 189:
4130 return 23;
4131 case 193 ... 197:
4132 return 24;
4133 case 198 ... 200:
4134 return PHY_TSSI_EXTRA_GROUP(24);
4135 case 201 ... 205:
4136 return 25;
4137 case 206 ... 208:
4138 return PHY_TSSI_EXTRA_GROUP(25);
4139 case 209 ... 213:
4140 return 26;
4141 case 214 ... 216:
4142 return PHY_TSSI_EXTRA_GROUP(26);
4143 case 217 ... 221:
4144 return 27;
4145 case 225 ... 229:
4146 return 28;
4147 case 230 ... 232:
4148 return PHY_TSSI_EXTRA_GROUP(28);
4149 case 233 ... 237:
4150 return 29;
4151 case 238 ... 240:
4152 return PHY_TSSI_EXTRA_GROUP(29);
4153 case 241 ... 245:
4154 return 30;
4155 case 246 ... 248:
4156 return PHY_TSSI_EXTRA_GROUP(30);
4157 case 249 ... 253:
4158 return 31;
4159 }
4160
4161 return 0;
4162 }
4163
phy_tssi_get_trim_group(u8 ch)4164 static u32 phy_tssi_get_trim_group(u8 ch)
4165 {
4166 switch (ch) {
4167 case 1 ... 8:
4168 return 0;
4169 case 9 ... 14:
4170 return 1;
4171 case 36 ... 48:
4172 return 2;
4173 case 49 ... 51:
4174 return PHY_TSSI_EXTRA_GROUP(2);
4175 case 52 ... 64:
4176 return 3;
4177 case 100 ... 112:
4178 return 4;
4179 case 113 ... 115:
4180 return PHY_TSSI_EXTRA_GROUP(4);
4181 case 116 ... 128:
4182 return 5;
4183 case 132 ... 144:
4184 return 6;
4185 case 149 ... 177:
4186 return 7;
4187 }
4188
4189 return 0;
4190 }
4191
phy_tssi_get_6g_trim_group(u8 ch)4192 static u32 phy_tssi_get_6g_trim_group(u8 ch)
4193 {
4194 switch (ch) {
4195 case 1 ... 13:
4196 return 0;
4197 case 14 ... 16:
4198 return PHY_TSSI_EXTRA_GROUP(0);
4199 case 17 ... 29:
4200 return 1;
4201 case 33 ... 45:
4202 return 2;
4203 case 46 ... 48:
4204 return PHY_TSSI_EXTRA_GROUP(2);
4205 case 49 ... 61:
4206 return 3;
4207 case 65 ... 77:
4208 return 4;
4209 case 78 ... 80:
4210 return PHY_TSSI_EXTRA_GROUP(4);
4211 case 81 ... 93:
4212 return 5;
4213 case 97 ... 109:
4214 return 6;
4215 case 110 ... 112:
4216 return PHY_TSSI_EXTRA_GROUP(6);
4217 case 113 ... 125:
4218 return 7;
4219 case 129 ... 141:
4220 return 8;
4221 case 142 ... 144:
4222 return PHY_TSSI_EXTRA_GROUP(8);
4223 case 145 ... 157:
4224 return 9;
4225 case 161 ... 173:
4226 return 10;
4227 case 174 ... 176:
4228 return PHY_TSSI_EXTRA_GROUP(10);
4229 case 177 ... 189:
4230 return 11;
4231 case 193 ... 205:
4232 return 12;
4233 case 206 ... 208:
4234 return PHY_TSSI_EXTRA_GROUP(12);
4235 case 209 ... 221:
4236 return 13;
4237 case 225 ... 237:
4238 return 14;
4239 case 238 ... 240:
4240 return PHY_TSSI_EXTRA_GROUP(14);
4241 case 241 ... 253:
4242 return 15;
4243 }
4244
4245 return 0;
4246 }
4247
phy_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4248 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
4249 enum rtw89_phy_idx phy,
4250 const struct rtw89_chan *chan,
4251 enum rtw89_rf_path path)
4252 {
4253 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4254 enum rtw89_band band = chan->band_type;
4255 u8 ch = chan->channel;
4256 u32 gidx_1st;
4257 u32 gidx_2nd;
4258 s8 de_1st;
4259 s8 de_2nd;
4260 u32 gidx;
4261 s8 val;
4262
4263 if (band == RTW89_BAND_6G)
4264 goto calc_6g;
4265
4266 gidx = phy_tssi_get_ofdm_group(ch);
4267
4268 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4269 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4270 path, gidx);
4271
4272 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4273 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4274 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4275 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
4276 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
4277 val = (de_1st + de_2nd) / 2;
4278
4279 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4280 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4281 path, val, de_1st, de_2nd);
4282 } else {
4283 val = tssi_info->tssi_mcs[path][gidx];
4284
4285 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4286 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4287 }
4288
4289 return val;
4290
4291 calc_6g:
4292 gidx = phy_tssi_get_6g_ofdm_group(ch);
4293
4294 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4295 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4296 path, gidx);
4297
4298 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4299 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4300 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4301 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
4302 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
4303 val = (de_1st + de_2nd) / 2;
4304
4305 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4306 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4307 path, val, de_1st, de_2nd);
4308 } else {
4309 val = tssi_info->tssi_6g_mcs[path][gidx];
4310
4311 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4312 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4313 }
4314
4315 return val;
4316 }
4317
phy_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4318 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
4319 enum rtw89_phy_idx phy,
4320 const struct rtw89_chan *chan,
4321 enum rtw89_rf_path path)
4322 {
4323 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4324 enum rtw89_band band = chan->band_type;
4325 u8 ch = chan->channel;
4326 u32 tgidx_1st;
4327 u32 tgidx_2nd;
4328 s8 tde_1st;
4329 s8 tde_2nd;
4330 u32 tgidx;
4331 s8 val;
4332
4333 if (band == RTW89_BAND_6G)
4334 goto calc_6g;
4335
4336 tgidx = phy_tssi_get_trim_group(ch);
4337
4338 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4339 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4340 path, tgidx);
4341
4342 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4343 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4344 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4345 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
4346 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
4347 val = (tde_1st + tde_2nd) / 2;
4348
4349 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4350 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4351 path, val, tde_1st, tde_2nd);
4352 } else {
4353 val = tssi_info->tssi_trim[path][tgidx];
4354
4355 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4356 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4357 path, val);
4358 }
4359
4360 return val;
4361
4362 calc_6g:
4363 tgidx = phy_tssi_get_6g_trim_group(ch);
4364
4365 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4366 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4367 path, tgidx);
4368
4369 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4370 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4371 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4372 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
4373 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
4374 val = (tde_1st + tde_2nd) / 2;
4375
4376 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4377 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4378 path, val, tde_1st, tde_2nd);
4379 } else {
4380 val = tssi_info->tssi_trim_6g[path][tgidx];
4381
4382 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4383 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4384 path, val);
4385 }
4386
4387 return val;
4388 }
4389
rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4390 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
4391 enum rtw89_phy_idx phy,
4392 const struct rtw89_chan *chan,
4393 struct rtw89_h2c_rf_tssi *h2c)
4394 {
4395 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4396 u8 ch = chan->channel;
4397 s8 trim_de;
4398 s8 ofdm_de;
4399 s8 cck_de;
4400 u8 gidx;
4401 s8 val;
4402 int i;
4403
4404 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
4405 phy, ch);
4406
4407 for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
4408 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
4409 h2c->curr_tssi_trim_de[i] = trim_de;
4410
4411 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4412 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de);
4413
4414 gidx = phy_tssi_get_cck_group(ch);
4415 cck_de = tssi_info->tssi_cck[i][gidx];
4416 val = u32_get_bits(cck_de + trim_de, 0xff);
4417
4418 h2c->curr_tssi_cck_de[i] = 0x0;
4419 h2c->curr_tssi_cck_de_20m[i] = val;
4420 h2c->curr_tssi_cck_de_40m[i] = val;
4421 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
4422
4423 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4424 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de);
4425
4426 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
4427 val = u32_get_bits(ofdm_de + trim_de, 0xff);
4428
4429 h2c->curr_tssi_ofdm_de[i] = 0x0;
4430 h2c->curr_tssi_ofdm_de_20m[i] = val;
4431 h2c->curr_tssi_ofdm_de_40m[i] = val;
4432 h2c->curr_tssi_ofdm_de_80m[i] = val;
4433 h2c->curr_tssi_ofdm_de_160m[i] = val;
4434 h2c->curr_tssi_ofdm_de_320m[i] = val;
4435 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
4436
4437 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4438 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de);
4439 }
4440 }
4441
rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4442 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
4443 enum rtw89_phy_idx phy,
4444 const struct rtw89_chan *chan,
4445 struct rtw89_h2c_rf_tssi *h2c)
4446 {
4447 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
4448 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4449 const s8 *thm_up[RF_PATH_B + 1] = {};
4450 const s8 *thm_down[RF_PATH_B + 1] = {};
4451 u8 subband = chan->subband_type;
4452 s8 thm_ofst[128] = {0};
4453 u8 thermal;
4454 u8 path;
4455 u8 i, j;
4456
4457 switch (subband) {
4458 default:
4459 case RTW89_CH_2G:
4460 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
4461 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
4462 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
4463 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
4464 break;
4465 case RTW89_CH_5G_BAND_1:
4466 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
4467 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
4468 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
4469 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
4470 break;
4471 case RTW89_CH_5G_BAND_3:
4472 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
4473 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
4474 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
4475 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
4476 break;
4477 case RTW89_CH_5G_BAND_4:
4478 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
4479 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
4480 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
4481 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
4482 break;
4483 case RTW89_CH_6G_BAND_IDX0:
4484 case RTW89_CH_6G_BAND_IDX1:
4485 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
4486 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
4487 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
4488 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
4489 break;
4490 case RTW89_CH_6G_BAND_IDX2:
4491 case RTW89_CH_6G_BAND_IDX3:
4492 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
4493 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
4494 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
4495 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
4496 break;
4497 case RTW89_CH_6G_BAND_IDX4:
4498 case RTW89_CH_6G_BAND_IDX5:
4499 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
4500 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
4501 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
4502 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
4503 break;
4504 case RTW89_CH_6G_BAND_IDX6:
4505 case RTW89_CH_6G_BAND_IDX7:
4506 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
4507 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
4508 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
4509 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
4510 break;
4511 }
4512
4513 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4514 "[TSSI] tmeter tbl on subband: %u\n", subband);
4515
4516 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
4517 thermal = tssi_info->thermal[path];
4518 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4519 "path: %u, pg thermal: 0x%x\n", path, thermal);
4520
4521 if (thermal == 0xff) {
4522 h2c->pg_thermal[path] = 0x38;
4523 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
4524 continue;
4525 }
4526
4527 h2c->pg_thermal[path] = thermal;
4528
4529 i = 0;
4530 for (j = 0; j < 64; j++)
4531 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4532 thm_up[path][i++] :
4533 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
4534
4535 i = 1;
4536 for (j = 127; j >= 64; j--)
4537 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4538 -thm_down[path][i++] :
4539 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
4540
4541 for (i = 0; i < 128; i += 4) {
4542 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
4543 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
4544 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
4545 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
4546
4547 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4548 "thm ofst [%x]: %02x %02x %02x %02x\n",
4549 i, thm_ofst[i], thm_ofst[i + 1],
4550 thm_ofst[i + 2], thm_ofst[i + 3]);
4551 }
4552 }
4553 }
4554
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)4555 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
4556 {
4557 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4558 u32 reg_mask;
4559
4560 if (sc_xo)
4561 reg_mask = xtal->sc_xo_mask;
4562 else
4563 reg_mask = xtal->sc_xi_mask;
4564
4565 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
4566 }
4567
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)4568 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
4569 u8 val)
4570 {
4571 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4572 u32 reg_mask;
4573
4574 if (sc_xo)
4575 reg_mask = xtal->sc_xo_mask;
4576 else
4577 reg_mask = xtal->sc_xi_mask;
4578
4579 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
4580 }
4581
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)4582 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
4583 u8 crystal_cap, bool force)
4584 {
4585 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4586 const struct rtw89_chip_info *chip = rtwdev->chip;
4587 u8 sc_xi_val, sc_xo_val;
4588
4589 if (!force && cfo->crystal_cap == crystal_cap)
4590 return;
4591 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
4592 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
4593 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
4594 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
4595 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
4596 } else {
4597 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
4598 crystal_cap, XTAL_SC_XO_MASK);
4599 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
4600 crystal_cap, XTAL_SC_XI_MASK);
4601 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
4602 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
4603 }
4604 cfo->crystal_cap = sc_xi_val;
4605 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
4606
4607 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
4608 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
4609 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
4610 cfo->x_cap_ofst);
4611 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
4612 }
4613
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)4614 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
4615 {
4616 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4617 u8 cap;
4618
4619 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
4620 cfo->is_adjust = false;
4621 if (cfo->crystal_cap == cfo->def_x_cap)
4622 return;
4623 cap = cfo->crystal_cap;
4624 cap += (cap > cfo->def_x_cap ? -1 : 1);
4625 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
4626 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4627 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
4628 cfo->def_x_cap);
4629 }
4630
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)4631 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
4632 {
4633 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
4634 bool is_linked = rtwdev->total_sta_assoc > 0;
4635 s32 cfo_avg_312;
4636 s32 dcfo_comp_val;
4637 int sign;
4638
4639 if (!dcfo_comp)
4640 return;
4641
4642 if (!is_linked) {
4643 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
4644 is_linked);
4645 return;
4646 }
4647 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
4648 if (curr_cfo == 0)
4649 return;
4650 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
4651 sign = curr_cfo > 0 ? 1 : -1;
4652 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val;
4653 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
4654 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
4655 cfo_avg_312 = -cfo_avg_312;
4656 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
4657 cfo_avg_312);
4658 }
4659
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)4660 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
4661 {
4662 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4663 const struct rtw89_chip_info *chip = rtwdev->chip;
4664 const struct rtw89_cfo_regs *cfo = phy->cfo;
4665
4666 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
4667 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
4668
4669 if (chip->chip_gen == RTW89_CHIP_AX) {
4670 if (chip->cfo_hw_comp) {
4671 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
4672 B_AX_PWR_UL_CFO_MASK, 0x6);
4673 } else {
4674 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
4675 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
4676 B_AX_PWR_UL_CFO_MASK);
4677 }
4678 }
4679 }
4680
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)4681 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
4682 {
4683 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4684 struct rtw89_efuse *efuse = &rtwdev->efuse;
4685
4686 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
4687 cfo->crystal_cap = cfo->crystal_cap_default;
4688 cfo->def_x_cap = cfo->crystal_cap;
4689 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4690 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4691 cfo->is_adjust = false;
4692 cfo->divergence_lock_en = false;
4693 cfo->x_cap_ofst = 0;
4694 cfo->lock_cnt = 0;
4695 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4696 cfo->apply_compensation = false;
4697 cfo->residual_cfo_acc = 0;
4698 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
4699 cfo->crystal_cap_default);
4700 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
4701 rtw89_dcfo_comp_init(rtwdev);
4702 cfo->cfo_timer_ms = 2000;
4703 cfo->cfo_trig_by_timer_en = false;
4704 cfo->phy_cfo_trk_cnt = 0;
4705 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4706 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
4707 }
4708
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)4709 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
4710 s32 curr_cfo)
4711 {
4712 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4713 int crystal_cap = cfo->crystal_cap;
4714 s32 cfo_abs = abs(curr_cfo);
4715 int sign;
4716
4717 if (curr_cfo == 0) {
4718 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
4719 return;
4720 }
4721 if (!cfo->is_adjust) {
4722 if (cfo_abs > CFO_TRK_ENABLE_TH)
4723 cfo->is_adjust = true;
4724 } else {
4725 if (cfo_abs <= CFO_TRK_STOP_TH)
4726 cfo->is_adjust = false;
4727 }
4728 if (!cfo->is_adjust) {
4729 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
4730 return;
4731 }
4732 sign = curr_cfo > 0 ? 1 : -1;
4733 if (cfo_abs > CFO_TRK_STOP_TH_4)
4734 crystal_cap += 3 * sign;
4735 else if (cfo_abs > CFO_TRK_STOP_TH_3)
4736 crystal_cap += 3 * sign;
4737 else if (cfo_abs > CFO_TRK_STOP_TH_2)
4738 crystal_cap += 1 * sign;
4739 else if (cfo_abs > CFO_TRK_STOP_TH_1)
4740 crystal_cap += 1 * sign;
4741 else
4742 return;
4743
4744 crystal_cap = clamp(crystal_cap, 0, 127);
4745 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
4746 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4747 "X_cap{Curr,Default}={0x%x,0x%x}\n",
4748 cfo->crystal_cap, cfo->def_x_cap);
4749 }
4750
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)4751 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
4752 {
4753 const struct rtw89_chip_info *chip = rtwdev->chip;
4754 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4755 s32 cfo_khz_all = 0;
4756 s32 cfo_cnt_all = 0;
4757 s32 cfo_all_avg = 0;
4758 u8 i;
4759
4760 if (rtwdev->total_sta_assoc != 1)
4761 return 0;
4762 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
4763 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4764 if (cfo->cfo_cnt[i] == 0)
4765 continue;
4766 cfo_khz_all += cfo->cfo_tail[i];
4767 cfo_cnt_all += cfo->cfo_cnt[i];
4768 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
4769 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4770 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
4771 cfo_cnt_all);
4772 }
4773 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4774 "CFO track for macid = %d\n", i);
4775 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4776 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
4777 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
4778 return cfo_all_avg;
4779 }
4780
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)4781 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
4782 {
4783 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4784 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4785 s32 target_cfo = 0;
4786 s32 cfo_khz_all = 0;
4787 s32 cfo_khz_all_tp_wgt = 0;
4788 s32 cfo_avg = 0;
4789 s32 max_cfo_lb = BIT(31);
4790 s32 min_cfo_ub = GENMASK(30, 0);
4791 u16 cfo_cnt_all = 0;
4792 u8 active_entry_cnt = 0;
4793 u8 sta_cnt = 0;
4794 u32 tp_all = 0;
4795 u8 i;
4796 u8 cfo_tol = 0;
4797
4798 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
4799 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
4800 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
4801 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4802 if (cfo->cfo_cnt[i] == 0)
4803 continue;
4804 cfo_khz_all += cfo->cfo_tail[i];
4805 cfo_cnt_all += cfo->cfo_cnt[i];
4806 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
4807 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4808 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
4809 cfo_khz_all, cfo_cnt_all, cfo_avg);
4810 target_cfo = cfo_avg;
4811 }
4812 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
4813 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
4814 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4815 if (cfo->cfo_cnt[i] == 0)
4816 continue;
4817 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4818 (s32)cfo->cfo_cnt[i]);
4819 cfo_khz_all += cfo->cfo_avg[i];
4820 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4821 "Macid=%d, cfo_avg=%d\n", i,
4822 cfo->cfo_avg[i]);
4823 }
4824 sta_cnt = rtwdev->total_sta_assoc;
4825 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
4826 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4827 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
4828 cfo_khz_all, sta_cnt, cfo_avg);
4829 target_cfo = cfo_avg;
4830 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
4831 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
4832 cfo_tol = cfo->sta_cfo_tolerance;
4833 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4834 sta_cnt++;
4835 if (cfo->cfo_cnt[i] != 0) {
4836 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4837 (s32)cfo->cfo_cnt[i]);
4838 active_entry_cnt++;
4839 } else {
4840 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
4841 }
4842 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
4843 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
4844 cfo_khz_all += cfo->cfo_avg[i];
4845 /* need tp for each entry */
4846 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4847 "[%d] cfo_avg=%d, tp=tbd\n",
4848 i, cfo->cfo_avg[i]);
4849 if (sta_cnt >= rtwdev->total_sta_assoc)
4850 break;
4851 }
4852 tp_all = stats->rx_throughput; /* need tp for each entry */
4853 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
4854
4855 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
4856 sta_cnt);
4857 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
4858 active_entry_cnt);
4859 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4860 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
4861 cfo_khz_all_tp_wgt, cfo_avg);
4862 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
4863 max_cfo_lb, min_cfo_ub);
4864 if (max_cfo_lb <= min_cfo_ub) {
4865 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4866 "cfo win_size=%d\n",
4867 min_cfo_ub - max_cfo_lb);
4868 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
4869 } else {
4870 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4871 "No intersection of cfo tolerance windows\n");
4872 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
4873 }
4874 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
4875 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4876 }
4877 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
4878 return target_cfo;
4879 }
4880
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)4881 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
4882 {
4883 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4884
4885 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
4886 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
4887 cfo->packet_count = 0;
4888 cfo->packet_count_pre = 0;
4889 cfo->cfo_avg_pre = 0;
4890 }
4891
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)4892 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
4893 {
4894 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4895 s32 new_cfo = 0;
4896 bool x_cap_update = false;
4897 u8 pre_x_cap = cfo->crystal_cap;
4898 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4899
4900 cfo->dcfo_avg = 0;
4901 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
4902 rtwdev->total_sta_assoc);
4903 if (rtwdev->total_sta_assoc == 0 || rtw89_is_mlo_1_1(rtwdev)) {
4904 rtw89_phy_cfo_reset(rtwdev);
4905 return;
4906 }
4907 if (cfo->packet_count == 0) {
4908 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
4909 return;
4910 }
4911 if (cfo->packet_count == cfo->packet_count_pre) {
4912 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
4913 return;
4914 }
4915 if (rtwdev->total_sta_assoc == 1)
4916 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
4917 else
4918 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
4919 if (cfo->divergence_lock_en) {
4920 cfo->lock_cnt++;
4921 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
4922 cfo->divergence_lock_en = false;
4923 cfo->lock_cnt = 0;
4924 } else {
4925 rtw89_phy_cfo_reset(rtwdev);
4926 }
4927 return;
4928 }
4929 if (cfo->crystal_cap >= cfo->x_cap_ub ||
4930 cfo->crystal_cap <= cfo->x_cap_lb) {
4931 cfo->divergence_lock_en = true;
4932 rtw89_phy_cfo_reset(rtwdev);
4933 return;
4934 }
4935
4936 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
4937 cfo->cfo_avg_pre = new_cfo;
4938 cfo->dcfo_avg_pre = cfo->dcfo_avg;
4939 x_cap_update = cfo->crystal_cap != pre_x_cap;
4940 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
4941 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4942 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
4943 cfo->x_cap_ofst);
4944 if (x_cap_update) {
4945 if (cfo->dcfo_avg > 0)
4946 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4947 else
4948 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4949 }
4950 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4951 rtw89_phy_cfo_statistics_reset(rtwdev);
4952 }
4953
rtw89_phy_cfo_track_work(struct wiphy * wiphy,struct wiphy_work * work)4954 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work)
4955 {
4956 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4957 cfo_track_work.work);
4958 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4959
4960 lockdep_assert_wiphy(wiphy);
4961
4962 if (!cfo->cfo_trig_by_timer_en)
4963 return;
4964 rtw89_leave_ps_mode(rtwdev);
4965 rtw89_phy_cfo_dm(rtwdev);
4966 wiphy_delayed_work_queue(wiphy, &rtwdev->cfo_track_work,
4967 msecs_to_jiffies(cfo->cfo_timer_ms));
4968 }
4969
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)4970 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
4971 {
4972 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4973
4974 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->cfo_track_work,
4975 msecs_to_jiffies(cfo->cfo_timer_ms));
4976 }
4977
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)4978 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
4979 {
4980 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4981 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4982 bool is_ul_ofdma = false, ofdma_acc_en = false;
4983
4984 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
4985 is_ul_ofdma = true;
4986 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
4987 is_ul_ofdma)
4988 ofdma_acc_en = true;
4989
4990 switch (cfo->phy_cfo_status) {
4991 case RTW89_PHY_DCFO_STATE_NORMAL:
4992 if (stats->tx_throughput >= CFO_TP_UPPER) {
4993 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
4994 cfo->cfo_trig_by_timer_en = true;
4995 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
4996 rtw89_phy_cfo_start_work(rtwdev);
4997 }
4998 break;
4999 case RTW89_PHY_DCFO_STATE_ENHANCE:
5000 if (stats->tx_throughput <= CFO_TP_LOWER)
5001 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5002 else if (ofdma_acc_en &&
5003 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
5004 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
5005 else
5006 cfo->phy_cfo_trk_cnt++;
5007
5008 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
5009 cfo->phy_cfo_trk_cnt = 0;
5010 cfo->cfo_trig_by_timer_en = false;
5011 }
5012 break;
5013 case RTW89_PHY_DCFO_STATE_HOLD:
5014 if (stats->tx_throughput <= CFO_TP_LOWER) {
5015 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5016 cfo->phy_cfo_trk_cnt = 0;
5017 cfo->cfo_trig_by_timer_en = false;
5018 } else {
5019 cfo->phy_cfo_trk_cnt++;
5020 }
5021 break;
5022 default:
5023 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5024 cfo->phy_cfo_trk_cnt = 0;
5025 break;
5026 }
5027 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5028 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
5029 stats->tx_throughput, cfo->phy_cfo_status,
5030 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
5031 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
5032 if (cfo->cfo_trig_by_timer_en)
5033 return;
5034 rtw89_phy_cfo_dm(rtwdev);
5035 }
5036
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)5037 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
5038 struct rtw89_rx_phy_ppdu *phy_ppdu)
5039 {
5040 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5041 u8 macid = phy_ppdu->mac_id;
5042
5043 if (macid >= CFO_TRACK_MAX_USER) {
5044 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
5045 return;
5046 }
5047
5048 cfo->cfo_tail[macid] += cfo_val;
5049 cfo->cfo_cnt[macid]++;
5050 cfo->packet_count++;
5051 }
5052
rtw89_phy_ul_tb_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5053 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
5054 {
5055 const struct rtw89_chip_info *chip = rtwdev->chip;
5056 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
5057 rtwvif_link->chanctx_idx);
5058 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5059
5060 if (!chip->ul_tb_waveform_ctrl)
5061 return;
5062
5063 rtwvif_link->def_tri_idx =
5064 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
5065
5066 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
5067 rtwvif_link->dyn_tb_bedge_en = false;
5068 else if (chan->band_type >= RTW89_BAND_5G &&
5069 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
5070 rtwvif_link->dyn_tb_bedge_en = true;
5071 else
5072 rtwvif_link->dyn_tb_bedge_en = false;
5073
5074 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5075 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
5076 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
5077 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5078 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
5079 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
5080 }
5081
5082 struct rtw89_phy_ul_tb_check_data {
5083 bool valid;
5084 bool high_tf_client;
5085 bool low_tf_client;
5086 bool dyn_tb_bedge_en;
5087 u8 def_tri_idx;
5088 };
5089
5090 struct rtw89_phy_power_diff {
5091 u32 q_00;
5092 u32 q_11;
5093 u32 q_matrix_en;
5094 u32 ultb_1t_norm_160;
5095 u32 ultb_2t_norm_160;
5096 u32 com1_norm_1sts;
5097 u32 com2_resp_1sts_path;
5098 };
5099
rtw89_phy_ofdma_power_diff(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5100 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
5101 struct rtw89_vif_link *rtwvif_link)
5102 {
5103 static const struct rtw89_phy_power_diff table[2] = {
5104 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3},
5105 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1},
5106 };
5107 const struct rtw89_phy_power_diff *param;
5108 u32 reg;
5109
5110 if (!rtwdev->chip->ul_tb_pwr_diff)
5111 return;
5112
5113 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
5114 rtwvif_link->pwr_diff_en = false;
5115 return;
5116 }
5117
5118 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
5119 param = &table[rtwvif_link->pwr_diff_en];
5120
5121 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
5122 param->q_00);
5123 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
5124 param->q_11);
5125 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
5126 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
5127
5128 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
5129 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
5130 param->ultb_1t_norm_160);
5131
5132 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
5133 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
5134 param->ultb_2t_norm_160);
5135
5136 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
5137 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
5138 param->com1_norm_1sts);
5139
5140 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
5141 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
5142 param->com2_resp_1sts_path);
5143 }
5144
5145 static
rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_phy_ul_tb_check_data * ul_tb_data)5146 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
5147 struct rtw89_vif_link *rtwvif_link,
5148 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
5149 {
5150 struct rtw89_traffic_stats *stats = &rtwdev->stats;
5151 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5152
5153 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
5154 return;
5155
5156 if (!vif->cfg.assoc)
5157 return;
5158
5159 if (rtwdev->chip->ul_tb_waveform_ctrl) {
5160 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
5161 ul_tb_data->high_tf_client = true;
5162 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
5163 ul_tb_data->low_tf_client = true;
5164
5165 ul_tb_data->valid = true;
5166 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
5167 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
5168 }
5169
5170 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link);
5171 }
5172
rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev * rtwdev,struct rtw89_phy_ul_tb_check_data * ul_tb_data)5173 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
5174 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
5175 {
5176 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5177
5178 if (!rtwdev->chip->ul_tb_waveform_ctrl)
5179 return;
5180
5181 if (ul_tb_data->dyn_tb_bedge_en) {
5182 if (ul_tb_data->high_tf_client) {
5183 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
5184 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5185 "[ULTB] Turn off if_bandedge\n");
5186 } else if (ul_tb_data->low_tf_client) {
5187 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
5188 ul_tb_info->def_if_bandedge);
5189 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5190 "[ULTB] Set to default if_bandedge = %d\n",
5191 ul_tb_info->def_if_bandedge);
5192 }
5193 }
5194
5195 if (ul_tb_info->dyn_tb_tri_en) {
5196 if (ul_tb_data->high_tf_client) {
5197 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
5198 B_TXSHAPE_TRIANGULAR_CFG, 0);
5199 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5200 "[ULTB] Turn off Tx triangle\n");
5201 } else if (ul_tb_data->low_tf_client) {
5202 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
5203 B_TXSHAPE_TRIANGULAR_CFG,
5204 ul_tb_data->def_tri_idx);
5205 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5206 "[ULTB] Set to default tx_shap_idx = %d\n",
5207 ul_tb_data->def_tri_idx);
5208 }
5209 }
5210 }
5211
rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev * rtwdev)5212 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
5213 {
5214 const struct rtw89_chip_info *chip = rtwdev->chip;
5215 struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
5216 struct rtw89_vif_link *rtwvif_link;
5217 struct rtw89_vif *rtwvif;
5218 unsigned int link_id;
5219
5220 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
5221 return;
5222
5223 if (rtwdev->total_sta_assoc != 1)
5224 return;
5225
5226 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5227 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
5228 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data);
5229
5230 if (!ul_tb_data.valid)
5231 return;
5232
5233 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
5234 }
5235
rtw89_phy_ul_tb_info_init(struct rtw89_dev * rtwdev)5236 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
5237 {
5238 const struct rtw89_chip_info *chip = rtwdev->chip;
5239 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5240
5241 if (!chip->ul_tb_waveform_ctrl)
5242 return;
5243
5244 ul_tb_info->dyn_tb_tri_en = true;
5245 ul_tb_info->def_if_bandedge =
5246 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
5247 }
5248
5249 static
rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats * antdiv_sts)5250 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
5251 {
5252 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
5253 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
5254 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
5255 antdiv_sts->pkt_cnt_cck = 0;
5256 antdiv_sts->pkt_cnt_ofdm = 0;
5257 antdiv_sts->pkt_cnt_non_legacy = 0;
5258 antdiv_sts->evm = 0;
5259 }
5260
rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_antdiv_stats * stats)5261 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
5262 struct rtw89_rx_phy_ppdu *phy_ppdu,
5263 struct rtw89_antdiv_stats *stats)
5264 {
5265 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
5266 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
5267 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
5268 stats->pkt_cnt_cck++;
5269 } else {
5270 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
5271 stats->pkt_cnt_ofdm++;
5272 stats->evm += phy_ppdu->ofdm.evm_min;
5273 }
5274 } else {
5275 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
5276 stats->pkt_cnt_non_legacy++;
5277 stats->evm += phy_ppdu->ofdm.evm_min;
5278 }
5279 }
5280
rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats * stats)5281 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
5282 {
5283 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
5284 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
5285 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
5286 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
5287 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
5288 return ewma_rssi_read(&stats->ofdm_rssi_avg);
5289 else
5290 return ewma_rssi_read(&stats->cck_rssi_avg);
5291 }
5292
rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats * stats)5293 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
5294 {
5295 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
5296 }
5297
rtw89_phy_antdiv_parse(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)5298 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
5299 struct rtw89_rx_phy_ppdu *phy_ppdu)
5300 {
5301 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5302 struct rtw89_hal *hal = &rtwdev->hal;
5303
5304 if (!hal->ant_diversity || hal->ant_diversity_fixed)
5305 return;
5306
5307 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
5308
5309 if (!antdiv->get_stats)
5310 return;
5311
5312 if (hal->antenna_rx == RF_A)
5313 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
5314 else if (hal->antenna_rx == RF_B)
5315 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
5316 }
5317
rtw89_phy_antdiv_reg_init(struct rtw89_dev * rtwdev)5318 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
5319 {
5320 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
5321 0x0, RTW89_PHY_0);
5322 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
5323 0x0, RTW89_PHY_0);
5324
5325 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
5326 0x0, RTW89_PHY_0);
5327 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
5328 0x0, RTW89_PHY_0);
5329
5330 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
5331 0x0, RTW89_PHY_0);
5332
5333 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
5334 0x0100, RTW89_PHY_0);
5335
5336 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
5337 0x1, RTW89_PHY_0);
5338 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
5339 0x0, RTW89_PHY_0);
5340 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
5341 0x0, RTW89_PHY_0);
5342 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
5343 0x0, RTW89_PHY_0);
5344 }
5345
rtw89_phy_antdiv_sts_reset(struct rtw89_dev * rtwdev)5346 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
5347 {
5348 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5349
5350 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
5351 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
5352 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
5353 }
5354
rtw89_phy_antdiv_init(struct rtw89_dev * rtwdev)5355 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
5356 {
5357 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5358 struct rtw89_hal *hal = &rtwdev->hal;
5359
5360 if (!hal->ant_diversity)
5361 return;
5362
5363 antdiv->get_stats = false;
5364 antdiv->rssi_pre = 0;
5365 rtw89_phy_antdiv_sts_reset(rtwdev);
5366 rtw89_phy_antdiv_reg_init(rtwdev);
5367 }
5368
rtw89_phy_thermal_protect(struct rtw89_dev * rtwdev)5369 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev)
5370 {
5371 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5372 struct rtw89_hal *hal = &rtwdev->hal;
5373 u8 th_max = phystat->last_thermal_max;
5374 u8 lv = hal->thermal_prot_lv;
5375
5376 if (!hal->thermal_prot_th ||
5377 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT)))
5378 return;
5379
5380 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX)
5381 lv++;
5382 else if (th_max < hal->thermal_prot_th - 2 && lv > 0)
5383 lv--;
5384 else
5385 return;
5386
5387 hal->thermal_prot_lv = lv;
5388
5389 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv);
5390
5391 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv);
5392 }
5393
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)5394 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
5395 {
5396 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5397 u8 th, th_max = 0;
5398 int i;
5399
5400 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
5401 th = rtw89_chip_get_thermal(rtwdev, i);
5402 if (th)
5403 ewma_thermal_add(&phystat->avg_thermal[i], th);
5404
5405 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
5406 "path(%d) thermal cur=%u avg=%ld", i, th,
5407 ewma_thermal_read(&phystat->avg_thermal[i]));
5408
5409 th_max = max(th_max, th);
5410 }
5411
5412 phystat->last_thermal_max = th_max;
5413 }
5414
5415 struct rtw89_phy_iter_rssi_data {
5416 struct rtw89_dev *rtwdev;
5417 bool rssi_changed;
5418 };
5419
5420 static
__rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link * rtwsta_link,struct rtw89_phy_iter_rssi_data * rssi_data)5421 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link,
5422 struct rtw89_phy_iter_rssi_data *rssi_data)
5423 {
5424 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
5425 struct rtw89_dev *rtwdev = rssi_data->rtwdev;
5426 struct rtw89_phy_ch_info *ch_info;
5427 struct rtw89_bb_ctx *bb;
5428 unsigned long rssi_curr;
5429
5430 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
5431 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
5432 ch_info = &bb->ch_info;
5433
5434 if (rssi_curr < ch_info->rssi_min) {
5435 ch_info->rssi_min = rssi_curr;
5436 ch_info->rssi_min_macid = rtwsta_link->mac_id;
5437 }
5438
5439 if (rtwsta_link->prev_rssi == 0) {
5440 rtwsta_link->prev_rssi = rssi_curr;
5441 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
5442 (3 << RSSI_FACTOR)) {
5443 rtwsta_link->prev_rssi = rssi_curr;
5444 rssi_data->rssi_changed = true;
5445 }
5446 }
5447
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)5448 static void rtw89_phy_stat_rssi_update_iter(void *data,
5449 struct ieee80211_sta *sta)
5450 {
5451 struct rtw89_phy_iter_rssi_data *rssi_data =
5452 (struct rtw89_phy_iter_rssi_data *)data;
5453 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
5454 struct rtw89_sta_link *rtwsta_link;
5455 unsigned int link_id;
5456
5457 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
5458 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data);
5459 }
5460
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)5461 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
5462 {
5463 struct rtw89_phy_iter_rssi_data rssi_data = {};
5464 struct rtw89_bb_ctx *bb;
5465
5466 rssi_data.rtwdev = rtwdev;
5467 rtw89_for_each_active_bb(rtwdev, bb)
5468 bb->ch_info.rssi_min = U8_MAX;
5469
5470 ieee80211_iterate_stations_atomic(rtwdev->hw,
5471 rtw89_phy_stat_rssi_update_iter,
5472 &rssi_data);
5473 if (rssi_data.rssi_changed)
5474 rtw89_btc_ntfy_wl_sta(rtwdev);
5475 }
5476
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)5477 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
5478 {
5479 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5480 int i;
5481
5482 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
5483 ewma_thermal_init(&phystat->avg_thermal[i]);
5484
5485 rtw89_phy_stat_thermal_update(rtwdev);
5486
5487 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5488 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
5489
5490 ewma_rssi_init(&phystat->bcn_rssi);
5491
5492 rtwdev->hal.thermal_prot_lv = 0;
5493 }
5494
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)5495 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
5496 {
5497 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5498
5499 rtw89_phy_stat_thermal_update(rtwdev);
5500 rtw89_phy_thermal_protect(rtwdev);
5501 rtw89_phy_stat_rssi_update(rtwdev);
5502
5503 phystat->last_pkt_stat = phystat->cur_pkt_stat;
5504 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5505 }
5506
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u32 time_us)5507 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev,
5508 struct rtw89_bb_ctx *bb, u32 time_us)
5509 {
5510 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5511
5512 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5513 }
5514
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 idx)5515 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev,
5516 struct rtw89_bb_ctx *bb, u16 idx)
5517 {
5518 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5519
5520 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5521 }
5522
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5523 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev,
5524 struct rtw89_bb_ctx *bb)
5525 {
5526 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5527 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5528 const struct rtw89_ccx_regs *ccx = phy->ccx;
5529
5530 env->ccx_manual_ctrl = false;
5531 env->ccx_ongoing = false;
5532 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5533 env->ccx_period = 0;
5534 env->ccx_unit_idx = RTW89_CCX_32_US;
5535
5536 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->en_mask, 1, bb->phy_idx);
5537 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1,
5538 bb->phy_idx);
5539 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5540 bb->phy_idx);
5541 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
5542 RTW89_CCX_EDCCA_BW20_0, bb->phy_idx);
5543 }
5544
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 report,u16 score)5545 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev,
5546 struct rtw89_bb_ctx *bb,
5547 u16 report, u16 score)
5548 {
5549 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5550 u32 numer = 0;
5551 u16 ret = 0;
5552
5553 numer = report * score + (env->ccx_period >> 1);
5554 if (env->ccx_period)
5555 ret = numer / env->ccx_period;
5556
5557 return ret >= score ? score - 1 : ret;
5558 }
5559
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)5560 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
5561 u16 time_ms, u32 *period,
5562 u32 *unit_idx)
5563 {
5564 u32 idx;
5565 u8 quotient;
5566
5567 if (time_ms >= CCX_MAX_PERIOD)
5568 time_ms = CCX_MAX_PERIOD;
5569
5570 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
5571
5572 if (quotient < 4)
5573 idx = RTW89_CCX_4_US;
5574 else if (quotient < 8)
5575 idx = RTW89_CCX_8_US;
5576 else if (quotient < 16)
5577 idx = RTW89_CCX_16_US;
5578 else
5579 idx = RTW89_CCX_32_US;
5580
5581 *unit_idx = idx;
5582 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
5583
5584 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5585 "[Trigger Time] period:%d, unit_idx:%d\n",
5586 *period, *unit_idx);
5587 }
5588
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5589 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev,
5590 struct rtw89_bb_ctx *bb)
5591 {
5592 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5593
5594 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5595 "lv:(%d)->(0)\n", env->ccx_rac_lv);
5596
5597 env->ccx_ongoing = false;
5598 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5599 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5600 }
5601
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)5602 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
5603 struct rtw89_bb_ctx *bb,
5604 struct rtw89_ccx_para_info *para)
5605 {
5606 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5607 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
5608 u8 i = 0;
5609 u16 *ifs_th_l = env->ifs_clm_th_l;
5610 u16 *ifs_th_h = env->ifs_clm_th_h;
5611 u32 ifs_th0_us = 0, ifs_th_times = 0;
5612 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
5613
5614 if (!is_update)
5615 goto ifs_update_finished;
5616
5617 switch (para->ifs_clm_app) {
5618 case RTW89_IFS_CLM_INIT:
5619 case RTW89_IFS_CLM_BACKGROUND:
5620 case RTW89_IFS_CLM_ACS:
5621 case RTW89_IFS_CLM_DBG:
5622 case RTW89_IFS_CLM_DIG:
5623 case RTW89_IFS_CLM_TDMA_DIG:
5624 ifs_th0_us = IFS_CLM_TH0_UPPER;
5625 ifs_th_times = IFS_CLM_TH_MUL;
5626 break;
5627 case RTW89_IFS_CLM_DBG_MANUAL:
5628 ifs_th0_us = para->ifs_clm_manual_th0;
5629 ifs_th_times = para->ifs_clm_manual_th_times;
5630 break;
5631 default:
5632 break;
5633 }
5634
5635 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
5636 * low[i] = high[i-1] + 1
5637 * high[i] = high[i-1] * ifs_th_times
5638 */
5639 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
5640 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
5641 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, bb,
5642 ifs_th0_us);
5643 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
5644 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
5645 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
5646 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, ifs_th_h_us[i]);
5647 }
5648
5649 ifs_update_finished:
5650 if (!is_update)
5651 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5652 "No need to update IFS_TH\n");
5653
5654 return is_update;
5655 }
5656
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5657 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev,
5658 struct rtw89_bb_ctx *bb)
5659 {
5660 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5661 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5662 const struct rtw89_ccx_regs *ccx = phy->ccx;
5663 u8 i = 0;
5664
5665 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
5666 env->ifs_clm_th_l[0], bb->phy_idx);
5667 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
5668 env->ifs_clm_th_l[1], bb->phy_idx);
5669 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
5670 env->ifs_clm_th_l[2], bb->phy_idx);
5671 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
5672 env->ifs_clm_th_l[3], bb->phy_idx);
5673
5674 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
5675 env->ifs_clm_th_h[0], bb->phy_idx);
5676 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
5677 env->ifs_clm_th_h[1], bb->phy_idx);
5678 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
5679 env->ifs_clm_th_h[2], bb->phy_idx);
5680 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
5681 env->ifs_clm_th_h[3], bb->phy_idx);
5682
5683 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5684 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5685 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
5686 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
5687 }
5688
__rtw89_phy_nhm_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5689 static void __rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev,
5690 struct rtw89_bb_ctx *bb)
5691 {
5692 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5693 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5694 const struct rtw89_ccx_regs *ccx = phy->ccx;
5695
5696 env->nhm_include_cca = false;
5697 env->nhm_mntr_time = 0;
5698 env->nhm_sum = 0;
5699
5700 rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_config, ccx->nhm_en_mask, bb->phy_idx);
5701 rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_method, ccx->nhm_pwr_method_msk,
5702 bb->phy_idx);
5703 }
5704
rtw89_phy_nhm_setting_init(struct rtw89_dev * rtwdev)5705 void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev)
5706 {
5707 const struct rtw89_chip_info *chip = rtwdev->chip;
5708 struct rtw89_bb_ctx *bb;
5709
5710 if (!chip->support_noise)
5711 return;
5712
5713 rtw89_for_each_active_bb(rtwdev, bb)
5714 __rtw89_phy_nhm_setting_init(rtwdev, bb);
5715 }
5716
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5717 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev,
5718 struct rtw89_bb_ctx *bb)
5719 {
5720 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5721 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5722 const struct rtw89_ccx_regs *ccx = phy->ccx;
5723 struct rtw89_ccx_para_info para = {};
5724
5725 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5726 env->ifs_clm_mntr_time = 0;
5727
5728 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
5729 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, ¶))
5730 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
5731
5732 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true,
5733 bb->phy_idx);
5734 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true,
5735 bb->phy_idx);
5736 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true,
5737 bb->phy_idx);
5738 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true,
5739 bb->phy_idx);
5740 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true,
5741 bb->phy_idx);
5742 }
5743
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,enum rtw89_env_racing_lv level)5744 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
5745 struct rtw89_bb_ctx *bb,
5746 enum rtw89_env_racing_lv level)
5747 {
5748 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5749 int ret = 0;
5750
5751 if (level >= RTW89_RAC_MAX_NUM) {
5752 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5753 "[WARNING] Wrong LV=%d\n", level);
5754 return -EINVAL;
5755 }
5756
5757 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5758 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
5759 env->ccx_rac_lv, level);
5760
5761 if (env->ccx_ongoing) {
5762 if (level <= env->ccx_rac_lv)
5763 ret = -EINVAL;
5764 else
5765 env->ccx_ongoing = false;
5766 }
5767
5768 if (ret == 0)
5769 env->ccx_rac_lv = level;
5770
5771 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
5772 !ret);
5773
5774 return ret;
5775 }
5776
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 sel)5777 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev,
5778 struct rtw89_bb_ctx *bb, u8 sel)
5779 {
5780 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5781 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5782 const struct rtw89_ccx_regs *ccx = phy->ccx;
5783
5784 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0,
5785 bb->phy_idx);
5786 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0,
5787 bb->phy_idx);
5788 if (sel & RTW89_PHY_ENV_MON_NHM)
5789 rtw89_phy_write32_idx_clr(rtwdev, ccx->nhm_config,
5790 ccx->nhm_en_mask, bb->phy_idx);
5791
5792 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1,
5793 bb->phy_idx);
5794 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5795 bb->phy_idx);
5796 if (sel & RTW89_PHY_ENV_MON_NHM)
5797 rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_config,
5798 ccx->nhm_en_mask, bb->phy_idx);
5799
5800 env->ccx_ongoing = true;
5801 }
5802
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5803 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev,
5804 struct rtw89_bb_ctx *bb)
5805 {
5806 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5807 u8 i = 0;
5808 u32 res = 0;
5809
5810 env->ifs_clm_tx_ratio =
5811 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_tx, PERCENT);
5812 env->ifs_clm_edcca_excl_cca_ratio =
5813 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_edcca_excl_cca,
5814 PERCENT);
5815 env->ifs_clm_cck_fa_ratio =
5816 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERCENT);
5817 env->ifs_clm_ofdm_fa_ratio =
5818 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERCENT);
5819 env->ifs_clm_cck_cca_excl_fa_ratio =
5820 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckcca_excl_fa,
5821 PERCENT);
5822 env->ifs_clm_ofdm_cca_excl_fa_ratio =
5823 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmcca_excl_fa,
5824 PERCENT);
5825 env->ifs_clm_cck_fa_permil =
5826 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERMIL);
5827 env->ifs_clm_ofdm_fa_permil =
5828 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERMIL);
5829
5830 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
5831 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
5832 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
5833 } else {
5834 env->ifs_clm_ifs_avg[i] =
5835 rtw89_phy_ccx_idx_to_us(rtwdev, bb,
5836 env->ifs_clm_avg[i]);
5837 }
5838
5839 res = rtw89_phy_ccx_idx_to_us(rtwdev, bb, env->ifs_clm_cca[i]);
5840 res += env->ifs_clm_his[i] >> 1;
5841 if (env->ifs_clm_his[i])
5842 res /= env->ifs_clm_his[i];
5843 else
5844 res = 0;
5845 env->ifs_clm_cca_avg[i] = res;
5846 }
5847
5848 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5849 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5850 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
5851 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5852 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
5853 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
5854 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5855 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
5856 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
5857 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5858 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
5859 env->ifs_clm_cck_cca_excl_fa_ratio,
5860 env->ifs_clm_ofdm_cca_excl_fa_ratio);
5861 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5862 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
5863 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5864 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
5865 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
5866 env->ifs_clm_cca_avg[i]);
5867 }
5868
rtw89_nhm_weighted_avg(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5869 static u8 rtw89_nhm_weighted_avg(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
5870 {
5871 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5872 u8 nhm_weight[RTW89_NHM_RPT_NUM];
5873 u32 nhm_weighted_sum = 0;
5874 u8 weight_zero;
5875 u8 i;
5876
5877 if (env->nhm_sum == 0)
5878 return 0;
5879
5880 weight_zero = clamp_t(u16, env->nhm_th[0] - RTW89_NHM_WEIGHT_OFFSET, 0, U8_MAX);
5881
5882 for (i = 0; i < RTW89_NHM_RPT_NUM; i++) {
5883 if (i == 0)
5884 nhm_weight[i] = weight_zero;
5885 else if (i == (RTW89_NHM_RPT_NUM - 1))
5886 nhm_weight[i] = env->nhm_th[i - 1] + RTW89_NHM_WEIGHT_OFFSET;
5887 else
5888 nhm_weight[i] = (env->nhm_th[i - 1] + env->nhm_th[i]) / 2;
5889 }
5890
5891 if (rtwdev->chip->chip_id == RTL8852A || rtwdev->chip->chip_id == RTL8852B ||
5892 rtwdev->chip->chip_id == RTL8852C) {
5893 if (env->nhm_th[RTW89_NHM_TH_NUM - 1] == RTW89_NHM_WA_TH) {
5894 nhm_weight[RTW89_NHM_RPT_NUM - 1] =
5895 env->nhm_th[RTW89_NHM_TH_NUM - 2] +
5896 RTW89_NHM_WEIGHT_OFFSET;
5897 nhm_weight[RTW89_NHM_RPT_NUM - 2] =
5898 nhm_weight[RTW89_NHM_RPT_NUM - 1];
5899 }
5900
5901 env->nhm_result[0] += env->nhm_result[RTW89_NHM_RPT_NUM - 1];
5902 env->nhm_result[RTW89_NHM_RPT_NUM - 1] = 0;
5903 }
5904
5905 for (i = 0; i < RTW89_NHM_RPT_NUM; i++)
5906 nhm_weighted_sum += env->nhm_result[i] * nhm_weight[i];
5907
5908 return (nhm_weighted_sum / env->nhm_sum) >> RTW89_NHM_TH_FACTOR;
5909 }
5910
__rtw89_phy_nhm_get_result(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,enum rtw89_band hw_band,u16 ch_hw_value)5911 static void __rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev,
5912 struct rtw89_bb_ctx *bb, enum rtw89_band hw_band,
5913 u16 ch_hw_value)
5914 {
5915 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5916 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5917 const struct rtw89_chip_info *chip = rtwdev->chip;
5918 const struct rtw89_ccx_regs *ccx = phy->ccx;
5919 struct ieee80211_supported_band *sband;
5920 const struct rtw89_reg_def *nhm_rpt;
5921 enum nl80211_band band;
5922 u32 sum = 0;
5923 u8 chan_idx;
5924 u8 nhm_pwr;
5925 u8 i;
5926
5927 if (!rtw89_phy_read32_idx(rtwdev, ccx->nhm, ccx->nhm_ready, bb->phy_idx)) {
5928 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "[NHM] Get NHM report Fail\n");
5929 return;
5930 }
5931
5932 for (i = 0; i < RTW89_NHM_RPT_NUM; i++) {
5933 nhm_rpt = &(*chip->nhm_report)[i];
5934
5935 env->nhm_result[i] =
5936 rtw89_phy_read32_idx(rtwdev, nhm_rpt->addr,
5937 nhm_rpt->mask, bb->phy_idx);
5938 sum += env->nhm_result[i];
5939 }
5940 env->nhm_sum = sum;
5941 nhm_pwr = rtw89_nhm_weighted_avg(rtwdev, bb);
5942
5943 if (!ch_hw_value)
5944 return;
5945
5946 band = rtw89_hw_to_nl80211_band(hw_band);
5947 sband = rtwdev->hw->wiphy->bands[band];
5948 if (!sband)
5949 return;
5950
5951 for (chan_idx = 0; chan_idx < sband->n_channels; chan_idx++) {
5952 struct ieee80211_channel *channel;
5953 struct rtw89_nhm_report *rpt;
5954 struct list_head *nhm_list;
5955
5956 channel = &sband->channels[chan_idx];
5957 if (channel->hw_value != ch_hw_value)
5958 continue;
5959
5960 rpt = &env->nhm_his[hw_band][chan_idx];
5961 nhm_list = &env->nhm_rpt_list;
5962
5963 rpt->channel = channel;
5964 rpt->noise = nhm_pwr;
5965
5966 if (list_empty(&rpt->list))
5967 list_add_tail(&rpt->list, nhm_list);
5968
5969 return;
5970 }
5971
5972 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "[NHM] channel not found\n");
5973 }
5974
rtw89_phy_nhm_get_result(struct rtw89_dev * rtwdev,enum rtw89_band hw_band,u16 ch_hw_value)5975 void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band,
5976 u16 ch_hw_value)
5977 {
5978 const struct rtw89_chip_info *chip = rtwdev->chip;
5979 struct rtw89_bb_ctx *bb;
5980
5981 if (!chip->support_noise)
5982 return;
5983
5984 rtw89_for_each_active_bb(rtwdev, bb)
5985 __rtw89_phy_nhm_get_result(rtwdev, bb, hw_band, ch_hw_value);
5986 }
5987
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5988 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev,
5989 struct rtw89_bb_ctx *bb)
5990 {
5991 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5992 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5993 const struct rtw89_ccx_regs *ccx = phy->ccx;
5994 u8 i = 0;
5995
5996 if (rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
5997 ccx->ifs_cnt_done_mask, bb->phy_idx) == 0) {
5998 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5999 "Get IFS_CLM report Fail\n");
6000 return false;
6001 }
6002
6003 env->ifs_clm_tx =
6004 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
6005 ccx->ifs_clm_tx_cnt_msk, bb->phy_idx);
6006 env->ifs_clm_edcca_excl_cca =
6007 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
6008 ccx->ifs_clm_edcca_excl_cca_fa_mask, bb->phy_idx);
6009 env->ifs_clm_cckcca_excl_fa =
6010 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
6011 ccx->ifs_clm_cckcca_excl_fa_mask, bb->phy_idx);
6012 env->ifs_clm_ofdmcca_excl_fa =
6013 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
6014 ccx->ifs_clm_ofdmcca_excl_fa_mask, bb->phy_idx);
6015 env->ifs_clm_cckfa =
6016 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
6017 ccx->ifs_clm_cck_fa_mask, bb->phy_idx);
6018 env->ifs_clm_ofdmfa =
6019 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
6020 ccx->ifs_clm_ofdm_fa_mask, bb->phy_idx);
6021
6022 env->ifs_clm_his[0] =
6023 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
6024 ccx->ifs_t1_his_mask, bb->phy_idx);
6025 env->ifs_clm_his[1] =
6026 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
6027 ccx->ifs_t2_his_mask, bb->phy_idx);
6028 env->ifs_clm_his[2] =
6029 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
6030 ccx->ifs_t3_his_mask, bb->phy_idx);
6031 env->ifs_clm_his[3] =
6032 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
6033 ccx->ifs_t4_his_mask, bb->phy_idx);
6034
6035 env->ifs_clm_avg[0] =
6036 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
6037 ccx->ifs_t1_avg_mask, bb->phy_idx);
6038 env->ifs_clm_avg[1] =
6039 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
6040 ccx->ifs_t2_avg_mask, bb->phy_idx);
6041 env->ifs_clm_avg[2] =
6042 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
6043 ccx->ifs_t3_avg_mask, bb->phy_idx);
6044 env->ifs_clm_avg[3] =
6045 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
6046 ccx->ifs_t4_avg_mask, bb->phy_idx);
6047
6048 env->ifs_clm_cca[0] =
6049 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
6050 ccx->ifs_t1_cca_mask, bb->phy_idx);
6051 env->ifs_clm_cca[1] =
6052 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
6053 ccx->ifs_t2_cca_mask, bb->phy_idx);
6054 env->ifs_clm_cca[2] =
6055 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
6056 ccx->ifs_t3_cca_mask, bb->phy_idx);
6057 env->ifs_clm_cca[3] =
6058 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
6059 ccx->ifs_t4_cca_mask, bb->phy_idx);
6060
6061 env->ifs_clm_total_ifs =
6062 rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
6063 ccx->ifs_total_mask, bb->phy_idx);
6064
6065 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
6066 env->ifs_clm_total_ifs);
6067 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6068 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
6069 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
6070 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6071 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
6072 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
6073 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6074 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
6075 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
6076
6077 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
6078 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
6079 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6080 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
6081 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
6082
6083 rtw89_phy_ifs_clm_get_utility(rtwdev, bb);
6084
6085 return true;
6086 }
6087
rtw89_phy_nhm_th_update(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6088 static void rtw89_phy_nhm_th_update(struct rtw89_dev *rtwdev,
6089 struct rtw89_bb_ctx *bb)
6090 {
6091 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6092 static const u8 nhm_th_11k[RTW89_NHM_RPT_NUM] = {
6093 18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60, 0
6094 };
6095 const struct rtw89_chip_info *chip = rtwdev->chip;
6096 const struct rtw89_reg_def *nhm_th;
6097 u8 i;
6098
6099 for (i = 0; i < RTW89_NHM_RPT_NUM; i++)
6100 env->nhm_th[i] = nhm_th_11k[i] << RTW89_NHM_TH_FACTOR;
6101
6102 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
6103 chip->chip_id == RTL8852C)
6104 env->nhm_th[RTW89_NHM_TH_NUM - 1] = RTW89_NHM_WA_TH;
6105
6106 for (i = 0; i < RTW89_NHM_TH_NUM; i++) {
6107 nhm_th = &(*chip->nhm_th)[i];
6108
6109 rtw89_phy_write32_idx(rtwdev, nhm_th->addr, nhm_th->mask,
6110 env->nhm_th[i], bb->phy_idx);
6111 }
6112 }
6113
rtw89_phy_nhm_set(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)6114 static int rtw89_phy_nhm_set(struct rtw89_dev *rtwdev,
6115 struct rtw89_bb_ctx *bb,
6116 struct rtw89_ccx_para_info *para)
6117 {
6118 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6119 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6120 const struct rtw89_ccx_regs *ccx = phy->ccx;
6121 u32 unit_idx = 0;
6122 u32 period = 0;
6123
6124 if (para->mntr_time == 0) {
6125 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6126 "[NHM] MNTR_TIME is 0\n");
6127 return -EINVAL;
6128 }
6129
6130 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv))
6131 return -EINVAL;
6132
6133 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6134 "[NHM]nhm_incld_cca=%d, mntr_time=%d ms\n",
6135 para->nhm_incld_cca, para->mntr_time);
6136
6137 if (para->mntr_time != env->nhm_mntr_time) {
6138 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
6139 &period, &unit_idx);
6140 rtw89_phy_write32_idx(rtwdev, ccx->nhm_config,
6141 ccx->nhm_period_mask, period, bb->phy_idx);
6142 rtw89_phy_write32_idx(rtwdev, ccx->nhm_config,
6143 ccx->nhm_unit_mask, period, bb->phy_idx);
6144
6145 env->nhm_mntr_time = para->mntr_time;
6146 env->ccx_period = period;
6147 env->ccx_unit_idx = unit_idx;
6148 }
6149
6150 if (para->nhm_incld_cca != env->nhm_include_cca) {
6151 rtw89_phy_write32_idx(rtwdev, ccx->nhm_config,
6152 ccx->nhm_include_cca_mask, para->nhm_incld_cca,
6153 bb->phy_idx);
6154
6155 env->nhm_include_cca = para->nhm_incld_cca;
6156 }
6157
6158 rtw89_phy_nhm_th_update(rtwdev, bb);
6159
6160 return 0;
6161 }
6162
__rtw89_phy_nhm_trigger(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6163 static void __rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6164 {
6165 struct rtw89_ccx_para_info para = {
6166 .mntr_time = RTW89_NHM_MNTR_TIME,
6167 .rac_lv = RTW89_RAC_LV_1,
6168 .nhm_incld_cca = true,
6169 };
6170
6171 rtw89_phy_ccx_racing_release(rtwdev, bb);
6172
6173 rtw89_phy_nhm_set(rtwdev, bb, ¶);
6174 rtw89_phy_ccx_trigger(rtwdev, bb, RTW89_PHY_ENV_MON_NHM);
6175 }
6176
rtw89_phy_nhm_trigger(struct rtw89_dev * rtwdev)6177 void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev)
6178 {
6179 const struct rtw89_chip_info *chip = rtwdev->chip;
6180 struct rtw89_bb_ctx *bb;
6181
6182 if (!chip->support_noise)
6183 return;
6184
6185 rtw89_for_each_active_bb(rtwdev, bb)
6186 __rtw89_phy_nhm_trigger(rtwdev, bb);
6187 }
6188
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)6189 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
6190 struct rtw89_bb_ctx *bb,
6191 struct rtw89_ccx_para_info *para)
6192 {
6193 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6194 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6195 const struct rtw89_ccx_regs *ccx = phy->ccx;
6196 u32 period = 0;
6197 u32 unit_idx = 0;
6198
6199 if (para->mntr_time == 0) {
6200 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6201 "[WARN] MNTR_TIME is 0\n");
6202 return -EINVAL;
6203 }
6204
6205 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv))
6206 return -EINVAL;
6207
6208 if (para->mntr_time != env->ifs_clm_mntr_time) {
6209 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
6210 &period, &unit_idx);
6211 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
6212 ccx->ifs_clm_period_mask, period, bb->phy_idx);
6213 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
6214 ccx->ifs_clm_cnt_unit_mask,
6215 unit_idx, bb->phy_idx);
6216
6217 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6218 "Update IFS-CLM time ((%d)) -> ((%d))\n",
6219 env->ifs_clm_mntr_time, para->mntr_time);
6220
6221 env->ifs_clm_mntr_time = para->mntr_time;
6222 env->ccx_period = (u16)period;
6223 env->ccx_unit_idx = (u8)unit_idx;
6224 }
6225
6226 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, para)) {
6227 env->ifs_clm_app = para->ifs_clm_app;
6228 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
6229 }
6230
6231 return 0;
6232 }
6233
__rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6234 static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev,
6235 struct rtw89_bb_ctx *bb)
6236 {
6237 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6238 struct rtw89_ccx_para_info para = {};
6239 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
6240
6241 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
6242 if (env->ccx_manual_ctrl) {
6243 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6244 "CCX in manual ctrl\n");
6245 return;
6246 }
6247
6248 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6249 "BB-%d env_monitor track\n", bb->phy_idx);
6250
6251 /* only ifs_clm for now */
6252 if (rtw89_phy_ifs_clm_get_result(rtwdev, bb))
6253 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
6254
6255 rtw89_phy_ccx_racing_release(rtwdev, bb);
6256 para.mntr_time = 1900;
6257 para.rac_lv = RTW89_RAC_LV_1;
6258 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
6259
6260 if (rtw89_phy_ifs_clm_set(rtwdev, bb, ¶) == 0)
6261 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
6262 if (chk_result)
6263 rtw89_phy_ccx_trigger(rtwdev, bb, chk_result);
6264
6265 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6266 "get_result=0x%x, chk_result:0x%x\n",
6267 env->ccx_watchdog_result, chk_result);
6268 }
6269
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)6270 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
6271 {
6272 struct rtw89_bb_ctx *bb;
6273
6274 rtw89_for_each_active_bb(rtwdev, bb)
6275 __rtw89_phy_env_monitor_track(rtwdev, bb);
6276 }
6277
rtw89_physts_ie_page_valid(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap * ie_page)6278 static bool rtw89_physts_ie_page_valid(struct rtw89_dev *rtwdev,
6279 enum rtw89_phy_status_bitmap *ie_page)
6280 {
6281 const struct rtw89_chip_info *chip = rtwdev->chip;
6282
6283 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM ||
6284 *ie_page == RTW89_RSVD_9)
6285 return false;
6286 else if (*ie_page > RTW89_RSVD_9 && *ie_page < RTW89_EHT_PKT)
6287 *ie_page -= 1;
6288
6289 if (*ie_page == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX)
6290 return false;
6291
6292 return true;
6293 }
6294
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)6295 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
6296 {
6297 static const u8 ie_page_shift = 2;
6298
6299 if (ie_page == RTW89_EHT_PKT)
6300 return R_PHY_STS_BITMAP_EHT;
6301
6302 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
6303 }
6304
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,enum rtw89_phy_idx phy_idx)6305 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
6306 enum rtw89_phy_status_bitmap ie_page,
6307 enum rtw89_phy_idx phy_idx)
6308 {
6309 u32 addr;
6310
6311 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page))
6312 return 0;
6313
6314 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
6315
6316 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx);
6317 }
6318
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val,enum rtw89_phy_idx phy_idx)6319 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
6320 enum rtw89_phy_status_bitmap ie_page,
6321 u32 val, enum rtw89_phy_idx phy_idx)
6322 {
6323 const struct rtw89_chip_info *chip = rtwdev->chip;
6324 u32 addr;
6325
6326 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page))
6327 return;
6328
6329 if (chip->chip_id == RTL8852A)
6330 val &= B_PHY_STS_BITMAP_MSK_52A;
6331
6332 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
6333 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
6334 }
6335
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)6336 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
6337 bool enable,
6338 enum rtw89_phy_idx phy_idx)
6339 {
6340 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6341 const struct rtw89_physts_regs *physts = phy->physts;
6342
6343 if (enable) {
6344 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
6345 physts->dis_trigger_fail_mask, phy_idx);
6346 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
6347 physts->dis_trigger_brk_mask, phy_idx);
6348 } else {
6349 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
6350 physts->dis_trigger_fail_mask, phy_idx);
6351 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
6352 physts->dis_trigger_brk_mask, phy_idx);
6353 }
6354 }
6355
__rtw89_physts_parsing_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6356 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
6357 enum rtw89_phy_idx phy_idx)
6358 {
6359 const struct rtw89_chip_info *chip = rtwdev->chip;
6360 u32 val;
6361 u8 i;
6362
6363 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
6364
6365 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
6366 if (i == RTW89_RSVD_9 ||
6367 (i == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX))
6368 continue;
6369
6370 val = rtw89_physts_get_ie_bitmap(rtwdev, i, phy_idx);
6371 if (i == RTW89_HE_MU || i == RTW89_VHT_MU) {
6372 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF);
6373 } else if (i == RTW89_TRIG_BASE_PPDU) {
6374 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF) |
6375 BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
6376 } else if (i >= RTW89_CCK_PKT) {
6377 val &= ~(GENMASK(RTW89_PHYSTS_IE07_CMN_EXT_PATH_D,
6378 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A));
6379
6380 if (i == RTW89_CCK_PKT)
6381 val |= BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
6382 else if (i >= RTW89_HT_PKT)
6383 val |= BIT(RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0);
6384 }
6385
6386 rtw89_physts_set_ie_bitmap(rtwdev, i, val, phy_idx);
6387 }
6388 }
6389
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)6390 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
6391 {
6392 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0);
6393 if (rtwdev->dbcc_en)
6394 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1);
6395 }
6396
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,int type)6397 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev,
6398 struct rtw89_bb_ctx *bb, int type)
6399 {
6400 const struct rtw89_chip_info *chip = rtwdev->chip;
6401 const struct rtw89_phy_dig_gain_cfg *cfg;
6402 struct rtw89_dig_info *dig = &bb->dig;
6403 const char *msg;
6404 u8 i;
6405 s8 gain_base;
6406 s8 *gain_arr;
6407 u32 tmp;
6408
6409 switch (type) {
6410 case RTW89_DIG_GAIN_LNA_G:
6411 gain_arr = dig->lna_gain_g;
6412 gain_base = LNA0_GAIN;
6413 cfg = chip->dig_table->cfg_lna_g;
6414 msg = "lna_gain_g";
6415 break;
6416 case RTW89_DIG_GAIN_TIA_G:
6417 gain_arr = dig->tia_gain_g;
6418 gain_base = TIA0_GAIN_G;
6419 cfg = chip->dig_table->cfg_tia_g;
6420 msg = "tia_gain_g";
6421 break;
6422 case RTW89_DIG_GAIN_LNA_A:
6423 gain_arr = dig->lna_gain_a;
6424 gain_base = LNA0_GAIN;
6425 cfg = chip->dig_table->cfg_lna_a;
6426 msg = "lna_gain_a";
6427 break;
6428 case RTW89_DIG_GAIN_TIA_A:
6429 gain_arr = dig->tia_gain_a;
6430 gain_base = TIA0_GAIN_A;
6431 cfg = chip->dig_table->cfg_tia_a;
6432 msg = "tia_gain_a";
6433 break;
6434 default:
6435 return;
6436 }
6437
6438 for (i = 0; i < cfg->size; i++) {
6439 tmp = rtw89_phy_read32_idx(rtwdev, cfg->table[i].addr,
6440 cfg->table[i].mask, bb->phy_idx);
6441 tmp >>= DIG_GAIN_SHIFT;
6442 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
6443 gain_base += DIG_GAIN;
6444
6445 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
6446 msg, i, gain_arr[i]);
6447 }
6448 }
6449
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6450 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev,
6451 struct rtw89_bb_ctx *bb)
6452 {
6453 struct rtw89_dig_info *dig = &bb->dig;
6454 u32 tmp;
6455 u8 i;
6456
6457 if (!rtwdev->hal.support_igi)
6458 return;
6459
6460 tmp = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PKPW,
6461 B_PATH0_IB_PKPW_MSK, bb->phy_idx);
6462 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
6463 dig->ib_pbk = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PBK,
6464 B_PATH0_IB_PBK_MSK, bb->phy_idx);
6465 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
6466 dig->ib_pkpwr, dig->ib_pbk);
6467
6468 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
6469 rtw89_phy_dig_read_gain_table(rtwdev, bb, i);
6470 }
6471
6472 static const u8 rssi_nolink = 22;
6473 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
6474 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
6475 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
6476 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
6477
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6478 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev,
6479 struct rtw89_bb_ctx *bb)
6480 {
6481 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
6482 struct rtw89_dig_info *dig = &bb->dig;
6483 bool is_linked = rtwdev->total_sta_assoc > 0;
6484
6485 if (is_linked) {
6486 dig->igi_rssi = ch_info->rssi_min >> 1;
6487 } else {
6488 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
6489 dig->igi_rssi = rssi_nolink;
6490 }
6491 }
6492
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6493 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev,
6494 struct rtw89_bb_ctx *bb)
6495 {
6496 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
6497 struct rtw89_dig_info *dig = &bb->dig;
6498 bool is_linked = rtwdev->total_sta_assoc > 0;
6499 const u16 *fa_th_src = NULL;
6500
6501 switch (chan->band_type) {
6502 case RTW89_BAND_2G:
6503 dig->lna_gain = dig->lna_gain_g;
6504 dig->tia_gain = dig->tia_gain_g;
6505 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
6506 dig->force_gaincode_idx_en = false;
6507 dig->dyn_pd_th_en = true;
6508 break;
6509 case RTW89_BAND_5G:
6510 default:
6511 dig->lna_gain = dig->lna_gain_a;
6512 dig->tia_gain = dig->tia_gain_a;
6513 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
6514 dig->force_gaincode_idx_en = true;
6515 dig->dyn_pd_th_en = true;
6516 break;
6517 }
6518 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
6519 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
6520 }
6521
6522 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20;
6523 static const u8 igi_max_performance_mode = 0x5a;
6524 static const u8 dynamic_pd_threshold_max;
6525
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6526 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev,
6527 struct rtw89_bb_ctx *bb)
6528 {
6529 struct rtw89_dig_info *dig = &bb->dig;
6530
6531 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
6532 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
6533 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
6534 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
6535 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
6536 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
6537
6538 dig->dyn_igi_max = igi_max_performance_mode;
6539 dig->dyn_igi_min = dynamic_igi_min;
6540 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
6541 dig->pd_low_th_ofst = pd_low_th_offset;
6542 dig->is_linked_pre = false;
6543 }
6544
__rtw89_phy_dig_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6545 static void __rtw89_phy_dig_init(struct rtw89_dev *rtwdev,
6546 struct rtw89_bb_ctx *bb)
6547 {
6548 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig_init\n", bb->phy_idx);
6549
6550 rtw89_phy_dig_update_gain_para(rtwdev, bb);
6551 rtw89_phy_dig_reset(rtwdev, bb);
6552 }
6553
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)6554 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
6555 {
6556 struct rtw89_bb_ctx *bb;
6557
6558 rtw89_for_each_capab_bb(rtwdev, bb)
6559 __rtw89_phy_dig_init(rtwdev, bb);
6560 }
6561
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6562 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev,
6563 struct rtw89_bb_ctx *bb, u8 rssi)
6564 {
6565 struct rtw89_dig_info *dig = &bb->dig;
6566 u8 lna_idx;
6567
6568 if (rssi < dig->igi_rssi_th[0])
6569 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
6570 else if (rssi < dig->igi_rssi_th[1])
6571 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
6572 else if (rssi < dig->igi_rssi_th[2])
6573 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
6574 else if (rssi < dig->igi_rssi_th[3])
6575 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
6576 else if (rssi < dig->igi_rssi_th[4])
6577 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
6578 else
6579 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
6580
6581 return lna_idx;
6582 }
6583
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6584 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev,
6585 struct rtw89_bb_ctx *bb, u8 rssi)
6586 {
6587 struct rtw89_dig_info *dig = &bb->dig;
6588 u8 tia_idx;
6589
6590 if (rssi < dig->igi_rssi_th[0])
6591 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
6592 else
6593 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
6594
6595 return tia_idx;
6596 }
6597
6598 #define IB_PBK_BASE 110
6599 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6600 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev,
6601 struct rtw89_bb_ctx *bb, u8 rssi,
6602 struct rtw89_agc_gaincode_set *set)
6603 {
6604 struct rtw89_dig_info *dig = &bb->dig;
6605 s8 lna_gain = dig->lna_gain[set->lna_idx];
6606 s8 tia_gain = dig->tia_gain[set->tia_idx];
6607 s32 wb_rssi = rssi + lna_gain + tia_gain;
6608 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
6609 u8 rxb_idx;
6610
6611 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
6612 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
6613
6614 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
6615 wb_rssi, rxb_idx_tmp);
6616
6617 return rxb_idx;
6618 }
6619
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6620 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev,
6621 struct rtw89_bb_ctx *bb, u8 rssi,
6622 struct rtw89_agc_gaincode_set *set)
6623 {
6624 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, bb, rssi);
6625 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, bb, rssi);
6626 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, bb, rssi, set);
6627
6628 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6629 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
6630 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
6631 }
6632
6633 #define IGI_OFFSET_MAX 25
6634 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6635 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev,
6636 struct rtw89_bb_ctx *bb)
6637 {
6638 struct rtw89_dig_info *dig = &bb->dig;
6639 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6640 enum rtw89_dig_noisy_level noisy_lv;
6641 u8 igi_offset = dig->fa_rssi_ofst;
6642 u16 fa_ratio = 0;
6643
6644 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
6645
6646 if (fa_ratio < dig->fa_th[0])
6647 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
6648 else if (fa_ratio < dig->fa_th[1])
6649 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
6650 else if (fa_ratio < dig->fa_th[2])
6651 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
6652 else if (fa_ratio < dig->fa_th[3])
6653 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
6654 else
6655 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
6656
6657 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
6658 igi_offset = 0;
6659 else
6660 igi_offset += noisy_lv * IGI_OFFSET_MUL;
6661
6662 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
6663 dig->fa_rssi_ofst = igi_offset;
6664
6665 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6666 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
6667 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
6668
6669 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6670 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
6671 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
6672 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
6673 noisy_lv, igi_offset);
6674 }
6675
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 lna_idx)6676 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev,
6677 struct rtw89_bb_ctx *bb, u8 lna_idx)
6678 {
6679 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6680
6681 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_lna_init.addr,
6682 dig_regs->p0_lna_init.mask, lna_idx, bb->phy_idx);
6683 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_lna_init.addr,
6684 dig_regs->p1_lna_init.mask, lna_idx, bb->phy_idx);
6685 }
6686
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 tia_idx)6687 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev,
6688 struct rtw89_bb_ctx *bb, u8 tia_idx)
6689 {
6690 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6691
6692 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_tia_init.addr,
6693 dig_regs->p0_tia_init.mask, tia_idx, bb->phy_idx);
6694 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_tia_init.addr,
6695 dig_regs->p1_tia_init.mask, tia_idx, bb->phy_idx);
6696 }
6697
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rxb_idx)6698 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev,
6699 struct rtw89_bb_ctx *bb, u8 rxb_idx)
6700 {
6701 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6702
6703 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_rxb_init.addr,
6704 dig_regs->p0_rxb_init.mask, rxb_idx, bb->phy_idx);
6705 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_rxb_init.addr,
6706 dig_regs->p1_rxb_init.mask, rxb_idx, bb->phy_idx);
6707 }
6708
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_agc_gaincode_set set)6709 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
6710 struct rtw89_bb_ctx *bb,
6711 const struct rtw89_agc_gaincode_set set)
6712 {
6713 if (!rtwdev->hal.support_igi)
6714 return;
6715
6716 rtw89_phy_dig_set_lna_idx(rtwdev, bb, set.lna_idx);
6717 rtw89_phy_dig_set_tia_idx(rtwdev, bb, set.tia_idx);
6718 rtw89_phy_dig_set_rxb_idx(rtwdev, bb, set.rxb_idx);
6719
6720 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
6721 set.lna_idx, set.tia_idx, set.rxb_idx);
6722 }
6723
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool enable)6724 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
6725 struct rtw89_bb_ctx *bb,
6726 bool enable)
6727 {
6728 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6729
6730 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
6731 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx);
6732 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
6733 dig_regs->p0_s20_pagcugc_en.mask, enable, bb->phy_idx);
6734 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
6735 dig_regs->p1_p20_pagcugc_en.mask, enable, bb->phy_idx);
6736 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
6737 dig_regs->p1_s20_pagcugc_en.mask, enable, bb->phy_idx);
6738
6739 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
6740 }
6741
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6742 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev,
6743 struct rtw89_bb_ctx *bb)
6744 {
6745 struct rtw89_dig_info *dig = &bb->dig;
6746
6747 if (!rtwdev->hal.support_igi)
6748 return;
6749
6750 if (dig->force_gaincode_idx_en) {
6751 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
6752 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6753 "Force gaincode index enabled.\n");
6754 } else {
6755 rtw89_phy_dig_gaincode_by_rssi(rtwdev, bb, dig->igi_fa_rssi,
6756 &dig->cur_gaincode);
6757 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->cur_gaincode);
6758 }
6759 }
6760
rtw89_phy_dig_cal_under_region(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_chan * chan)6761 static u8 rtw89_phy_dig_cal_under_region(struct rtw89_dev *rtwdev,
6762 struct rtw89_bb_ctx *bb,
6763 const struct rtw89_chan *chan)
6764 {
6765 enum rtw89_bandwidth cbw = chan->band_width;
6766 struct rtw89_dig_info *dig = &bb->dig;
6767 u8 under_region = dig->pd_low_th_ofst;
6768
6769 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
6770 under_region += PD_TH_SB_FLTR_CMP_VAL;
6771
6772 switch (cbw) {
6773 case RTW89_CHANNEL_WIDTH_40:
6774 under_region += PD_TH_BW40_CMP_VAL;
6775 break;
6776 case RTW89_CHANNEL_WIDTH_80:
6777 under_region += PD_TH_BW80_CMP_VAL;
6778 break;
6779 case RTW89_CHANNEL_WIDTH_160:
6780 under_region += PD_TH_BW160_CMP_VAL;
6781 break;
6782 case RTW89_CHANNEL_WIDTH_20:
6783 fallthrough;
6784 default:
6785 under_region += PD_TH_BW20_CMP_VAL;
6786 break;
6787 }
6788
6789 return under_region;
6790 }
6791
__rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable,const struct rtw89_chan * chan)6792 static u32 __rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
6793 struct rtw89_bb_ctx *bb,
6794 u8 rssi, bool enable,
6795 const struct rtw89_chan *chan)
6796 {
6797 struct rtw89_dig_info *dig = &bb->dig;
6798 u8 ofdm_cca_th, under_region;
6799 u8 final_rssi;
6800 u32 pd_val;
6801
6802 under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
6803 dig->dyn_pd_th_max = dig->igi_rssi;
6804
6805 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6806 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
6807 PD_TH_MAX_RSSI + under_region);
6808
6809 if (enable) {
6810 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
6811 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6812 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
6813 final_rssi, ofdm_cca_th, under_region, pd_val);
6814 } else {
6815 pd_val = 0;
6816 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6817 "Dynamic PD th disabled, Set PD_low_bd=0\n");
6818 }
6819
6820 return pd_val;
6821 }
6822
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable)6823 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
6824 struct rtw89_bb_ctx *bb,
6825 u8 rssi, bool enable)
6826 {
6827 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
6828 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6829 struct rtw89_dig_info *dig = &bb->dig;
6830 u8 final_rssi, under_region = dig->pd_low_th_ofst;
6831 s8 cck_cca_th;
6832 u32 pd_val;
6833
6834 pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi, enable, chan);
6835 dig->bak_dig = pd_val;
6836
6837 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6838 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
6839 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6840 dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx);
6841
6842 if (!rtwdev->hal.support_cckpd)
6843 return;
6844
6845 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6846 under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
6847 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
6848 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
6849
6850 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6851 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
6852 final_rssi, cck_cca_th, under_region, pd_val);
6853
6854 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg,
6855 dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx);
6856 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
6857 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val, bb->phy_idx);
6858 }
6859
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6860 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6861 {
6862 struct rtw89_dig_info *dig = &bb->dig;
6863
6864 dig->bypass_dig = false;
6865 rtw89_phy_dig_para_reset(rtwdev, bb);
6866 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
6867 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi_nolink, false);
6868 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
6869 rtw89_phy_dig_update_para(rtwdev, bb);
6870 }
6871
6872 #define IGI_RSSI_MIN 10
6873 #define ABS_IGI_MIN 0xc
6874 static
rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6875 void rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6876 {
6877 struct rtw89_dig_info *dig = &bb->dig;
6878 u8 igi_min;
6879
6880 rtw89_phy_dig_igi_offset_by_env(rtwdev, bb);
6881
6882 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
6883 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
6884 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
6885
6886 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
6887 dig->igi_fa_rssi += dig->fa_rssi_ofst;
6888 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
6889 dig->dyn_igi_max);
6890 } else {
6891 dig->igi_fa_rssi = dig->dyn_igi_max;
6892 }
6893 }
6894
6895 struct rtw89_phy_iter_mcc_dig {
6896 struct rtw89_vif_link *rtwvif_link;
6897 bool has_sta;
6898 u8 rssi_min;
6899 };
6900
rtw89_phy_set_mcc_dig(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_bb_ctx * bb,u8 rssi_min,u8 mcc_role_idx,bool is_linked)6901 static void rtw89_phy_set_mcc_dig(struct rtw89_dev *rtwdev,
6902 struct rtw89_vif_link *rtwvif_link,
6903 struct rtw89_bb_ctx *bb,
6904 u8 rssi_min, u8 mcc_role_idx,
6905 bool is_linked)
6906 {
6907 struct rtw89_dig_info *dig = &bb->dig;
6908 const struct rtw89_chan *chan;
6909 u8 pd_val;
6910
6911 if (is_linked) {
6912 dig->igi_rssi = rssi_min >> 1;
6913 dig->igi_fa_rssi = dig->igi_rssi;
6914 } else {
6915 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
6916 dig->igi_rssi = rssi_nolink;
6917 dig->igi_fa_rssi = dig->igi_rssi;
6918 }
6919
6920 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
6921 rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
6922 pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi,
6923 is_linked, chan);
6924 rtw89_fw_h2c_mcc_dig(rtwdev, rtwvif_link->chanctx_idx,
6925 mcc_role_idx, pd_val, true);
6926
6927 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6928 "MCC chanctx_idx %d chan %d rssi %d pd_val %d",
6929 rtwvif_link->chanctx_idx, chan->primary_channel,
6930 dig->igi_rssi, pd_val);
6931 }
6932
rtw89_phy_set_mcc_dig_iter(void * data,struct ieee80211_sta * sta)6933 static void rtw89_phy_set_mcc_dig_iter(void *data, struct ieee80211_sta *sta)
6934 {
6935 struct rtw89_phy_iter_mcc_dig *mcc_dig = (struct rtw89_phy_iter_mcc_dig *)data;
6936 unsigned int link_id = mcc_dig->rtwvif_link->link_id;
6937 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
6938 struct rtw89_sta_link *rtwsta_link;
6939
6940 if (rtwsta->rtwvif != mcc_dig->rtwvif_link->rtwvif)
6941 return;
6942
6943 rtwsta_link = rtwsta->links[link_id];
6944 if (!rtwsta_link)
6945 return;
6946
6947 mcc_dig->has_sta = true;
6948 if (ewma_rssi_read(&rtwsta_link->avg_rssi) < mcc_dig->rssi_min)
6949 mcc_dig->rssi_min = ewma_rssi_read(&rtwsta_link->avg_rssi);
6950 }
6951
rtw89_phy_dig_mcc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6952 static void rtw89_phy_dig_mcc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6953 {
6954 struct rtw89_phy_iter_mcc_dig mcc_dig;
6955 struct rtw89_vif_link *rtwvif_link;
6956 struct rtw89_mcc_links_info info;
6957 int i;
6958
6959 rtw89_mcc_get_links(rtwdev, &info);
6960 for (i = 0; i < ARRAY_SIZE(info.links); i++) {
6961 rtwvif_link = info.links[i];
6962 if (!rtwvif_link)
6963 continue;
6964
6965 memset(&mcc_dig, 0, sizeof(mcc_dig));
6966 mcc_dig.rtwvif_link = rtwvif_link;
6967 mcc_dig.has_sta = false;
6968 mcc_dig.rssi_min = U8_MAX;
6969 ieee80211_iterate_stations_atomic(rtwdev->hw,
6970 rtw89_phy_set_mcc_dig_iter,
6971 &mcc_dig);
6972
6973 rtw89_phy_set_mcc_dig(rtwdev, rtwvif_link, bb,
6974 mcc_dig.rssi_min, i, mcc_dig.has_sta);
6975 }
6976 }
6977
rtw89_phy_dig_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool pause_dig,bool restore)6978 static void rtw89_phy_dig_ctrl(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb,
6979 bool pause_dig, bool restore)
6980 {
6981 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6982 struct rtw89_dig_info *dig = &bb->dig;
6983 bool en_dig;
6984 u32 pd_val;
6985
6986 if (dig->pause_dig == pause_dig)
6987 return;
6988
6989 if (pause_dig) {
6990 en_dig = false;
6991 pd_val = 0;
6992 } else {
6993 en_dig = rtwdev->total_sta_assoc > 0;
6994 pd_val = restore ? dig->bak_dig : 0;
6995 }
6996
6997 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s <%s> PD_low=%d", __func__,
6998 pause_dig ? "suspend" : "resume", pd_val);
6999
7000 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
7001 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
7002 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
7003 dig_regs->pd_spatial_reuse_en, en_dig, bb->phy_idx);
7004
7005 dig->pause_dig = pause_dig;
7006 }
7007
rtw89_phy_dig_suspend(struct rtw89_dev * rtwdev)7008 void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev)
7009 {
7010 struct rtw89_bb_ctx *bb;
7011
7012 rtw89_for_each_active_bb(rtwdev, bb)
7013 rtw89_phy_dig_ctrl(rtwdev, bb, true, false);
7014 }
7015
rtw89_phy_dig_resume(struct rtw89_dev * rtwdev,bool restore)7016 void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore)
7017 {
7018 struct rtw89_bb_ctx *bb;
7019
7020 rtw89_for_each_active_bb(rtwdev, bb)
7021 rtw89_phy_dig_ctrl(rtwdev, bb, false, restore);
7022 }
7023
__rtw89_phy_dig(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7024 static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7025 {
7026 struct rtw89_dig_info *dig = &bb->dig;
7027 bool is_linked = rtwdev->total_sta_assoc > 0;
7028 enum rtw89_entity_mode mode;
7029
7030 if (unlikely(dig->bypass_dig)) {
7031 dig->bypass_dig = false;
7032 return;
7033 }
7034
7035 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig track\n", bb->phy_idx);
7036
7037 rtw89_phy_dig_update_rssi_info(rtwdev, bb);
7038
7039 mode = rtw89_get_entity_mode(rtwdev);
7040 if (mode == RTW89_ENTITY_MODE_MCC) {
7041 rtw89_phy_dig_mcc(rtwdev, bb);
7042 return;
7043 }
7044
7045 if (unlikely(dig->pause_dig))
7046 return;
7047
7048 if (!dig->is_linked_pre && is_linked) {
7049 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
7050 rtw89_phy_dig_update_para(rtwdev, bb);
7051 dig->igi_fa_rssi = dig->igi_rssi;
7052 } else if (dig->is_linked_pre && !is_linked) {
7053 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
7054 rtw89_phy_dig_update_para(rtwdev, bb);
7055 dig->igi_fa_rssi = dig->igi_rssi;
7056 }
7057 dig->is_linked_pre = is_linked;
7058
7059 rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
7060
7061 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7062 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
7063 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
7064 dig->igi_fa_rssi);
7065
7066 rtw89_phy_dig_config_igi(rtwdev, bb);
7067
7068 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi, dig->dyn_pd_th_en);
7069
7070 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
7071 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, true);
7072 else
7073 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
7074 }
7075
rtw89_phy_dig(struct rtw89_dev * rtwdev)7076 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
7077 {
7078 struct rtw89_bb_ctx *bb;
7079
7080 rtw89_for_each_active_bb(rtwdev, bb)
7081 __rtw89_phy_dig(rtwdev, bb);
7082 }
7083
__rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)7084 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev,
7085 struct rtw89_sta_link *rtwsta_link)
7086 {
7087 struct rtw89_hal *hal = &rtwdev->hal;
7088 u8 rssi_a, rssi_b;
7089 u32 candidate;
7090
7091 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
7092 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
7093
7094 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
7095 candidate = RF_A;
7096 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
7097 candidate = RF_B;
7098 else
7099 return;
7100
7101 if (hal->antenna_tx == candidate)
7102 return;
7103
7104 hal->antenna_tx = candidate;
7105 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link);
7106
7107 if (hal->antenna_tx == RF_A) {
7108 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
7109 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
7110 } else if (hal->antenna_tx == RF_B) {
7111 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
7112 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
7113 }
7114 }
7115
rtw89_phy_tx_path_div_sta_iter(void * data,struct ieee80211_sta * sta)7116 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
7117 {
7118 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
7119 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
7120 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
7121 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
7122 struct rtw89_vif_link *rtwvif_link;
7123 struct rtw89_sta_link *rtwsta_link;
7124 unsigned int link_id;
7125 bool *done = data;
7126
7127 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n"))
7128 return;
7129
7130 if (sta->tdls)
7131 return;
7132
7133 if (*done)
7134 return;
7135
7136 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
7137 rtwvif_link = rtwsta_link->rtwvif_link;
7138 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
7139 continue;
7140
7141 *done = true;
7142 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link);
7143 return;
7144 }
7145 }
7146
rtw89_phy_tx_path_div_track(struct rtw89_dev * rtwdev)7147 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
7148 {
7149 struct rtw89_hal *hal = &rtwdev->hal;
7150 bool done = false;
7151
7152 if (!hal->tx_path_diversity)
7153 return;
7154
7155 ieee80211_iterate_stations_atomic(rtwdev->hw,
7156 rtw89_phy_tx_path_div_sta_iter,
7157 &done);
7158 }
7159
7160 #define ANTDIV_MAIN 0
7161 #define ANTDIV_AUX 1
7162
rtw89_phy_antdiv_set_ant(struct rtw89_dev * rtwdev)7163 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
7164 {
7165 struct rtw89_hal *hal = &rtwdev->hal;
7166 u8 default_ant, optional_ant;
7167
7168 if (!hal->ant_diversity || hal->antenna_tx == 0)
7169 return;
7170
7171 if (hal->antenna_tx == RF_B) {
7172 default_ant = ANTDIV_AUX;
7173 optional_ant = ANTDIV_MAIN;
7174 } else {
7175 default_ant = ANTDIV_MAIN;
7176 optional_ant = ANTDIV_AUX;
7177 }
7178
7179 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
7180 default_ant, RTW89_PHY_0);
7181 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
7182 default_ant, RTW89_PHY_0);
7183 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
7184 optional_ant, RTW89_PHY_0);
7185 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
7186 default_ant, RTW89_PHY_0);
7187 }
7188
rtw89_phy_swap_hal_antenna(struct rtw89_dev * rtwdev)7189 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
7190 {
7191 struct rtw89_hal *hal = &rtwdev->hal;
7192
7193 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
7194 hal->antenna_tx = hal->antenna_rx;
7195 }
7196
rtw89_phy_antdiv_decision_state(struct rtw89_dev * rtwdev)7197 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
7198 {
7199 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7200 struct rtw89_hal *hal = &rtwdev->hal;
7201 bool no_change = false;
7202 u8 main_rssi, aux_rssi;
7203 u8 main_evm, aux_evm;
7204 u32 candidate;
7205
7206 antdiv->get_stats = false;
7207 antdiv->training_count = 0;
7208
7209 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
7210 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
7211 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
7212 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
7213
7214 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
7215 candidate = RF_A;
7216 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
7217 candidate = RF_B;
7218 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
7219 candidate = RF_A;
7220 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
7221 candidate = RF_B;
7222 else
7223 no_change = true;
7224
7225 if (no_change) {
7226 /* swap back from training antenna to original */
7227 rtw89_phy_swap_hal_antenna(rtwdev);
7228 return;
7229 }
7230
7231 hal->antenna_tx = candidate;
7232 hal->antenna_rx = candidate;
7233 }
7234
rtw89_phy_antdiv_training_state(struct rtw89_dev * rtwdev)7235 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
7236 {
7237 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7238 u64 state_period;
7239
7240 if (antdiv->training_count % 2 == 0) {
7241 if (antdiv->training_count == 0)
7242 rtw89_phy_antdiv_sts_reset(rtwdev);
7243
7244 antdiv->get_stats = true;
7245 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
7246 } else {
7247 antdiv->get_stats = false;
7248 state_period = msecs_to_jiffies(ANTDIV_DELAY);
7249
7250 rtw89_phy_swap_hal_antenna(rtwdev);
7251 rtw89_phy_antdiv_set_ant(rtwdev);
7252 }
7253
7254 antdiv->training_count++;
7255 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work,
7256 state_period);
7257 }
7258
rtw89_phy_antdiv_work(struct wiphy * wiphy,struct wiphy_work * work)7259 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work)
7260 {
7261 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
7262 antdiv_work.work);
7263 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7264
7265 lockdep_assert_wiphy(wiphy);
7266
7267 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
7268 rtw89_phy_antdiv_training_state(rtwdev);
7269 } else {
7270 rtw89_phy_antdiv_decision_state(rtwdev);
7271 rtw89_phy_antdiv_set_ant(rtwdev);
7272 }
7273 }
7274
rtw89_phy_antdiv_track(struct rtw89_dev * rtwdev)7275 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
7276 {
7277 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7278 struct rtw89_hal *hal = &rtwdev->hal;
7279 u8 rssi, rssi_pre;
7280
7281 if (!hal->ant_diversity || hal->ant_diversity_fixed)
7282 return;
7283
7284 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
7285 rssi_pre = antdiv->rssi_pre;
7286 antdiv->rssi_pre = rssi;
7287 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
7288
7289 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
7290 return;
7291
7292 antdiv->training_count = 0;
7293 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 0);
7294 }
7295
__rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7296 static void __rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev,
7297 struct rtw89_bb_ctx *bb)
7298 {
7299 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
7300 "BB-%d env_monitor init\n", bb->phy_idx);
7301
7302 rtw89_phy_ccx_top_setting_init(rtwdev, bb);
7303 rtw89_phy_ifs_clm_setting_init(rtwdev, bb);
7304 }
7305
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)7306 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
7307 {
7308 struct rtw89_bb_ctx *bb;
7309
7310 rtw89_for_each_capab_bb(rtwdev, bb)
7311 __rtw89_phy_env_monitor_init(rtwdev, bb);
7312 }
7313
__rtw89_phy_edcca_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7314 static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev,
7315 struct rtw89_bb_ctx *bb)
7316 {
7317 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7318 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7319
7320 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca init\n", bb->phy_idx);
7321
7322 memset(edcca_bak, 0, sizeof(*edcca_bak));
7323
7324 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
7325 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
7326 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
7327 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
7328 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
7329 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
7330 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
7331 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
7332 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
7333 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
7334 }
7335
7336 rtw89_phy_write32_idx(rtwdev, edcca_regs->tx_collision_t2r_st,
7337 edcca_regs->tx_collision_t2r_st_mask, 0x29, bb->phy_idx);
7338 }
7339
rtw89_phy_edcca_init(struct rtw89_dev * rtwdev)7340 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
7341 {
7342 struct rtw89_bb_ctx *bb;
7343
7344 rtw89_for_each_capab_bb(rtwdev, bb)
7345 __rtw89_phy_edcca_init(rtwdev, bb);
7346 }
7347
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)7348 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
7349 {
7350 rtw89_phy_stat_init(rtwdev);
7351
7352 rtw89_chip_bb_sethw(rtwdev);
7353
7354 rtw89_phy_env_monitor_init(rtwdev);
7355 rtw89_phy_nhm_setting_init(rtwdev);
7356 rtw89_physts_parsing_init(rtwdev);
7357 rtw89_phy_dig_init(rtwdev);
7358 rtw89_phy_cfo_init(rtwdev);
7359 rtw89_phy_bb_wrap_init(rtwdev);
7360 rtw89_phy_edcca_init(rtwdev);
7361 rtw89_phy_ch_info_init(rtwdev);
7362 rtw89_phy_ul_tb_info_init(rtwdev);
7363 rtw89_phy_antdiv_init(rtwdev);
7364 rtw89_chip_rfe_gpio(rtwdev);
7365 rtw89_phy_antdiv_set_ant(rtwdev);
7366
7367 rtw89_chip_rfk_hw_init(rtwdev);
7368 rtw89_phy_init_rf_nctl(rtwdev);
7369 rtw89_chip_rfk_init(rtwdev);
7370 rtw89_chip_set_txpwr_ctrl(rtwdev);
7371 rtw89_chip_power_trim(rtwdev);
7372 rtw89_chip_cfg_txrx_path(rtwdev);
7373 }
7374
rtw89_phy_dm_reinit(struct rtw89_dev * rtwdev)7375 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev)
7376 {
7377 rtw89_phy_env_monitor_init(rtwdev);
7378 rtw89_physts_parsing_init(rtwdev);
7379 }
7380
__rtw89_phy_dm_init_data(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7381 static void __rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7382 {
7383 struct rtw89_env_monitor_info *env = &bb->env_monitor;
7384 const struct rtw89_chip_info *chip = rtwdev->chip;
7385 struct ieee80211_supported_band *sband;
7386 enum rtw89_band hw_band;
7387 enum nl80211_band band;
7388 u8 idx;
7389
7390 if (!chip->support_noise)
7391 return;
7392
7393 for (band = 0; band < NUM_NL80211_BANDS; band++) {
7394 sband = rtwdev->hw->wiphy->bands[band];
7395 if (!sband)
7396 continue;
7397
7398 hw_band = rtw89_nl80211_to_hw_band(band);
7399 env->nhm_his[hw_band] =
7400 devm_kcalloc(rtwdev->dev, sband->n_channels,
7401 sizeof(*env->nhm_his[0]), GFP_KERNEL);
7402
7403 for (idx = 0; idx < sband->n_channels; idx++)
7404 INIT_LIST_HEAD(&env->nhm_his[hw_band][idx].list);
7405
7406 INIT_LIST_HEAD(&env->nhm_rpt_list);
7407 }
7408 }
7409
rtw89_phy_dm_init_data(struct rtw89_dev * rtwdev)7410 void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev)
7411 {
7412 struct rtw89_bb_ctx *bb;
7413
7414 rtw89_for_each_capab_bb(rtwdev, bb)
7415 __rtw89_phy_dm_init_data(rtwdev, bb);
7416 }
7417
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)7418 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
7419 struct rtw89_vif_link *rtwvif_link)
7420 {
7421 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
7422 const struct rtw89_chip_info *chip = rtwdev->chip;
7423 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
7424 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
7425 struct ieee80211_bss_conf *bss_conf;
7426 u8 bss_color;
7427
7428 rcu_read_lock();
7429
7430 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
7431 if (!bss_conf->he_support || !vif->cfg.assoc) {
7432 rcu_read_unlock();
7433 return;
7434 }
7435
7436 bss_color = bss_conf->he_bss_color.color;
7437
7438 rcu_read_unlock();
7439
7440 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
7441 phy_idx);
7442 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
7443 bss_color, phy_idx);
7444 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
7445 vif->cfg.aid, phy_idx);
7446 }
7447
rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc * desc)7448 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
7449 {
7450 return desc->ch != 0;
7451 }
7452
rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc * desc,const struct rtw89_chan * chan)7453 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
7454 const struct rtw89_chan *chan)
7455 {
7456 if (!rfk_chan_validate_desc(desc))
7457 return false;
7458
7459 if (desc->ch != chan->channel)
7460 return false;
7461
7462 if (desc->has_band && desc->band != chan->band_type)
7463 return false;
7464
7465 if (desc->has_bw && desc->bw != chan->band_width)
7466 return false;
7467
7468 return true;
7469 }
7470
7471 struct rfk_chan_iter_data {
7472 const struct rtw89_rfk_chan_desc desc;
7473 unsigned int found;
7474 };
7475
rfk_chan_iter_search(const struct rtw89_chan * chan,void * data)7476 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
7477 {
7478 struct rfk_chan_iter_data *iter_data = data;
7479
7480 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
7481 iter_data->found++;
7482
7483 return 0;
7484 }
7485
rtw89_rfk_chan_lookup(struct rtw89_dev * rtwdev,const struct rtw89_rfk_chan_desc * desc,u8 desc_nr,const struct rtw89_chan * target_chan)7486 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
7487 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
7488 const struct rtw89_chan *target_chan)
7489 {
7490 int sel = -1;
7491 u8 i;
7492
7493 for (i = 0; i < desc_nr; i++) {
7494 struct rfk_chan_iter_data iter_data = {
7495 .desc = desc[i],
7496 };
7497
7498 if (rfk_chan_is_equivalent(&desc[i], target_chan))
7499 return i;
7500
7501 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
7502 if (!iter_data.found && sel == -1)
7503 sel = i;
7504 }
7505
7506 if (sel == -1) {
7507 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7508 "no idle rfk entry; force replace the first\n");
7509 sel = 0;
7510 }
7511
7512 return sel;
7513 }
7514 EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
7515
7516 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7517 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7518 {
7519 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
7520 }
7521
7522 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7523 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7524 {
7525 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
7526 }
7527
7528 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7529 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7530 {
7531 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
7532 }
7533
7534 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7535 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7536 {
7537 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
7538 }
7539
7540 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7541 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7542 {
7543 udelay(def->data);
7544 }
7545
7546 static void
7547 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
7548 [RTW89_RFK_F_WRF] = _rfk_write_rf,
7549 [RTW89_RFK_F_WM] = _rfk_write32_mask,
7550 [RTW89_RFK_F_WS] = _rfk_write32_set,
7551 [RTW89_RFK_F_WC] = _rfk_write32_clr,
7552 [RTW89_RFK_F_DELAY] = _rfk_delay,
7553 };
7554
7555 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
7556
7557 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)7558 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
7559 {
7560 const struct rtw89_reg5_def *p = tbl->defs;
7561 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
7562
7563 for (; p < end; p++)
7564 _rfk_handler[p->flag](rtwdev, p);
7565 }
7566 EXPORT_SYMBOL(rtw89_rfk_parser);
7567
7568 #define RTW89_TSSI_FAST_MODE_NUM 4
7569
7570 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
7571 {0xD934, 0xff0000},
7572 {0xD934, 0xff000000},
7573 {0xD938, 0xff},
7574 {0xD934, 0xff00},
7575 };
7576
7577 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
7578 {0xD930, 0xff0000},
7579 {0xD930, 0xff000000},
7580 {0xD934, 0xff},
7581 {0xD930, 0xff00},
7582 };
7583
7584 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)7585 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
7586 enum rtw89_mac_idx mac_idx,
7587 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
7588 u32 val)
7589 {
7590 const struct rtw89_reg_def *regs;
7591 u32 reg;
7592 int i;
7593
7594 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
7595 regs = rtw89_tssi_fastmode_regs_flat;
7596 else
7597 regs = rtw89_tssi_fastmode_regs_level;
7598
7599 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
7600 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
7601 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
7602 }
7603 }
7604
7605 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
7606 {0xD91C, 0xff000000},
7607 {0xD920, 0xff},
7608 {0xD920, 0xff00},
7609 {0xD920, 0xff0000},
7610 {0xD920, 0xff000000},
7611 {0xD924, 0xff},
7612 {0xD924, 0xff00},
7613 {0xD914, 0xff000000},
7614 {0xD918, 0xff},
7615 {0xD918, 0xff00},
7616 {0xD918, 0xff0000},
7617 {0xD918, 0xff000000},
7618 {0xD91C, 0xff},
7619 {0xD91C, 0xff00},
7620 {0xD91C, 0xff0000},
7621 };
7622
7623 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
7624 {0xD910, 0xff},
7625 {0xD910, 0xff00},
7626 {0xD910, 0xff0000},
7627 {0xD910, 0xff000000},
7628 {0xD914, 0xff},
7629 {0xD914, 0xff00},
7630 {0xD914, 0xff0000},
7631 {0xD908, 0xff},
7632 {0xD908, 0xff00},
7633 {0xD908, 0xff0000},
7634 {0xD908, 0xff000000},
7635 {0xD90C, 0xff},
7636 {0xD90C, 0xff00},
7637 {0xD90C, 0xff0000},
7638 {0xD90C, 0xff000000},
7639 };
7640
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)7641 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
7642 enum rtw89_mac_idx mac_idx,
7643 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
7644 {
7645 const struct rtw89_chip_info *chip = rtwdev->chip;
7646 const struct rtw89_reg_def *regs;
7647 const u32 *data;
7648 u32 reg;
7649 int i;
7650
7651 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
7652 return;
7653
7654 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
7655 regs = rtw89_tssi_bandedge_regs_flat;
7656 else
7657 regs = rtw89_tssi_bandedge_regs_level;
7658
7659 data = chip->tssi_dbw_table->data[bandedge_cfg];
7660
7661 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
7662 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
7663 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
7664 }
7665
7666 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
7667 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
7668
7669 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
7670 data[RTW89_TSSI_SBW20]);
7671 }
7672 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
7673
7674 static
7675 const u8 rtw89_ch_base_table[16] = {1, 0xff,
7676 36, 100, 132, 149, 0xff,
7677 1, 33, 65, 97, 129, 161, 193, 225, 0xff};
7678 #define RTW89_CH_BASE_IDX_2G 0
7679 #define RTW89_CH_BASE_IDX_5G_FIRST 2
7680 #define RTW89_CH_BASE_IDX_5G_LAST 5
7681 #define RTW89_CH_BASE_IDX_6G_FIRST 7
7682 #define RTW89_CH_BASE_IDX_6G_LAST 14
7683
7684 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)
7685 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0)
7686
rtw89_encode_chan_idx(struct rtw89_dev * rtwdev,u8 central_ch,u8 band)7687 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
7688 {
7689 u8 chan_idx;
7690 u8 last, first;
7691 u8 idx;
7692
7693 switch (band) {
7694 case RTW89_BAND_2G:
7695 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) |
7696 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch);
7697 return chan_idx;
7698 case RTW89_BAND_5G:
7699 first = RTW89_CH_BASE_IDX_5G_FIRST;
7700 last = RTW89_CH_BASE_IDX_5G_LAST;
7701 break;
7702 case RTW89_BAND_6G:
7703 first = RTW89_CH_BASE_IDX_6G_FIRST;
7704 last = RTW89_CH_BASE_IDX_6G_LAST;
7705 break;
7706 default:
7707 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
7708 return 0;
7709 }
7710
7711 for (idx = last; idx >= first; idx--)
7712 if (central_ch >= rtw89_ch_base_table[idx])
7713 break;
7714
7715 if (idx < first) {
7716 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
7717 return 0;
7718 }
7719
7720 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) |
7721 FIELD_PREP(RTW89_CH_OFFSET_MASK,
7722 (central_ch - rtw89_ch_base_table[idx]) >> 1);
7723 return chan_idx;
7724 }
7725 EXPORT_SYMBOL(rtw89_encode_chan_idx);
7726
rtw89_decode_chan_idx(struct rtw89_dev * rtwdev,u8 chan_idx,u8 * ch,enum nl80211_band * band)7727 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
7728 u8 *ch, enum nl80211_band *band)
7729 {
7730 u8 idx, offset;
7731
7732 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx);
7733 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx);
7734
7735 if (idx == RTW89_CH_BASE_IDX_2G) {
7736 *band = NL80211_BAND_2GHZ;
7737 *ch = offset;
7738 return;
7739 }
7740
7741 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
7742 *ch = rtw89_ch_base_table[idx] + (offset << 1);
7743 }
7744 EXPORT_SYMBOL(rtw89_decode_chan_idx);
7745
rtw89_phy_config_edcca(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool scan)7746 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
7747 struct rtw89_bb_ctx *bb, bool scan)
7748 {
7749 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7750 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7751
7752 if (scan) {
7753 edcca_bak->a =
7754 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
7755 edcca_regs->edcca_mask, bb->phy_idx);
7756 edcca_bak->p =
7757 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
7758 edcca_regs->edcca_p_mask, bb->phy_idx);
7759 edcca_bak->ppdu =
7760 rtw89_phy_read32_idx(rtwdev, edcca_regs->ppdu_level,
7761 edcca_regs->ppdu_mask, bb->phy_idx);
7762
7763 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7764 edcca_regs->edcca_mask, EDCCA_MAX, bb->phy_idx);
7765 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7766 edcca_regs->edcca_p_mask, EDCCA_MAX, bb->phy_idx);
7767 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7768 edcca_regs->ppdu_mask, EDCCA_MAX, bb->phy_idx);
7769 } else {
7770 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7771 edcca_regs->edcca_mask,
7772 edcca_bak->a, bb->phy_idx);
7773 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7774 edcca_regs->edcca_p_mask,
7775 edcca_bak->p, bb->phy_idx);
7776 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7777 edcca_regs->ppdu_mask,
7778 edcca_bak->ppdu, bb->phy_idx);
7779 }
7780 }
7781
rtw89_phy_edcca_log(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7782 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7783 {
7784 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7785 const struct rtw89_edcca_p_regs *edcca_p_regs;
7786 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
7787 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
7788 u8 path, per20_bitmap = 0;
7789 u8 pwdb[8];
7790 u32 tmp;
7791
7792 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
7793 return;
7794
7795 if (bb->phy_idx == RTW89_PHY_1)
7796 edcca_p_regs = &edcca_regs->p[RTW89_PHY_1];
7797 else
7798 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0];
7799
7800 if (rtwdev->chip->chip_id == RTL8922A)
7801 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7802 edcca_regs->rpt_sel_be_mask, 0);
7803
7804 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7805 edcca_p_regs->rpt_sel_mask, 0);
7806 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7807 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
7808 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
7809 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
7810 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20);
7811 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20);
7812 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB);
7813 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1);
7814 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
7815 pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
7816
7817 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7818 edcca_p_regs->rpt_sel_mask, 5);
7819 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7820 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
7821 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
7822
7823 if (rtwdev->chip->chip_id == RTL8922A) {
7824 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7825 edcca_regs->rpt_sel_be_mask, 4);
7826 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7827 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
7828 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
7829 pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
7830 pwdb[3] = u32_get_bits(tmp, MASKBYTE0);
7831 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a,
7832 MASKBYTE0);
7833
7834 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7835 edcca_regs->rpt_sel_be_mask, 5);
7836 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7837 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
7838 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
7839 pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
7840 pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
7841 } else {
7842 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7843 edcca_p_regs->rpt_sel_mask, 0);
7844 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7845 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
7846 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
7847
7848 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7849 edcca_p_regs->rpt_sel_mask, 5);
7850 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7851 pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
7852 pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
7853
7854 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7855 edcca_p_regs->rpt_sel_mask, 2);
7856 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7857 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
7858 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
7859
7860 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7861 edcca_p_regs->rpt_sel_mask, 3);
7862 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7863 pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
7864 pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
7865 }
7866
7867 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7868 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap);
7869
7870 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7871 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
7872 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5],
7873 pwdb[6], pwdb[7]);
7874
7875 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7876 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n",
7877 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80);
7878
7879 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7880 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n",
7881 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80);
7882 }
7883
rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7884 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev,
7885 struct rtw89_bb_ctx *bb)
7886 {
7887 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
7888 bool is_linked = rtwdev->total_sta_assoc > 0;
7889 u8 rssi_min = ch_info->rssi_min >> 1;
7890 u8 edcca_thre;
7891
7892 if (!is_linked) {
7893 edcca_thre = EDCCA_MAX;
7894 } else {
7895 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
7896 EDCCA_TH_REF;
7897 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB);
7898 }
7899
7900 return edcca_thre;
7901 }
7902
rtw89_phy_edcca_thre_calc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7903 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7904 {
7905 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7906 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7907 u8 th;
7908
7909 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev, bb);
7910 if (th == edcca_bak->th_old)
7911 return;
7912
7913 edcca_bak->th_old = th;
7914
7915 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7916 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th);
7917
7918 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7919 edcca_regs->edcca_mask, th, bb->phy_idx);
7920 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7921 edcca_regs->edcca_p_mask, th, bb->phy_idx);
7922 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7923 edcca_regs->ppdu_mask, th, bb->phy_idx);
7924 }
7925
7926 static
__rtw89_phy_edcca_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7927 void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7928 {
7929 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca track\n", bb->phy_idx);
7930
7931 rtw89_phy_edcca_thre_calc(rtwdev, bb);
7932 rtw89_phy_edcca_log(rtwdev, bb);
7933 }
7934
rtw89_phy_edcca_track(struct rtw89_dev * rtwdev)7935 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
7936 {
7937 struct rtw89_hal *hal = &rtwdev->hal;
7938 struct rtw89_bb_ctx *bb;
7939
7940 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
7941 return;
7942
7943 rtw89_for_each_active_bb(rtwdev, bb)
7944 __rtw89_phy_edcca_track(rtwdev, bb);
7945 }
7946
rtw89_phy_get_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7947 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
7948 enum rtw89_phy_idx phy_idx)
7949 {
7950 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7951 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7952 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7953
7954 switch (rtwdev->mlo_dbcc_mode) {
7955 case MLO_1_PLUS_1_1RF:
7956 if (phy_idx == RTW89_PHY_0)
7957 return RF_A;
7958 else
7959 return RF_B;
7960 case MLO_1_PLUS_1_2RF:
7961 if (phy_idx == RTW89_PHY_0)
7962 return RF_A;
7963 else
7964 return RF_D;
7965 case MLO_0_PLUS_2_1RF:
7966 case MLO_2_PLUS_0_1RF:
7967 /* for both PHY 0/1 */
7968 return RF_AB;
7969 case MLO_0_PLUS_2_2RF:
7970 case MLO_2_PLUS_0_2RF:
7971 case MLO_2_PLUS_2_2RF:
7972 default:
7973 if (phy_idx == RTW89_PHY_0)
7974 return RF_AB;
7975 else
7976 return RF_CD;
7977 }
7978 }
7979 EXPORT_SYMBOL(rtw89_phy_get_kpath);
7980
rtw89_phy_get_syn_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7981 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
7982 enum rtw89_phy_idx phy_idx)
7983 {
7984 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7985 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7986 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7987
7988 switch (rtwdev->mlo_dbcc_mode) {
7989 case MLO_1_PLUS_1_1RF:
7990 if (phy_idx == RTW89_PHY_0)
7991 return RF_PATH_A;
7992 else
7993 return RF_PATH_B;
7994 case MLO_1_PLUS_1_2RF:
7995 if (phy_idx == RTW89_PHY_0)
7996 return RF_PATH_A;
7997 else
7998 return RF_PATH_D;
7999 case MLO_0_PLUS_2_1RF:
8000 case MLO_2_PLUS_0_1RF:
8001 if (phy_idx == RTW89_PHY_0)
8002 return RF_PATH_A;
8003 else
8004 return RF_PATH_B;
8005 case MLO_0_PLUS_2_2RF:
8006 case MLO_2_PLUS_0_2RF:
8007 case MLO_2_PLUS_2_2RF:
8008 default:
8009 if (phy_idx == RTW89_PHY_0)
8010 return RF_PATH_A;
8011 else
8012 return RF_PATH_C;
8013 }
8014 }
8015 EXPORT_SYMBOL(rtw89_phy_get_syn_sel);
8016
8017 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
8018 .setting_addr = R_CCX,
8019 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
8020 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
8021 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
8022 .en_mask = B_CCX_EN_MSK,
8023 .ifs_cnt_addr = R_IFS_COUNTER,
8024 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
8025 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
8026 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
8027 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
8028 .ifs_t1_addr = R_IFS_T1,
8029 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
8030 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
8031 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
8032 .ifs_t2_addr = R_IFS_T2,
8033 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
8034 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
8035 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
8036 .ifs_t3_addr = R_IFS_T3,
8037 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
8038 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
8039 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
8040 .ifs_t4_addr = R_IFS_T4,
8041 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
8042 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
8043 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
8044 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
8045 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
8046 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
8047 .ifs_clm_cca_addr = R_IFS_CLM_CCA,
8048 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
8049 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
8050 .ifs_clm_fa_addr = R_IFS_CLM_FA,
8051 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
8052 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
8053 .ifs_his_addr = R_IFS_HIS,
8054 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
8055 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
8056 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
8057 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
8058 .ifs_avg_l_addr = R_IFS_AVG_L,
8059 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
8060 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
8061 .ifs_avg_h_addr = R_IFS_AVG_H,
8062 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
8063 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
8064 .ifs_cca_l_addr = R_IFS_CCA_L,
8065 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
8066 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
8067 .ifs_cca_h_addr = R_IFS_CCA_H,
8068 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
8069 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
8070 .ifs_total_addr = R_IFSCNT,
8071 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
8072 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
8073 .nhm = R_NHM_AX,
8074 .nhm_ready = B_NHM_READY_MSK,
8075 .nhm_config = R_NHM_CFG,
8076 .nhm_period_mask = B_NHM_PERIOD_MSK,
8077 .nhm_unit_mask = B_NHM_COUNTER_MSK,
8078 .nhm_include_cca_mask = B_NHM_INCLUDE_CCA_MSK,
8079 .nhm_en_mask = B_NHM_EN_MSK,
8080 .nhm_method = R_NHM_TH9,
8081 .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK,
8082 };
8083
8084 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
8085 .setting_addr = R_PLCP_HISTOGRAM,
8086 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
8087 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
8088 };
8089
8090 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
8091 .comp = R_DCFO_WEIGHT,
8092 .weighting_mask = B_DCFO_WEIGHT_MSK,
8093 .comp_seg0 = R_DCFO_OPT,
8094 .valid_0_mask = B_DCFO_OPT_EN,
8095 };
8096
8097 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
8098 .cr_base = 0x10000,
8099 .ccx = &rtw89_ccx_regs_ax,
8100 .physts = &rtw89_physts_regs_ax,
8101 .cfo = &rtw89_cfo_regs_ax,
8102 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
8103 .config_bb_gain = rtw89_phy_config_bb_gain_ax,
8104 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
8105 .bb_wrap_init = NULL,
8106 .ch_info_init = NULL,
8107
8108 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
8109 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
8110 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax,
8111 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax,
8112 };
8113 EXPORT_SYMBOL(rtw89_phy_gen_ax);
8114