1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "chan.h"
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15 #include "txrx.h"
16 #include "util.h"
17
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
19 {
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
21
22 return phy->phy0_phy1_offset(rtwdev, addr);
23 }
24
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
26 const struct rtw89_ra_report *report)
27 {
28 u32 bit_rate = report->bit_rate;
29
30 /* lower than ofdm, do not aggregate */
31 if (bit_rate < 550)
32 return 1;
33
34 /* avoid AMSDU for legacy rate */
35 if (report->might_fallback_legacy)
36 return 1;
37
38 /* lower than 20M vht 2ss mcs8, make it small */
39 if (bit_rate < 1800)
40 return 1200;
41
42 /* lower than 40M vht 2ss mcs9, make it medium */
43 if (bit_rate < 4000)
44 return 2600;
45
46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
47 if (bit_rate < 7000)
48 return 3500;
49
50 return rtwdev->chip->max_amsdu_limit;
51 }
52
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
54 {
55 u64 ra_mask = 0;
56 u8 mcs_cap;
57 int i, nss;
58
59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
60 mcs_cap = mcs_map & 0x3;
61 switch (mcs_cap) {
62 case 2:
63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
64 break;
65 case 1:
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
67 break;
68 case 0:
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
70 break;
71 default:
72 break;
73 }
74 }
75
76 return ra_mask;
77 }
78
get_he_ra_mask(struct ieee80211_link_sta * link_sta)79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta)
80 {
81 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
82 u16 mcs_map;
83
84 switch (link_sta->bandwidth) {
85 case IEEE80211_STA_RX_BW_160:
86 if (cap.he_cap_elem.phy_cap_info[0] &
87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
89 else
90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
91 break;
92 default:
93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
94 }
95
96 /* MCS11, MCS9, MCS7 */
97 return get_mcs_ra_mask(mcs_map, 11, 2);
98 }
99
get_eht_mcs_ra_mask(u8 * max_nss,u8 start_mcs,u8 n_nss)100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)
101 {
102 u64 nss_mcs_shift;
103 u64 nss_mcs_val;
104 u64 mask = 0;
105 int i, j;
106 u8 nss;
107
108 for (i = 0; i < n_nss; i++) {
109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);
110 if (!nss)
111 continue;
112
113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);
114
115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)
116 mask |= nss_mcs_val << nss_mcs_shift;
117 }
118
119 return mask;
120 }
121
get_eht_ra_mask(struct rtw89_vif_link * rtwvif_link,struct ieee80211_link_sta * link_sta)122 static u64 get_eht_ra_mask(struct rtw89_vif_link *rtwvif_link,
123 struct ieee80211_link_sta *link_sta)
124 {
125 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
126 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;
127 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
128 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;
129 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
130
131 switch (link_sta->bandwidth) {
132 case IEEE80211_STA_RX_BW_320:
133 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
134 /* MCS 9, 11, 13 */
135 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
136 case IEEE80211_STA_RX_BW_160:
137 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
138 /* MCS 9, 11, 13 */
139 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
140 case IEEE80211_STA_RX_BW_20:
141 if (vif->type == NL80211_IFTYPE_AP &&
142 !(he_phy_cap[0] & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
143 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
144 /* MCS 7, 9, 11, 13 */
145 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
146 }
147 fallthrough;
148 case IEEE80211_STA_RX_BW_80:
149 default:
150 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
151 /* MCS 9, 11, 13 */
152 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
153 }
154 }
155
156 #define RA_FLOOR_TABLE_SIZE 7
157 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)158 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
159 u8 ratr_state)
160 {
161 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
162 u8 rssi_lv = 0;
163 u8 i;
164
165 rssi >>= 1;
166 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
167 if (i >= ratr_state)
168 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
169 if (rssi < rssi_lv_t[i]) {
170 rssi_lv = i;
171 break;
172 }
173 }
174 if (rssi_lv == 0)
175 return 0xffffffffffffffffULL;
176 else if (rssi_lv == 1)
177 return 0xfffffffffffffff0ULL;
178 else if (rssi_lv == 2)
179 return 0xffffffffffffefe0ULL;
180 else if (rssi_lv == 3)
181 return 0xffffffffffffcfc0ULL;
182 else if (rssi_lv == 4)
183 return 0xffffffffffff8f80ULL;
184 else if (rssi_lv >= 5)
185 return 0xffffffffffff0f00ULL;
186
187 return 0xffffffffffffffffULL;
188 }
189
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)190 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
191 {
192 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
193 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
194
195 if (ra_mask == 0)
196 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
197
198 return ra_mask;
199 }
200
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan)201 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev,
202 struct rtw89_sta_link *rtwsta_link,
203 struct ieee80211_link_sta *link_sta,
204 const struct rtw89_chan *chan)
205 {
206 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
207 enum nl80211_band band;
208 u64 cfg_mask;
209
210 if (!rtwsta_link->use_cfg_mask)
211 return -1;
212
213 switch (chan->band_type) {
214 case RTW89_BAND_2G:
215 band = NL80211_BAND_2GHZ;
216 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
217 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
218 break;
219 case RTW89_BAND_5G:
220 band = NL80211_BAND_5GHZ;
221 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
222 RA_MASK_OFDM_RATES);
223 break;
224 case RTW89_BAND_6G:
225 band = NL80211_BAND_6GHZ;
226 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
227 RA_MASK_OFDM_RATES);
228 break;
229 default:
230 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
231 return -1;
232 }
233
234 if (link_sta->eht_cap.has_eht) {
235 cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[0],
236 RA_MASK_EHT_1SS_RATES);
237 cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[1],
238 RA_MASK_EHT_2SS_RATES);
239 } else if (link_sta->he_cap.has_he) {
240 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
241 RA_MASK_HE_1SS_RATES);
242 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
243 RA_MASK_HE_2SS_RATES);
244 } else if (link_sta->vht_cap.vht_supported) {
245 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
246 RA_MASK_VHT_1SS_RATES);
247 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
248 RA_MASK_VHT_2SS_RATES);
249 } else if (link_sta->ht_cap.ht_supported) {
250 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
251 RA_MASK_HT_1SS_RATES);
252 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
253 RA_MASK_HT_2SS_RATES);
254 }
255
256 return cfg_mask;
257 }
258
259 static const u64
260 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
261 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
262 static const u64
263 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
264 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
265 static const u64
266 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
267 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
268 static const u64
269 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,
270 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};
271 static const u64
272 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11,
273 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11};
274
rtw89_phy_ra_gi_ltf(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan,bool * fix_giltf_en,u8 * fix_giltf)275 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
276 struct rtw89_sta_link *rtwsta_link,
277 struct ieee80211_link_sta *link_sta,
278 const struct rtw89_chan *chan,
279 bool *fix_giltf_en, u8 *fix_giltf)
280 {
281 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
282 u8 band = chan->band_type;
283 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
284 u8 ltf, gi;
285
286 *fix_giltf_en = true;
287
288 if (rtwdev->chip->chip_id == RTL8852C &&
289 chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
290 rtw89_sta_link_has_su_mu_4xhe08(link_sta))
291 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
292 else
293 *fix_giltf = RTW89_GILTF_2XHE08;
294
295 if (!rtwsta_link->use_cfg_mask)
296 return;
297
298 if (link_sta->eht_cap.has_eht) {
299 ltf = mask->control[nl_band].eht_ltf;
300 gi = mask->control[nl_band].eht_gi;
301 } else if (link_sta->he_cap.has_he) {
302 ltf = mask->control[nl_band].he_ltf;
303 gi = mask->control[nl_band].he_gi;
304 } else {
305 return;
306 }
307
308 if (ltf == 2 && gi == 2)
309 *fix_giltf = RTW89_GILTF_LGI_4XHE32;
310 else if (ltf == 2 && gi == 0)
311 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
312 else if (ltf == 1 && gi == 1)
313 *fix_giltf = RTW89_GILTF_2XHE16;
314 else if (ltf == 1 && gi == 0)
315 *fix_giltf = RTW89_GILTF_2XHE08;
316 else if (ltf == 0 && gi == 1)
317 *fix_giltf = RTW89_GILTF_1XHE16;
318 else if (ltf == 0 && gi == 0)
319 *fix_giltf = RTW89_GILTF_1XHE08;
320 }
321
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,bool p2p,bool csi)322 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
323 struct rtw89_vif_link *rtwvif_link,
324 struct rtw89_sta_link *rtwsta_link,
325 struct ieee80211_link_sta *link_sta,
326 bool p2p, bool csi)
327 {
328 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
329 struct rtw89_ra_info *ra = &rtwsta_link->ra;
330 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
331 rtwvif_link->chanctx_idx);
332 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
333 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
334 u64 ra_mask = 0;
335 u64 ra_mask_bak;
336 u8 mode = 0;
337 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
338 u8 bw_mode = 0;
339 u8 stbc_en = 0;
340 u8 ldpc_en = 0;
341 u8 fix_giltf = 0;
342 u8 i;
343 bool sgi = false;
344 bool fix_giltf_en = false;
345
346 memset(ra, 0, sizeof(*ra));
347 /* Set the ra mask from sta's capability */
348 if (link_sta->eht_cap.has_eht) {
349 mode |= RTW89_RA_MODE_EHT;
350 ra_mask |= get_eht_ra_mask(rtwvif_link, link_sta);
351
352 if (rtwdev->hal.no_mcs_12_13)
353 high_rate_masks = rtw89_ra_mask_eht_mcs0_11;
354 else
355 high_rate_masks = rtw89_ra_mask_eht_rates;
356
357 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
358 chan, &fix_giltf_en, &fix_giltf);
359 } else if (link_sta->he_cap.has_he) {
360 mode |= RTW89_RA_MODE_HE;
361 csi_mode = RTW89_RA_RPT_MODE_HE;
362 ra_mask |= get_he_ra_mask(link_sta);
363 high_rate_masks = rtw89_ra_mask_he_rates;
364 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
365 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
366 stbc_en = 1;
367 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
368 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
369 ldpc_en = 1;
370 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
371 chan, &fix_giltf_en, &fix_giltf);
372 } else if (link_sta->vht_cap.vht_supported) {
373 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
374
375 mode |= RTW89_RA_MODE_VHT;
376 csi_mode = RTW89_RA_RPT_MODE_VHT;
377 /* MCS9 (non-20MHz), MCS8, MCS7 */
378 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
379 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1);
380 else
381 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
382 high_rate_masks = rtw89_ra_mask_vht_rates;
383 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
384 stbc_en = 1;
385 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
386 ldpc_en = 1;
387 } else if (link_sta->ht_cap.ht_supported) {
388 mode |= RTW89_RA_MODE_HT;
389 csi_mode = RTW89_RA_RPT_MODE_HT;
390 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
391 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
392 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
393 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
394 high_rate_masks = rtw89_ra_mask_ht_rates;
395 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
396 stbc_en = 1;
397 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
398 ldpc_en = 1;
399 }
400
401 switch (chan->band_type) {
402 case RTW89_BAND_2G:
403 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
404 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
405 mode |= RTW89_RA_MODE_CCK;
406 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
407 mode |= RTW89_RA_MODE_OFDM;
408 break;
409 case RTW89_BAND_5G:
410 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
411 mode |= RTW89_RA_MODE_OFDM;
412 break;
413 case RTW89_BAND_6G:
414 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
415 mode |= RTW89_RA_MODE_OFDM;
416 break;
417 default:
418 rtw89_err(rtwdev, "Unknown band type\n");
419 break;
420 }
421
422 ra_mask_bak = ra_mask;
423
424 if (mode >= RTW89_RA_MODE_HT) {
425 u64 mask = 0;
426 for (i = 0; i < rtwdev->hal.tx_nss; i++)
427 mask |= high_rate_masks[i];
428 if (mode & RTW89_RA_MODE_OFDM)
429 mask |= RA_MASK_SUBOFDM_RATES;
430 if (mode & RTW89_RA_MODE_CCK)
431 mask |= RA_MASK_SUBCCK_RATES;
432 ra_mask &= mask;
433 } else if (mode & RTW89_RA_MODE_OFDM) {
434 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
435 }
436
437 if (mode != RTW89_RA_MODE_CCK)
438 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
439
440 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
441 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
442
443 switch (link_sta->bandwidth) {
444 case IEEE80211_STA_RX_BW_160:
445 bw_mode = RTW89_CHANNEL_WIDTH_160;
446 sgi = link_sta->vht_cap.vht_supported &&
447 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
448 break;
449 case IEEE80211_STA_RX_BW_80:
450 bw_mode = RTW89_CHANNEL_WIDTH_80;
451 sgi = link_sta->vht_cap.vht_supported &&
452 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
453 break;
454 case IEEE80211_STA_RX_BW_40:
455 bw_mode = RTW89_CHANNEL_WIDTH_40;
456 sgi = link_sta->ht_cap.ht_supported &&
457 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
458 break;
459 default:
460 bw_mode = RTW89_CHANNEL_WIDTH_20;
461 sgi = link_sta->ht_cap.ht_supported &&
462 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
463 break;
464 }
465
466 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
467 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
468 ra->dcm_cap = 1;
469
470 if (rate_pattern->enable && !p2p) {
471 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
472 ra_mask &= rate_pattern->ra_mask;
473 mode = rate_pattern->ra_mode;
474 }
475
476 ra->bw_cap = bw_mode;
477 ra->er_cap = rtwsta_link->er_cap;
478 ra->mode_ctrl = mode;
479 ra->macid = rtwsta_link->mac_id;
480 ra->stbc_cap = stbc_en;
481 ra->ldpc_cap = ldpc_en;
482 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
483 ra->en_sgi = sgi;
484 ra->ra_mask = ra_mask;
485 ra->fix_giltf_en = fix_giltf_en;
486 ra->fix_giltf = fix_giltf;
487 ra->partial_bw_er = link_sta->he_cap.has_he ?
488 !!(link_sta->he_cap.he_cap_elem.phy_cap_info[6] &
489 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE) : 0;
490 ra->band = chan->band_type;
491
492 if (!csi)
493 return;
494
495 ra->fixed_csi_rate_en = false;
496 ra->ra_csi_rate_en = true;
497 ra->cr_tbl_sel = false;
498 ra->band_num = rtwvif_link->phy_idx;
499 ra->csi_bw = bw_mode;
500 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
501 ra->csi_mcs_ss_idx = 5;
502 ra->csi_mode = csi_mode;
503 }
504
rtw89_phy_ra_update_sta_link(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u32 changed)505 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
506 struct rtw89_sta_link *rtwsta_link,
507 u32 changed)
508 {
509 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
510 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
511 struct rtw89_ra_info *ra = &rtwsta_link->ra;
512 struct ieee80211_link_sta *link_sta;
513
514 rcu_read_lock();
515
516 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
517 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
518 link_sta, vif->p2p, false);
519
520 rcu_read_unlock();
521
522 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
523 ra->upd_mask = 1;
524 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
525 ra->upd_bw_nss_mask = 1;
526
527 rtw89_debug(rtwdev, RTW89_DBG_RA,
528 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
529 ra->macid,
530 ra->bw_cap,
531 ra->ss_num,
532 ra->en_sgi,
533 ra->giltf);
534
535 rtw89_fw_h2c_ra(rtwdev, ra, false);
536 }
537
rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)538 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
539 u32 changed)
540 {
541 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
542 struct rtw89_sta_link *rtwsta_link;
543 unsigned int link_id;
544
545 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
546 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed);
547 }
548
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)549 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
550 u16 rate_base, u64 ra_mask, u8 ra_mode,
551 u32 rate_ctrl, u32 ctrl_skip, bool force)
552 {
553 u8 n, c;
554
555 if (rate_ctrl == ctrl_skip)
556 return true;
557
558 n = hweight32(rate_ctrl);
559 if (n == 0)
560 return true;
561
562 if (force && n != 1)
563 return false;
564
565 if (next->enable)
566 return false;
567
568 c = __fls(rate_ctrl);
569 next->rate = rate_base + c;
570 next->ra_mode = ra_mode;
571 next->ra_mask = ra_mask;
572 next->enable = true;
573
574 return true;
575 }
576
577 enum __rtw89_hw_rate_invalid_bases {
578 /* no EHT rate for ax chip */
579 RTW89_HW_RATE_EHT_NSS1_MCS0 = RTW89_HW_RATE_INVAL,
580 RTW89_HW_RATE_EHT_NSS2_MCS0 = RTW89_HW_RATE_INVAL,
581 RTW89_HW_RATE_EHT_NSS3_MCS0 = RTW89_HW_RATE_INVAL,
582 RTW89_HW_RATE_EHT_NSS4_MCS0 = RTW89_HW_RATE_INVAL,
583 };
584
585 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
586 { \
587 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
588 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \
589 }
590
591 static
__rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const struct cfg80211_bitrate_mask * mask)592 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
593 struct rtw89_vif_link *rtwvif_link,
594 const struct cfg80211_bitrate_mask *mask)
595 {
596 struct ieee80211_supported_band *sband;
597 struct rtw89_phy_rate_pattern next_pattern = {0};
598 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
599 rtwvif_link->chanctx_idx);
600 static const u16 hw_rate_eht[][RTW89_CHIP_GEN_NUM] = {
601 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS1_MCS0),
602 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS2_MCS0),
603 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS3_MCS0),
604 RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS4_MCS0),
605 };
606 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
607 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
608 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
609 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0),
610 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0),
611 };
612 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = {
613 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0),
614 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0),
615 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0),
616 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0),
617 };
618 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = {
619 RTW89_HW_RATE_BY_CHIP_GEN(MCS0),
620 RTW89_HW_RATE_BY_CHIP_GEN(MCS8),
621 RTW89_HW_RATE_BY_CHIP_GEN(MCS16),
622 RTW89_HW_RATE_BY_CHIP_GEN(MCS24),
623 };
624 u8 band = chan->band_type;
625 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
626 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
627 u8 tx_nss = rtwdev->hal.tx_nss;
628 u8 i;
629
630 if (chip_gen == RTW89_CHIP_AX)
631 goto rs_11ax;
632
633 for (i = 0; i < tx_nss; i++)
634 if (!__check_rate_pattern(&next_pattern, hw_rate_eht[i][chip_gen],
635 RA_MASK_EHT_RATES, RTW89_RA_MODE_EHT,
636 mask->control[nl_band].eht_mcs[i],
637 0, true))
638 goto out;
639
640 rs_11ax:
641 for (i = 0; i < tx_nss; i++)
642 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
643 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
644 mask->control[nl_band].he_mcs[i],
645 0, true))
646 goto out;
647
648 for (i = 0; i < tx_nss; i++)
649 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen],
650 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
651 mask->control[nl_band].vht_mcs[i],
652 0, true))
653 goto out;
654
655 for (i = 0; i < tx_nss; i++)
656 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen],
657 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
658 mask->control[nl_band].ht_mcs[i],
659 0, true))
660 goto out;
661
662 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
663 * require at least one basic rate for ieee80211_set_bitrate_mask,
664 * so the decision just depends on if all bitrates are set or not.
665 */
666 sband = rtwdev->hw->wiphy->bands[nl_band];
667 if (band == RTW89_BAND_2G) {
668 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
669 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
670 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
671 mask->control[nl_band].legacy,
672 BIT(sband->n_bitrates) - 1, false))
673 goto out;
674 } else {
675 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
676 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
677 mask->control[nl_band].legacy,
678 BIT(sband->n_bitrates) - 1, false))
679 goto out;
680 }
681
682 if (!next_pattern.enable)
683 goto out;
684
685 if (unlikely(next_pattern.rate >= RTW89_HW_RATE_INVAL)) {
686 rtw89_debug(rtwdev, RTW89_DBG_RA,
687 "pattern invalid target: chip_gen %d, mode 0x%x\n",
688 chip_gen, next_pattern.ra_mode);
689 goto out;
690 }
691
692 rtwvif_link->rate_pattern = next_pattern;
693 rtw89_debug(rtwdev, RTW89_DBG_RA,
694 #if defined(__linux__)
695 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
696 #elif defined(__FreeBSD__)
697 "configure pattern: rate 0x%x, mask 0x%jx, mode 0x%x\n",
698 #endif
699 next_pattern.rate,
700 #if defined(__FreeBSD__)
701 (uintmax_t)
702 #endif
703 next_pattern.ra_mask,
704 next_pattern.ra_mode);
705 return;
706
707 out:
708 rtwvif_link->rate_pattern.enable = false;
709 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
710 }
711
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)712 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
713 struct ieee80211_vif *vif,
714 const struct cfg80211_bitrate_mask *mask)
715 {
716 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
717 struct rtw89_vif_link *rtwvif_link;
718 unsigned int link_id;
719
720 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
721 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask);
722 }
723
rtw89_phy_ra_update_sta_iter(void * data,struct ieee80211_sta * sta)724 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta)
725 {
726 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
727
728 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
729 }
730
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)731 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
732 {
733 ieee80211_iterate_stations_atomic(rtwdev->hw,
734 rtw89_phy_ra_update_sta_iter,
735 rtwdev);
736 }
737
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)738 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link)
739 {
740 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
741 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
742 struct rtw89_ra_info *ra = &rtwsta_link->ra;
743 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
744 struct ieee80211_link_sta *link_sta;
745 bool csi;
746
747 rcu_read_lock();
748
749 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
750 csi = rtw89_sta_has_beamformer_cap(link_sta);
751
752 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
753 link_sta, vif->p2p, csi);
754
755 rcu_read_unlock();
756
757 if (rssi > 40)
758 ra->init_rate_lv = 1;
759 else if (rssi > 20)
760 ra->init_rate_lv = 2;
761 else if (rssi > 1)
762 ra->init_rate_lv = 3;
763 else
764 ra->init_rate_lv = 0;
765 ra->upd_all = 1;
766 rtw89_debug(rtwdev, RTW89_DBG_RA,
767 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
768 ra->macid,
769 ra->mode_ctrl,
770 ra->bw_cap,
771 ra->ss_num,
772 ra->init_rate_lv);
773 rtw89_debug(rtwdev, RTW89_DBG_RA,
774 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
775 ra->dcm_cap,
776 ra->er_cap,
777 ra->ldpc_cap,
778 ra->stbc_cap,
779 ra->en_sgi,
780 ra->giltf);
781
782 rtw89_fw_h2c_ra(rtwdev, ra, csi);
783 }
784
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)785 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
786 const struct rtw89_chan *chan,
787 enum rtw89_bandwidth dbw)
788 {
789 enum rtw89_bandwidth cbw = chan->band_width;
790 u8 pri_ch = chan->primary_channel;
791 u8 central_ch = chan->channel;
792 u8 txsc_idx = 0;
793 u8 tmp = 0;
794
795 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
796 return txsc_idx;
797
798 switch (cbw) {
799 case RTW89_CHANNEL_WIDTH_40:
800 txsc_idx = pri_ch > central_ch ? 1 : 2;
801 break;
802 case RTW89_CHANNEL_WIDTH_80:
803 if (dbw == RTW89_CHANNEL_WIDTH_20) {
804 if (pri_ch > central_ch)
805 txsc_idx = (pri_ch - central_ch) >> 1;
806 else
807 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
808 } else {
809 txsc_idx = pri_ch > central_ch ? 9 : 10;
810 }
811 break;
812 case RTW89_CHANNEL_WIDTH_160:
813 if (pri_ch > central_ch)
814 tmp = (pri_ch - central_ch) >> 1;
815 else
816 tmp = ((central_ch - pri_ch) >> 1) + 1;
817
818 if (dbw == RTW89_CHANNEL_WIDTH_20) {
819 txsc_idx = tmp;
820 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
821 if (tmp == 1 || tmp == 3)
822 txsc_idx = 9;
823 else if (tmp == 5 || tmp == 7)
824 txsc_idx = 11;
825 else if (tmp == 2 || tmp == 4)
826 txsc_idx = 10;
827 else if (tmp == 6 || tmp == 8)
828 txsc_idx = 12;
829 else
830 return 0xff;
831 } else {
832 txsc_idx = pri_ch > central_ch ? 13 : 14;
833 }
834 break;
835 case RTW89_CHANNEL_WIDTH_80_80:
836 if (dbw == RTW89_CHANNEL_WIDTH_20) {
837 if (pri_ch > central_ch)
838 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
839 else
840 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
841 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
842 txsc_idx = pri_ch > central_ch ? 10 : 12;
843 } else {
844 txsc_idx = 14;
845 }
846 break;
847 default:
848 break;
849 }
850
851 return txsc_idx;
852 }
853 EXPORT_SYMBOL(rtw89_phy_get_txsc);
854
rtw89_phy_get_txsb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)855 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
856 enum rtw89_bandwidth dbw)
857 {
858 enum rtw89_bandwidth cbw = chan->band_width;
859 u8 pri_ch = chan->primary_channel;
860 u8 central_ch = chan->channel;
861 u8 txsb_idx = 0;
862
863 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
864 return txsb_idx;
865
866 switch (cbw) {
867 case RTW89_CHANNEL_WIDTH_40:
868 txsb_idx = pri_ch > central_ch ? 1 : 0;
869 break;
870 case RTW89_CHANNEL_WIDTH_80:
871 if (dbw == RTW89_CHANNEL_WIDTH_20)
872 txsb_idx = (pri_ch - central_ch + 6) / 4;
873 else
874 txsb_idx = pri_ch > central_ch ? 1 : 0;
875 break;
876 case RTW89_CHANNEL_WIDTH_160:
877 if (dbw == RTW89_CHANNEL_WIDTH_20)
878 txsb_idx = (pri_ch - central_ch + 14) / 4;
879 else if (dbw == RTW89_CHANNEL_WIDTH_40)
880 txsb_idx = (pri_ch - central_ch + 12) / 8;
881 else
882 txsb_idx = pri_ch > central_ch ? 1 : 0;
883 break;
884 case RTW89_CHANNEL_WIDTH_320:
885 if (dbw == RTW89_CHANNEL_WIDTH_20)
886 txsb_idx = (pri_ch - central_ch + 30) / 4;
887 else if (dbw == RTW89_CHANNEL_WIDTH_40)
888 txsb_idx = (pri_ch - central_ch + 28) / 8;
889 else if (dbw == RTW89_CHANNEL_WIDTH_80)
890 txsb_idx = (pri_ch - central_ch + 24) / 16;
891 else
892 txsb_idx = pri_ch > central_ch ? 1 : 0;
893 break;
894 default:
895 break;
896 }
897
898 return txsb_idx;
899 }
900 EXPORT_SYMBOL(rtw89_phy_get_txsb);
901
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)902 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
903 {
904 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
905 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
906 }
907
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)908 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
909 u32 addr, u32 mask)
910 {
911 const struct rtw89_chip_info *chip = rtwdev->chip;
912 const u32 *base_addr = chip->rf_base_addr;
913 u32 val, direct_addr;
914
915 if (rf_path >= rtwdev->chip->rf_path_num) {
916 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
917 return INV_RF_DATA;
918 }
919
920 addr &= 0xff;
921 direct_addr = base_addr[rf_path] + (addr << 2);
922 mask &= RFREG_MASK;
923
924 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
925
926 return val;
927 }
928 EXPORT_SYMBOL(rtw89_phy_read_rf);
929
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)930 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
931 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
932 {
933 bool busy;
934 bool done;
935 u32 val;
936 int ret;
937
938 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
939 1, 30, false, rtwdev);
940 if (ret) {
941 rtw89_err(rtwdev, "read rf busy swsi\n");
942 return INV_RF_DATA;
943 }
944
945 mask &= RFREG_MASK;
946
947 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
948 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
949 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
950 udelay(2);
951
952 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
953 30, false, rtwdev, R_SWSI_V1,
954 B_SWSI_R_DATA_DONE_V1);
955 if (ret) {
956 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags))
957 rtw89_err(rtwdev, "read swsi busy\n");
958 return INV_RF_DATA;
959 }
960
961 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
962 }
963
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)964 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
965 u32 addr, u32 mask)
966 {
967 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
968
969 if (rf_path >= rtwdev->chip->rf_path_num) {
970 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
971 return INV_RF_DATA;
972 }
973
974 if (ad_sel)
975 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
976 else
977 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
978 }
979 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
980
rtw89_phy_read_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)981 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
982 enum rtw89_rf_path rf_path, u32 addr)
983 {
984 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24};
985 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC};
986 bool busy, done;
987 int ret;
988 u32 val;
989
990 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
991 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
992 1, 3800, false,
993 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
994 if (ret) {
995 rtw89_warn(rtwdev, "poll HWSI is busy\n");
996 return INV_RF_DATA;
997 }
998
999 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
1000 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
1001 udelay(2);
1002
1003 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
1004 1, 3800, false,
1005 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
1006 if (ret) {
1007 rtw89_warn(rtwdev, "read HWSI is busy\n");
1008 val = INV_RF_DATA;
1009 goto out;
1010 }
1011
1012 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
1013 out:
1014 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
1015
1016 return val;
1017 }
1018
rtw89_phy_read_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)1019 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
1020 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
1021 {
1022 u32 val;
1023
1024 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1025
1026 return (val & mask) >> __ffs(mask);
1027 }
1028
rtw89_phy_read_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)1029 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1030 u32 addr, u32 mask)
1031 {
1032 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1033
1034 if (rf_path >= rtwdev->chip->rf_path_num) {
1035 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1036 return INV_RF_DATA;
1037 }
1038
1039 if (ad_sel)
1040 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
1041 else
1042 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
1043 }
1044 EXPORT_SYMBOL(rtw89_phy_read_rf_v2);
1045
rtw89_phy_read_full_rf_v3_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)1046 static u32 rtw89_phy_read_full_rf_v3_a(struct rtw89_dev *rtwdev,
1047 enum rtw89_rf_path rf_path, u32 addr)
1048 {
1049 bool done;
1050 u32 busy;
1051 int ret;
1052 u32 val;
1053
1054 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1055 1, 30, false,
1056 rtwdev, R_SW_SI_DATA_BE4,
1057 B_SW_SI_W_BUSY_BE4 | B_SW_SI_R_BUSY_BE4);
1058 if (ret) {
1059 rtw89_warn(rtwdev, "poll HWSI is busy\n");
1060 return INV_RF_DATA;
1061 }
1062
1063 val = u32_encode_bits(rf_path, GENMASK(10, 8)) |
1064 u32_encode_bits(addr, GENMASK(7, 0));
1065
1066 rtw89_phy_write32_mask(rtwdev, R_SW_SI_READ_ADDR_BE4, B_SW_SI_READ_ADDR_BE4, val);
1067
1068 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
1069 1, 30, false,
1070 rtwdev, R_SW_SI_DATA_BE4, B_SW_SI_READ_DATA_DONE_BE4);
1071 if (ret) {
1072 rtw89_warn(rtwdev, "read HWSI is busy\n");
1073 return INV_RF_DATA;
1074 }
1075
1076 val = rtw89_phy_read32_mask(rtwdev, R_SW_SI_DATA_BE4, B_SW_SI_READ_DATA_BE4);
1077
1078 return val;
1079 }
1080
rtw89_phy_read_rf_v3_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)1081 static u32 rtw89_phy_read_rf_v3_a(struct rtw89_dev *rtwdev,
1082 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
1083 {
1084 u32 val;
1085
1086 val = rtw89_phy_read_full_rf_v3_a(rtwdev, rf_path, addr);
1087
1088 return (val & mask) >> __ffs(mask);
1089 }
1090
rtw89_phy_read_rf_v3(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)1091 u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1092 u32 addr, u32 mask)
1093 {
1094 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1095
1096 if (rf_path >= rtwdev->chip->rf_path_num) {
1097 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1098 return INV_RF_DATA;
1099 }
1100
1101 if (ad_sel)
1102 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
1103 else
1104 return rtw89_phy_read_rf_v3_a(rtwdev, rf_path, addr, mask);
1105 }
1106 EXPORT_SYMBOL(rtw89_phy_read_rf_v3);
1107
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1108 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1109 u32 addr, u32 mask, u32 data)
1110 {
1111 const struct rtw89_chip_info *chip = rtwdev->chip;
1112 const u32 *base_addr = chip->rf_base_addr;
1113 u32 direct_addr;
1114
1115 if (rf_path >= rtwdev->chip->rf_path_num) {
1116 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1117 return false;
1118 }
1119
1120 addr &= 0xff;
1121 direct_addr = base_addr[rf_path] + (addr << 2);
1122 mask &= RFREG_MASK;
1123
1124 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
1125
1126 /* delay to ensure writing properly */
1127 udelay(1);
1128
1129 return true;
1130 }
1131 EXPORT_SYMBOL(rtw89_phy_write_rf);
1132
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1133 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
1134 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
1135 u32 data)
1136 {
1137 u8 bit_shift;
1138 u32 val;
1139 bool busy, b_msk_en = false;
1140 int ret;
1141
1142 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
1143 1, 30, false, rtwdev);
1144 if (ret) {
1145 rtw89_err(rtwdev, "write rf busy swsi\n");
1146 return false;
1147 }
1148
1149 data &= RFREG_MASK;
1150 mask &= RFREG_MASK;
1151
1152 if (mask != RFREG_MASK) {
1153 b_msk_en = true;
1154 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
1155 mask);
1156 bit_shift = __ffs(mask);
1157 data = (data << bit_shift) & RFREG_MASK;
1158 }
1159
1160 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
1161 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
1162 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
1163 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
1164
1165 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
1166
1167 return true;
1168 }
1169
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1170 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1171 u32 addr, u32 mask, u32 data)
1172 {
1173 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
1174
1175 if (rf_path >= rtwdev->chip->rf_path_num) {
1176 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1177 return false;
1178 }
1179
1180 if (ad_sel)
1181 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1182 else
1183 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1184 }
1185 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
1186
1187 static
rtw89_phy_write_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1188 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1189 u32 addr, u32 data)
1190 {
1191 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24};
1192 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0};
1193 bool busy;
1194 u32 val;
1195 int ret;
1196
1197 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1198 1, 3800, false,
1199 rtwdev, addr_is_idle[rf_path], BIT(29));
1200 if (ret) {
1201 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1202 return false;
1203 }
1204
1205 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) |
1206 u32_encode_bits(data, B_HWSI_DATA_VAL);
1207
1208 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1209
1210 return true;
1211 }
1212
1213 static
rtw89_phy_write_rf_a_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1214 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1215 u32 addr, u32 mask, u32 data)
1216 {
1217 u32 val;
1218
1219 if (mask == RFREG_MASK) {
1220 val = data;
1221 } else {
1222 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1223 val &= ~mask;
1224 val |= (data << __ffs(mask)) & mask;
1225 }
1226
1227 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1228 }
1229
rtw89_phy_write_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1230 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1231 u32 addr, u32 mask, u32 data)
1232 {
1233 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1234
1235 if (rf_path >= rtwdev->chip->rf_path_num) {
1236 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1237 return INV_RF_DATA;
1238 }
1239
1240 if (ad_sel)
1241 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1242 else
1243 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1244 }
1245 EXPORT_SYMBOL(rtw89_phy_write_rf_v2);
1246
1247 static
rtw89_phy_write_full_rf_v3_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1248 bool rtw89_phy_write_full_rf_v3_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1249 u32 addr, u32 data)
1250 {
1251 u32 busy;
1252 u32 val;
1253 int ret;
1254
1255 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1256 1, 30, false,
1257 rtwdev, R_SW_SI_DATA_BE4,
1258 B_SW_SI_W_BUSY_BE4 | B_SW_SI_R_BUSY_BE4);
1259 if (ret) {
1260 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1261 return false;
1262 }
1263
1264 val = u32_encode_bits(rf_path, B_SW_SI_DATA_PATH_BE4) |
1265 u32_encode_bits(addr, B_SW_SI_DATA_ADR_BE4) |
1266 u32_encode_bits(data, B_SW_SI_DATA_DAT_BE4);
1267
1268 rtw89_phy_write32(rtwdev, R_SW_SI_WDATA_BE4, val);
1269
1270 return true;
1271 }
1272
1273 static
rtw89_phy_write_rf_a_v3(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1274 bool rtw89_phy_write_rf_a_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1275 u32 addr, u32 mask, u32 data)
1276 {
1277 u32 val;
1278
1279 if (mask == RFREG_MASK) {
1280 val = data;
1281 } else {
1282 val = rtw89_phy_read_full_rf_v3_a(rtwdev, rf_path, addr);
1283 val &= ~mask;
1284 val |= (data << __ffs(mask)) & mask;
1285 }
1286
1287 return rtw89_phy_write_full_rf_v3_a(rtwdev, rf_path, addr, val);
1288 }
1289
rtw89_phy_write_rf_v3(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1290 bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1291 u32 addr, u32 mask, u32 data)
1292 {
1293 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1294
1295 if (rf_path >= rtwdev->chip->rf_path_num) {
1296 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1297 return INV_RF_DATA;
1298 }
1299
1300 if (ad_sel)
1301 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1302 else
1303 return rtw89_phy_write_rf_a_v3(rtwdev, rf_path, addr, mask, data);
1304 }
1305 EXPORT_SYMBOL(rtw89_phy_write_rf_v3);
1306
rtw89_chip_rf_v1(struct rtw89_dev * rtwdev)1307 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1308 {
1309 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1310 }
1311
__rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1312 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1313 enum rtw89_phy_idx phy_idx)
1314 {
1315 const struct rtw89_chip_info *chip = rtwdev->chip;
1316
1317 chip->ops->bb_reset(rtwdev, phy_idx);
1318 }
1319
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev)1320 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev)
1321 {
1322 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1323 if (rtwdev->dbcc_en)
1324 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1);
1325 }
1326
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1327 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1328 const struct rtw89_reg2_def *reg,
1329 enum rtw89_rf_path rf_path,
1330 void *extra_data)
1331 {
1332 u32 addr;
1333
1334 if (reg->addr == 0xfe) {
1335 mdelay(50);
1336 } else if (reg->addr == 0xfd) {
1337 mdelay(5);
1338 } else if (reg->addr == 0xfc) {
1339 mdelay(1);
1340 } else if (reg->addr == 0xfb) {
1341 udelay(50);
1342 } else if (reg->addr == 0xfa) {
1343 udelay(5);
1344 } else if (reg->addr == 0xf9) {
1345 udelay(1);
1346 } else if (reg->data == BYPASS_CR_DATA) {
1347 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1348 } else {
1349 addr = reg->addr;
1350
1351 if ((uintptr_t)extra_data == RTW89_PHY_1)
1352 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1353
1354 rtw89_phy_write32(rtwdev, addr, reg->data);
1355 }
1356 }
1357
1358 union rtw89_phy_bb_gain_arg {
1359 u32 addr;
1360 struct {
1361 union {
1362 u8 type;
1363 struct {
1364 u8 rxsc_start:4;
1365 u8 bw:4;
1366 };
1367 };
1368 u8 path;
1369 u8 gain_band;
1370 u8 cfg_type;
1371 };
1372 } __packed;
1373
1374 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1375 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1376 union rtw89_phy_bb_gain_arg arg, u32 data)
1377 {
1378 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1379 u8 type = arg.type;
1380 u8 path = arg.path;
1381 u8 gband = arg.gain_band;
1382 int i;
1383
1384 switch (type) {
1385 case 0:
1386 for (i = 0; i < 4; i++, data >>= 8)
1387 gain->lna_gain[gband][path][i] = data & 0xff;
1388 break;
1389 case 1:
1390 for (i = 4; i < 7; i++, data >>= 8)
1391 gain->lna_gain[gband][path][i] = data & 0xff;
1392 break;
1393 case 2:
1394 for (i = 0; i < 2; i++, data >>= 8)
1395 gain->tia_gain[gband][path][i] = data & 0xff;
1396 break;
1397 default:
1398 rtw89_warn(rtwdev,
1399 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
1400 arg.addr, data, type);
1401 break;
1402 }
1403 }
1404
1405 enum rtw89_phy_bb_rxsc_start_idx {
1406 RTW89_BB_RXSC_START_IDX_FULL = 0,
1407 RTW89_BB_RXSC_START_IDX_20 = 1,
1408 RTW89_BB_RXSC_START_IDX_20_1 = 5,
1409 RTW89_BB_RXSC_START_IDX_40 = 9,
1410 RTW89_BB_RXSC_START_IDX_80 = 13,
1411 };
1412
1413 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1414 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1415 union rtw89_phy_bb_gain_arg arg, u32 data)
1416 {
1417 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1418 u8 rxsc_start = arg.rxsc_start;
1419 u8 bw = arg.bw;
1420 u8 path = arg.path;
1421 u8 gband = arg.gain_band;
1422 u8 rxsc;
1423 s8 ofst;
1424 int i;
1425
1426 switch (bw) {
1427 case RTW89_CHANNEL_WIDTH_20:
1428 gain->rpl_ofst_20[gband][path] = (s8)data;
1429 break;
1430 case RTW89_CHANNEL_WIDTH_40:
1431 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1432 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1433 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1434 for (i = 0; i < 2; i++, data >>= 8) {
1435 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1436 ofst = (s8)(data & 0xff);
1437 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1438 }
1439 }
1440 break;
1441 case RTW89_CHANNEL_WIDTH_80:
1442 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1443 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1444 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1445 for (i = 0; i < 4; i++, data >>= 8) {
1446 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1447 ofst = (s8)(data & 0xff);
1448 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1449 }
1450 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1451 for (i = 0; i < 2; i++, data >>= 8) {
1452 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1453 ofst = (s8)(data & 0xff);
1454 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1455 }
1456 }
1457 break;
1458 case RTW89_CHANNEL_WIDTH_160:
1459 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1460 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1461 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1462 for (i = 0; i < 4; i++, data >>= 8) {
1463 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1464 ofst = (s8)(data & 0xff);
1465 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1466 }
1467 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
1468 for (i = 0; i < 4; i++, data >>= 8) {
1469 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
1470 ofst = (s8)(data & 0xff);
1471 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1472 }
1473 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1474 for (i = 0; i < 4; i++, data >>= 8) {
1475 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1476 ofst = (s8)(data & 0xff);
1477 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1478 }
1479 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
1480 for (i = 0; i < 2; i++, data >>= 8) {
1481 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
1482 ofst = (s8)(data & 0xff);
1483 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1484 }
1485 }
1486 break;
1487 default:
1488 rtw89_warn(rtwdev,
1489 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1490 arg.addr, data, bw);
1491 break;
1492 }
1493 }
1494
1495 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1496 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1497 union rtw89_phy_bb_gain_arg arg, u32 data)
1498 {
1499 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1500 u8 type = arg.type;
1501 u8 path = arg.path;
1502 u8 gband = arg.gain_band;
1503 int i;
1504
1505 switch (type) {
1506 case 0:
1507 for (i = 0; i < 4; i++, data >>= 8)
1508 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1509 break;
1510 case 1:
1511 for (i = 4; i < 7; i++, data >>= 8)
1512 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1513 break;
1514 default:
1515 rtw89_warn(rtwdev,
1516 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
1517 arg.addr, data, type);
1518 break;
1519 }
1520 }
1521
1522 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1523 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1524 union rtw89_phy_bb_gain_arg arg, u32 data)
1525 {
1526 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1527 u8 type = arg.type;
1528 u8 path = arg.path;
1529 u8 gband = arg.gain_band;
1530 int i;
1531
1532 switch (type) {
1533 case 0:
1534 for (i = 0; i < 4; i++, data >>= 8)
1535 gain->lna_op1db[gband][path][i] = data & 0xff;
1536 break;
1537 case 1:
1538 for (i = 4; i < 7; i++, data >>= 8)
1539 gain->lna_op1db[gband][path][i] = data & 0xff;
1540 break;
1541 case 2:
1542 for (i = 0; i < 4; i++, data >>= 8)
1543 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1544 break;
1545 case 3:
1546 for (i = 4; i < 8; i++, data >>= 8)
1547 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1548 break;
1549 default:
1550 rtw89_warn(rtwdev,
1551 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
1552 arg.addr, data, type);
1553 break;
1554 }
1555 }
1556
rtw89_phy_config_bb_gain_ax(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1557 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1558 const struct rtw89_reg2_def *reg,
1559 enum rtw89_rf_path rf_path,
1560 void *extra_data)
1561 {
1562 const struct rtw89_chip_info *chip = rtwdev->chip;
1563 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1564 struct rtw89_efuse *efuse = &rtwdev->efuse;
1565
1566 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1567 return;
1568
1569 if (arg.path >= chip->rf_path_num)
1570 return;
1571
1572 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1573 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1574 return;
1575 }
1576
1577 switch (arg.cfg_type) {
1578 case 0:
1579 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1580 break;
1581 case 1:
1582 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1583 break;
1584 case 2:
1585 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1586 break;
1587 case 3:
1588 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1589 break;
1590 case 4:
1591 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
1592 if (efuse->rfe_type < 50)
1593 break;
1594 fallthrough;
1595 default:
1596 rtw89_warn(rtwdev,
1597 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1598 arg.addr, reg->data, arg.cfg_type);
1599 break;
1600 }
1601 }
1602
1603 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1604 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1605 const struct rtw89_reg2_def *reg,
1606 enum rtw89_rf_path rf_path,
1607 struct rtw89_fw_h2c_rf_reg_info *info)
1608 {
1609 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1610 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1611
1612 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1613 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1614 rf_path, info->curr_idx);
1615 return;
1616 }
1617
1618 info->rtw89_phy_config_rf_h2c[page][idx] =
1619 cpu_to_le32((reg->addr << 20) | reg->data);
1620 info->curr_idx++;
1621 }
1622
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1623 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1624 struct rtw89_fw_h2c_rf_reg_info *info)
1625 {
1626 u16 remain = info->curr_idx;
1627 u16 len = 0;
1628 u8 i;
1629 int ret = 0;
1630
1631 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1632 rtw89_warn(rtwdev,
1633 "rf reg h2c total len %d larger than %d\n",
1634 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1635 ret = -EINVAL;
1636 goto out;
1637 }
1638
1639 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1640 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1641 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1642 if (ret)
1643 goto out;
1644 }
1645 out:
1646 info->curr_idx = 0;
1647
1648 return ret;
1649 }
1650
rtw89_phy_config_rf_reg_noio(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1651 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1652 const struct rtw89_reg2_def *reg,
1653 enum rtw89_rf_path rf_path,
1654 void *extra_data)
1655 {
1656 u32 addr = reg->addr;
1657
1658 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1659 addr == 0xfa || addr == 0xf9)
1660 return;
1661
1662 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1663 return;
1664
1665 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1666 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1667 }
1668
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1669 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1670 const struct rtw89_reg2_def *reg,
1671 enum rtw89_rf_path rf_path,
1672 void *extra_data)
1673 {
1674 if (reg->addr == 0xfe) {
1675 mdelay(50);
1676 } else if (reg->addr == 0xfd) {
1677 mdelay(5);
1678 } else if (reg->addr == 0xfc) {
1679 mdelay(1);
1680 } else if (reg->addr == 0xfb) {
1681 udelay(50);
1682 } else if (reg->addr == 0xfa) {
1683 udelay(5);
1684 } else if (reg->addr == 0xf9) {
1685 udelay(1);
1686 } else {
1687 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1688 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1689 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1690 }
1691 }
1692
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1693 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1694 const struct rtw89_reg2_def *reg,
1695 enum rtw89_rf_path rf_path,
1696 void *extra_data)
1697 {
1698 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1699
1700 if (reg->addr < 0x100)
1701 return;
1702
1703 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1704 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1705 }
1706 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1707
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1708 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1709 const struct rtw89_phy_table *table,
1710 u32 *headline_size, u32 *headline_idx,
1711 u8 rfe, u8 cv)
1712 {
1713 const struct rtw89_reg2_def *reg;
1714 u32 headline;
1715 u32 compare, target;
1716 u8 rfe_para, cv_para;
1717 u8 cv_max = 0;
1718 bool case_matched = false;
1719 u32 i;
1720
1721 for (i = 0; i < table->n_regs; i++) {
1722 reg = &table->regs[i];
1723 headline = get_phy_headline(reg->addr);
1724 if (headline != PHY_HEADLINE_VALID)
1725 break;
1726 }
1727 *headline_size = i;
1728 if (*headline_size == 0)
1729 return 0;
1730
1731 /* case 1: RFE match, CV match */
1732 compare = get_phy_compare(rfe, cv);
1733 for (i = 0; i < *headline_size; i++) {
1734 reg = &table->regs[i];
1735 target = get_phy_target(reg->addr);
1736 if (target == compare) {
1737 *headline_idx = i;
1738 return 0;
1739 }
1740 }
1741
1742 /* case 2: RFE match, CV don't care */
1743 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1744 for (i = 0; i < *headline_size; i++) {
1745 reg = &table->regs[i];
1746 target = get_phy_target(reg->addr);
1747 if (target == compare) {
1748 *headline_idx = i;
1749 return 0;
1750 }
1751 }
1752
1753 /* case 3: RFE match, CV max in table */
1754 for (i = 0; i < *headline_size; i++) {
1755 reg = &table->regs[i];
1756 rfe_para = get_phy_cond_rfe(reg->addr);
1757 cv_para = get_phy_cond_cv(reg->addr);
1758 if (rfe_para == rfe) {
1759 if (cv_para >= cv_max) {
1760 cv_max = cv_para;
1761 *headline_idx = i;
1762 case_matched = true;
1763 }
1764 }
1765 }
1766
1767 if (case_matched)
1768 return 0;
1769
1770 /* case 4: RFE don't care, CV max in table */
1771 for (i = 0; i < *headline_size; i++) {
1772 reg = &table->regs[i];
1773 rfe_para = get_phy_cond_rfe(reg->addr);
1774 cv_para = get_phy_cond_cv(reg->addr);
1775 if (rfe_para == PHY_COND_DONT_CARE) {
1776 if (cv_para >= cv_max) {
1777 cv_max = cv_para;
1778 *headline_idx = i;
1779 case_matched = true;
1780 }
1781 }
1782 }
1783
1784 if (case_matched)
1785 return 0;
1786
1787 return -EINVAL;
1788 }
1789
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1790 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1791 const struct rtw89_phy_table *table,
1792 void (*config)(struct rtw89_dev *rtwdev,
1793 const struct rtw89_reg2_def *reg,
1794 enum rtw89_rf_path rf_path,
1795 void *data),
1796 void *extra_data)
1797 {
1798 const struct rtw89_reg2_def *reg;
1799 enum rtw89_rf_path rf_path = table->rf_path;
1800 u8 rfe = rtwdev->efuse.rfe_type;
1801 u8 cv = rtwdev->hal.cv;
1802 u32 i;
1803 u32 headline_size = 0, headline_idx = 0;
1804 u32 target = 0, cfg_target;
1805 u8 cond;
1806 bool is_matched = true;
1807 bool target_found = false;
1808 int ret;
1809
1810 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1811 &headline_idx, rfe, cv);
1812 if (ret) {
1813 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1814 return;
1815 }
1816
1817 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1818 for (i = headline_size; i < table->n_regs; i++) {
1819 reg = &table->regs[i];
1820 cond = get_phy_cond(reg->addr);
1821 switch (cond) {
1822 case PHY_COND_BRANCH_IF:
1823 case PHY_COND_BRANCH_ELIF:
1824 target = get_phy_target(reg->addr);
1825 break;
1826 case PHY_COND_BRANCH_ELSE:
1827 is_matched = false;
1828 if (!target_found) {
1829 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1830 reg->addr, reg->data);
1831 return;
1832 }
1833 break;
1834 case PHY_COND_BRANCH_END:
1835 is_matched = true;
1836 target_found = false;
1837 break;
1838 case PHY_COND_CHECK:
1839 if (target_found) {
1840 is_matched = false;
1841 break;
1842 }
1843
1844 if (target == cfg_target) {
1845 is_matched = true;
1846 target_found = true;
1847 } else {
1848 is_matched = false;
1849 target_found = false;
1850 }
1851 break;
1852 default:
1853 if (is_matched)
1854 config(rtwdev, reg, rf_path, extra_data);
1855 break;
1856 }
1857 }
1858 }
1859
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1860 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1861 {
1862 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1863 const struct rtw89_chip_info *chip = rtwdev->chip;
1864 const struct rtw89_phy_table *bb_table;
1865 const struct rtw89_phy_table *bb_gain_table;
1866
1867 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1868 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1869 if (rtwdev->dbcc_en)
1870 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1871 (void *)RTW89_PHY_1);
1872
1873 rtw89_chip_init_txpwr_unit(rtwdev);
1874
1875 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1876 if (bb_gain_table)
1877 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1878 chip->phy_def->config_bb_gain, NULL);
1879
1880 rtw89_phy_bb_reset(rtwdev);
1881 }
1882
rtw89_phy_init_bb_afe(struct rtw89_dev * rtwdev)1883 void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev)
1884 {
1885 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1886 const struct rtw89_fw_element_hdr *afe_elm = elm_info->afe;
1887 const struct rtw89_phy_afe_info *info;
1888 u32 action, cat, class;
1889 u32 addr, mask, val;
1890 u32 poll, rpt;
1891 u32 n, i;
1892
1893 if (!afe_elm)
1894 return;
1895
1896 n = le32_to_cpu(afe_elm->size) / sizeof(*info);
1897
1898 for (i = 0; i < n; i++) {
1899 info = &afe_elm->u.afe.infos[i];
1900
1901 class = le32_to_cpu(info->class);
1902 switch (class) {
1903 case RTW89_FW_AFE_CLASS_P0:
1904 case RTW89_FW_AFE_CLASS_P1:
1905 case RTW89_FW_AFE_CLASS_CMN:
1906 /* Currently support two paths */
1907 break;
1908 case RTW89_FW_AFE_CLASS_P2:
1909 case RTW89_FW_AFE_CLASS_P3:
1910 case RTW89_FW_AFE_CLASS_P4:
1911 default:
1912 rtw89_warn(rtwdev, "unexpected AFE class %u\n", class);
1913 continue;
1914 }
1915
1916 addr = le32_to_cpu(info->addr);
1917 mask = le32_to_cpu(info->mask);
1918 val = le32_to_cpu(info->val);
1919 cat = le32_to_cpu(info->cat);
1920 action = le32_to_cpu(info->action);
1921
1922 switch (action) {
1923 case RTW89_FW_AFE_ACTION_WRITE:
1924 switch (cat) {
1925 case RTW89_FW_AFE_CAT_MAC:
1926 case RTW89_FW_AFE_CAT_MAC1:
1927 rtw89_write32_mask(rtwdev, addr, mask, val);
1928 break;
1929 case RTW89_FW_AFE_CAT_AFEDIG:
1930 case RTW89_FW_AFE_CAT_AFEDIG1:
1931 rtw89_write32_mask(rtwdev, addr, mask, val);
1932 break;
1933 case RTW89_FW_AFE_CAT_BB:
1934 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1935 break;
1936 case RTW89_FW_AFE_CAT_BB1:
1937 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1938 break;
1939 default:
1940 rtw89_warn(rtwdev,
1941 "unexpected AFE writing action %u\n", action);
1942 break;
1943 }
1944 break;
1945 case RTW89_FW_AFE_ACTION_POLL:
1946 for (poll = 0; poll <= 10; poll++) {
1947 /*
1948 * For CAT_BB, AFE reads register with mcu_offset 0,
1949 * so both CAT_MAC and CAT_BB use the same method.
1950 */
1951 rpt = rtw89_read32_mask(rtwdev, addr, mask);
1952 if (rpt == val)
1953 goto poll_done;
1954
1955 fsleep(1);
1956 }
1957 rtw89_warn(rtwdev, "failed to poll AFE cat=%u addr=0x%x mask=0x%x\n",
1958 cat, addr, mask);
1959 poll_done:
1960 break;
1961 case RTW89_FW_AFE_ACTION_DELAY:
1962 fsleep(addr);
1963 break;
1964 }
1965 }
1966 }
1967
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1968 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1969 {
1970 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1971 udelay(1);
1972 return rtw89_phy_read32(rtwdev, 0x8080);
1973 }
1974
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev,bool noio)1975 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1976 {
1977 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1978 enum rtw89_rf_path rf_path, void *data);
1979 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1980 const struct rtw89_chip_info *chip = rtwdev->chip;
1981 const struct rtw89_phy_table *rf_table;
1982 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1983 u8 path;
1984
1985 rf_reg_info = kzalloc_obj(*rf_reg_info);
1986 if (!rf_reg_info)
1987 return;
1988
1989 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1990 rf_table = elm_info->rf_radio[path] ?
1991 elm_info->rf_radio[path] : chip->rf_table[path];
1992 rf_reg_info->rf_path = rf_table->rf_path;
1993 if (noio)
1994 config = rtw89_phy_config_rf_reg_noio;
1995 else
1996 config = rf_table->config ? rf_table->config :
1997 rtw89_phy_config_rf_reg;
1998 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1999 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
2000 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
2001 rf_reg_info->rf_path);
2002 }
2003 kfree(rf_reg_info);
2004 }
2005
rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev * rtwdev)2006 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
2007 {
2008 const struct rtw89_chip_info *chip = rtwdev->chip;
2009 u32 val;
2010 int ret;
2011
2012 /* IQK/DPK clock & reset */
2013 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
2014 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
2015 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
2016 if (chip->chip_id != RTL8851B)
2017 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
2018 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
2019 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
2020
2021 /* check 0x8080 */
2022 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
2023
2024 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
2025 1000, false, rtwdev);
2026 if (ret)
2027 #if defined(__linux__)
2028 rtw89_err(rtwdev, "failed to poll nctl block\n");
2029 #elif defined(__FreeBSD__)
2030 rtw89_err(rtwdev, "failed to poll nctl block: ret %d val %#06x\n", ret, val);
2031 #endif
2032 }
2033
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)2034 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
2035 {
2036 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
2037 const struct rtw89_chip_info *chip = rtwdev->chip;
2038 const struct rtw89_phy_table *nctl_table;
2039
2040 rtw89_phy_preinit_rf_nctl(rtwdev);
2041
2042 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
2043 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
2044
2045 if (chip->nctl_post_table)
2046 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
2047 }
2048
rtw89_phy0_phy1_offset_ax(struct rtw89_dev * rtwdev,u32 addr)2049 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
2050 {
2051 u32 phy_page = addr >> 8;
2052 u32 ofst = 0;
2053
2054 switch (phy_page) {
2055 case 0x6:
2056 case 0x7:
2057 case 0x8:
2058 case 0x9:
2059 case 0xa:
2060 case 0xb:
2061 case 0xc:
2062 case 0xd:
2063 case 0x19:
2064 case 0x1a:
2065 case 0x1b:
2066 ofst = 0x2000;
2067 break;
2068 default:
2069 /* warning case */
2070 ofst = 0;
2071 break;
2072 }
2073
2074 if (phy_page >= 0x40 && phy_page <= 0x4f)
2075 ofst = 0x2000;
2076
2077 return ofst;
2078 }
2079
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)2080 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
2081 u32 data, enum rtw89_phy_idx phy_idx)
2082 {
2083 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
2084 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
2085 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
2086 }
2087 EXPORT_SYMBOL(rtw89_phy_write32_idx);
2088
rtw89_phy_write32_idx_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)2089 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
2090 enum rtw89_phy_idx phy_idx)
2091 {
2092 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
2093 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
2094 rtw89_phy_write32_set(rtwdev, addr, bits);
2095 }
2096 EXPORT_SYMBOL(rtw89_phy_write32_idx_set);
2097
rtw89_phy_write32_idx_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)2098 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
2099 enum rtw89_phy_idx phy_idx)
2100 {
2101 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
2102 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
2103 rtw89_phy_write32_clr(rtwdev, addr, bits);
2104 }
2105 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr);
2106
rtw89_phy_read32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,enum rtw89_phy_idx phy_idx)2107 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
2108 enum rtw89_phy_idx phy_idx)
2109 {
2110 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
2111 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
2112 return rtw89_phy_read32_mask(rtwdev, addr, mask);
2113 }
2114 EXPORT_SYMBOL(rtw89_phy_read32_idx);
2115
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)2116 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
2117 u32 val)
2118 {
2119 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
2120
2121 if (!rtwdev->dbcc_en)
2122 return;
2123
2124 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
2125 }
2126 EXPORT_SYMBOL(rtw89_phy_set_phy_regs);
2127
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)2128 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
2129 const struct rtw89_phy_reg3_tbl *tbl)
2130 {
2131 const struct rtw89_reg3_def *reg3;
2132 int i;
2133
2134 for (i = 0; i < tbl->size; i++) {
2135 reg3 = &tbl->reg3[i];
2136 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
2137 }
2138 }
2139 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
2140
rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev * rtwdev,u8 ant_gain_regd)2141 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd)
2142 {
2143 switch (ant_gain_regd) {
2144 case RTW89_ANT_GAIN_ETSI:
2145 return RTW89_ETSI;
2146 default:
2147 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2148 "unknown antenna gain domain: %d\n",
2149 ant_gain_regd);
2150 return RTW89_REGD_NUM;
2151 }
2152 }
2153
2154 /* antenna gain in unit of 0.25 dbm */
2155 #define RTW89_ANT_GAIN_2GHZ_MIN -8
2156 #define RTW89_ANT_GAIN_2GHZ_MAX 14
2157 #define RTW89_ANT_GAIN_5GHZ_MIN -8
2158 #define RTW89_ANT_GAIN_5GHZ_MAX 20
2159 #define RTW89_ANT_GAIN_6GHZ_MIN -8
2160 #define RTW89_ANT_GAIN_6GHZ_MAX 20
2161
2162 #define RTW89_ANT_GAIN_REF_2GHZ 14
2163 #define RTW89_ANT_GAIN_REF_5GHZ 20
2164 #define RTW89_ANT_GAIN_REF_6GHZ 20
2165
rtw89_phy_ant_gain_init(struct rtw89_dev * rtwdev)2166 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev)
2167 {
2168 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2169 const struct rtw89_chip_info *chip = rtwdev->chip;
2170 struct rtw89_acpi_rtag_result res = {};
2171 u32 domain;
2172 int ret;
2173 u8 i, j;
2174 u8 regd;
2175 u8 val;
2176
2177 if (!chip->support_ant_gain)
2178 return;
2179
2180 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res);
2181 if (ret) {
2182 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2183 "acpi: cannot eval rtag: %d\n", ret);
2184 return;
2185 }
2186
2187 if (res.revision != 0) {
2188 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2189 "unknown rtag revision: %d\n", res.revision);
2190 return;
2191 }
2192
2193 domain = get_unaligned_le32(&res.domain);
2194
2195 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) {
2196 if (!(domain & BIT(i)))
2197 continue;
2198
2199 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i);
2200 if (regd >= RTW89_REGD_NUM)
2201 continue;
2202 ant_gain->regd_enabled |= BIT(regd);
2203 }
2204
2205 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) {
2206 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) {
2207 val = res.ant_gain_table[i][j];
2208 switch (j) {
2209 default:
2210 case RTW89_ANT_GAIN_2GHZ_SUBBAND:
2211 val = RTW89_ANT_GAIN_REF_2GHZ -
2212 clamp_t(s8, val,
2213 RTW89_ANT_GAIN_2GHZ_MIN,
2214 RTW89_ANT_GAIN_2GHZ_MAX);
2215 break;
2216 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1:
2217 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2:
2218 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E:
2219 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4:
2220 val = RTW89_ANT_GAIN_REF_5GHZ -
2221 clamp_t(s8, val,
2222 RTW89_ANT_GAIN_5GHZ_MIN,
2223 RTW89_ANT_GAIN_5GHZ_MAX);
2224 break;
2225 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L:
2226 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H:
2227 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6:
2228 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L:
2229 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H:
2230 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8:
2231 val = RTW89_ANT_GAIN_REF_6GHZ -
2232 clamp_t(s8, val,
2233 RTW89_ANT_GAIN_6GHZ_MIN,
2234 RTW89_ANT_GAIN_6GHZ_MAX);
2235 }
2236 ant_gain->offset[i][j] = val;
2237 }
2238 }
2239 }
2240
2241 static
rtw89_phy_ant_gain_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)2242 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev,
2243 u32 center_freq)
2244 {
2245 switch (center_freq) {
2246 default:
2247 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2248 "center freq: %u to antenna gain subband is unhandled\n",
2249 center_freq);
2250 fallthrough;
2251 case 2412 ... 2484:
2252 return RTW89_ANT_GAIN_2GHZ_SUBBAND;
2253 case 5180 ... 5240:
2254 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1;
2255 case 5250 ... 5320:
2256 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2;
2257 case 5500 ... 5720:
2258 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E;
2259 case 5745 ... 5885:
2260 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4;
2261 case 5955 ... 6155:
2262 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L;
2263 case 6175 ... 6415:
2264 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H;
2265 case 6435 ... 6515:
2266 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6;
2267 case 6535 ... 6695:
2268 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L;
2269 case 6715 ... 6855:
2270 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H;
2271
2272 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H
2273 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with
2274 * struct rtw89_6ghz_span.
2275 */
2276
2277 case 6895 ... 7115:
2278 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8;
2279 }
2280 }
2281
rtw89_phy_ant_gain_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u32 center_freq)2282 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev,
2283 enum rtw89_rf_path path, u32 center_freq)
2284 {
2285 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2286 enum rtw89_ant_gain_subband subband_l, subband_h;
2287 const struct rtw89_6ghz_span *span;
2288
2289 span = rtw89_get_6ghz_span(rtwdev, center_freq);
2290
2291 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) {
2292 subband_l = span->ant_gain_subband_low;
2293 subband_h = span->ant_gain_subband_high;
2294 } else {
2295 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq);
2296 subband_h = subband_l;
2297 }
2298
2299 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2300 "center_freq %u: antenna gain subband {%u, %u}\n",
2301 center_freq, subband_l, subband_h);
2302
2303 return min(ant_gain->offset[path][subband_l],
2304 ant_gain->offset[path][subband_h]);
2305 }
2306
rtw89_phy_ant_gain_offset(struct rtw89_dev * rtwdev,u32 center_freq)2307 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u32 center_freq)
2308 {
2309 s8 offset_patha, offset_pathb;
2310
2311 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq);
2312 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq);
2313
2314 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2315 return min(offset_patha, offset_pathb);
2316
2317 return max(offset_patha, offset_pathb);
2318 }
2319
rtw89_can_apply_ant_gain(struct rtw89_dev * rtwdev,u8 band)2320 static bool rtw89_can_apply_ant_gain(struct rtw89_dev *rtwdev, u8 band)
2321 {
2322 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2323 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2324 const struct rtw89_chip_info *chip = rtwdev->chip;
2325 u8 regd = rtw89_regd_get(rtwdev, band);
2326
2327 if (!chip->support_ant_gain)
2328 return false;
2329
2330 if (ant_gain->block_country || !(ant_gain->regd_enabled & BIT(regd)))
2331 return false;
2332
2333 if (!rfe_parms->has_da)
2334 return false;
2335
2336 return true;
2337 }
2338
rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2339 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
2340 const struct rtw89_chan *chan)
2341 {
2342 s8 offset_patha, offset_pathb;
2343
2344 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type))
2345 return 0;
2346
2347 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2348 return 0;
2349
2350 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2351 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2352
2353 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb);
2354 }
2355 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset);
2356
rtw89_print_ant_gain(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_chan * chan)2357 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
2358 const struct rtw89_chan *chan)
2359 {
2360 char *p = buf, *end = buf + bufsz;
2361 s8 offset_patha, offset_pathb;
2362
2363 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type)) {
2364 p += scnprintf(p, end - p, "no DAG is applied\n");
2365 goto out;
2366 }
2367
2368 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2369 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2370
2371 p += scnprintf(p, end - p, "ChainA offset: %d dBm\n", offset_patha);
2372 p += scnprintf(p, end - p, "ChainB offset: %d dBm\n", offset_pathb);
2373
2374 out:
2375 return p - buf;
2376 }
2377
2378 static const u8 rtw89_rs_idx_num_ax[] = {
2379 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
2380 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
2381 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
2382 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
2383 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
2384 };
2385
2386 static const u8 rtw89_rs_nss_num_ax[] = {
2387 [RTW89_RS_CCK] = 1,
2388 [RTW89_RS_OFDM] = 1,
2389 [RTW89_RS_MCS] = RTW89_NSS_NUM,
2390 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
2391 [RTW89_RS_OFFSET] = 1,
2392 };
2393
rtw89_phy_raw_byr_seek(struct rtw89_dev * rtwdev,struct rtw89_txpwr_byrate * head,const struct rtw89_rate_desc * desc)2394 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
2395 struct rtw89_txpwr_byrate *head,
2396 const struct rtw89_rate_desc *desc)
2397 {
2398 switch (desc->rs) {
2399 case RTW89_RS_CCK:
2400 return &head->cck[desc->idx];
2401 case RTW89_RS_OFDM:
2402 return &head->ofdm[desc->idx];
2403 case RTW89_RS_MCS:
2404 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
2405 case RTW89_RS_HEDCM:
2406 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
2407 case RTW89_RS_OFFSET:
2408 return &head->offset[desc->idx];
2409 default:
2410 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
2411 return &head->trap;
2412 }
2413 }
2414
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)2415 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
2416 const struct rtw89_txpwr_table *tbl)
2417 {
2418 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
2419 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
2420 struct rtw89_txpwr_byrate *byr_head;
2421 struct rtw89_rate_desc desc = {};
2422 s8 *byr;
2423 u32 data;
2424 u8 i;
2425
2426 for (; cfg < end; cfg++) {
2427 byr_head = &rtwdev->byr[cfg->band][0];
2428 desc.rs = cfg->rs;
2429 desc.nss = cfg->nss;
2430 data = cfg->data;
2431
2432 for (i = 0; i < cfg->len; i++, data >>= 8) {
2433 desc.idx = cfg->shf + i;
2434 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
2435 *byr = data & 0xff;
2436 }
2437 }
2438 }
2439 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
2440
rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)2441 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
2442 {
2443 const u8 tssi_deviation_point = 0;
2444 const u8 tssi_max_deviation = 2;
2445
2446 if (dbm <= tssi_deviation_point)
2447 dbm -= tssi_max_deviation;
2448
2449 return dbm;
2450 }
2451
rtw89_phy_get_tpe_constraint(struct rtw89_dev * rtwdev,u8 band)2452 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
2453 {
2454 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2455 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
2456 s8 cstr = S8_MAX;
2457
2458 if (band == RTW89_BAND_6G && tpe->valid)
2459 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
2460
2461 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
2462 }
2463
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,u8 bw,const struct rtw89_rate_desc * rate_desc)2464 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
2465 const struct rtw89_rate_desc *rate_desc)
2466 {
2467 struct rtw89_txpwr_byrate *byr_head;
2468 s8 *byr;
2469
2470 if (rate_desc->rs == RTW89_RS_CCK)
2471 band = RTW89_BAND_2G;
2472
2473 byr_head = &rtwdev->byr[band][bw];
2474 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
2475
2476 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
2477 }
2478
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)2479 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
2480 {
2481 switch (channel_6g) {
2482 case 1 ... 29:
2483 return (channel_6g - 1) / 2;
2484 case 33 ... 61:
2485 return (channel_6g - 3) / 2;
2486 case 65 ... 93:
2487 return (channel_6g - 5) / 2;
2488 case 97 ... 125:
2489 return (channel_6g - 7) / 2;
2490 case 129 ... 157:
2491 return (channel_6g - 9) / 2;
2492 case 161 ... 189:
2493 return (channel_6g - 11) / 2;
2494 case 193 ... 221:
2495 return (channel_6g - 13) / 2;
2496 case 225 ... 253:
2497 return (channel_6g - 15) / 2;
2498 default:
2499 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
2500 return 0;
2501 }
2502 }
2503
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)2504 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
2505 {
2506 if (band == RTW89_BAND_6G)
2507 return rtw89_channel_6g_to_idx(rtwdev, channel);
2508
2509 switch (channel) {
2510 case 1 ... 14:
2511 return channel - 1;
2512 case 36 ... 64:
2513 return (channel - 36) / 2;
2514 case 100 ... 144:
2515 return ((channel - 100) / 2) + 15;
2516 case 149 ... 177:
2517 return ((channel - 149) / 2) + 38;
2518 default:
2519 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
2520 return 0;
2521 }
2522 }
2523
rtw89_phy_validate_txpwr_limit_bw(struct rtw89_dev * rtwdev,u8 band,u8 bw)2524 static bool rtw89_phy_validate_txpwr_limit_bw(struct rtw89_dev *rtwdev,
2525 u8 band, u8 bw)
2526 {
2527 switch (band) {
2528 case RTW89_BAND_2G:
2529 return bw < RTW89_2G_BW_NUM;
2530 case RTW89_BAND_5G:
2531 return bw < RTW89_5G_BW_NUM;
2532 case RTW89_BAND_6G:
2533 return bw < RTW89_6G_BW_NUM;
2534 default:
2535 return false;
2536 }
2537 }
2538
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)2539 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2540 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
2541 {
2542 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2543 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz;
2544 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz;
2545 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz;
2546 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2547 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2548 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2549 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2550 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2551 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band);
2552 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2553 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2554 s8 lmt = 0, da_lmt = S8_MAX, sar, offset = 0;
2555 u8 regd = rtw89_regd_get(rtwdev, band);
2556 u8 reg6 = regulatory->reg_6ghz_power;
2557 struct rtw89_sar_parm sar_parm = {
2558 .center_freq = freq,
2559 .ntx = ntx,
2560 };
2561 s8 cstr;
2562
2563 if (!rtw89_phy_validate_txpwr_limit_bw(rtwdev, band, bw)) {
2564 rtw89_warn(rtwdev, "invalid band %u bandwidth %u\n", band, bw);
2565 return 0;
2566 }
2567
2568 switch (band) {
2569 case RTW89_BAND_2G:
2570 if (has_ant_gain)
2571 da_lmt = (*rule_da_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2572
2573 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2574 if (lmt)
2575 break;
2576
2577 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2578 break;
2579 case RTW89_BAND_5G:
2580 if (has_ant_gain)
2581 da_lmt = (*rule_da_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2582
2583 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2584 if (lmt)
2585 break;
2586
2587 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2588 break;
2589 case RTW89_BAND_6G:
2590 if (has_ant_gain)
2591 da_lmt = (*rule_da_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2592
2593 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2594 if (lmt)
2595 break;
2596
2597 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2598 [RTW89_REG_6GHZ_POWER_DFLT]
2599 [ch_idx];
2600 break;
2601 default:
2602 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2603 return 0;
2604 }
2605
2606 da_lmt = da_lmt ?: S8_MAX;
2607 if (da_lmt != S8_MAX)
2608 offset = rtw89_phy_ant_gain_offset(rtwdev, freq);
2609
2610 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt + offset, da_lmt));
2611 sar = rtw89_query_sar(rtwdev, &sar_parm);
2612 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2613
2614 return min3(lmt, sar, cstr);
2615 }
2616 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
2617
2618 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2619 do { \
2620 u8 __i; \
2621 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
2622 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2623 band, \
2624 bw, ntx, \
2625 rs, __i, \
2626 (ch)); \
2627 } while (0)
2628
rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch)2629 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2630 struct rtw89_txpwr_limit_ax *lmt,
2631 u8 band, u8 ntx, u8 ch)
2632 {
2633 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2634 ntx, RTW89_RS_CCK, ch);
2635 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2636 ntx, RTW89_RS_CCK, ch);
2637 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2638 ntx, RTW89_RS_OFDM, ch);
2639 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2640 RTW89_CHANNEL_WIDTH_20,
2641 ntx, RTW89_RS_MCS, ch);
2642 }
2643
rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2644 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2645 struct rtw89_txpwr_limit_ax *lmt,
2646 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2647 {
2648 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2649 ntx, RTW89_RS_CCK, ch - 2);
2650 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2651 ntx, RTW89_RS_CCK, ch);
2652 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2653 ntx, RTW89_RS_OFDM, pri_ch);
2654 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2655 RTW89_CHANNEL_WIDTH_20,
2656 ntx, RTW89_RS_MCS, ch - 2);
2657 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2658 RTW89_CHANNEL_WIDTH_20,
2659 ntx, RTW89_RS_MCS, ch + 2);
2660 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2661 RTW89_CHANNEL_WIDTH_40,
2662 ntx, RTW89_RS_MCS, ch);
2663 }
2664
rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2665 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2666 struct rtw89_txpwr_limit_ax *lmt,
2667 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2668 {
2669 s8 val_0p5_n[RTW89_BF_NUM];
2670 s8 val_0p5_p[RTW89_BF_NUM];
2671 u8 i;
2672
2673 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2674 ntx, RTW89_RS_OFDM, pri_ch);
2675 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2676 RTW89_CHANNEL_WIDTH_20,
2677 ntx, RTW89_RS_MCS, ch - 6);
2678 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2679 RTW89_CHANNEL_WIDTH_20,
2680 ntx, RTW89_RS_MCS, ch - 2);
2681 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2682 RTW89_CHANNEL_WIDTH_20,
2683 ntx, RTW89_RS_MCS, ch + 2);
2684 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2685 RTW89_CHANNEL_WIDTH_20,
2686 ntx, RTW89_RS_MCS, ch + 6);
2687 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2688 RTW89_CHANNEL_WIDTH_40,
2689 ntx, RTW89_RS_MCS, ch - 4);
2690 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2691 RTW89_CHANNEL_WIDTH_40,
2692 ntx, RTW89_RS_MCS, ch + 4);
2693 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2694 RTW89_CHANNEL_WIDTH_80,
2695 ntx, RTW89_RS_MCS, ch);
2696
2697 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2698 ntx, RTW89_RS_MCS, ch - 4);
2699 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2700 ntx, RTW89_RS_MCS, ch + 4);
2701
2702 for (i = 0; i < RTW89_BF_NUM; i++)
2703 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2704 }
2705
rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2706 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2707 struct rtw89_txpwr_limit_ax *lmt,
2708 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2709 {
2710 s8 val_0p5_n[RTW89_BF_NUM];
2711 s8 val_0p5_p[RTW89_BF_NUM];
2712 s8 val_2p5_n[RTW89_BF_NUM];
2713 s8 val_2p5_p[RTW89_BF_NUM];
2714 u8 i;
2715
2716 /* fill ofdm section */
2717 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2718 ntx, RTW89_RS_OFDM, pri_ch);
2719
2720 /* fill mcs 20m section */
2721 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2722 RTW89_CHANNEL_WIDTH_20,
2723 ntx, RTW89_RS_MCS, ch - 14);
2724 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2725 RTW89_CHANNEL_WIDTH_20,
2726 ntx, RTW89_RS_MCS, ch - 10);
2727 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2728 RTW89_CHANNEL_WIDTH_20,
2729 ntx, RTW89_RS_MCS, ch - 6);
2730 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2731 RTW89_CHANNEL_WIDTH_20,
2732 ntx, RTW89_RS_MCS, ch - 2);
2733 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2734 RTW89_CHANNEL_WIDTH_20,
2735 ntx, RTW89_RS_MCS, ch + 2);
2736 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2737 RTW89_CHANNEL_WIDTH_20,
2738 ntx, RTW89_RS_MCS, ch + 6);
2739 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2740 RTW89_CHANNEL_WIDTH_20,
2741 ntx, RTW89_RS_MCS, ch + 10);
2742 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2743 RTW89_CHANNEL_WIDTH_20,
2744 ntx, RTW89_RS_MCS, ch + 14);
2745
2746 /* fill mcs 40m section */
2747 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2748 RTW89_CHANNEL_WIDTH_40,
2749 ntx, RTW89_RS_MCS, ch - 12);
2750 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2751 RTW89_CHANNEL_WIDTH_40,
2752 ntx, RTW89_RS_MCS, ch - 4);
2753 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2754 RTW89_CHANNEL_WIDTH_40,
2755 ntx, RTW89_RS_MCS, ch + 4);
2756 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2757 RTW89_CHANNEL_WIDTH_40,
2758 ntx, RTW89_RS_MCS, ch + 12);
2759
2760 /* fill mcs 80m section */
2761 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2762 RTW89_CHANNEL_WIDTH_80,
2763 ntx, RTW89_RS_MCS, ch - 8);
2764 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2765 RTW89_CHANNEL_WIDTH_80,
2766 ntx, RTW89_RS_MCS, ch + 8);
2767
2768 /* fill mcs 160m section */
2769 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2770 RTW89_CHANNEL_WIDTH_160,
2771 ntx, RTW89_RS_MCS, ch);
2772
2773 /* fill mcs 40m 0p5 section */
2774 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2775 ntx, RTW89_RS_MCS, ch - 4);
2776 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2777 ntx, RTW89_RS_MCS, ch + 4);
2778
2779 for (i = 0; i < RTW89_BF_NUM; i++)
2780 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2781
2782 /* fill mcs 40m 2p5 section */
2783 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2784 ntx, RTW89_RS_MCS, ch - 8);
2785 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2786 ntx, RTW89_RS_MCS, ch + 8);
2787
2788 for (i = 0; i < RTW89_BF_NUM; i++)
2789 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2790 }
2791
2792 static
rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ax * lmt,u8 ntx)2793 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2794 const struct rtw89_chan *chan,
2795 struct rtw89_txpwr_limit_ax *lmt,
2796 u8 ntx)
2797 {
2798 u8 band = chan->band_type;
2799 u8 pri_ch = chan->primary_channel;
2800 u8 ch = chan->channel;
2801 u8 bw = chan->band_width;
2802
2803 memset(lmt, 0, sizeof(*lmt));
2804
2805 switch (bw) {
2806 case RTW89_CHANNEL_WIDTH_20:
2807 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2808 break;
2809 case RTW89_CHANNEL_WIDTH_40:
2810 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2811 pri_ch);
2812 break;
2813 case RTW89_CHANNEL_WIDTH_80:
2814 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2815 pri_ch);
2816 break;
2817 case RTW89_CHANNEL_WIDTH_160:
2818 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2819 pri_ch);
2820 break;
2821 }
2822 }
2823
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)2824 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2825 u8 ru, u8 ntx, u8 ch)
2826 {
2827 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2828 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz;
2829 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz;
2830 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz;
2831 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2832 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2833 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2834 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2835 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2836 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band);
2837 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2838 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2839 s8 lmt_ru = 0, da_lmt_ru = S8_MAX, sar, offset = 0;
2840 u8 regd = rtw89_regd_get(rtwdev, band);
2841 u8 reg6 = regulatory->reg_6ghz_power;
2842 struct rtw89_sar_parm sar_parm = {
2843 .center_freq = freq,
2844 .ntx = ntx,
2845 };
2846 s8 cstr;
2847
2848 switch (band) {
2849 case RTW89_BAND_2G:
2850 if (has_ant_gain)
2851 da_lmt_ru = (*rule_da_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2852
2853 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2854 if (lmt_ru)
2855 break;
2856
2857 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2858 break;
2859 case RTW89_BAND_5G:
2860 if (has_ant_gain)
2861 da_lmt_ru = (*rule_da_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2862
2863 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2864 if (lmt_ru)
2865 break;
2866
2867 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2868 break;
2869 case RTW89_BAND_6G:
2870 if (has_ant_gain)
2871 da_lmt_ru = (*rule_da_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2872
2873 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2874 if (lmt_ru)
2875 break;
2876
2877 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2878 [RTW89_REG_6GHZ_POWER_DFLT]
2879 [ch_idx];
2880 break;
2881 default:
2882 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2883 return 0;
2884 }
2885
2886 da_lmt_ru = da_lmt_ru ?: S8_MAX;
2887 if (da_lmt_ru != S8_MAX)
2888 offset = rtw89_phy_ant_gain_offset(rtwdev, freq);
2889
2890 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt_ru + offset, da_lmt_ru));
2891 sar = rtw89_query_sar(rtwdev, &sar_parm);
2892 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2893
2894 return min3(lmt_ru, sar, cstr);
2895 }
2896
2897 static void
rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2898 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2899 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2900 u8 band, u8 ntx, u8 ch)
2901 {
2902 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2903 RTW89_RU26,
2904 ntx, ch);
2905 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2906 RTW89_RU52,
2907 ntx, ch);
2908 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2909 RTW89_RU106,
2910 ntx, ch);
2911 }
2912
2913 static void
rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2914 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2915 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2916 u8 band, u8 ntx, u8 ch)
2917 {
2918 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2919 RTW89_RU26,
2920 ntx, ch - 2);
2921 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2922 RTW89_RU26,
2923 ntx, ch + 2);
2924 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2925 RTW89_RU52,
2926 ntx, ch - 2);
2927 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2928 RTW89_RU52,
2929 ntx, ch + 2);
2930 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2931 RTW89_RU106,
2932 ntx, ch - 2);
2933 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2934 RTW89_RU106,
2935 ntx, ch + 2);
2936 }
2937
2938 static void
rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2939 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2940 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2941 u8 band, u8 ntx, u8 ch)
2942 {
2943 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2944 RTW89_RU26,
2945 ntx, ch - 6);
2946 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2947 RTW89_RU26,
2948 ntx, ch - 2);
2949 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2950 RTW89_RU26,
2951 ntx, ch + 2);
2952 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2953 RTW89_RU26,
2954 ntx, ch + 6);
2955 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2956 RTW89_RU52,
2957 ntx, ch - 6);
2958 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2959 RTW89_RU52,
2960 ntx, ch - 2);
2961 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2962 RTW89_RU52,
2963 ntx, ch + 2);
2964 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2965 RTW89_RU52,
2966 ntx, ch + 6);
2967 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2968 RTW89_RU106,
2969 ntx, ch - 6);
2970 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2971 RTW89_RU106,
2972 ntx, ch - 2);
2973 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2974 RTW89_RU106,
2975 ntx, ch + 2);
2976 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2977 RTW89_RU106,
2978 ntx, ch + 6);
2979 }
2980
2981 static void
rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2982 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2983 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2984 u8 band, u8 ntx, u8 ch)
2985 {
2986 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2987 int i;
2988
2989 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2990 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) {
2991 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2992 RTW89_RU26,
2993 ntx,
2994 ch + ofst[i]);
2995 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2996 RTW89_RU52,
2997 ntx,
2998 ch + ofst[i]);
2999 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
3000 RTW89_RU106,
3001 ntx,
3002 ch + ofst[i]);
3003 }
3004 }
3005
3006 static
rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 ntx)3007 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
3008 const struct rtw89_chan *chan,
3009 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
3010 u8 ntx)
3011 {
3012 u8 band = chan->band_type;
3013 u8 ch = chan->channel;
3014 u8 bw = chan->band_width;
3015
3016 memset(lmt_ru, 0, sizeof(*lmt_ru));
3017
3018 switch (bw) {
3019 case RTW89_CHANNEL_WIDTH_20:
3020 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
3021 ch);
3022 break;
3023 case RTW89_CHANNEL_WIDTH_40:
3024 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
3025 ch);
3026 break;
3027 case RTW89_CHANNEL_WIDTH_80:
3028 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
3029 ch);
3030 break;
3031 case RTW89_CHANNEL_WIDTH_160:
3032 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
3033 ch);
3034 break;
3035 }
3036 }
3037
rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)3038 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
3039 const struct rtw89_chan *chan,
3040 enum rtw89_phy_idx phy_idx)
3041 {
3042 u8 max_nss_num = rtwdev->chip->rf_path_num;
3043 static const u8 rs[] = {
3044 RTW89_RS_CCK,
3045 RTW89_RS_OFDM,
3046 RTW89_RS_MCS,
3047 RTW89_RS_HEDCM,
3048 };
3049 struct rtw89_rate_desc cur = {};
3050 u8 band = chan->band_type;
3051 u8 ch = chan->channel;
3052 u32 addr, val;
3053 s8 v[4] = {};
3054 u8 i;
3055
3056 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
3057 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
3058
3059 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
3060 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
3061 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
3062 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
3063
3064 addr = R_AX_PWR_BY_RATE;
3065 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
3066 for (i = 0; i < ARRAY_SIZE(rs); i++) {
3067 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
3068 continue;
3069
3070 cur.rs = rs[i];
3071 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
3072 cur.idx++) {
3073 v[cur.idx % 4] =
3074 rtw89_phy_read_txpwr_byrate(rtwdev,
3075 band, 0,
3076 &cur);
3077
3078 if ((cur.idx + 1) % 4)
3079 continue;
3080
3081 val = FIELD_PREP(GENMASK(7, 0), v[0]) |
3082 FIELD_PREP(GENMASK(15, 8), v[1]) |
3083 FIELD_PREP(GENMASK(23, 16), v[2]) |
3084 FIELD_PREP(GENMASK(31, 24), v[3]);
3085
3086 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
3087 val);
3088 addr += 4;
3089 }
3090 }
3091 }
3092 }
3093
3094 static
rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)3095 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
3096 const struct rtw89_chan *chan,
3097 enum rtw89_phy_idx phy_idx)
3098 {
3099 struct rtw89_rate_desc desc = {
3100 .nss = RTW89_NSS_1,
3101 .rs = RTW89_RS_OFFSET,
3102 };
3103 u8 band = chan->band_type;
3104 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
3105 u32 val;
3106
3107 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
3108
3109 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++)
3110 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
3111
3112 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5);
3113 val = FIELD_PREP(GENMASK(3, 0), v[0]) |
3114 FIELD_PREP(GENMASK(7, 4), v[1]) |
3115 FIELD_PREP(GENMASK(11, 8), v[2]) |
3116 FIELD_PREP(GENMASK(15, 12), v[3]) |
3117 FIELD_PREP(GENMASK(19, 16), v[4]);
3118
3119 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
3120 GENMASK(19, 0), val);
3121 }
3122
rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)3123 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
3124 const struct rtw89_chan *chan,
3125 enum rtw89_phy_idx phy_idx)
3126 {
3127 u8 max_ntx_num = rtwdev->chip->rf_path_num;
3128 struct rtw89_txpwr_limit_ax lmt;
3129 u8 ch = chan->channel;
3130 u8 bw = chan->band_width;
3131 const s8 *ptr;
3132 u32 addr, val;
3133 u8 i, j;
3134
3135 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
3136 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
3137
3138 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) !=
3139 RTW89_TXPWR_LMT_PAGE_SIZE_AX);
3140
3141 addr = R_AX_PWR_LMT;
3142 for (i = 0; i < max_ntx_num; i++) {
3143 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
3144
3145 ptr = (s8 *)&lmt;
3146 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX;
3147 j += 4, addr += 4, ptr += 4) {
3148 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
3149 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
3150 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
3151 FIELD_PREP(GENMASK(31, 24), ptr[3]);
3152
3153 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
3154 }
3155 }
3156 }
3157
rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)3158 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
3159 const struct rtw89_chan *chan,
3160 enum rtw89_phy_idx phy_idx)
3161 {
3162 u8 max_ntx_num = rtwdev->chip->rf_path_num;
3163 struct rtw89_txpwr_limit_ru_ax lmt_ru;
3164 u8 ch = chan->channel;
3165 u8 bw = chan->band_width;
3166 const s8 *ptr;
3167 u32 addr, val;
3168 u8 i, j;
3169
3170 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
3171 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
3172
3173 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) !=
3174 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX);
3175
3176 addr = R_AX_PWR_RU_LMT;
3177 for (i = 0; i < max_ntx_num; i++) {
3178 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
3179
3180 ptr = (s8 *)&lmt_ru;
3181 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX;
3182 j += 4, addr += 4, ptr += 4) {
3183 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
3184 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
3185 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
3186 FIELD_PREP(GENMASK(31, 24), ptr[3]);
3187
3188 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
3189 }
3190 }
3191 }
3192
3193 struct rtw89_phy_iter_ra_data {
3194 struct rtw89_dev *rtwdev;
3195 struct sk_buff *c2h;
3196 };
3197
__rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,struct rtw89_phy_iter_ra_data * ra_data)3198 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
3199 struct ieee80211_link_sta *link_sta,
3200 struct rtw89_phy_iter_ra_data *ra_data)
3201 {
3202 struct rtw89_dev *rtwdev = ra_data->rtwdev;
3203 const struct rtw89_c2h_ra_rpt *c2h =
3204 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
3205 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
3206 const struct rtw89_chip_info *chip = rtwdev->chip;
3207 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
3208 u8 mode, rate, bw, giltf, mac_id;
3209 u16 legacy_bitrate;
3210 bool valid;
3211 u8 mcs = 0;
3212 u8 t;
3213
3214 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
3215 if (mac_id != rtwsta_link->mac_id)
3216 return;
3217
3218 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
3219 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
3220 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
3221 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
3222
3223 if (format_v1) {
3224 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
3225 rate |= u8_encode_bits(t, BIT(7));
3226 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
3227 bw |= u8_encode_bits(t, BIT(2));
3228 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
3229 mode |= u8_encode_bits(t, BIT(2));
3230 }
3231
3232 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
3233 valid = rtw89_legacy_rate_to_bitrate(rtwdev, rate, &legacy_bitrate);
3234 if (!valid)
3235 return;
3236 }
3237
3238 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
3239
3240 switch (mode) {
3241 case RTW89_RA_RPT_MODE_LEGACY:
3242 ra_report->txrate.legacy = legacy_bitrate;
3243 break;
3244 case RTW89_RA_RPT_MODE_HT:
3245 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
3246 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
3247 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
3248 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
3249 else
3250 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
3251 ra_report->txrate.mcs = rate;
3252 if (giltf)
3253 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
3254 mcs = ra_report->txrate.mcs & 0x07;
3255 break;
3256 case RTW89_RA_RPT_MODE_VHT:
3257 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
3258 ra_report->txrate.mcs = format_v1 ?
3259 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
3260 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
3261 ra_report->txrate.nss = format_v1 ?
3262 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
3263 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
3264 if (giltf)
3265 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
3266 mcs = ra_report->txrate.mcs;
3267 break;
3268 case RTW89_RA_RPT_MODE_HE:
3269 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
3270 ra_report->txrate.mcs = format_v1 ?
3271 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
3272 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
3273 ra_report->txrate.nss = format_v1 ?
3274 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
3275 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
3276 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
3277 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
3278 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
3279 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
3280 else
3281 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
3282 mcs = ra_report->txrate.mcs;
3283 break;
3284 case RTW89_RA_RPT_MODE_EHT:
3285 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
3286 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
3287 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
3288 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
3289 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
3290 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
3291 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
3292 else
3293 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
3294 mcs = ra_report->txrate.mcs;
3295 break;
3296 }
3297
3298 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
3299 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
3300 ra_report->hw_rate = format_v1 ?
3301 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
3302 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
3303 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
3304 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
3305 ra_report->might_fallback_legacy = mcs <= 2;
3306 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
3307 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
3308 }
3309
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)3310 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
3311 {
3312 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
3313 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3314 struct rtw89_sta_link *rtwsta_link;
3315 struct ieee80211_link_sta *link_sta;
3316 unsigned int link_id;
3317
3318 rcu_read_lock();
3319
3320 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
3321 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
3322 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
3323 }
3324
3325 rcu_read_unlock();
3326 }
3327
3328 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3329 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3330 {
3331 struct rtw89_phy_iter_ra_data ra_data;
3332
3333 ra_data.rtwdev = rtwdev;
3334 ra_data.c2h = c2h;
3335 ieee80211_iterate_stations_atomic(rtwdev->hw,
3336 rtw89_phy_c2h_ra_rpt_iter,
3337 &ra_data);
3338 }
3339
3340 static
3341 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
3342 struct sk_buff *c2h, u32 len) = {
3343 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
3344 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
3345 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
3346 [RTW89_PHY_C2H_FUNC_ACCELERATE_EN] = rtw89_fw_c2h_dummy_handler,
3347 };
3348
3349 static void
rtw89_phy_c2h_lowrt_rty(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3350 rtw89_phy_c2h_lowrt_rty(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3351 {
3352 }
3353
3354 static void
rtw89_phy_c2h_lps_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3355 rtw89_phy_c2h_lps_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3356 {
3357 const struct rtw89_c2h_lps_rpt *c2h_rpt = (const void *)c2h->data;
3358 const __le32 *data_a, *data_b;
3359 u16 len_info, cr_len, idx;
3360 const __le16 *addr;
3361 const u8 *info;
3362
3363 /* elements size of BBCR/BBMCUCR/RFCR are 6/6/10 bytes respectively */
3364 cr_len = c2h_rpt->cnt_bbcr * 6 +
3365 c2h_rpt->cnt_bbmcucr * 6 +
3366 c2h_rpt->cnt_rfcr * 10;
3367 len_info = len - (sizeof(*c2h_rpt) + cr_len);
3368
3369 if (len < sizeof(*c2h_rpt) + cr_len || len_info % 4 != 0) {
3370 rtw89_debug(rtwdev, RTW89_DBG_PS,
3371 "Invalid LPS RPT len(%d) TYPE(%d) CRCNT: BB(%d) MCU(%d) RF(%d)\n",
3372 len, c2h_rpt->type, c2h_rpt->cnt_bbcr,
3373 c2h_rpt->cnt_bbmcucr, c2h_rpt->cnt_rfcr);
3374 return;
3375 }
3376
3377 rtw89_debug(rtwdev, RTW89_DBG_PS,
3378 "LPS RPT TYPE(%d), CRCNT: BB(%d) MCU(%d) RF(%d)\n",
3379 c2h_rpt->type, c2h_rpt->cnt_bbcr,
3380 c2h_rpt->cnt_bbmcucr, c2h_rpt->cnt_rfcr);
3381
3382 info = &c2h_rpt->data[0];
3383 for (idx = 0; idx < len_info; idx += 4, info += 4)
3384 rtw89_debug(rtwdev, RTW89_DBG_PS,
3385 "BB LPS INFO (%02d) - 0x%02x,0x%02x,0x%02x,0x%02x\n",
3386 idx, info[3], info[2], info[1], info[0]);
3387
3388 addr = (const void *)(info);
3389 data_a = (const void *)(addr + c2h_rpt->cnt_bbcr);
3390 for (idx = 0; idx < c2h_rpt->cnt_bbcr; idx++, addr++, data_a++)
3391 rtw89_debug(rtwdev, RTW89_DBG_PS,
3392 "LPS BB CR - 0x%04x=0x%08x\n",
3393 le16_to_cpu(*addr), le32_to_cpu(*data_a));
3394
3395 addr = (const void *)data_a;
3396 data_a = (const void *)(addr + c2h_rpt->cnt_bbmcucr);
3397 for (idx = 0; idx < c2h_rpt->cnt_bbmcucr; idx++, addr++, data_a++)
3398 rtw89_debug(rtwdev, RTW89_DBG_PS,
3399 "LPS BBMCU - 0x%04x=0x%08x\n",
3400 le16_to_cpu(*addr), le32_to_cpu(*data_a));
3401
3402 addr = (const void *)data_a;
3403 data_a = (const void *)(addr + c2h_rpt->cnt_rfcr);
3404 data_b = (const void *)(data_a + c2h_rpt->cnt_rfcr);
3405 for (idx = 0; idx < c2h_rpt->cnt_rfcr; idx++, addr++, data_a++, data_b++)
3406 rtw89_debug(rtwdev, RTW89_DBG_PS,
3407 "LPS RFCR - 0x%04x=0x%05x,0x%05x\n",
3408 le16_to_cpu(*addr), le32_to_cpu(*data_a),
3409 le32_to_cpu(*data_b));
3410 }
3411
3412 static void
rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3413 rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3414 {
3415 const struct rtw89_c2h_fw_scan_rpt *c2h_rpt =
3416 (const struct rtw89_c2h_fw_scan_rpt *)c2h->data;
3417
3418 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3419 "%s: band: %u, op_chan: %u, PD_low_bd(ofdm, cck): (-%d, %d), phy_idx: %u\n",
3420 __func__, c2h_rpt->band, c2h_rpt->center_ch,
3421 PD_LOWER_BOUND_BASE - (c2h_rpt->ofdm_pd_idx << 1),
3422 c2h_rpt->cck_pd_idx, c2h_rpt->phy_idx);
3423 }
3424
3425 static
3426 void (* const rtw89_phy_c2h_dm_handler[])(struct rtw89_dev *rtwdev,
3427 struct sk_buff *c2h, u32 len) = {
3428 [RTW89_PHY_C2H_DM_FUNC_FW_TEST] = NULL,
3429 [RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT] = NULL,
3430 [RTW89_PHY_C2H_DM_FUNC_SIGB] = NULL,
3431 [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty,
3432 [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL,
3433 [RTW89_PHY_C2H_DM_FUNC_LPS] = rtw89_phy_c2h_lps_rpt,
3434 [RTW89_PHY_C2H_DM_FUNC_ENV_MNTR] = rtw89_fw_c2h_dummy_handler,
3435 [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt,
3436 };
3437
3438 static
rtw89_phy_c2h_rfk_tas_pwr(struct rtw89_dev * rtwdev,const struct rtw89_c2h_rf_tas_rpt_log * content)3439 void rtw89_phy_c2h_rfk_tas_pwr(struct rtw89_dev *rtwdev,
3440 const struct rtw89_c2h_rf_tas_rpt_log *content)
3441 {
3442 const enum rtw89_sar_sources src = rtwdev->sar.src;
3443 struct rtw89_tas_info *tas = &rtwdev->tas;
3444 u64 linear = 0;
3445 u32 i, cur_idx;
3446 s16 txpwr;
3447
3448 if (!tas->enable || src == RTW89_SAR_SOURCE_NONE)
3449 return;
3450
3451 cur_idx = le32_to_cpu(content->cur_idx);
3452 for (i = 0; i < cur_idx; i++) {
3453 txpwr = le16_to_cpu(content->txpwr_history[i]);
3454 linear += rtw89_db_quarter_to_linear(txpwr);
3455
3456 rtw89_debug(rtwdev, RTW89_DBG_SAR,
3457 "tas: index: %u, txpwr: %d\n", i, txpwr);
3458 }
3459
3460 if (cur_idx == 0)
3461 tas->instant_txpwr = rtw89_db_to_linear(0);
3462 else
3463 tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx);
3464 }
3465
rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3466 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
3467 enum rtw89_phy_c2h_rfk_log_func func,
3468 void *content, u16 len)
3469 {
3470 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk;
3471 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck;
3472 struct rtw89_c2h_rf_txiqk_rpt_log *txiqk;
3473 struct rtw89_c2h_rf_cim3k_rpt_log *cim3k;
3474 struct rtw89_c2h_rf_dack_rpt_log *dack;
3475 struct rtw89_c2h_rf_tssi_rpt_log *tssi;
3476 struct rtw89_c2h_rf_dpk_rpt_log *dpk;
3477 struct rtw89_c2h_rf_iqk_rpt_log *iqk;
3478 int i, j, k;
3479
3480 switch (func) {
3481 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3482 if (len != sizeof(*iqk))
3483 goto out;
3484
3485 iqk = content;
3486 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3487 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init);
3488 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3489 "[IQK] iqk->is_reload = %x\n", iqk->is_reload);
3490 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3491 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk);
3492 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3493 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en);
3494 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3495 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en);
3496 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3497 "[IQK] iqk->lok_en = %x\n", iqk->lok_en);
3498 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3499 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en);
3500 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3501 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en);
3502 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3503 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en);
3504 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3505 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk);
3506 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3507 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable);
3508 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3509 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en);
3510 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3511 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en);
3512 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3513 "[IQK] iqk->version = %x\n", iqk->version);
3514 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3515 "[IQK] iqk->phy = %x\n", iqk->phy);
3516 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3517 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status);
3518
3519 for (i = 0; i < 2; i++) {
3520 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3521 "[IQK] ======== Path %x ========\n", i);
3522 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n",
3523 i, iqk->iqk_band[i]);
3524 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n",
3525 i, iqk->iqk_ch[i]);
3526 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n",
3527 i, iqk->iqk_bw[i]);
3528 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->rf_0x18[%d] = %x\n",
3529 i, le32_to_cpu(iqk->rf_0x18[i]));
3530 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n",
3531 i, le32_to_cpu(iqk->lok_idac[i]));
3532 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n",
3533 i, le32_to_cpu(iqk->lok_vbuf[i]));
3534 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n",
3535 i, iqk->iqk_tx_fail[i]);
3536 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n",
3537 i, iqk->iqk_rx_fail[i]);
3538 for (j = 0; j < 6; j++)
3539 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3540 "[IQK] iqk->rftxgain[%d][%d] = %x\n",
3541 i, j, le32_to_cpu(iqk->rftxgain[i][j]));
3542 for (j = 0; j < 6; j++)
3543 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3544 "[IQK] iqk->tx_xym[%d][%d] = %x\n",
3545 i, j, le32_to_cpu(iqk->tx_xym[i][j]));
3546 for (j = 0; j < 6; j++)
3547 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3548 "[IQK] iqk->rfrxgain[%d][%d] = %x\n",
3549 i, j, le32_to_cpu(iqk->rfrxgain[i][j]));
3550 for (j = 0; j < 6; j++)
3551 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3552 "[IQK] iqk->rx_xym[%d][%d] = %x\n",
3553 i, j, le32_to_cpu(iqk->rx_xym[i][j]));
3554
3555 if (!iqk->iqk_xym_en)
3556 continue;
3557
3558 for (j = 0; j < 32; j++)
3559 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3560 "[IQK] iqk->rx_wb_xym[%d][%d] = %x\n",
3561 i, j, iqk->rx_wb_xym[i][j]);
3562 }
3563 return;
3564 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3565 if (len != sizeof(*dpk))
3566 goto out;
3567
3568 dpk = content;
3569 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3570 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
3571 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
3572 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3573 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n",
3574 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
3575 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3576 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n",
3577 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
3578 return;
3579 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3580 if (len != sizeof(*dack))
3581 goto out;
3582
3583 dack = content;
3584
3585 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n");
3586 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3587 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n",
3588 dack->fwdack_ver, dack->fwdack_info_ver, 0x2);
3589
3590 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3591 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n",
3592 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout,
3593 dack->adgaink_timeout, dack->msbk_timeout);
3594 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3595 "[DACK]DACK fail = 0x%x\n", dack->dack_fail);
3596 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3597 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]);
3598 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3599 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]);
3600 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3601 "[DACK]DRCK = [0x%x]\n", dack->rck_d);
3602 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
3603 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
3604 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
3605 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
3606 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
3607 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
3608 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
3609 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
3610
3611 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
3612 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0],
3613 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]);
3614 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
3615 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0],
3616 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]);
3617 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
3618 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0],
3619 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]);
3620 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
3621 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0],
3622 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]);
3623
3624 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3625 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
3626 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3627 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
3628
3629 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3630 dack->dadck_d[0][0], dack->dadck_d[0][1]);
3631 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3632 dack->dadck_d[1][0], dack->dadck_d[1][1]);
3633
3634 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
3635 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]);
3636 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
3637 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]);
3638
3639 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
3640 for (i = 0; i < 0x10; i++)
3641 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3642 dack->msbk_d[0][0][i]);
3643
3644 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
3645 for (i = 0; i < 0x10; i++)
3646 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3647 dack->msbk_d[0][1][i]);
3648
3649 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
3650 for (i = 0; i < 0x10; i++)
3651 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3652 dack->msbk_d[1][0][i]);
3653
3654 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
3655 for (i = 0; i < 0x10; i++)
3656 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3657 dack->msbk_d[1][1][i]);
3658 return;
3659 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3660 if (len != sizeof(*rxdck))
3661 goto out;
3662
3663 rxdck = content;
3664 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3665 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
3666 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
3667 rxdck->timeout);
3668 return;
3669 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3670 if (len != sizeof(*tssi))
3671 goto out;
3672
3673 tssi = content;
3674 for (i = 0; i < 2; i++) {
3675 for (j = 0; j < 2; j++) {
3676 for (k = 0; k < 4; k++) {
3677 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3678 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n",
3679 i, j, k, tssi->alignment_power_cw_h[i][j][k]);
3680 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3681 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n",
3682 i, j, k, tssi->alignment_power_cw_l[i][j][k]);
3683 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3684 "[TSSI] alignment_power[%d][%d][%d]=%d\n",
3685 i, j, k, tssi->alignment_power[i][j][k]);
3686 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3687 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n",
3688 i, j, k,
3689 (tssi->alignment_power_cw_h[i][j][k] << 8) +
3690 tssi->alignment_power_cw_l[i][j][k]);
3691 }
3692
3693 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3694 "[TSSI] tssi_alimk_state[%d][%d]=%d\n",
3695 i, j, tssi->tssi_alimk_state[i][j]);
3696 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3697 "[TSSI] default_txagc_offset[%d]=%d\n",
3698 j, tssi->default_txagc_offset[0][j]);
3699 }
3700 }
3701 return;
3702 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3703 if (len != sizeof(*txgapk))
3704 goto out;
3705
3706 txgapk = content;
3707 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3708 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n",
3709 le32_to_cpu(txgapk->r0x8010[0]),
3710 le32_to_cpu(txgapk->r0x8010[1]));
3711 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
3712 txgapk->chk_id);
3713 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
3714 le32_to_cpu(txgapk->chk_cnt));
3715 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
3716 txgapk->ver);
3717 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt d_bnd_ok = %d\n",
3718 txgapk->d_bnd_ok);
3719 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt stage[0] = 0x%x\n",
3720 le32_to_cpu(txgapk->stage[0]));
3721 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt stage[1] = 0x%x\n",
3722 le32_to_cpu(txgapk->stage[1]));
3723 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]failcode[0] = 0x%x\n",
3724 le16_to_cpu(txgapk->failcode[0]));
3725 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]failcode[1] = 0x%x\n",
3726 le16_to_cpu(txgapk->failcode[1]));
3727
3728 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
3729 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
3730 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
3731 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
3732 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
3733 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
3734 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
3735 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
3736 return;
3737 case RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR:
3738 if (len != sizeof(struct rtw89_c2h_rf_tas_rpt_log))
3739 goto out;
3740
3741 rtw89_phy_c2h_rfk_tas_pwr(rtwdev, content);
3742 return;
3743 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK:
3744 if (len != sizeof(*txiqk))
3745 goto out;
3746 return;
3747 case RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K:
3748 if (len != sizeof(*cim3k))
3749 goto out;
3750 return;
3751 default:
3752 break;
3753 }
3754
3755 out:
3756 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3757 "unexpected RFK func %d report log with length %d\n", func, len);
3758 }
3759
rtw89_phy_c2h_rfk_run_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3760 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
3761 enum rtw89_phy_c2h_rfk_log_func func,
3762 void *content, u16 len)
3763 {
3764 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
3765 const struct rtw89_c2h_rf_run_log *log = content;
3766 const struct rtw89_fw_element_hdr *elm;
3767 u32 fmt_idx;
3768 u16 offset;
3769
3770 if (sizeof(*log) != len)
3771 return false;
3772
3773 if (!elm_info->rfk_log_fmt)
3774 return false;
3775
3776 elm = elm_info->rfk_log_fmt->elm[func];
3777 fmt_idx = le32_to_cpu(log->fmt_idx);
3778 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
3779 return false;
3780
3781 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
3782 if (offset == 0)
3783 return false;
3784
3785 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
3786 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
3787 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
3788
3789 return true;
3790 }
3791
rtw89_phy_c2h_rfk_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len,enum rtw89_phy_c2h_rfk_log_func func,const char * rfk_name)3792 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3793 u32 len, enum rtw89_phy_c2h_rfk_log_func func,
3794 const char *rfk_name)
3795 {
3796 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
3797 struct rtw89_c2h_rf_log_hdr *log_hdr;
3798 #if defined(__linux__)
3799 void *log_ptr = c2h_hdr;
3800 #elif defined(__FreeBSD__)
3801 u8 *log_ptr = (void *)c2h_hdr;
3802 #endif
3803 u16 content_len;
3804 u16 chunk_len;
3805 bool handled;
3806
3807 log_ptr += sizeof(*c2h_hdr);
3808 len -= sizeof(*c2h_hdr);
3809
3810 while (len > sizeof(*log_hdr)) {
3811 #if defined(__linux__)
3812 log_hdr = log_ptr;
3813 #elif defined(__FreeBSD__)
3814 log_hdr = (void *)log_ptr;
3815 #endif
3816 content_len = le16_to_cpu(log_hdr->len);
3817 chunk_len = content_len + sizeof(*log_hdr);
3818
3819 if (chunk_len > len)
3820 break;
3821
3822 switch (log_hdr->type) {
3823 case RTW89_RF_RUN_LOG:
3824 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
3825 log_hdr->content, content_len);
3826 if (handled)
3827 break;
3828
3829 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
3830 rfk_name, content_len, log_hdr->content);
3831 break;
3832 case RTW89_RF_RPT_LOG:
3833 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
3834 log_hdr->content, content_len);
3835 break;
3836 default:
3837 return;
3838 }
3839
3840 log_ptr += chunk_len;
3841 len -= chunk_len;
3842 }
3843 }
3844
3845 static void
rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3846 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3847 {
3848 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3849 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK");
3850 }
3851
3852 static void
rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3853 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3854 {
3855 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3856 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK");
3857 }
3858
3859 static void
rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3860 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3861 {
3862 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3863 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK");
3864 }
3865
3866 static void
rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3867 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3868 {
3869 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3870 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK");
3871 }
3872
3873 static void
rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3874 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3875 {
3876 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3877 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI");
3878 }
3879
3880 static void
rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3881 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3882 {
3883 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3884 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK");
3885 }
3886
3887 static void
rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3888 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3889 {
3890 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3891 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR, "TAS");
3892 }
3893
3894 static void
rtw89_phy_c2h_rfk_log_txiqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3895 rtw89_phy_c2h_rfk_log_txiqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3896 {
3897 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3898 RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK, "TXIQK");
3899 }
3900
3901 static void
rtw89_phy_c2h_rfk_log_cim3k(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3902 rtw89_phy_c2h_rfk_log_cim3k(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3903 {
3904 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3905 RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K, "CIM3K");
3906 }
3907
3908 static
3909 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
3910 struct sk_buff *c2h, u32 len) = {
3911 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk,
3912 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk,
3913 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack,
3914 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck,
3915 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi,
3916 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk,
3917 [RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr,
3918 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK] = rtw89_phy_c2h_rfk_log_txiqk,
3919 [RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K] = rtw89_phy_c2h_rfk_log_cim3k,
3920 };
3921
3922 static
rtw89_phy_rfk_report_prep(struct rtw89_dev * rtwdev)3923 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
3924 {
3925 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3926
3927 wait->state = RTW89_RFK_STATE_START;
3928 wait->start_time = ktime_get();
3929 reinit_completion(&wait->completion);
3930 }
3931
3932 static
rtw89_phy_rfk_report_wait(struct rtw89_dev * rtwdev,const char * rfk_name,unsigned int ms)3933 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
3934 unsigned int ms)
3935 {
3936 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3937 unsigned long time_left;
3938
3939 /* Since we can't receive C2H event during SER, use a fixed delay. */
3940 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3941 fsleep(1000 * ms / 2);
3942 goto out;
3943 }
3944
3945 time_left = wait_for_completion_timeout(&wait->completion,
3946 msecs_to_jiffies(ms));
3947 if (time_left == 0) {
3948 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
3949 return -ETIMEDOUT;
3950 } else if (wait->state != RTW89_RFK_STATE_OK) {
3951 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
3952 rfk_name, wait->state);
3953 return -EFAULT;
3954 }
3955
3956 out:
3957 #if defined(__linux__)
3958 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3959 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3960 #elif defined(__FreeBSD__)
3961 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %jd ms to complete\n",
3962 rfk_name, ktime_ms_delta(ktime_get(), (intmax_t)wait->start_time));
3963 #endif
3964
3965 return 0;
3966 }
3967
3968 static void
rtw89_phy_c2h_rfk_report_state(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3969 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3970 {
3971 const struct rtw89_c2h_rfk_report *report =
3972 (const struct rtw89_c2h_rfk_report *)c2h->data;
3973 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3974
3975 wait->state = report->state;
3976 wait->version = report->version;
3977
3978 complete(&wait->completion);
3979
3980 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3981 "RFK report state %d with version %d (%*ph)\n",
3982 wait->state, wait->version,
3983 (int)(len - sizeof(report->hdr)), &report->state);
3984 }
3985
3986 static void
rtw89_phy_c2h_rfk_report_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3987 rtw89_phy_c2h_rfk_report_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3988 {
3989 const struct rtw89_c2h_rf_tas_info *report =
3990 (const struct rtw89_c2h_rf_tas_info *)c2h->data;
3991
3992 rtw89_phy_c2h_rfk_tas_pwr(rtwdev, &report->content);
3993 }
3994
3995 static
3996 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3997 struct sk_buff *c2h, u32 len) = {
3998 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state,
3999 [RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_report_tas_pwr,
4000 };
4001
rtw89_phy_c2h_chk_atomic(struct rtw89_dev * rtwdev,u8 class,u8 func)4002 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
4003 {
4004 switch (class) {
4005 case RTW89_PHY_C2H_RFK_LOG:
4006 switch (func) {
4007 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
4008 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
4009 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
4010 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
4011 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
4012 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
4013 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK:
4014 return true;
4015 default:
4016 return false;
4017 }
4018 case RTW89_PHY_C2H_RFK_REPORT:
4019 switch (func) {
4020 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE:
4021 return true;
4022 default:
4023 return false;
4024 }
4025 default:
4026 return false;
4027 }
4028 }
4029
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)4030 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4031 u32 len, u8 class, u8 func)
4032 {
4033 void (*handler)(struct rtw89_dev *rtwdev,
4034 struct sk_buff *c2h, u32 len) = NULL;
4035
4036 switch (class) {
4037 case RTW89_PHY_C2H_CLASS_RA:
4038 if (func < ARRAY_SIZE(rtw89_phy_c2h_ra_handler))
4039 handler = rtw89_phy_c2h_ra_handler[func];
4040 break;
4041 case RTW89_PHY_C2H_RFK_LOG:
4042 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler))
4043 handler = rtw89_phy_c2h_rfk_log_handler[func];
4044 break;
4045 case RTW89_PHY_C2H_RFK_REPORT:
4046 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler))
4047 handler = rtw89_phy_c2h_rfk_report_handler[func];
4048 break;
4049 case RTW89_PHY_C2H_CLASS_DM:
4050 if (func < ARRAY_SIZE(rtw89_phy_c2h_dm_handler))
4051 handler = rtw89_phy_c2h_dm_handler[func];
4052 break;
4053 default:
4054 break;
4055 }
4056 if (!handler) {
4057 rtw89_info_once(rtwdev, "PHY c2h class %d func %d not support\n",
4058 class, func);
4059 return;
4060 }
4061 handler(rtwdev, skb, len);
4062 }
4063
rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,unsigned int ms)4064 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
4065 enum rtw89_phy_idx phy_idx,
4066 unsigned int ms)
4067 {
4068 int ret;
4069
4070 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw)) {
4071 rtw89_phy_rfk_report_prep(rtwdev);
4072 rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
4073 ret = rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
4074 if (ret)
4075 return ret;
4076 }
4077
4078 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC, &rtwdev->fw)) {
4079 ret = rtw89_fw_h2c_rf_pre_ntfy_mcc(rtwdev, phy_idx);
4080 if (ret)
4081 return ret;
4082 }
4083
4084 return 0;
4085
4086 }
4087 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
4088
rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)4089 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
4090 enum rtw89_phy_idx phy_idx,
4091 const struct rtw89_chan *chan,
4092 enum rtw89_tssi_mode tssi_mode,
4093 unsigned int ms)
4094 {
4095 int ret;
4096
4097 rtw89_phy_rfk_report_prep(rtwdev);
4098
4099 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
4100 if (ret)
4101 return ret;
4102
4103 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
4104 }
4105 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait);
4106
rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)4107 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
4108 enum rtw89_phy_idx phy_idx,
4109 const struct rtw89_chan *chan,
4110 unsigned int ms)
4111 {
4112 int ret;
4113
4114 rtw89_phy_rfk_report_prep(rtwdev);
4115
4116 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
4117 if (ret)
4118 return ret;
4119
4120 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
4121 }
4122 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait);
4123
rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)4124 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
4125 enum rtw89_phy_idx phy_idx,
4126 const struct rtw89_chan *chan,
4127 unsigned int ms)
4128 {
4129 int ret;
4130
4131 rtw89_phy_rfk_report_prep(rtwdev);
4132
4133 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
4134 if (ret)
4135 return ret;
4136
4137 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
4138 }
4139 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait);
4140
rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)4141 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
4142 enum rtw89_phy_idx phy_idx,
4143 const struct rtw89_chan *chan,
4144 unsigned int ms)
4145 {
4146 int ret;
4147
4148 rtw89_phy_rfk_report_prep(rtwdev);
4149
4150 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
4151 if (ret)
4152 return ret;
4153
4154 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
4155 }
4156 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait);
4157
rtw89_phy_rfk_dack_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)4158 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
4159 enum rtw89_phy_idx phy_idx,
4160 const struct rtw89_chan *chan,
4161 unsigned int ms)
4162 {
4163 int ret;
4164
4165 rtw89_phy_rfk_report_prep(rtwdev);
4166
4167 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
4168 if (ret)
4169 return ret;
4170
4171 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
4172 }
4173 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait);
4174
rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,bool is_chl_k,unsigned int ms)4175 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
4176 enum rtw89_phy_idx phy_idx,
4177 const struct rtw89_chan *chan,
4178 bool is_chl_k, unsigned int ms)
4179 {
4180 int ret;
4181
4182 rtw89_phy_rfk_report_prep(rtwdev);
4183
4184 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k);
4185 if (ret)
4186 return ret;
4187
4188 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
4189 }
4190 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait);
4191
rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)4192 int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev,
4193 enum rtw89_phy_idx phy_idx,
4194 const struct rtw89_chan *chan,
4195 unsigned int ms)
4196 {
4197 int ret;
4198
4199 rtw89_phy_rfk_report_prep(rtwdev);
4200
4201 ret = rtw89_fw_h2c_rf_txiqk(rtwdev, phy_idx, chan);
4202 if (ret)
4203 return ret;
4204
4205 return rtw89_phy_rfk_report_wait(rtwdev, "TX_IQK", ms);
4206 }
4207 EXPORT_SYMBOL(rtw89_phy_rfk_txiqk_and_wait);
4208
rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)4209 int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev,
4210 enum rtw89_phy_idx phy_idx,
4211 const struct rtw89_chan *chan,
4212 unsigned int ms)
4213 {
4214 int ret;
4215
4216 rtw89_phy_rfk_report_prep(rtwdev);
4217
4218 ret = rtw89_fw_h2c_rf_cim3k(rtwdev, phy_idx, chan);
4219 if (ret)
4220 return ret;
4221
4222 return rtw89_phy_rfk_report_wait(rtwdev, "CIM3k", ms);
4223 }
4224 EXPORT_SYMBOL(rtw89_phy_rfk_cim3k_and_wait);
4225
phy_tssi_get_cck_group(u8 ch)4226 static u32 phy_tssi_get_cck_group(u8 ch)
4227 {
4228 switch (ch) {
4229 case 1 ... 2:
4230 return 0;
4231 case 3 ... 5:
4232 return 1;
4233 case 6 ... 8:
4234 return 2;
4235 case 9 ... 11:
4236 return 3;
4237 case 12 ... 13:
4238 return 4;
4239 case 14:
4240 return 5;
4241 }
4242
4243 return 0;
4244 }
4245
4246 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31)
4247 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx))
4248 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT)
4249 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \
4250 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT)
4251 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \
4252 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
4253
phy_tssi_get_ofdm_group(u8 ch)4254 static u32 phy_tssi_get_ofdm_group(u8 ch)
4255 {
4256 switch (ch) {
4257 case 1 ... 2:
4258 return 0;
4259 case 3 ... 5:
4260 return 1;
4261 case 6 ... 8:
4262 return 2;
4263 case 9 ... 11:
4264 return 3;
4265 case 12 ... 14:
4266 return 4;
4267 case 36 ... 40:
4268 return 5;
4269 case 41 ... 43:
4270 return PHY_TSSI_EXTRA_GROUP(5);
4271 case 44 ... 48:
4272 return 6;
4273 case 49 ... 51:
4274 return PHY_TSSI_EXTRA_GROUP(6);
4275 case 52 ... 56:
4276 return 7;
4277 case 57 ... 59:
4278 return PHY_TSSI_EXTRA_GROUP(7);
4279 case 60 ... 64:
4280 return 8;
4281 case 100 ... 104:
4282 return 9;
4283 case 105 ... 107:
4284 return PHY_TSSI_EXTRA_GROUP(9);
4285 case 108 ... 112:
4286 return 10;
4287 case 113 ... 115:
4288 return PHY_TSSI_EXTRA_GROUP(10);
4289 case 116 ... 120:
4290 return 11;
4291 case 121 ... 123:
4292 return PHY_TSSI_EXTRA_GROUP(11);
4293 case 124 ... 128:
4294 return 12;
4295 case 129 ... 131:
4296 return PHY_TSSI_EXTRA_GROUP(12);
4297 case 132 ... 136:
4298 return 13;
4299 case 137 ... 139:
4300 return PHY_TSSI_EXTRA_GROUP(13);
4301 case 140 ... 144:
4302 return 14;
4303 case 149 ... 153:
4304 return 15;
4305 case 154 ... 156:
4306 return PHY_TSSI_EXTRA_GROUP(15);
4307 case 157 ... 161:
4308 return 16;
4309 case 162 ... 164:
4310 return PHY_TSSI_EXTRA_GROUP(16);
4311 case 165 ... 169:
4312 return 17;
4313 case 170 ... 172:
4314 return PHY_TSSI_EXTRA_GROUP(17);
4315 case 173 ... 177:
4316 return 18;
4317 }
4318
4319 return 0;
4320 }
4321
phy_tssi_get_6g_ofdm_group(u8 ch)4322 static u32 phy_tssi_get_6g_ofdm_group(u8 ch)
4323 {
4324 switch (ch) {
4325 case 1 ... 5:
4326 return 0;
4327 case 6 ... 8:
4328 return PHY_TSSI_EXTRA_GROUP(0);
4329 case 9 ... 13:
4330 return 1;
4331 case 14 ... 16:
4332 return PHY_TSSI_EXTRA_GROUP(1);
4333 case 17 ... 21:
4334 return 2;
4335 case 22 ... 24:
4336 return PHY_TSSI_EXTRA_GROUP(2);
4337 case 25 ... 29:
4338 return 3;
4339 case 33 ... 37:
4340 return 4;
4341 case 38 ... 40:
4342 return PHY_TSSI_EXTRA_GROUP(4);
4343 case 41 ... 45:
4344 return 5;
4345 case 46 ... 48:
4346 return PHY_TSSI_EXTRA_GROUP(5);
4347 case 49 ... 53:
4348 return 6;
4349 case 54 ... 56:
4350 return PHY_TSSI_EXTRA_GROUP(6);
4351 case 57 ... 61:
4352 return 7;
4353 case 65 ... 69:
4354 return 8;
4355 case 70 ... 72:
4356 return PHY_TSSI_EXTRA_GROUP(8);
4357 case 73 ... 77:
4358 return 9;
4359 case 78 ... 80:
4360 return PHY_TSSI_EXTRA_GROUP(9);
4361 case 81 ... 85:
4362 return 10;
4363 case 86 ... 88:
4364 return PHY_TSSI_EXTRA_GROUP(10);
4365 case 89 ... 93:
4366 return 11;
4367 case 97 ... 101:
4368 return 12;
4369 case 102 ... 104:
4370 return PHY_TSSI_EXTRA_GROUP(12);
4371 case 105 ... 109:
4372 return 13;
4373 case 110 ... 112:
4374 return PHY_TSSI_EXTRA_GROUP(13);
4375 case 113 ... 117:
4376 return 14;
4377 case 118 ... 120:
4378 return PHY_TSSI_EXTRA_GROUP(14);
4379 case 121 ... 125:
4380 return 15;
4381 case 129 ... 133:
4382 return 16;
4383 case 134 ... 136:
4384 return PHY_TSSI_EXTRA_GROUP(16);
4385 case 137 ... 141:
4386 return 17;
4387 case 142 ... 144:
4388 return PHY_TSSI_EXTRA_GROUP(17);
4389 case 145 ... 149:
4390 return 18;
4391 case 150 ... 152:
4392 return PHY_TSSI_EXTRA_GROUP(18);
4393 case 153 ... 157:
4394 return 19;
4395 case 161 ... 165:
4396 return 20;
4397 case 166 ... 168:
4398 return PHY_TSSI_EXTRA_GROUP(20);
4399 case 169 ... 173:
4400 return 21;
4401 case 174 ... 176:
4402 return PHY_TSSI_EXTRA_GROUP(21);
4403 case 177 ... 181:
4404 return 22;
4405 case 182 ... 184:
4406 return PHY_TSSI_EXTRA_GROUP(22);
4407 case 185 ... 189:
4408 return 23;
4409 case 193 ... 197:
4410 return 24;
4411 case 198 ... 200:
4412 return PHY_TSSI_EXTRA_GROUP(24);
4413 case 201 ... 205:
4414 return 25;
4415 case 206 ... 208:
4416 return PHY_TSSI_EXTRA_GROUP(25);
4417 case 209 ... 213:
4418 return 26;
4419 case 214 ... 216:
4420 return PHY_TSSI_EXTRA_GROUP(26);
4421 case 217 ... 221:
4422 return 27;
4423 case 225 ... 229:
4424 return 28;
4425 case 230 ... 232:
4426 return PHY_TSSI_EXTRA_GROUP(28);
4427 case 233 ... 237:
4428 return 29;
4429 case 238 ... 240:
4430 return PHY_TSSI_EXTRA_GROUP(29);
4431 case 241 ... 245:
4432 return 30;
4433 case 246 ... 248:
4434 return PHY_TSSI_EXTRA_GROUP(30);
4435 case 249 ... 253:
4436 return 31;
4437 }
4438
4439 return 0;
4440 }
4441
phy_tssi_get_trim_group(u8 ch)4442 static u32 phy_tssi_get_trim_group(u8 ch)
4443 {
4444 switch (ch) {
4445 case 1 ... 8:
4446 return 0;
4447 case 9 ... 14:
4448 return 1;
4449 case 36 ... 48:
4450 return 2;
4451 case 49 ... 51:
4452 return PHY_TSSI_EXTRA_GROUP(2);
4453 case 52 ... 64:
4454 return 3;
4455 case 100 ... 112:
4456 return 4;
4457 case 113 ... 115:
4458 return PHY_TSSI_EXTRA_GROUP(4);
4459 case 116 ... 128:
4460 return 5;
4461 case 132 ... 144:
4462 return 6;
4463 case 149 ... 177:
4464 return 7;
4465 }
4466
4467 return 0;
4468 }
4469
phy_tssi_get_6g_trim_group(u8 ch)4470 static u32 phy_tssi_get_6g_trim_group(u8 ch)
4471 {
4472 switch (ch) {
4473 case 1 ... 13:
4474 return 0;
4475 case 14 ... 16:
4476 return PHY_TSSI_EXTRA_GROUP(0);
4477 case 17 ... 29:
4478 return 1;
4479 case 33 ... 45:
4480 return 2;
4481 case 46 ... 48:
4482 return PHY_TSSI_EXTRA_GROUP(2);
4483 case 49 ... 61:
4484 return 3;
4485 case 65 ... 77:
4486 return 4;
4487 case 78 ... 80:
4488 return PHY_TSSI_EXTRA_GROUP(4);
4489 case 81 ... 93:
4490 return 5;
4491 case 97 ... 109:
4492 return 6;
4493 case 110 ... 112:
4494 return PHY_TSSI_EXTRA_GROUP(6);
4495 case 113 ... 125:
4496 return 7;
4497 case 129 ... 141:
4498 return 8;
4499 case 142 ... 144:
4500 return PHY_TSSI_EXTRA_GROUP(8);
4501 case 145 ... 157:
4502 return 9;
4503 case 161 ... 173:
4504 return 10;
4505 case 174 ... 176:
4506 return PHY_TSSI_EXTRA_GROUP(10);
4507 case 177 ... 189:
4508 return 11;
4509 case 193 ... 205:
4510 return 12;
4511 case 206 ... 208:
4512 return PHY_TSSI_EXTRA_GROUP(12);
4513 case 209 ... 221:
4514 return 13;
4515 case 225 ... 237:
4516 return 14;
4517 case 238 ... 240:
4518 return PHY_TSSI_EXTRA_GROUP(14);
4519 case 241 ... 253:
4520 return 15;
4521 }
4522
4523 return 0;
4524 }
4525
phy_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4526 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
4527 enum rtw89_phy_idx phy,
4528 const struct rtw89_chan *chan,
4529 enum rtw89_rf_path path)
4530 {
4531 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4532 enum rtw89_band band = chan->band_type;
4533 u8 ch = chan->channel;
4534 u32 gidx_1st;
4535 u32 gidx_2nd;
4536 s8 de_1st;
4537 s8 de_2nd;
4538 u32 gidx;
4539 s8 val;
4540
4541 if (band == RTW89_BAND_6G)
4542 goto calc_6g;
4543
4544 gidx = phy_tssi_get_ofdm_group(ch);
4545
4546 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4547 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4548 path, gidx);
4549
4550 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4551 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4552 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4553 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
4554 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
4555 val = (de_1st + de_2nd) / 2;
4556
4557 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4558 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4559 path, val, de_1st, de_2nd);
4560 } else {
4561 val = tssi_info->tssi_mcs[path][gidx];
4562
4563 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4564 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4565 }
4566
4567 return val;
4568
4569 calc_6g:
4570 gidx = phy_tssi_get_6g_ofdm_group(ch);
4571
4572 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4573 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4574 path, gidx);
4575
4576 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4577 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4578 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4579 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
4580 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
4581 val = (de_1st + de_2nd) / 2;
4582
4583 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4584 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4585 path, val, de_1st, de_2nd);
4586 } else {
4587 val = tssi_info->tssi_6g_mcs[path][gidx];
4588
4589 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4590 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4591 }
4592
4593 return val;
4594 }
4595
phy_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4596 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
4597 enum rtw89_phy_idx phy,
4598 const struct rtw89_chan *chan,
4599 enum rtw89_rf_path path)
4600 {
4601 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4602 enum rtw89_band band = chan->band_type;
4603 u8 ch = chan->channel;
4604 u32 tgidx_1st;
4605 u32 tgidx_2nd;
4606 s8 tde_1st;
4607 s8 tde_2nd;
4608 u32 tgidx;
4609 s8 val;
4610
4611 if (band == RTW89_BAND_6G)
4612 goto calc_6g;
4613
4614 tgidx = phy_tssi_get_trim_group(ch);
4615
4616 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4617 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4618 path, tgidx);
4619
4620 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4621 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4622 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4623 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
4624 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
4625 val = (tde_1st + tde_2nd) / 2;
4626
4627 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4628 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4629 path, val, tde_1st, tde_2nd);
4630 } else {
4631 val = tssi_info->tssi_trim[path][tgidx];
4632
4633 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4634 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4635 path, val);
4636 }
4637
4638 return val;
4639
4640 calc_6g:
4641 tgidx = phy_tssi_get_6g_trim_group(ch);
4642
4643 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4644 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4645 path, tgidx);
4646
4647 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4648 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4649 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4650 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
4651 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
4652 val = (tde_1st + tde_2nd) / 2;
4653
4654 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4655 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4656 path, val, tde_1st, tde_2nd);
4657 } else {
4658 val = tssi_info->tssi_trim_6g[path][tgidx];
4659
4660 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4661 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4662 path, val);
4663 }
4664
4665 return val;
4666 }
4667
rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4668 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
4669 enum rtw89_phy_idx phy,
4670 const struct rtw89_chan *chan,
4671 struct rtw89_h2c_rf_tssi *h2c)
4672 {
4673 const struct rtw89_chip_info *chip = rtwdev->chip;
4674 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4675 u8 ch = chan->channel;
4676 s8 trim_de;
4677 s8 ofdm_de;
4678 s8 cck_de;
4679 u8 gidx;
4680 s8 val;
4681 int i;
4682
4683 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
4684 phy, ch);
4685
4686 for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
4687 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
4688 h2c->curr_tssi_trim_de[i] = trim_de;
4689
4690 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4691 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de);
4692
4693 gidx = phy_tssi_get_cck_group(ch);
4694 cck_de = tssi_info->tssi_cck[i][gidx];
4695 val = u32_get_bits(cck_de + trim_de, 0xff);
4696
4697 if (chip->chip_id == RTL8922A) {
4698 h2c->curr_tssi_cck_de[i] = 0x0;
4699 h2c->curr_tssi_cck_de_20m[i] = val;
4700 h2c->curr_tssi_cck_de_40m[i] = val;
4701 } else {
4702 h2c->curr_tssi_cck_de[i] = val;
4703 }
4704
4705 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
4706
4707 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4708 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de);
4709
4710 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
4711 val = u32_get_bits(ofdm_de + trim_de, 0xff);
4712
4713 if (chip->chip_id == RTL8922A) {
4714 h2c->curr_tssi_ofdm_de[i] = 0x0;
4715 h2c->curr_tssi_ofdm_de_20m[i] = val;
4716 h2c->curr_tssi_ofdm_de_40m[i] = val;
4717 h2c->curr_tssi_ofdm_de_80m[i] = val;
4718 h2c->curr_tssi_ofdm_de_160m[i] = val;
4719 h2c->curr_tssi_ofdm_de_320m[i] = val;
4720 } else {
4721 h2c->curr_tssi_ofdm_de[i] = val;
4722 }
4723
4724 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
4725
4726 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4727 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de);
4728 }
4729 }
4730
rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4731 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
4732 enum rtw89_phy_idx phy,
4733 const struct rtw89_chan *chan,
4734 struct rtw89_h2c_rf_tssi *h2c)
4735 {
4736 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
4737 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4738 const struct rtw89_chip_info *chip = rtwdev->chip;
4739 const s8 *thm_up[RF_PATH_B + 1] = {};
4740 const s8 *thm_down[RF_PATH_B + 1] = {};
4741 u8 subband = chan->subband_type;
4742 s8 thm_ofst[128] = {};
4743 int multiplier;
4744 u8 thermal;
4745 u8 path;
4746 u8 i, j;
4747
4748 switch (subband) {
4749 default:
4750 case RTW89_CH_2G:
4751 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
4752 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
4753 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
4754 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
4755 break;
4756 case RTW89_CH_5G_BAND_1:
4757 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
4758 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
4759 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
4760 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
4761 break;
4762 case RTW89_CH_5G_BAND_3:
4763 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
4764 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
4765 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
4766 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
4767 break;
4768 case RTW89_CH_5G_BAND_4:
4769 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
4770 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
4771 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
4772 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
4773 break;
4774 case RTW89_CH_6G_BAND_IDX0:
4775 case RTW89_CH_6G_BAND_IDX1:
4776 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
4777 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
4778 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
4779 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
4780 break;
4781 case RTW89_CH_6G_BAND_IDX2:
4782 case RTW89_CH_6G_BAND_IDX3:
4783 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
4784 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
4785 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
4786 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
4787 break;
4788 case RTW89_CH_6G_BAND_IDX4:
4789 case RTW89_CH_6G_BAND_IDX5:
4790 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
4791 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
4792 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
4793 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
4794 break;
4795 case RTW89_CH_6G_BAND_IDX6:
4796 case RTW89_CH_6G_BAND_IDX7:
4797 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
4798 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
4799 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
4800 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
4801 break;
4802 }
4803
4804 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4805 "[TSSI] tmeter tbl on subband: %u\n", subband);
4806
4807 if (chip->chip_id == RTL8922A)
4808 multiplier = 1;
4809 else
4810 multiplier = -1;
4811
4812 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
4813 thermal = tssi_info->thermal[path];
4814 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4815 "path: %u, pg thermal: 0x%x\n", path, thermal);
4816
4817 if (thermal == 0xff) {
4818 h2c->pg_thermal[path] = 0x38;
4819 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
4820 continue;
4821 }
4822
4823 h2c->pg_thermal[path] = thermal;
4824
4825 i = 0;
4826 for (j = 0; j < 64; j++) {
4827 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4828 thm_up[path][i++] :
4829 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
4830 thm_ofst[j] *= multiplier;
4831 }
4832
4833 i = 1;
4834 for (j = 127; j >= 64; j--) {
4835 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4836 -thm_down[path][i++] :
4837 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
4838 thm_ofst[j] *= multiplier;
4839 }
4840
4841 for (i = 0; i < 128; i += 4) {
4842 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
4843 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
4844 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
4845 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
4846
4847 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4848 "thm ofst [%x]: %02x %02x %02x %02x\n",
4849 i, thm_ofst[i], thm_ofst[i + 1],
4850 thm_ofst[i + 2], thm_ofst[i + 3]);
4851 }
4852 }
4853 }
4854
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)4855 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
4856 {
4857 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4858 u32 reg_mask;
4859
4860 if (sc_xo)
4861 reg_mask = xtal->sc_xo_mask;
4862 else
4863 reg_mask = xtal->sc_xi_mask;
4864
4865 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
4866 }
4867
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)4868 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
4869 u8 val)
4870 {
4871 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4872 u32 reg_mask;
4873
4874 if (sc_xo)
4875 reg_mask = xtal->sc_xo_mask;
4876 else
4877 reg_mask = xtal->sc_xi_mask;
4878
4879 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
4880 }
4881
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)4882 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
4883 u8 crystal_cap, bool force)
4884 {
4885 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4886 const struct rtw89_chip_info *chip = rtwdev->chip;
4887 u8 sc_xi_val, sc_xo_val;
4888
4889 if (!force && cfo->crystal_cap == crystal_cap)
4890 return;
4891 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
4892 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
4893 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
4894 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
4895 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
4896 } else {
4897 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
4898 crystal_cap, XTAL_SC_XO_MASK);
4899 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
4900 crystal_cap, XTAL_SC_XI_MASK);
4901 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
4902 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
4903 }
4904 cfo->crystal_cap = sc_xi_val;
4905 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
4906
4907 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
4908 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
4909 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
4910 cfo->x_cap_ofst);
4911 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
4912 }
4913
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)4914 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
4915 {
4916 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4917 u8 cap;
4918
4919 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
4920 cfo->is_adjust = false;
4921 if (cfo->crystal_cap == cfo->def_x_cap)
4922 return;
4923 cap = cfo->crystal_cap;
4924 cap += (cap > cfo->def_x_cap ? -1 : 1);
4925 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
4926 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4927 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
4928 cfo->def_x_cap);
4929 }
4930
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)4931 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
4932 {
4933 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
4934 bool is_linked = rtwdev->total_sta_assoc > 0;
4935 s32 cfo_avg_312;
4936 s32 dcfo_comp_val;
4937 int sign;
4938
4939 if (!dcfo_comp)
4940 return;
4941
4942 if (!is_linked) {
4943 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
4944 is_linked);
4945 return;
4946 }
4947 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
4948 if (curr_cfo == 0)
4949 return;
4950 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
4951 sign = curr_cfo > 0 ? 1 : -1;
4952 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val;
4953 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
4954 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
4955 cfo_avg_312 = -cfo_avg_312;
4956 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
4957 cfo_avg_312);
4958 }
4959
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)4960 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
4961 {
4962 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4963 const struct rtw89_chip_info *chip = rtwdev->chip;
4964 const struct rtw89_cfo_regs *cfo = phy->cfo;
4965
4966 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
4967 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
4968
4969 if (chip->chip_gen == RTW89_CHIP_AX) {
4970 if (chip->cfo_hw_comp) {
4971 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
4972 B_AX_PWR_UL_CFO_MASK, 0x6);
4973 } else {
4974 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
4975 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
4976 B_AX_PWR_UL_CFO_MASK);
4977 }
4978 }
4979 }
4980
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)4981 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
4982 {
4983 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4984 struct rtw89_efuse *efuse = &rtwdev->efuse;
4985
4986 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
4987 cfo->crystal_cap = cfo->crystal_cap_default;
4988 cfo->def_x_cap = cfo->crystal_cap;
4989 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4990 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4991 cfo->is_adjust = false;
4992 cfo->divergence_lock_en = false;
4993 cfo->x_cap_ofst = 0;
4994 cfo->lock_cnt = 0;
4995 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4996 cfo->apply_compensation = false;
4997 cfo->residual_cfo_acc = 0;
4998 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
4999 cfo->crystal_cap_default);
5000 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
5001 rtw89_dcfo_comp_init(rtwdev);
5002 cfo->cfo_timer_ms = 2000;
5003 cfo->cfo_trig_by_timer_en = false;
5004 cfo->phy_cfo_trk_cnt = 0;
5005 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5006 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
5007 }
5008
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)5009 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
5010 s32 curr_cfo)
5011 {
5012 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5013 int crystal_cap = cfo->crystal_cap;
5014 s32 cfo_abs = abs(curr_cfo);
5015 int sign;
5016
5017 if (curr_cfo == 0) {
5018 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
5019 return;
5020 }
5021 if (!cfo->is_adjust) {
5022 if (cfo_abs > CFO_TRK_ENABLE_TH)
5023 cfo->is_adjust = true;
5024 } else {
5025 if (cfo_abs <= CFO_TRK_STOP_TH)
5026 cfo->is_adjust = false;
5027 }
5028 if (!cfo->is_adjust) {
5029 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
5030 return;
5031 }
5032 sign = curr_cfo > 0 ? 1 : -1;
5033 if (cfo_abs > CFO_TRK_STOP_TH_4)
5034 crystal_cap += 3 * sign;
5035 else if (cfo_abs > CFO_TRK_STOP_TH_3)
5036 crystal_cap += 3 * sign;
5037 else if (cfo_abs > CFO_TRK_STOP_TH_2)
5038 crystal_cap += 1 * sign;
5039 else if (cfo_abs > CFO_TRK_STOP_TH_1)
5040 crystal_cap += 1 * sign;
5041 else
5042 return;
5043
5044 crystal_cap = clamp(crystal_cap, 0, 127);
5045 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
5046 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5047 "X_cap{Curr,Default}={0x%x,0x%x}\n",
5048 cfo->crystal_cap, cfo->def_x_cap);
5049 }
5050
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)5051 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
5052 {
5053 const struct rtw89_chip_info *chip = rtwdev->chip;
5054 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5055 s32 cfo_khz_all = 0;
5056 s32 cfo_cnt_all = 0;
5057 s32 cfo_all_avg = 0;
5058 u8 i;
5059
5060 if (rtwdev->total_sta_assoc != 1)
5061 return 0;
5062 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
5063 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
5064 if (cfo->cfo_cnt[i] == 0)
5065 continue;
5066 cfo_khz_all += cfo->cfo_tail[i];
5067 cfo_cnt_all += cfo->cfo_cnt[i];
5068 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
5069 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
5070 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
5071 cfo_cnt_all);
5072 }
5073 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5074 "CFO track for macid = %d\n", i);
5075 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5076 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
5077 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
5078 return cfo_all_avg;
5079 }
5080
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)5081 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
5082 {
5083 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5084 struct rtw89_traffic_stats *stats = &rtwdev->stats;
5085 s32 target_cfo = 0;
5086 s32 cfo_khz_all = 0;
5087 s32 cfo_khz_all_tp_wgt = 0;
5088 s32 cfo_avg = 0;
5089 s32 max_cfo_lb = BIT(31);
5090 s32 min_cfo_ub = GENMASK(30, 0);
5091 u16 cfo_cnt_all = 0;
5092 u8 active_entry_cnt = 0;
5093 u8 sta_cnt = 0;
5094 u32 tp_all = 0;
5095 u8 i;
5096 u8 cfo_tol = 0;
5097
5098 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
5099 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
5100 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
5101 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
5102 if (cfo->cfo_cnt[i] == 0)
5103 continue;
5104 cfo_khz_all += cfo->cfo_tail[i];
5105 cfo_cnt_all += cfo->cfo_cnt[i];
5106 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
5107 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5108 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
5109 cfo_khz_all, cfo_cnt_all, cfo_avg);
5110 target_cfo = cfo_avg;
5111 }
5112 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
5113 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
5114 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
5115 if (cfo->cfo_cnt[i] == 0)
5116 continue;
5117 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
5118 (s32)cfo->cfo_cnt[i]);
5119 cfo_khz_all += cfo->cfo_avg[i];
5120 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5121 "Macid=%d, cfo_avg=%d\n", i,
5122 cfo->cfo_avg[i]);
5123 }
5124 sta_cnt = rtwdev->total_sta_assoc;
5125 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
5126 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5127 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
5128 cfo_khz_all, sta_cnt, cfo_avg);
5129 target_cfo = cfo_avg;
5130 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
5131 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
5132 cfo_tol = cfo->sta_cfo_tolerance;
5133 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
5134 sta_cnt++;
5135 if (cfo->cfo_cnt[i] != 0) {
5136 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
5137 (s32)cfo->cfo_cnt[i]);
5138 active_entry_cnt++;
5139 } else {
5140 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
5141 }
5142 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
5143 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
5144 cfo_khz_all += cfo->cfo_avg[i];
5145 /* need tp for each entry */
5146 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5147 "[%d] cfo_avg=%d, tp=tbd\n",
5148 i, cfo->cfo_avg[i]);
5149 if (sta_cnt >= rtwdev->total_sta_assoc)
5150 break;
5151 }
5152 tp_all = stats->rx_throughput; /* need tp for each entry */
5153 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
5154
5155 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
5156 sta_cnt);
5157 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
5158 active_entry_cnt);
5159 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5160 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
5161 cfo_khz_all_tp_wgt, cfo_avg);
5162 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
5163 max_cfo_lb, min_cfo_ub);
5164 if (max_cfo_lb <= min_cfo_ub) {
5165 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5166 "cfo win_size=%d\n",
5167 min_cfo_ub - max_cfo_lb);
5168 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
5169 } else {
5170 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5171 "No intersection of cfo tolerance windows\n");
5172 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
5173 }
5174 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
5175 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
5176 }
5177 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
5178 return target_cfo;
5179 }
5180
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)5181 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
5182 {
5183 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5184
5185 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
5186 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
5187 cfo->packet_count = 0;
5188 cfo->packet_count_pre = 0;
5189 cfo->cfo_avg_pre = 0;
5190 }
5191
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)5192 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
5193 {
5194 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5195 s32 new_cfo = 0;
5196 bool x_cap_update = false;
5197 u8 pre_x_cap = cfo->crystal_cap;
5198 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
5199
5200 cfo->dcfo_avg = 0;
5201 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
5202 rtwdev->total_sta_assoc);
5203 if (rtwdev->total_sta_assoc == 0 || rtw89_is_mlo_1_1(rtwdev)) {
5204 rtw89_phy_cfo_reset(rtwdev);
5205 return;
5206 }
5207 if (cfo->packet_count == 0) {
5208 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
5209 return;
5210 }
5211 if (cfo->packet_count == cfo->packet_count_pre) {
5212 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
5213 return;
5214 }
5215 if (rtwdev->total_sta_assoc == 1)
5216 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
5217 else
5218 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
5219 if (cfo->divergence_lock_en) {
5220 cfo->lock_cnt++;
5221 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
5222 cfo->divergence_lock_en = false;
5223 cfo->lock_cnt = 0;
5224 } else {
5225 rtw89_phy_cfo_reset(rtwdev);
5226 }
5227 return;
5228 }
5229 if (cfo->crystal_cap >= cfo->x_cap_ub ||
5230 cfo->crystal_cap <= cfo->x_cap_lb) {
5231 cfo->divergence_lock_en = true;
5232 rtw89_phy_cfo_reset(rtwdev);
5233 return;
5234 }
5235
5236 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
5237 cfo->cfo_avg_pre = new_cfo;
5238 cfo->dcfo_avg_pre = cfo->dcfo_avg;
5239 x_cap_update = cfo->crystal_cap != pre_x_cap;
5240 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
5241 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
5242 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
5243 cfo->x_cap_ofst);
5244 if (x_cap_update) {
5245 if (cfo->dcfo_avg > 0)
5246 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
5247 else
5248 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
5249 }
5250 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
5251 rtw89_phy_cfo_statistics_reset(rtwdev);
5252 }
5253
rtw89_phy_cfo_track_work(struct wiphy * wiphy,struct wiphy_work * work)5254 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work)
5255 {
5256 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
5257 cfo_track_work.work);
5258 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5259
5260 lockdep_assert_wiphy(wiphy);
5261
5262 if (!cfo->cfo_trig_by_timer_en)
5263 return;
5264 rtw89_leave_ps_mode(rtwdev);
5265 rtw89_phy_cfo_dm(rtwdev);
5266 wiphy_delayed_work_queue(wiphy, &rtwdev->cfo_track_work,
5267 msecs_to_jiffies(cfo->cfo_timer_ms));
5268 }
5269
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)5270 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
5271 {
5272 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5273
5274 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->cfo_track_work,
5275 msecs_to_jiffies(cfo->cfo_timer_ms));
5276 }
5277
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)5278 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
5279 {
5280 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5281 struct rtw89_traffic_stats *stats = &rtwdev->stats;
5282 bool is_ul_ofdma = false, ofdma_acc_en = false;
5283
5284 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
5285 is_ul_ofdma = true;
5286 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
5287 is_ul_ofdma)
5288 ofdma_acc_en = true;
5289
5290 switch (cfo->phy_cfo_status) {
5291 case RTW89_PHY_DCFO_STATE_NORMAL:
5292 if (stats->tx_throughput >= CFO_TP_UPPER) {
5293 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
5294 cfo->cfo_trig_by_timer_en = true;
5295 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
5296 rtw89_phy_cfo_start_work(rtwdev);
5297 }
5298 break;
5299 case RTW89_PHY_DCFO_STATE_ENHANCE:
5300 if (stats->tx_throughput <= CFO_TP_LOWER)
5301 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5302 else if (ofdma_acc_en &&
5303 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
5304 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
5305 else
5306 cfo->phy_cfo_trk_cnt++;
5307
5308 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
5309 cfo->phy_cfo_trk_cnt = 0;
5310 cfo->cfo_trig_by_timer_en = false;
5311 }
5312 break;
5313 case RTW89_PHY_DCFO_STATE_HOLD:
5314 if (stats->tx_throughput <= CFO_TP_LOWER) {
5315 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5316 cfo->phy_cfo_trk_cnt = 0;
5317 cfo->cfo_trig_by_timer_en = false;
5318 } else {
5319 cfo->phy_cfo_trk_cnt++;
5320 }
5321 break;
5322 default:
5323 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
5324 cfo->phy_cfo_trk_cnt = 0;
5325 break;
5326 }
5327 rtw89_debug(rtwdev, RTW89_DBG_CFO,
5328 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
5329 stats->tx_throughput, cfo->phy_cfo_status,
5330 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
5331 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
5332 if (cfo->cfo_trig_by_timer_en)
5333 return;
5334 rtw89_phy_cfo_dm(rtwdev);
5335 }
5336
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)5337 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
5338 struct rtw89_rx_phy_ppdu *phy_ppdu)
5339 {
5340 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
5341 u8 macid = phy_ppdu->mac_id;
5342
5343 if (macid >= CFO_TRACK_MAX_USER) {
5344 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
5345 return;
5346 }
5347
5348 cfo->cfo_tail[macid] += cfo_val;
5349 cfo->cfo_cnt[macid]++;
5350 cfo->packet_count++;
5351 }
5352
rtw89_phy_ul_tb_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5353 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
5354 {
5355 const struct rtw89_chip_info *chip = rtwdev->chip;
5356 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
5357 rtwvif_link->chanctx_idx);
5358 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5359
5360 if (!chip->ul_tb_waveform_ctrl)
5361 return;
5362
5363 rtwvif_link->def_tri_idx =
5364 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
5365
5366 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
5367 rtwvif_link->dyn_tb_bedge_en = false;
5368 else if (chan->band_type >= RTW89_BAND_5G &&
5369 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
5370 rtwvif_link->dyn_tb_bedge_en = true;
5371 else
5372 rtwvif_link->dyn_tb_bedge_en = false;
5373
5374 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5375 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
5376 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
5377 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5378 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
5379 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
5380 }
5381
5382 struct rtw89_phy_ul_tb_check_data {
5383 bool valid;
5384 bool high_tf_client;
5385 bool low_tf_client;
5386 bool dyn_tb_bedge_en;
5387 u8 def_tri_idx;
5388 };
5389
5390 struct rtw89_phy_power_diff {
5391 u32 q_00;
5392 u32 q_11;
5393 u32 q_matrix_en;
5394 u32 ultb_1t_norm_160;
5395 u32 ultb_2t_norm_160;
5396 u32 com1_norm_1sts;
5397 u32 com2_resp_1sts_path;
5398 };
5399
rtw89_phy_ofdma_power_diff(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5400 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
5401 struct rtw89_vif_link *rtwvif_link)
5402 {
5403 static const struct rtw89_phy_power_diff table[2] = {
5404 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3},
5405 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1},
5406 };
5407 const struct rtw89_phy_power_diff *param;
5408 u32 reg;
5409
5410 if (!rtwdev->chip->ul_tb_pwr_diff)
5411 return;
5412
5413 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
5414 rtwvif_link->pwr_diff_en = false;
5415 return;
5416 }
5417
5418 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
5419 param = &table[rtwvif_link->pwr_diff_en];
5420
5421 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
5422 param->q_00);
5423 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
5424 param->q_11);
5425 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
5426 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
5427
5428 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
5429 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
5430 param->ultb_1t_norm_160);
5431
5432 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
5433 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
5434 param->ultb_2t_norm_160);
5435
5436 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
5437 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
5438 param->com1_norm_1sts);
5439
5440 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
5441 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
5442 param->com2_resp_1sts_path);
5443 }
5444
5445 static
rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_phy_ul_tb_check_data * ul_tb_data)5446 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
5447 struct rtw89_vif_link *rtwvif_link,
5448 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
5449 {
5450 struct rtw89_traffic_stats *stats = &rtwdev->stats;
5451 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5452
5453 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
5454 return;
5455
5456 if (!vif->cfg.assoc)
5457 return;
5458
5459 if (rtwdev->chip->ul_tb_waveform_ctrl) {
5460 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
5461 ul_tb_data->high_tf_client = true;
5462 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
5463 ul_tb_data->low_tf_client = true;
5464
5465 ul_tb_data->valid = true;
5466 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
5467 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
5468 }
5469
5470 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link);
5471 }
5472
rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev * rtwdev,struct rtw89_phy_ul_tb_check_data * ul_tb_data)5473 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
5474 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
5475 {
5476 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5477
5478 if (!rtwdev->chip->ul_tb_waveform_ctrl)
5479 return;
5480
5481 if (ul_tb_data->dyn_tb_bedge_en) {
5482 if (ul_tb_data->high_tf_client) {
5483 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
5484 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5485 "[ULTB] Turn off if_bandedge\n");
5486 } else if (ul_tb_data->low_tf_client) {
5487 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
5488 ul_tb_info->def_if_bandedge);
5489 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5490 "[ULTB] Set to default if_bandedge = %d\n",
5491 ul_tb_info->def_if_bandedge);
5492 }
5493 }
5494
5495 if (ul_tb_info->dyn_tb_tri_en) {
5496 if (ul_tb_data->high_tf_client) {
5497 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
5498 B_TXSHAPE_TRIANGULAR_CFG, 0);
5499 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5500 "[ULTB] Turn off Tx triangle\n");
5501 } else if (ul_tb_data->low_tf_client) {
5502 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
5503 B_TXSHAPE_TRIANGULAR_CFG,
5504 ul_tb_data->def_tri_idx);
5505 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
5506 "[ULTB] Set to default tx_shap_idx = %d\n",
5507 ul_tb_data->def_tri_idx);
5508 }
5509 }
5510 }
5511
rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev * rtwdev)5512 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
5513 {
5514 const struct rtw89_chip_info *chip = rtwdev->chip;
5515 struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
5516 struct rtw89_vif_link *rtwvif_link;
5517 struct rtw89_vif *rtwvif;
5518 unsigned int link_id;
5519
5520 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
5521 return;
5522
5523 if (rtwdev->total_sta_assoc != 1)
5524 return;
5525
5526 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5527 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
5528 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data);
5529
5530 if (!ul_tb_data.valid)
5531 return;
5532
5533 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
5534 }
5535
rtw89_phy_ul_tb_info_init(struct rtw89_dev * rtwdev)5536 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
5537 {
5538 const struct rtw89_chip_info *chip = rtwdev->chip;
5539 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
5540
5541 if (!chip->ul_tb_waveform_ctrl)
5542 return;
5543
5544 ul_tb_info->dyn_tb_tri_en = true;
5545 ul_tb_info->def_if_bandedge =
5546 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
5547 }
5548
5549 static
rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats * antdiv_sts)5550 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
5551 {
5552 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
5553 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
5554 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
5555 antdiv_sts->pkt_cnt_cck = 0;
5556 antdiv_sts->pkt_cnt_ofdm = 0;
5557 antdiv_sts->pkt_cnt_non_legacy = 0;
5558 antdiv_sts->evm = 0;
5559 }
5560
rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_antdiv_stats * stats)5561 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
5562 struct rtw89_rx_phy_ppdu *phy_ppdu,
5563 struct rtw89_antdiv_stats *stats)
5564 {
5565 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
5566 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
5567 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
5568 stats->pkt_cnt_cck++;
5569 } else {
5570 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
5571 stats->pkt_cnt_ofdm++;
5572 stats->evm += phy_ppdu->ofdm.evm_min;
5573 }
5574 } else {
5575 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
5576 stats->pkt_cnt_non_legacy++;
5577 stats->evm += phy_ppdu->ofdm.evm_min;
5578 }
5579 }
5580
rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats * stats)5581 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
5582 {
5583 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
5584 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
5585 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
5586 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
5587 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
5588 return ewma_rssi_read(&stats->ofdm_rssi_avg);
5589 else
5590 return ewma_rssi_read(&stats->cck_rssi_avg);
5591 }
5592
rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats * stats)5593 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
5594 {
5595 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
5596 }
5597
rtw89_phy_antdiv_parse(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)5598 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
5599 struct rtw89_rx_phy_ppdu *phy_ppdu)
5600 {
5601 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5602 struct rtw89_hal *hal = &rtwdev->hal;
5603
5604 if (!hal->ant_diversity || hal->ant_diversity_fixed)
5605 return;
5606
5607 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
5608
5609 if (!antdiv->get_stats)
5610 return;
5611
5612 if (hal->antenna_rx == RF_A)
5613 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
5614 else if (hal->antenna_rx == RF_B)
5615 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
5616 }
5617
rtw89_phy_antdiv_reg_init(struct rtw89_dev * rtwdev)5618 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
5619 {
5620 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
5621 0x0, RTW89_PHY_0);
5622 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
5623 0x0, RTW89_PHY_0);
5624
5625 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
5626 0x0, RTW89_PHY_0);
5627 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
5628 0x0, RTW89_PHY_0);
5629
5630 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
5631 0x0, RTW89_PHY_0);
5632
5633 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
5634 0x0100, RTW89_PHY_0);
5635
5636 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
5637 0x1, RTW89_PHY_0);
5638 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
5639 0x0, RTW89_PHY_0);
5640 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
5641 0x0, RTW89_PHY_0);
5642 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
5643 0x0, RTW89_PHY_0);
5644 }
5645
rtw89_phy_antdiv_sts_reset(struct rtw89_dev * rtwdev)5646 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
5647 {
5648 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5649
5650 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
5651 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
5652 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
5653 }
5654
rtw89_phy_antdiv_init(struct rtw89_dev * rtwdev)5655 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
5656 {
5657 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5658 struct rtw89_hal *hal = &rtwdev->hal;
5659
5660 if (!hal->ant_diversity)
5661 return;
5662
5663 antdiv->get_stats = false;
5664 antdiv->rssi_pre = 0;
5665 rtw89_phy_antdiv_sts_reset(rtwdev);
5666 rtw89_phy_antdiv_reg_init(rtwdev);
5667 }
5668
rtw89_phy_thermal_protect(struct rtw89_dev * rtwdev)5669 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev)
5670 {
5671 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5672 struct rtw89_hal *hal = &rtwdev->hal;
5673 u8 th_max = phystat->last_thermal_max;
5674 u8 lv = hal->thermal_prot_lv;
5675
5676 if (!hal->thermal_prot_th ||
5677 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT)))
5678 return;
5679
5680 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX)
5681 lv++;
5682 else if (th_max < hal->thermal_prot_th - 2 && lv > 0)
5683 lv--;
5684 else
5685 return;
5686
5687 hal->thermal_prot_lv = lv;
5688
5689 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv);
5690
5691 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv);
5692 }
5693
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)5694 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
5695 {
5696 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5697 u8 th, th_max = 0;
5698 int i;
5699
5700 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
5701 th = rtw89_chip_get_thermal(rtwdev, i);
5702 if (th)
5703 ewma_thermal_add(&phystat->avg_thermal[i], th);
5704
5705 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
5706 "path(%d) thermal cur=%u avg=%ld", i, th,
5707 ewma_thermal_read(&phystat->avg_thermal[i]));
5708
5709 th_max = max(th_max, th);
5710 }
5711
5712 phystat->last_thermal_max = th_max;
5713 }
5714
5715 struct rtw89_phy_iter_rssi_data {
5716 struct rtw89_dev *rtwdev;
5717 bool rssi_changed;
5718 };
5719
5720 static
__rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link * rtwsta_link,struct rtw89_phy_iter_rssi_data * rssi_data)5721 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link,
5722 struct rtw89_phy_iter_rssi_data *rssi_data)
5723 {
5724 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
5725 struct rtw89_dev *rtwdev = rssi_data->rtwdev;
5726 struct rtw89_phy_ch_info *ch_info;
5727 struct rtw89_bb_ctx *bb;
5728 unsigned long rssi_curr;
5729
5730 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
5731 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
5732 ch_info = &bb->ch_info;
5733
5734 if (rssi_curr < ch_info->rssi_min) {
5735 ch_info->rssi_min = rssi_curr;
5736 ch_info->rssi_min_macid = rtwsta_link->mac_id;
5737 }
5738
5739 if (rtwsta_link->prev_rssi == 0) {
5740 rtwsta_link->prev_rssi = rssi_curr;
5741 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
5742 (3 << RSSI_FACTOR)) {
5743 rtwsta_link->prev_rssi = rssi_curr;
5744 rssi_data->rssi_changed = true;
5745 }
5746 }
5747
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)5748 static void rtw89_phy_stat_rssi_update_iter(void *data,
5749 struct ieee80211_sta *sta)
5750 {
5751 struct rtw89_phy_iter_rssi_data *rssi_data =
5752 (struct rtw89_phy_iter_rssi_data *)data;
5753 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
5754 struct rtw89_sta_link *rtwsta_link;
5755 unsigned int link_id;
5756
5757 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
5758 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data);
5759 }
5760
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)5761 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
5762 {
5763 struct rtw89_phy_iter_rssi_data rssi_data = {};
5764 struct rtw89_bb_ctx *bb;
5765
5766 rssi_data.rtwdev = rtwdev;
5767 rtw89_for_each_active_bb(rtwdev, bb)
5768 bb->ch_info.rssi_min = U8_MAX;
5769
5770 ieee80211_iterate_stations_atomic(rtwdev->hw,
5771 rtw89_phy_stat_rssi_update_iter,
5772 &rssi_data);
5773 if (rssi_data.rssi_changed)
5774 rtw89_btc_ntfy_wl_sta(rtwdev);
5775 }
5776
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)5777 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
5778 {
5779 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5780 int i;
5781
5782 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
5783 ewma_thermal_init(&phystat->avg_thermal[i]);
5784
5785 rtw89_phy_stat_thermal_update(rtwdev);
5786
5787 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5788 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
5789
5790 ewma_rssi_init(&phystat->bcn_rssi);
5791
5792 rtwdev->hal.thermal_prot_lv = 0;
5793 }
5794
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)5795 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
5796 {
5797 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5798
5799 rtw89_phy_stat_thermal_update(rtwdev);
5800 rtw89_phy_thermal_protect(rtwdev);
5801 rtw89_phy_stat_rssi_update(rtwdev);
5802
5803 phystat->last_pkt_stat = phystat->cur_pkt_stat;
5804 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5805 }
5806
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u32 time_us)5807 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev,
5808 struct rtw89_bb_ctx *bb, u32 time_us)
5809 {
5810 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5811
5812 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5813 }
5814
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 idx)5815 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev,
5816 struct rtw89_bb_ctx *bb, u16 idx)
5817 {
5818 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5819
5820 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5821 }
5822
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5823 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev,
5824 struct rtw89_bb_ctx *bb)
5825 {
5826 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5827 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5828 const struct rtw89_ccx_regs *ccx = phy->ccx;
5829
5830 env->ccx_manual_ctrl = false;
5831 env->ccx_ongoing = false;
5832 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5833 env->ccx_period = 0;
5834 env->ccx_unit_idx = RTW89_CCX_32_US;
5835
5836 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->en_mask, 1, bb->phy_idx);
5837 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1,
5838 bb->phy_idx);
5839 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5840 bb->phy_idx);
5841 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
5842 RTW89_CCX_EDCCA_BW20_0, bb->phy_idx);
5843 }
5844
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 report,u16 score)5845 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev,
5846 struct rtw89_bb_ctx *bb,
5847 u16 report, u16 score)
5848 {
5849 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5850 u32 numer = 0;
5851 u16 ret = 0;
5852
5853 numer = report * score + (env->ccx_period >> 1);
5854 if (env->ccx_period)
5855 ret = numer / env->ccx_period;
5856
5857 return ret >= score ? score - 1 : ret;
5858 }
5859
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)5860 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
5861 u16 time_ms, u32 *period,
5862 u32 *unit_idx)
5863 {
5864 u32 idx;
5865 u8 quotient;
5866
5867 if (time_ms >= CCX_MAX_PERIOD)
5868 time_ms = CCX_MAX_PERIOD;
5869
5870 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
5871
5872 if (quotient < 4)
5873 idx = RTW89_CCX_4_US;
5874 else if (quotient < 8)
5875 idx = RTW89_CCX_8_US;
5876 else if (quotient < 16)
5877 idx = RTW89_CCX_16_US;
5878 else
5879 idx = RTW89_CCX_32_US;
5880
5881 *unit_idx = idx;
5882 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
5883
5884 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5885 "[Trigger Time] period:%d, unit_idx:%d\n",
5886 *period, *unit_idx);
5887 }
5888
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5889 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev,
5890 struct rtw89_bb_ctx *bb)
5891 {
5892 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5893
5894 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5895 "lv:(%d)->(0)\n", env->ccx_rac_lv);
5896
5897 env->ccx_ongoing = false;
5898 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5899 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5900 }
5901
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)5902 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
5903 struct rtw89_bb_ctx *bb,
5904 struct rtw89_ccx_para_info *para)
5905 {
5906 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5907 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
5908 u8 i = 0;
5909 u16 *ifs_th_l = env->ifs_clm_th_l;
5910 u16 *ifs_th_h = env->ifs_clm_th_h;
5911 u32 ifs_th0_us = 0, ifs_th_times = 0;
5912 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
5913
5914 if (!is_update)
5915 goto ifs_update_finished;
5916
5917 switch (para->ifs_clm_app) {
5918 case RTW89_IFS_CLM_INIT:
5919 case RTW89_IFS_CLM_BACKGROUND:
5920 case RTW89_IFS_CLM_ACS:
5921 case RTW89_IFS_CLM_DBG:
5922 case RTW89_IFS_CLM_DIG:
5923 case RTW89_IFS_CLM_TDMA_DIG:
5924 ifs_th0_us = IFS_CLM_TH0_UPPER;
5925 ifs_th_times = IFS_CLM_TH_MUL;
5926 break;
5927 case RTW89_IFS_CLM_DBG_MANUAL:
5928 ifs_th0_us = para->ifs_clm_manual_th0;
5929 ifs_th_times = para->ifs_clm_manual_th_times;
5930 break;
5931 default:
5932 break;
5933 }
5934
5935 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
5936 * low[i] = high[i-1] + 1
5937 * high[i] = high[i-1] * ifs_th_times
5938 */
5939 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
5940 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
5941 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, bb,
5942 ifs_th0_us);
5943 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
5944 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
5945 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
5946 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, ifs_th_h_us[i]);
5947 }
5948
5949 ifs_update_finished:
5950 if (!is_update)
5951 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5952 "No need to update IFS_TH\n");
5953
5954 return is_update;
5955 }
5956
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5957 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev,
5958 struct rtw89_bb_ctx *bb)
5959 {
5960 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5961 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5962 const struct rtw89_ccx_regs *ccx = phy->ccx;
5963 u8 i = 0;
5964
5965 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
5966 env->ifs_clm_th_l[0], bb->phy_idx);
5967 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
5968 env->ifs_clm_th_l[1], bb->phy_idx);
5969 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
5970 env->ifs_clm_th_l[2], bb->phy_idx);
5971 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
5972 env->ifs_clm_th_l[3], bb->phy_idx);
5973
5974 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
5975 env->ifs_clm_th_h[0], bb->phy_idx);
5976 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
5977 env->ifs_clm_th_h[1], bb->phy_idx);
5978 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
5979 env->ifs_clm_th_h[2], bb->phy_idx);
5980 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
5981 env->ifs_clm_th_h[3], bb->phy_idx);
5982
5983 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5984 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5985 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
5986 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
5987 }
5988
__rtw89_phy_nhm_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5989 static void __rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev,
5990 struct rtw89_bb_ctx *bb)
5991 {
5992 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5993 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5994 const struct rtw89_ccx_regs *ccx = phy->ccx;
5995
5996 env->nhm_include_cca = false;
5997 env->nhm_mntr_time = 0;
5998 env->nhm_sum = 0;
5999
6000 rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_config, ccx->nhm_en_mask, bb->phy_idx);
6001 rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_method, ccx->nhm_pwr_method_msk,
6002 bb->phy_idx);
6003 }
6004
rtw89_phy_nhm_setting_init(struct rtw89_dev * rtwdev)6005 void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev)
6006 {
6007 const struct rtw89_chip_info *chip = rtwdev->chip;
6008 struct rtw89_bb_ctx *bb;
6009
6010 if (!chip->support_noise)
6011 return;
6012
6013 rtw89_for_each_active_bb(rtwdev, bb)
6014 __rtw89_phy_nhm_setting_init(rtwdev, bb);
6015 }
6016
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6017 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev,
6018 struct rtw89_bb_ctx *bb)
6019 {
6020 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6021 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6022 const struct rtw89_ccx_regs *ccx = phy->ccx;
6023 struct rtw89_ccx_para_info para = {};
6024
6025 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
6026 env->ifs_clm_mntr_time = 0;
6027
6028 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
6029 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, ¶))
6030 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
6031
6032 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true,
6033 bb->phy_idx);
6034 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true,
6035 bb->phy_idx);
6036 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true,
6037 bb->phy_idx);
6038 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true,
6039 bb->phy_idx);
6040 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true,
6041 bb->phy_idx);
6042 }
6043
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,enum rtw89_env_racing_lv level)6044 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
6045 struct rtw89_bb_ctx *bb,
6046 enum rtw89_env_racing_lv level)
6047 {
6048 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6049 int ret = 0;
6050
6051 if (level >= RTW89_RAC_MAX_NUM) {
6052 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6053 "[WARNING] Wrong LV=%d\n", level);
6054 return -EINVAL;
6055 }
6056
6057 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6058 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
6059 env->ccx_rac_lv, level);
6060
6061 if (env->ccx_ongoing) {
6062 if (level <= env->ccx_rac_lv)
6063 ret = -EINVAL;
6064 else
6065 env->ccx_ongoing = false;
6066 }
6067
6068 if (ret == 0)
6069 env->ccx_rac_lv = level;
6070
6071 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
6072 !ret);
6073
6074 return ret;
6075 }
6076
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 sel)6077 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev,
6078 struct rtw89_bb_ctx *bb, u8 sel)
6079 {
6080 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6081 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6082 const struct rtw89_ccx_regs *ccx = phy->ccx;
6083
6084 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0,
6085 bb->phy_idx);
6086 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0,
6087 bb->phy_idx);
6088 if (sel & RTW89_PHY_ENV_MON_NHM)
6089 rtw89_phy_write32_idx_clr(rtwdev, ccx->nhm_config,
6090 ccx->nhm_en_mask, bb->phy_idx);
6091
6092 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1,
6093 bb->phy_idx);
6094 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
6095 bb->phy_idx);
6096 if (sel & RTW89_PHY_ENV_MON_NHM)
6097 rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_config,
6098 ccx->nhm_en_mask, bb->phy_idx);
6099
6100 env->ccx_ongoing = true;
6101 }
6102
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6103 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev,
6104 struct rtw89_bb_ctx *bb)
6105 {
6106 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6107 u8 i = 0;
6108 u32 res = 0;
6109
6110 env->ifs_clm_tx_ratio =
6111 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_tx, PERCENT);
6112 env->ifs_clm_edcca_excl_cca_ratio =
6113 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_edcca_excl_cca,
6114 PERCENT);
6115 env->ifs_clm_cck_fa_ratio =
6116 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERCENT);
6117 env->ifs_clm_ofdm_fa_ratio =
6118 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERCENT);
6119 env->ifs_clm_cck_cca_excl_fa_ratio =
6120 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckcca_excl_fa,
6121 PERCENT);
6122 env->ifs_clm_ofdm_cca_excl_fa_ratio =
6123 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmcca_excl_fa,
6124 PERCENT);
6125 env->ifs_clm_cck_fa_permil =
6126 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERMIL);
6127 env->ifs_clm_ofdm_fa_permil =
6128 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERMIL);
6129
6130 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
6131 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
6132 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
6133 } else {
6134 env->ifs_clm_ifs_avg[i] =
6135 rtw89_phy_ccx_idx_to_us(rtwdev, bb,
6136 env->ifs_clm_avg[i]);
6137 }
6138
6139 res = rtw89_phy_ccx_idx_to_us(rtwdev, bb, env->ifs_clm_cca[i]);
6140 res += env->ifs_clm_his[i] >> 1;
6141 if (env->ifs_clm_his[i])
6142 res /= env->ifs_clm_his[i];
6143 else
6144 res = 0;
6145 env->ifs_clm_cca_avg[i] = res;
6146 }
6147
6148 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6149 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
6150 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
6151 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6152 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
6153 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
6154 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6155 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
6156 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
6157 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6158 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
6159 env->ifs_clm_cck_cca_excl_fa_ratio,
6160 env->ifs_clm_ofdm_cca_excl_fa_ratio);
6161 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6162 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
6163 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
6164 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
6165 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
6166 env->ifs_clm_cca_avg[i]);
6167 }
6168
rtw89_nhm_weighted_avg(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6169 static u8 rtw89_nhm_weighted_avg(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6170 {
6171 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6172 u8 nhm_weight[RTW89_NHM_RPT_NUM];
6173 u32 nhm_weighted_sum = 0;
6174 u8 weight_zero;
6175 u8 i;
6176
6177 if (env->nhm_sum == 0)
6178 return 0;
6179
6180 weight_zero = clamp_t(u16, env->nhm_th[0] - RTW89_NHM_WEIGHT_OFFSET, 0, U8_MAX);
6181
6182 for (i = 0; i < RTW89_NHM_RPT_NUM; i++) {
6183 if (i == 0)
6184 nhm_weight[i] = weight_zero;
6185 else if (i == (RTW89_NHM_RPT_NUM - 1))
6186 nhm_weight[i] = env->nhm_th[i - 1] + RTW89_NHM_WEIGHT_OFFSET;
6187 else
6188 nhm_weight[i] = (env->nhm_th[i - 1] + env->nhm_th[i]) / 2;
6189 }
6190
6191 if (rtwdev->chip->chip_id == RTL8852A || rtwdev->chip->chip_id == RTL8852B ||
6192 rtwdev->chip->chip_id == RTL8852C) {
6193 if (env->nhm_th[RTW89_NHM_TH_NUM - 1] == RTW89_NHM_WA_TH) {
6194 nhm_weight[RTW89_NHM_RPT_NUM - 1] =
6195 env->nhm_th[RTW89_NHM_TH_NUM - 2] +
6196 RTW89_NHM_WEIGHT_OFFSET;
6197 nhm_weight[RTW89_NHM_RPT_NUM - 2] =
6198 nhm_weight[RTW89_NHM_RPT_NUM - 1];
6199 }
6200
6201 env->nhm_result[0] += env->nhm_result[RTW89_NHM_RPT_NUM - 1];
6202 env->nhm_result[RTW89_NHM_RPT_NUM - 1] = 0;
6203 }
6204
6205 for (i = 0; i < RTW89_NHM_RPT_NUM; i++)
6206 nhm_weighted_sum += env->nhm_result[i] * nhm_weight[i];
6207
6208 return (nhm_weighted_sum / env->nhm_sum) >> RTW89_NHM_TH_FACTOR;
6209 }
6210
__rtw89_phy_nhm_get_result(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,enum rtw89_band hw_band,u16 ch_hw_value)6211 static void __rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev,
6212 struct rtw89_bb_ctx *bb, enum rtw89_band hw_band,
6213 u16 ch_hw_value)
6214 {
6215 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6216 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6217 const struct rtw89_chip_info *chip = rtwdev->chip;
6218 const struct rtw89_ccx_regs *ccx = phy->ccx;
6219 struct ieee80211_supported_band *sband;
6220 const struct rtw89_reg_def *nhm_rpt;
6221 enum nl80211_band band;
6222 u32 sum = 0;
6223 u8 chan_idx;
6224 u8 nhm_pwr;
6225 u8 i;
6226
6227 if (!rtw89_phy_read32_idx(rtwdev, ccx->nhm, ccx->nhm_ready, bb->phy_idx)) {
6228 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "[NHM] Get NHM report Fail\n");
6229 return;
6230 }
6231
6232 for (i = 0; i < RTW89_NHM_RPT_NUM; i++) {
6233 nhm_rpt = &(*chip->nhm_report)[i];
6234
6235 env->nhm_result[i] =
6236 rtw89_phy_read32_idx(rtwdev, nhm_rpt->addr,
6237 nhm_rpt->mask, bb->phy_idx);
6238 sum += env->nhm_result[i];
6239 }
6240 env->nhm_sum = sum;
6241 nhm_pwr = rtw89_nhm_weighted_avg(rtwdev, bb);
6242
6243 if (!ch_hw_value)
6244 return;
6245
6246 band = rtw89_hw_to_nl80211_band(hw_band);
6247 sband = rtwdev->hw->wiphy->bands[band];
6248 if (!sband)
6249 return;
6250
6251 for (chan_idx = 0; chan_idx < sband->n_channels; chan_idx++) {
6252 struct ieee80211_channel *channel;
6253 struct rtw89_nhm_report *rpt;
6254 struct list_head *nhm_list;
6255
6256 channel = &sband->channels[chan_idx];
6257 if (channel->hw_value != ch_hw_value)
6258 continue;
6259
6260 rpt = &env->nhm_his[hw_band][chan_idx];
6261 nhm_list = &env->nhm_rpt_list;
6262
6263 rpt->channel = channel;
6264 rpt->noise = nhm_pwr;
6265
6266 if (list_empty(&rpt->list))
6267 list_add_tail(&rpt->list, nhm_list);
6268
6269 return;
6270 }
6271
6272 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "[NHM] channel not found\n");
6273 }
6274
rtw89_phy_nhm_get_result(struct rtw89_dev * rtwdev,enum rtw89_band hw_band,u16 ch_hw_value)6275 void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band,
6276 u16 ch_hw_value)
6277 {
6278 const struct rtw89_chip_info *chip = rtwdev->chip;
6279 struct rtw89_bb_ctx *bb;
6280
6281 if (!chip->support_noise)
6282 return;
6283
6284 rtw89_for_each_active_bb(rtwdev, bb)
6285 __rtw89_phy_nhm_get_result(rtwdev, bb, hw_band, ch_hw_value);
6286 }
6287
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6288 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev,
6289 struct rtw89_bb_ctx *bb)
6290 {
6291 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6292 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6293 const struct rtw89_ccx_regs *ccx = phy->ccx;
6294 u8 i = 0;
6295
6296 if (rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
6297 ccx->ifs_cnt_done_mask, bb->phy_idx) == 0) {
6298 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6299 "Get IFS_CLM report Fail\n");
6300 return false;
6301 }
6302
6303 env->ifs_clm_tx =
6304 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
6305 ccx->ifs_clm_tx_cnt_msk, bb->phy_idx);
6306 env->ifs_clm_edcca_excl_cca =
6307 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
6308 ccx->ifs_clm_edcca_excl_cca_fa_mask, bb->phy_idx);
6309 env->ifs_clm_cckcca_excl_fa =
6310 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
6311 ccx->ifs_clm_cckcca_excl_fa_mask, bb->phy_idx);
6312 env->ifs_clm_ofdmcca_excl_fa =
6313 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
6314 ccx->ifs_clm_ofdmcca_excl_fa_mask, bb->phy_idx);
6315 env->ifs_clm_cckfa =
6316 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
6317 ccx->ifs_clm_cck_fa_mask, bb->phy_idx);
6318 env->ifs_clm_ofdmfa =
6319 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
6320 ccx->ifs_clm_ofdm_fa_mask, bb->phy_idx);
6321
6322 env->ifs_clm_his[0] =
6323 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
6324 ccx->ifs_t1_his_mask, bb->phy_idx);
6325 env->ifs_clm_his[1] =
6326 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
6327 ccx->ifs_t2_his_mask, bb->phy_idx);
6328
6329 env->ifs_clm_his[2] =
6330 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr2,
6331 ccx->ifs_t3_his_mask, bb->phy_idx);
6332 env->ifs_clm_his[3] =
6333 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr2,
6334 ccx->ifs_t4_his_mask, bb->phy_idx);
6335
6336 env->ifs_clm_avg[0] =
6337 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
6338 ccx->ifs_t1_avg_mask, bb->phy_idx);
6339 env->ifs_clm_avg[1] =
6340 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
6341 ccx->ifs_t2_avg_mask, bb->phy_idx);
6342 env->ifs_clm_avg[2] =
6343 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
6344 ccx->ifs_t3_avg_mask, bb->phy_idx);
6345 env->ifs_clm_avg[3] =
6346 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
6347 ccx->ifs_t4_avg_mask, bb->phy_idx);
6348
6349 env->ifs_clm_cca[0] =
6350 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
6351 ccx->ifs_t1_cca_mask, bb->phy_idx);
6352 env->ifs_clm_cca[1] =
6353 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
6354 ccx->ifs_t2_cca_mask, bb->phy_idx);
6355 env->ifs_clm_cca[2] =
6356 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
6357 ccx->ifs_t3_cca_mask, bb->phy_idx);
6358 env->ifs_clm_cca[3] =
6359 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
6360 ccx->ifs_t4_cca_mask, bb->phy_idx);
6361
6362 env->ifs_clm_total_ifs =
6363 rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
6364 ccx->ifs_total_mask, bb->phy_idx);
6365
6366 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
6367 env->ifs_clm_total_ifs);
6368 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6369 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
6370 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
6371 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6372 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
6373 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
6374 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6375 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
6376 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
6377
6378 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
6379 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
6380 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6381 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
6382 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
6383
6384 rtw89_phy_ifs_clm_get_utility(rtwdev, bb);
6385
6386 return true;
6387 }
6388
rtw89_phy_nhm_th_update(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6389 static void rtw89_phy_nhm_th_update(struct rtw89_dev *rtwdev,
6390 struct rtw89_bb_ctx *bb)
6391 {
6392 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6393 static const u8 nhm_th_11k[RTW89_NHM_RPT_NUM] = {
6394 18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60, 0
6395 };
6396 const struct rtw89_chip_info *chip = rtwdev->chip;
6397 const struct rtw89_reg_def *nhm_th;
6398 u8 i;
6399
6400 for (i = 0; i < RTW89_NHM_RPT_NUM; i++)
6401 env->nhm_th[i] = nhm_th_11k[i] << RTW89_NHM_TH_FACTOR;
6402
6403 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
6404 chip->chip_id == RTL8852C)
6405 env->nhm_th[RTW89_NHM_TH_NUM - 1] = RTW89_NHM_WA_TH;
6406
6407 for (i = 0; i < RTW89_NHM_TH_NUM; i++) {
6408 nhm_th = &(*chip->nhm_th)[i];
6409
6410 rtw89_phy_write32_idx(rtwdev, nhm_th->addr, nhm_th->mask,
6411 env->nhm_th[i], bb->phy_idx);
6412 }
6413 }
6414
rtw89_phy_nhm_set(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)6415 static int rtw89_phy_nhm_set(struct rtw89_dev *rtwdev,
6416 struct rtw89_bb_ctx *bb,
6417 struct rtw89_ccx_para_info *para)
6418 {
6419 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6420 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6421 const struct rtw89_ccx_regs *ccx = phy->ccx;
6422 u32 unit_idx = 0;
6423 u32 period = 0;
6424
6425 if (para->mntr_time == 0) {
6426 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6427 "[NHM] MNTR_TIME is 0\n");
6428 return -EINVAL;
6429 }
6430
6431 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv))
6432 return -EINVAL;
6433
6434 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6435 "[NHM]nhm_incld_cca=%d, mntr_time=%d ms\n",
6436 para->nhm_incld_cca, para->mntr_time);
6437
6438 if (para->mntr_time != env->nhm_mntr_time) {
6439 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
6440 &period, &unit_idx);
6441 rtw89_phy_write32_idx(rtwdev, ccx->nhm_config,
6442 ccx->nhm_period_mask, period, bb->phy_idx);
6443 rtw89_phy_write32_idx(rtwdev, ccx->nhm_config,
6444 ccx->nhm_unit_mask, period, bb->phy_idx);
6445
6446 env->nhm_mntr_time = para->mntr_time;
6447 env->ccx_period = period;
6448 env->ccx_unit_idx = unit_idx;
6449 }
6450
6451 if (para->nhm_incld_cca != env->nhm_include_cca) {
6452 rtw89_phy_write32_idx(rtwdev, ccx->nhm_config,
6453 ccx->nhm_include_cca_mask, para->nhm_incld_cca,
6454 bb->phy_idx);
6455
6456 env->nhm_include_cca = para->nhm_incld_cca;
6457 }
6458
6459 rtw89_phy_nhm_th_update(rtwdev, bb);
6460
6461 return 0;
6462 }
6463
__rtw89_phy_nhm_trigger(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6464 static void __rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6465 {
6466 struct rtw89_ccx_para_info para = {
6467 .mntr_time = RTW89_NHM_MNTR_TIME,
6468 .rac_lv = RTW89_RAC_LV_1,
6469 .nhm_incld_cca = true,
6470 };
6471
6472 rtw89_phy_ccx_racing_release(rtwdev, bb);
6473
6474 rtw89_phy_nhm_set(rtwdev, bb, ¶);
6475 rtw89_phy_ccx_trigger(rtwdev, bb, RTW89_PHY_ENV_MON_NHM);
6476 }
6477
rtw89_phy_nhm_trigger(struct rtw89_dev * rtwdev)6478 void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev)
6479 {
6480 const struct rtw89_chip_info *chip = rtwdev->chip;
6481 struct rtw89_bb_ctx *bb;
6482
6483 if (!chip->support_noise)
6484 return;
6485
6486 rtw89_for_each_active_bb(rtwdev, bb)
6487 __rtw89_phy_nhm_trigger(rtwdev, bb);
6488 }
6489
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)6490 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
6491 struct rtw89_bb_ctx *bb,
6492 struct rtw89_ccx_para_info *para)
6493 {
6494 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6495 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6496 const struct rtw89_ccx_regs *ccx = phy->ccx;
6497 u32 period = 0;
6498 u32 unit_idx = 0;
6499
6500 if (para->mntr_time == 0) {
6501 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6502 "[WARN] MNTR_TIME is 0\n");
6503 return -EINVAL;
6504 }
6505
6506 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv))
6507 return -EINVAL;
6508
6509 if (para->mntr_time != env->ifs_clm_mntr_time) {
6510 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
6511 &period, &unit_idx);
6512 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
6513 ccx->ifs_clm_period_mask, period, bb->phy_idx);
6514 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
6515 ccx->ifs_clm_cnt_unit_mask,
6516 unit_idx, bb->phy_idx);
6517
6518 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6519 "Update IFS-CLM time ((%d)) -> ((%d))\n",
6520 env->ifs_clm_mntr_time, para->mntr_time);
6521
6522 env->ifs_clm_mntr_time = para->mntr_time;
6523 env->ccx_period = (u16)period;
6524 env->ccx_unit_idx = (u8)unit_idx;
6525 }
6526
6527 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, para)) {
6528 env->ifs_clm_app = para->ifs_clm_app;
6529 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
6530 }
6531
6532 return 0;
6533 }
6534
__rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6535 static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev,
6536 struct rtw89_bb_ctx *bb)
6537 {
6538 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6539 struct rtw89_ccx_para_info para = {};
6540 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
6541
6542 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
6543 if (env->ccx_manual_ctrl) {
6544 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6545 "CCX in manual ctrl\n");
6546 return;
6547 }
6548
6549 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6550 "BB-%d env_monitor track\n", bb->phy_idx);
6551
6552 /* only ifs_clm for now */
6553 if (rtw89_phy_ifs_clm_get_result(rtwdev, bb))
6554 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
6555
6556 rtw89_phy_ccx_racing_release(rtwdev, bb);
6557 para.mntr_time = 1900;
6558 para.rac_lv = RTW89_RAC_LV_1;
6559 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
6560
6561 if (rtw89_phy_ifs_clm_set(rtwdev, bb, ¶) == 0)
6562 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
6563 if (chk_result)
6564 rtw89_phy_ccx_trigger(rtwdev, bb, chk_result);
6565
6566 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6567 "get_result=0x%x, chk_result:0x%x\n",
6568 env->ccx_watchdog_result, chk_result);
6569 }
6570
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)6571 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
6572 {
6573 struct rtw89_bb_ctx *bb;
6574
6575 rtw89_for_each_active_bb(rtwdev, bb)
6576 __rtw89_phy_env_monitor_track(rtwdev, bb);
6577 }
6578
rtw89_physts_ie_page_valid(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap * ie_page)6579 static bool rtw89_physts_ie_page_valid(struct rtw89_dev *rtwdev,
6580 enum rtw89_phy_status_bitmap *ie_page)
6581 {
6582 const struct rtw89_chip_info *chip = rtwdev->chip;
6583
6584 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM ||
6585 *ie_page == RTW89_RSVD_9)
6586 return false;
6587 else if (*ie_page > RTW89_RSVD_9 && *ie_page < RTW89_EHT_PKT)
6588 *ie_page -= 1;
6589
6590 if (*ie_page == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX)
6591 return false;
6592
6593 return true;
6594 }
6595
rtw89_phy_get_ie_bitmap_addr(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page)6596 static u32 rtw89_phy_get_ie_bitmap_addr(struct rtw89_dev *rtwdev,
6597 enum rtw89_phy_status_bitmap ie_page)
6598 {
6599 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6600 static const u8 ie_page_shift = 2;
6601
6602 if (ie_page == RTW89_EHT_PKT)
6603 return phy->physt_bmp_eht;
6604
6605 return phy->physt_bmp_start + (ie_page << ie_page_shift);
6606 }
6607
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,enum rtw89_phy_idx phy_idx)6608 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
6609 enum rtw89_phy_status_bitmap ie_page,
6610 enum rtw89_phy_idx phy_idx)
6611 {
6612 u32 addr;
6613
6614 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page))
6615 return 0;
6616
6617 addr = rtw89_phy_get_ie_bitmap_addr(rtwdev, ie_page);
6618
6619 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx);
6620 }
6621
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val,enum rtw89_phy_idx phy_idx)6622 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
6623 enum rtw89_phy_status_bitmap ie_page,
6624 u32 val, enum rtw89_phy_idx phy_idx)
6625 {
6626 const struct rtw89_chip_info *chip = rtwdev->chip;
6627 u32 addr;
6628
6629 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page))
6630 return;
6631
6632 if (chip->chip_id == RTL8852A)
6633 val &= B_PHY_STS_BITMAP_MSK_52A;
6634
6635 addr = rtw89_phy_get_ie_bitmap_addr(rtwdev, ie_page);
6636 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
6637 }
6638
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)6639 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
6640 bool enable,
6641 enum rtw89_phy_idx phy_idx)
6642 {
6643 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
6644 const struct rtw89_physts_regs *physts = phy->physts;
6645
6646 if (enable) {
6647 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
6648 physts->dis_trigger_fail_mask, phy_idx);
6649 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
6650 physts->dis_trigger_brk_mask, phy_idx);
6651 } else {
6652 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
6653 physts->dis_trigger_fail_mask, phy_idx);
6654 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
6655 physts->dis_trigger_brk_mask, phy_idx);
6656 }
6657 }
6658
rtw89_physts_enable_hdr_2(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6659 static void rtw89_physts_enable_hdr_2(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6660 {
6661 const struct rtw89_chip_info *chip = rtwdev->chip;
6662
6663 if (chip->chip_gen == RTW89_CHIP_AX || chip->chip_id == RTL8922A)
6664 return;
6665
6666 rtw89_phy_write32_idx_set(rtwdev, R_STS_HDR2_PARSING_BE4,
6667 B_STS_HDR2_PARSING_BE4, phy_idx);
6668 }
6669
__rtw89_physts_parsing_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6670 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
6671 enum rtw89_phy_idx phy_idx)
6672 {
6673 const struct rtw89_chip_info *chip = rtwdev->chip;
6674 u32 val;
6675 u8 i;
6676
6677 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
6678
6679 /* enable hdr_2 for 8922D (PHYSTS_BE_GEN2 above) */
6680 rtw89_physts_enable_hdr_2(rtwdev, phy_idx);
6681
6682 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
6683 if (i == RTW89_RSVD_9 ||
6684 (i == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX))
6685 continue;
6686
6687 val = rtw89_physts_get_ie_bitmap(rtwdev, i, phy_idx);
6688 if (i == RTW89_HE_MU || i == RTW89_VHT_MU) {
6689 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF);
6690 } else if (i == RTW89_TRIG_BASE_PPDU) {
6691 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF) |
6692 BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
6693 } else if (i >= RTW89_CCK_PKT) {
6694 val &= ~(GENMASK(RTW89_PHYSTS_IE07_CMN_EXT_PATH_D,
6695 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A));
6696
6697 if (i == RTW89_CCK_PKT)
6698 val |= BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
6699 else if (i >= RTW89_HT_PKT)
6700 val |= BIT(RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0);
6701 }
6702
6703 rtw89_physts_set_ie_bitmap(rtwdev, i, val, phy_idx);
6704 }
6705 }
6706
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)6707 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
6708 {
6709 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0);
6710 if (rtwdev->dbcc_en)
6711 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1);
6712 }
6713
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,int type)6714 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev,
6715 struct rtw89_bb_ctx *bb, int type)
6716 {
6717 const struct rtw89_chip_info *chip = rtwdev->chip;
6718 const struct rtw89_phy_dig_gain_cfg *cfg;
6719 struct rtw89_dig_info *dig = &bb->dig;
6720 const char *msg;
6721 u8 i;
6722 s8 gain_base;
6723 s8 *gain_arr;
6724 u32 tmp;
6725
6726 switch (type) {
6727 case RTW89_DIG_GAIN_LNA_G:
6728 gain_arr = dig->lna_gain_g;
6729 gain_base = LNA0_GAIN;
6730 cfg = chip->dig_table->cfg_lna_g;
6731 msg = "lna_gain_g";
6732 break;
6733 case RTW89_DIG_GAIN_TIA_G:
6734 gain_arr = dig->tia_gain_g;
6735 gain_base = TIA0_GAIN_G;
6736 cfg = chip->dig_table->cfg_tia_g;
6737 msg = "tia_gain_g";
6738 break;
6739 case RTW89_DIG_GAIN_LNA_A:
6740 gain_arr = dig->lna_gain_a;
6741 gain_base = LNA0_GAIN;
6742 cfg = chip->dig_table->cfg_lna_a;
6743 msg = "lna_gain_a";
6744 break;
6745 case RTW89_DIG_GAIN_TIA_A:
6746 gain_arr = dig->tia_gain_a;
6747 gain_base = TIA0_GAIN_A;
6748 cfg = chip->dig_table->cfg_tia_a;
6749 msg = "tia_gain_a";
6750 break;
6751 default:
6752 return;
6753 }
6754
6755 for (i = 0; i < cfg->size; i++) {
6756 tmp = rtw89_phy_read32_idx(rtwdev, cfg->table[i].addr,
6757 cfg->table[i].mask, bb->phy_idx);
6758 tmp >>= DIG_GAIN_SHIFT;
6759 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
6760 gain_base += DIG_GAIN;
6761
6762 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
6763 msg, i, gain_arr[i]);
6764 }
6765 }
6766
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6767 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev,
6768 struct rtw89_bb_ctx *bb)
6769 {
6770 struct rtw89_dig_info *dig = &bb->dig;
6771 u32 tmp;
6772 u8 i;
6773
6774 if (!rtwdev->hal.support_igi)
6775 return;
6776
6777 tmp = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PKPW,
6778 B_PATH0_IB_PKPW_MSK, bb->phy_idx);
6779 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
6780 dig->ib_pbk = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PBK,
6781 B_PATH0_IB_PBK_MSK, bb->phy_idx);
6782 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
6783 dig->ib_pkpwr, dig->ib_pbk);
6784
6785 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
6786 rtw89_phy_dig_read_gain_table(rtwdev, bb, i);
6787 }
6788
6789 static const u8 rssi_nolink = 22;
6790 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
6791 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
6792 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
6793 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
6794
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6795 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev,
6796 struct rtw89_bb_ctx *bb)
6797 {
6798 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
6799 struct rtw89_dig_info *dig = &bb->dig;
6800 bool is_linked = rtwdev->total_sta_assoc > 0;
6801
6802 if (is_linked) {
6803 dig->igi_rssi = ch_info->rssi_min >> 1;
6804 } else {
6805 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
6806 dig->igi_rssi = rssi_nolink;
6807 }
6808 }
6809
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6810 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev,
6811 struct rtw89_bb_ctx *bb)
6812 {
6813 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
6814 struct rtw89_dig_info *dig = &bb->dig;
6815 bool is_linked = rtwdev->total_sta_assoc > 0;
6816 const u16 *fa_th_src = NULL;
6817
6818 switch (chan->band_type) {
6819 case RTW89_BAND_2G:
6820 dig->lna_gain = dig->lna_gain_g;
6821 dig->tia_gain = dig->tia_gain_g;
6822 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
6823 dig->force_gaincode_idx_en = false;
6824 dig->dyn_pd_th_en = true;
6825 break;
6826 case RTW89_BAND_5G:
6827 default:
6828 dig->lna_gain = dig->lna_gain_a;
6829 dig->tia_gain = dig->tia_gain_a;
6830 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
6831 dig->force_gaincode_idx_en = true;
6832 dig->dyn_pd_th_en = true;
6833 break;
6834 }
6835 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
6836 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
6837 }
6838
6839 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20;
6840 static const u8 igi_max_performance_mode = 0x5a;
6841 static const u8 dynamic_pd_threshold_max;
6842
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6843 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev,
6844 struct rtw89_bb_ctx *bb)
6845 {
6846 struct rtw89_dig_info *dig = &bb->dig;
6847
6848 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
6849 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
6850 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
6851 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
6852 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
6853 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
6854
6855 dig->dyn_igi_max = igi_max_performance_mode;
6856 dig->dyn_igi_min = dynamic_igi_min;
6857 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
6858 dig->pd_low_th_ofst = pd_low_th_offset;
6859 dig->is_linked_pre = false;
6860 }
6861
__rtw89_phy_dig_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6862 static void __rtw89_phy_dig_init(struct rtw89_dev *rtwdev,
6863 struct rtw89_bb_ctx *bb)
6864 {
6865 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig_init\n", bb->phy_idx);
6866
6867 rtw89_phy_dig_update_gain_para(rtwdev, bb);
6868 rtw89_phy_dig_reset(rtwdev, bb);
6869 }
6870
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)6871 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
6872 {
6873 struct rtw89_bb_ctx *bb;
6874
6875 rtw89_for_each_capab_bb(rtwdev, bb)
6876 __rtw89_phy_dig_init(rtwdev, bb);
6877 }
6878
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6879 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev,
6880 struct rtw89_bb_ctx *bb, u8 rssi)
6881 {
6882 struct rtw89_dig_info *dig = &bb->dig;
6883 u8 lna_idx;
6884
6885 if (rssi < dig->igi_rssi_th[0])
6886 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
6887 else if (rssi < dig->igi_rssi_th[1])
6888 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
6889 else if (rssi < dig->igi_rssi_th[2])
6890 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
6891 else if (rssi < dig->igi_rssi_th[3])
6892 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
6893 else if (rssi < dig->igi_rssi_th[4])
6894 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
6895 else
6896 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
6897
6898 return lna_idx;
6899 }
6900
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6901 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev,
6902 struct rtw89_bb_ctx *bb, u8 rssi)
6903 {
6904 struct rtw89_dig_info *dig = &bb->dig;
6905 u8 tia_idx;
6906
6907 if (rssi < dig->igi_rssi_th[0])
6908 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
6909 else
6910 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
6911
6912 return tia_idx;
6913 }
6914
6915 #define IB_PBK_BASE 110
6916 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6917 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev,
6918 struct rtw89_bb_ctx *bb, u8 rssi,
6919 struct rtw89_agc_gaincode_set *set)
6920 {
6921 struct rtw89_dig_info *dig = &bb->dig;
6922 s8 lna_gain = dig->lna_gain[set->lna_idx];
6923 s8 tia_gain = dig->tia_gain[set->tia_idx];
6924 s32 wb_rssi = rssi + lna_gain + tia_gain;
6925 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
6926 u8 rxb_idx;
6927
6928 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
6929 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
6930
6931 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
6932 wb_rssi, rxb_idx_tmp);
6933
6934 return rxb_idx;
6935 }
6936
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6937 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev,
6938 struct rtw89_bb_ctx *bb, u8 rssi,
6939 struct rtw89_agc_gaincode_set *set)
6940 {
6941 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, bb, rssi);
6942 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, bb, rssi);
6943 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, bb, rssi, set);
6944
6945 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6946 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
6947 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
6948 }
6949
6950 #define IGI_OFFSET_MAX 25
6951 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6952 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev,
6953 struct rtw89_bb_ctx *bb)
6954 {
6955 struct rtw89_dig_info *dig = &bb->dig;
6956 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6957 enum rtw89_dig_noisy_level noisy_lv;
6958 u8 igi_offset = dig->fa_rssi_ofst;
6959 u16 fa_ratio = 0;
6960
6961 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
6962
6963 if (fa_ratio < dig->fa_th[0])
6964 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
6965 else if (fa_ratio < dig->fa_th[1])
6966 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
6967 else if (fa_ratio < dig->fa_th[2])
6968 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
6969 else if (fa_ratio < dig->fa_th[3])
6970 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
6971 else
6972 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
6973
6974 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
6975 igi_offset = 0;
6976 else
6977 igi_offset += noisy_lv * IGI_OFFSET_MUL;
6978
6979 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
6980 dig->fa_rssi_ofst = igi_offset;
6981
6982 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6983 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
6984 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
6985
6986 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6987 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
6988 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
6989 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
6990 noisy_lv, igi_offset);
6991 }
6992
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 lna_idx)6993 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev,
6994 struct rtw89_bb_ctx *bb, u8 lna_idx)
6995 {
6996 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6997
6998 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_lna_init.addr,
6999 dig_regs->p0_lna_init.mask, lna_idx, bb->phy_idx);
7000 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_lna_init.addr,
7001 dig_regs->p1_lna_init.mask, lna_idx, bb->phy_idx);
7002 }
7003
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 tia_idx)7004 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev,
7005 struct rtw89_bb_ctx *bb, u8 tia_idx)
7006 {
7007 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
7008
7009 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_tia_init.addr,
7010 dig_regs->p0_tia_init.mask, tia_idx, bb->phy_idx);
7011 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_tia_init.addr,
7012 dig_regs->p1_tia_init.mask, tia_idx, bb->phy_idx);
7013 }
7014
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rxb_idx)7015 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev,
7016 struct rtw89_bb_ctx *bb, u8 rxb_idx)
7017 {
7018 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
7019
7020 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_rxb_init.addr,
7021 dig_regs->p0_rxb_init.mask, rxb_idx, bb->phy_idx);
7022 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_rxb_init.addr,
7023 dig_regs->p1_rxb_init.mask, rxb_idx, bb->phy_idx);
7024 }
7025
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_agc_gaincode_set set)7026 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
7027 struct rtw89_bb_ctx *bb,
7028 const struct rtw89_agc_gaincode_set set)
7029 {
7030 if (!rtwdev->hal.support_igi)
7031 return;
7032
7033 rtw89_phy_dig_set_lna_idx(rtwdev, bb, set.lna_idx);
7034 rtw89_phy_dig_set_tia_idx(rtwdev, bb, set.tia_idx);
7035 rtw89_phy_dig_set_rxb_idx(rtwdev, bb, set.rxb_idx);
7036
7037 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
7038 set.lna_idx, set.tia_idx, set.rxb_idx);
7039 }
7040
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool enable)7041 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
7042 struct rtw89_bb_ctx *bb,
7043 bool enable)
7044 {
7045 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
7046
7047 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
7048 return;
7049
7050 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
7051 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx);
7052 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
7053 dig_regs->p0_s20_pagcugc_en.mask, enable, bb->phy_idx);
7054 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
7055 dig_regs->p1_p20_pagcugc_en.mask, enable, bb->phy_idx);
7056 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
7057 dig_regs->p1_s20_pagcugc_en.mask, enable, bb->phy_idx);
7058
7059 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
7060 }
7061
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7062 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev,
7063 struct rtw89_bb_ctx *bb)
7064 {
7065 struct rtw89_dig_info *dig = &bb->dig;
7066
7067 if (!rtwdev->hal.support_igi)
7068 return;
7069
7070 if (dig->force_gaincode_idx_en) {
7071 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
7072 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7073 "Force gaincode index enabled.\n");
7074 } else {
7075 rtw89_phy_dig_gaincode_by_rssi(rtwdev, bb, dig->igi_fa_rssi,
7076 &dig->cur_gaincode);
7077 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->cur_gaincode);
7078 }
7079 }
7080
rtw89_phy_dig_cal_under_region(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_chan * chan)7081 static u8 rtw89_phy_dig_cal_under_region(struct rtw89_dev *rtwdev,
7082 struct rtw89_bb_ctx *bb,
7083 const struct rtw89_chan *chan)
7084 {
7085 enum rtw89_bandwidth cbw = chan->band_width;
7086 struct rtw89_dig_info *dig = &bb->dig;
7087 u8 under_region = dig->pd_low_th_ofst;
7088
7089 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
7090 under_region += PD_TH_SB_FLTR_CMP_VAL;
7091
7092 switch (cbw) {
7093 case RTW89_CHANNEL_WIDTH_40:
7094 under_region += PD_TH_BW40_CMP_VAL;
7095 break;
7096 case RTW89_CHANNEL_WIDTH_80:
7097 under_region += PD_TH_BW80_CMP_VAL;
7098 break;
7099 case RTW89_CHANNEL_WIDTH_160:
7100 under_region += PD_TH_BW160_CMP_VAL;
7101 break;
7102 case RTW89_CHANNEL_WIDTH_20:
7103 fallthrough;
7104 default:
7105 under_region += PD_TH_BW20_CMP_VAL;
7106 break;
7107 }
7108
7109 return under_region;
7110 }
7111
__rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable,const struct rtw89_chan * chan)7112 static u32 __rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
7113 struct rtw89_bb_ctx *bb,
7114 u8 rssi, bool enable,
7115 const struct rtw89_chan *chan)
7116 {
7117 struct rtw89_dig_info *dig = &bb->dig;
7118 u8 ofdm_cca_th, under_region;
7119 u8 final_rssi;
7120 u32 pd_val;
7121
7122 under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
7123 dig->dyn_pd_th_max = dig->igi_rssi;
7124
7125 final_rssi = min_t(u8, rssi, dig->igi_rssi);
7126 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
7127 PD_TH_MAX_RSSI + under_region);
7128
7129 if (enable) {
7130 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
7131 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7132 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
7133 final_rssi, ofdm_cca_th, under_region, pd_val);
7134 } else {
7135 pd_val = 0;
7136 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7137 "Dynamic PD th disabled, Set PD_low_bd=0\n");
7138 }
7139
7140 return pd_val;
7141 }
7142
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable)7143 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
7144 struct rtw89_bb_ctx *bb,
7145 u8 rssi, bool enable)
7146 {
7147 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
7148 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
7149 struct rtw89_dig_info *dig = &bb->dig;
7150 u8 final_rssi, under_region = dig->pd_low_th_ofst;
7151 s8 cck_cca_th;
7152 u32 pd_val;
7153
7154 pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi, enable, chan);
7155 dig->bak_dig = pd_val;
7156
7157 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
7158 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
7159 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
7160 dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx);
7161
7162 if (!rtwdev->hal.support_cckpd)
7163 return;
7164
7165 final_rssi = min_t(u8, rssi, dig->igi_rssi);
7166 under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
7167 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
7168 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
7169
7170 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7171 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
7172 final_rssi, cck_cca_th, under_region, pd_val);
7173
7174 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg,
7175 dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx);
7176 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
7177 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val, bb->phy_idx);
7178 }
7179
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7180 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7181 {
7182 struct rtw89_dig_info *dig = &bb->dig;
7183
7184 dig->bypass_dig = false;
7185 rtw89_phy_dig_para_reset(rtwdev, bb);
7186 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
7187 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi_nolink, false);
7188 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
7189 rtw89_phy_dig_update_para(rtwdev, bb);
7190 }
7191
7192 #define IGI_RSSI_MIN 10
7193 #define ABS_IGI_MIN 0xc
7194 static
rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7195 void rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7196 {
7197 struct rtw89_dig_info *dig = &bb->dig;
7198 u8 igi_min;
7199
7200 rtw89_phy_dig_igi_offset_by_env(rtwdev, bb);
7201
7202 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
7203 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
7204 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
7205
7206 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
7207 dig->igi_fa_rssi += dig->fa_rssi_ofst;
7208 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
7209 dig->dyn_igi_max);
7210 } else {
7211 dig->igi_fa_rssi = dig->dyn_igi_max;
7212 }
7213 }
7214
7215 struct rtw89_phy_iter_mcc_dig {
7216 struct rtw89_vif_link *rtwvif_link;
7217 bool has_sta;
7218 u8 rssi_min;
7219 };
7220
rtw89_phy_set_mcc_dig(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_bb_ctx * bb,u8 rssi_min,u8 mcc_role_idx,bool is_linked)7221 static void rtw89_phy_set_mcc_dig(struct rtw89_dev *rtwdev,
7222 struct rtw89_vif_link *rtwvif_link,
7223 struct rtw89_bb_ctx *bb,
7224 u8 rssi_min, u8 mcc_role_idx,
7225 bool is_linked)
7226 {
7227 struct rtw89_dig_info *dig = &bb->dig;
7228 const struct rtw89_chan *chan;
7229 u8 pd_val;
7230
7231 if (is_linked) {
7232 dig->igi_rssi = rssi_min >> 1;
7233 dig->igi_fa_rssi = dig->igi_rssi;
7234 } else {
7235 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
7236 dig->igi_rssi = rssi_nolink;
7237 dig->igi_fa_rssi = dig->igi_rssi;
7238 }
7239
7240 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
7241 rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
7242 pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi,
7243 is_linked, chan);
7244 rtw89_fw_h2c_mcc_dig(rtwdev, rtwvif_link->chanctx_idx,
7245 mcc_role_idx, pd_val, true);
7246
7247 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7248 "MCC chanctx_idx %d chan %d rssi %d pd_val %d",
7249 rtwvif_link->chanctx_idx, chan->primary_channel,
7250 dig->igi_rssi, pd_val);
7251 }
7252
rtw89_phy_set_mcc_dig_iter(void * data,struct ieee80211_sta * sta)7253 static void rtw89_phy_set_mcc_dig_iter(void *data, struct ieee80211_sta *sta)
7254 {
7255 struct rtw89_phy_iter_mcc_dig *mcc_dig = (struct rtw89_phy_iter_mcc_dig *)data;
7256 unsigned int link_id = mcc_dig->rtwvif_link->link_id;
7257 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
7258 struct rtw89_sta_link *rtwsta_link;
7259
7260 if (rtwsta->rtwvif != mcc_dig->rtwvif_link->rtwvif)
7261 return;
7262
7263 rtwsta_link = rtwsta->links[link_id];
7264 if (!rtwsta_link)
7265 return;
7266
7267 mcc_dig->has_sta = true;
7268 if (ewma_rssi_read(&rtwsta_link->avg_rssi) < mcc_dig->rssi_min)
7269 mcc_dig->rssi_min = ewma_rssi_read(&rtwsta_link->avg_rssi);
7270 }
7271
rtw89_phy_dig_mcc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7272 static void rtw89_phy_dig_mcc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7273 {
7274 struct rtw89_phy_iter_mcc_dig mcc_dig;
7275 struct rtw89_vif_link *rtwvif_link;
7276 struct rtw89_mcc_links_info info;
7277 int i;
7278
7279 rtw89_mcc_get_links(rtwdev, &info);
7280 for (i = 0; i < ARRAY_SIZE(info.links); i++) {
7281 rtwvif_link = info.links[i];
7282 if (!rtwvif_link)
7283 continue;
7284
7285 memset(&mcc_dig, 0, sizeof(mcc_dig));
7286 mcc_dig.rtwvif_link = rtwvif_link;
7287 mcc_dig.has_sta = false;
7288 mcc_dig.rssi_min = U8_MAX;
7289 ieee80211_iterate_stations_atomic(rtwdev->hw,
7290 rtw89_phy_set_mcc_dig_iter,
7291 &mcc_dig);
7292
7293 rtw89_phy_set_mcc_dig(rtwdev, rtwvif_link, bb,
7294 mcc_dig.rssi_min, i, mcc_dig.has_sta);
7295 }
7296 }
7297
rtw89_phy_dig_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool pause_dig,bool restore)7298 static void rtw89_phy_dig_ctrl(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb,
7299 bool pause_dig, bool restore)
7300 {
7301 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
7302 struct rtw89_dig_info *dig = &bb->dig;
7303 bool en_dig;
7304 u32 pd_val;
7305
7306 if (dig->pause_dig == pause_dig)
7307 return;
7308
7309 if (pause_dig) {
7310 en_dig = false;
7311 pd_val = 0;
7312 } else {
7313 en_dig = rtwdev->total_sta_assoc > 0;
7314 pd_val = restore ? dig->bak_dig : 0;
7315 }
7316
7317 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s <%s> PD_low=%d", __func__,
7318 pause_dig ? "suspend" : "resume", pd_val);
7319
7320 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
7321 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
7322 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
7323 dig_regs->pd_spatial_reuse_en, en_dig, bb->phy_idx);
7324
7325 dig->pause_dig = pause_dig;
7326 }
7327
rtw89_phy_dig_suspend(struct rtw89_dev * rtwdev)7328 void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev)
7329 {
7330 struct rtw89_bb_ctx *bb;
7331
7332 rtw89_for_each_active_bb(rtwdev, bb)
7333 rtw89_phy_dig_ctrl(rtwdev, bb, true, false);
7334 }
7335
rtw89_phy_dig_resume(struct rtw89_dev * rtwdev,bool restore)7336 void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore)
7337 {
7338 struct rtw89_bb_ctx *bb;
7339
7340 rtw89_for_each_active_bb(rtwdev, bb)
7341 rtw89_phy_dig_ctrl(rtwdev, bb, false, restore);
7342 }
7343
__rtw89_phy_dig(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7344 static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7345 {
7346 struct rtw89_dig_info *dig = &bb->dig;
7347 bool is_linked = rtwdev->total_sta_assoc > 0;
7348 enum rtw89_entity_mode mode;
7349
7350 if (unlikely(dig->bypass_dig)) {
7351 dig->bypass_dig = false;
7352 return;
7353 }
7354
7355 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig track\n", bb->phy_idx);
7356
7357 rtw89_phy_dig_update_rssi_info(rtwdev, bb);
7358
7359 mode = rtw89_get_entity_mode(rtwdev);
7360 if (mode == RTW89_ENTITY_MODE_MCC) {
7361 rtw89_phy_dig_mcc(rtwdev, bb);
7362 return;
7363 }
7364
7365 if (unlikely(dig->pause_dig))
7366 return;
7367
7368 if (!dig->is_linked_pre && is_linked) {
7369 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
7370 rtw89_phy_dig_update_para(rtwdev, bb);
7371 dig->igi_fa_rssi = dig->igi_rssi;
7372 } else if (dig->is_linked_pre && !is_linked) {
7373 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
7374 rtw89_phy_dig_update_para(rtwdev, bb);
7375 dig->igi_fa_rssi = dig->igi_rssi;
7376 }
7377 dig->is_linked_pre = is_linked;
7378
7379 rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
7380
7381 rtw89_debug(rtwdev, RTW89_DBG_DIG,
7382 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
7383 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
7384 dig->igi_fa_rssi);
7385
7386 rtw89_phy_dig_config_igi(rtwdev, bb);
7387
7388 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi, dig->dyn_pd_th_en);
7389
7390 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
7391 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, true);
7392 else
7393 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
7394 }
7395
rtw89_phy_dig(struct rtw89_dev * rtwdev)7396 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
7397 {
7398 struct rtw89_bb_ctx *bb;
7399
7400 rtw89_for_each_active_bb(rtwdev, bb)
7401 __rtw89_phy_dig(rtwdev, bb);
7402 }
7403
__rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)7404 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev,
7405 struct rtw89_sta_link *rtwsta_link)
7406 {
7407 struct rtw89_hal *hal = &rtwdev->hal;
7408 u8 rssi_a, rssi_b;
7409 u32 candidate;
7410
7411 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
7412 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
7413
7414 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
7415 candidate = RF_A;
7416 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
7417 candidate = RF_B;
7418 else
7419 return;
7420
7421 if (hal->antenna_tx == candidate)
7422 return;
7423
7424 hal->antenna_tx = candidate;
7425 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link);
7426
7427 if (hal->antenna_tx == RF_A) {
7428 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
7429 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
7430 } else if (hal->antenna_tx == RF_B) {
7431 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
7432 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
7433 }
7434 }
7435
rtw89_phy_tx_path_div_sta_iter(void * data,struct ieee80211_sta * sta)7436 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
7437 {
7438 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
7439 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
7440 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
7441 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
7442 struct rtw89_vif_link *rtwvif_link;
7443 struct rtw89_sta_link *rtwsta_link;
7444 unsigned int link_id;
7445 bool *done = data;
7446
7447 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n"))
7448 return;
7449
7450 if (sta->tdls)
7451 return;
7452
7453 if (*done)
7454 return;
7455
7456 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
7457 rtwvif_link = rtwsta_link->rtwvif_link;
7458 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
7459 continue;
7460
7461 *done = true;
7462 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link);
7463 return;
7464 }
7465 }
7466
rtw89_phy_tx_path_div_track(struct rtw89_dev * rtwdev)7467 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
7468 {
7469 struct rtw89_hal *hal = &rtwdev->hal;
7470 bool done = false;
7471
7472 if (!hal->tx_path_diversity)
7473 return;
7474
7475 ieee80211_iterate_stations_atomic(rtwdev->hw,
7476 rtw89_phy_tx_path_div_sta_iter,
7477 &done);
7478 }
7479
7480 #define ANTDIV_MAIN 0
7481 #define ANTDIV_AUX 1
7482
rtw89_phy_antdiv_set_ant(struct rtw89_dev * rtwdev)7483 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
7484 {
7485 struct rtw89_hal *hal = &rtwdev->hal;
7486 u8 default_ant, optional_ant;
7487
7488 if (!hal->ant_diversity || hal->antenna_tx == 0)
7489 return;
7490
7491 if (hal->antenna_tx == RF_B) {
7492 default_ant = ANTDIV_AUX;
7493 optional_ant = ANTDIV_MAIN;
7494 } else {
7495 default_ant = ANTDIV_MAIN;
7496 optional_ant = ANTDIV_AUX;
7497 }
7498
7499 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
7500 default_ant, RTW89_PHY_0);
7501 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
7502 default_ant, RTW89_PHY_0);
7503 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
7504 optional_ant, RTW89_PHY_0);
7505 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
7506 default_ant, RTW89_PHY_0);
7507 }
7508
rtw89_phy_swap_hal_antenna(struct rtw89_dev * rtwdev)7509 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
7510 {
7511 struct rtw89_hal *hal = &rtwdev->hal;
7512
7513 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
7514 hal->antenna_tx = hal->antenna_rx;
7515 }
7516
rtw89_phy_antdiv_decision_state(struct rtw89_dev * rtwdev)7517 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
7518 {
7519 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7520 struct rtw89_hal *hal = &rtwdev->hal;
7521 bool no_change = false;
7522 u8 main_rssi, aux_rssi;
7523 u8 main_evm, aux_evm;
7524 u32 candidate;
7525
7526 antdiv->get_stats = false;
7527 antdiv->training_count = 0;
7528
7529 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
7530 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
7531 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
7532 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
7533
7534 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
7535 candidate = RF_A;
7536 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
7537 candidate = RF_B;
7538 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
7539 candidate = RF_A;
7540 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
7541 candidate = RF_B;
7542 else
7543 no_change = true;
7544
7545 if (no_change) {
7546 /* swap back from training antenna to original */
7547 rtw89_phy_swap_hal_antenna(rtwdev);
7548 return;
7549 }
7550
7551 hal->antenna_tx = candidate;
7552 hal->antenna_rx = candidate;
7553 }
7554
rtw89_phy_antdiv_training_state(struct rtw89_dev * rtwdev)7555 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
7556 {
7557 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7558 u64 state_period;
7559
7560 if (antdiv->training_count % 2 == 0) {
7561 if (antdiv->training_count == 0)
7562 rtw89_phy_antdiv_sts_reset(rtwdev);
7563
7564 antdiv->get_stats = true;
7565 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
7566 } else {
7567 antdiv->get_stats = false;
7568 state_period = msecs_to_jiffies(ANTDIV_DELAY);
7569
7570 rtw89_phy_swap_hal_antenna(rtwdev);
7571 rtw89_phy_antdiv_set_ant(rtwdev);
7572 }
7573
7574 antdiv->training_count++;
7575 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work,
7576 state_period);
7577 }
7578
rtw89_phy_antdiv_work(struct wiphy * wiphy,struct wiphy_work * work)7579 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work)
7580 {
7581 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
7582 antdiv_work.work);
7583 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7584
7585 lockdep_assert_wiphy(wiphy);
7586
7587 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
7588 rtw89_phy_antdiv_training_state(rtwdev);
7589 } else {
7590 rtw89_phy_antdiv_decision_state(rtwdev);
7591 rtw89_phy_antdiv_set_ant(rtwdev);
7592 }
7593 }
7594
rtw89_phy_antdiv_track(struct rtw89_dev * rtwdev)7595 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
7596 {
7597 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
7598 struct rtw89_hal *hal = &rtwdev->hal;
7599 u8 rssi, rssi_pre;
7600
7601 if (!hal->ant_diversity || hal->ant_diversity_fixed)
7602 return;
7603
7604 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
7605 rssi_pre = antdiv->rssi_pre;
7606 antdiv->rssi_pre = rssi;
7607 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
7608
7609 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
7610 return;
7611
7612 antdiv->training_count = 0;
7613 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 0);
7614 }
7615
__rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7616 static void __rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev,
7617 struct rtw89_bb_ctx *bb)
7618 {
7619 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
7620 "BB-%d env_monitor init\n", bb->phy_idx);
7621
7622 rtw89_phy_ccx_top_setting_init(rtwdev, bb);
7623 rtw89_phy_ifs_clm_setting_init(rtwdev, bb);
7624 }
7625
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)7626 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
7627 {
7628 struct rtw89_bb_ctx *bb;
7629
7630 rtw89_for_each_capab_bb(rtwdev, bb)
7631 __rtw89_phy_env_monitor_init(rtwdev, bb);
7632 }
7633
__rtw89_phy_edcca_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7634 static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev,
7635 struct rtw89_bb_ctx *bb)
7636 {
7637 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7638 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7639
7640 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca init\n", bb->phy_idx);
7641
7642 memset(edcca_bak, 0, sizeof(*edcca_bak));
7643
7644 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
7645 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
7646 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
7647 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
7648 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
7649 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
7650 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
7651 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
7652 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
7653 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
7654 }
7655
7656 rtw89_phy_write32_idx(rtwdev, edcca_regs->tx_collision_t2r_st,
7657 edcca_regs->tx_collision_t2r_st_mask, 0x29, bb->phy_idx);
7658 }
7659
rtw89_phy_edcca_init(struct rtw89_dev * rtwdev)7660 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
7661 {
7662 struct rtw89_bb_ctx *bb;
7663
7664 rtw89_for_each_capab_bb(rtwdev, bb)
7665 __rtw89_phy_edcca_init(rtwdev, bb);
7666 }
7667
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)7668 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
7669 {
7670 rtw89_phy_stat_init(rtwdev);
7671
7672 rtw89_chip_bb_sethw(rtwdev);
7673
7674 rtw89_phy_env_monitor_init(rtwdev);
7675 rtw89_phy_nhm_setting_init(rtwdev);
7676 rtw89_physts_parsing_init(rtwdev);
7677 rtw89_phy_dig_init(rtwdev);
7678 rtw89_phy_cfo_init(rtwdev);
7679 rtw89_phy_bb_wrap_init(rtwdev);
7680 rtw89_phy_edcca_init(rtwdev);
7681 rtw89_phy_ch_info_init(rtwdev);
7682 rtw89_phy_ul_tb_info_init(rtwdev);
7683 rtw89_phy_antdiv_init(rtwdev);
7684 rtw89_chip_rfe_gpio(rtwdev);
7685 rtw89_phy_antdiv_set_ant(rtwdev);
7686
7687 rtw89_chip_rfk_hw_init(rtwdev);
7688 rtw89_phy_init_rf_nctl(rtwdev);
7689 rtw89_chip_rfk_init(rtwdev);
7690 rtw89_chip_set_txpwr_ctrl(rtwdev);
7691 rtw89_chip_power_trim(rtwdev);
7692 rtw89_chip_cfg_txrx_path(rtwdev);
7693 }
7694
rtw89_phy_dm_reinit(struct rtw89_dev * rtwdev)7695 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev)
7696 {
7697 rtw89_phy_env_monitor_init(rtwdev);
7698 rtw89_physts_parsing_init(rtwdev);
7699 }
7700
__rtw89_phy_dm_init_data(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7701 static void __rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7702 {
7703 struct rtw89_env_monitor_info *env = &bb->env_monitor;
7704 const struct rtw89_chip_info *chip = rtwdev->chip;
7705 struct ieee80211_supported_band *sband;
7706 enum rtw89_band hw_band;
7707 enum nl80211_band band;
7708 u8 idx;
7709
7710 if (!chip->support_noise)
7711 return;
7712
7713 for (band = 0; band < NUM_NL80211_BANDS; band++) {
7714 sband = rtwdev->hw->wiphy->bands[band];
7715 if (!sband)
7716 continue;
7717
7718 hw_band = rtw89_nl80211_to_hw_band(band);
7719 env->nhm_his[hw_band] =
7720 devm_kcalloc(rtwdev->dev, sband->n_channels,
7721 sizeof(*env->nhm_his[0]), GFP_KERNEL);
7722
7723 for (idx = 0; idx < sband->n_channels; idx++)
7724 INIT_LIST_HEAD(&env->nhm_his[hw_band][idx].list);
7725
7726 INIT_LIST_HEAD(&env->nhm_rpt_list);
7727 }
7728 }
7729
rtw89_phy_dm_init_data(struct rtw89_dev * rtwdev)7730 void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev)
7731 {
7732 struct rtw89_bb_ctx *bb;
7733
7734 rtw89_for_each_capab_bb(rtwdev, bb)
7735 __rtw89_phy_dm_init_data(rtwdev, bb);
7736 }
7737
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)7738 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
7739 struct rtw89_vif_link *rtwvif_link)
7740 {
7741 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
7742 const struct rtw89_chip_info *chip = rtwdev->chip;
7743 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
7744 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
7745 struct ieee80211_bss_conf *bss_conf;
7746 u8 bss_color;
7747
7748 rcu_read_lock();
7749
7750 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
7751 if (!bss_conf->he_support || !vif->cfg.assoc) {
7752 rcu_read_unlock();
7753 return;
7754 }
7755
7756 bss_color = bss_conf->he_bss_color.color;
7757
7758 rcu_read_unlock();
7759
7760 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
7761 phy_idx);
7762 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
7763 bss_color, phy_idx);
7764 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
7765 vif->cfg.aid, phy_idx);
7766 }
7767
rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc * desc)7768 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
7769 {
7770 return desc->ch != 0;
7771 }
7772
rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc * desc,const struct rtw89_chan * chan)7773 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
7774 const struct rtw89_chan *chan)
7775 {
7776 if (!rfk_chan_validate_desc(desc))
7777 return false;
7778
7779 if (desc->ch != chan->channel)
7780 return false;
7781
7782 if (desc->has_band && desc->band != chan->band_type)
7783 return false;
7784
7785 if (desc->has_bw && desc->bw != chan->band_width)
7786 return false;
7787
7788 return true;
7789 }
7790
7791 struct rfk_chan_iter_data {
7792 const struct rtw89_rfk_chan_desc desc;
7793 unsigned int found;
7794 };
7795
rfk_chan_iter_search(const struct rtw89_chan * chan,void * data)7796 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
7797 {
7798 struct rfk_chan_iter_data *iter_data = data;
7799
7800 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
7801 iter_data->found++;
7802
7803 return 0;
7804 }
7805
rtw89_rfk_chan_lookup(struct rtw89_dev * rtwdev,const struct rtw89_rfk_chan_desc * desc,u8 desc_nr,const struct rtw89_chan * target_chan)7806 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
7807 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
7808 const struct rtw89_chan *target_chan)
7809 {
7810 int sel = -1;
7811 u8 i;
7812
7813 for (i = 0; i < desc_nr; i++) {
7814 struct rfk_chan_iter_data iter_data = {
7815 .desc = desc[i],
7816 };
7817
7818 if (rfk_chan_is_equivalent(&desc[i], target_chan))
7819 return i;
7820
7821 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
7822 if (!iter_data.found && sel == -1)
7823 sel = i;
7824 }
7825
7826 if (sel == -1) {
7827 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7828 "no idle rfk entry; force replace the first\n");
7829 sel = 0;
7830 }
7831
7832 return sel;
7833 }
7834 EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
7835
7836 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7837 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7838 {
7839 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
7840 }
7841
7842 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7843 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7844 {
7845 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
7846 }
7847
7848 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7849 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7850 {
7851 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
7852 }
7853
7854 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7855 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7856 {
7857 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
7858 }
7859
7860 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)7861 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
7862 {
7863 udelay(def->data);
7864 }
7865
7866 static void
7867 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
7868 [RTW89_RFK_F_WRF] = _rfk_write_rf,
7869 [RTW89_RFK_F_WM] = _rfk_write32_mask,
7870 [RTW89_RFK_F_WS] = _rfk_write32_set,
7871 [RTW89_RFK_F_WC] = _rfk_write32_clr,
7872 [RTW89_RFK_F_DELAY] = _rfk_delay,
7873 };
7874
7875 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
7876
7877 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)7878 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
7879 {
7880 const struct rtw89_reg5_def *p = tbl->defs;
7881 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
7882
7883 for (; p < end; p++)
7884 _rfk_handler[p->flag](rtwdev, p);
7885 }
7886 EXPORT_SYMBOL(rtw89_rfk_parser);
7887
7888 #define RTW89_TSSI_FAST_MODE_NUM 4
7889
7890 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
7891 {0xD934, 0xff0000},
7892 {0xD934, 0xff000000},
7893 {0xD938, 0xff},
7894 {0xD934, 0xff00},
7895 };
7896
7897 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
7898 {0xD930, 0xff0000},
7899 {0xD930, 0xff000000},
7900 {0xD934, 0xff},
7901 {0xD930, 0xff00},
7902 };
7903
7904 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)7905 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
7906 enum rtw89_mac_idx mac_idx,
7907 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
7908 u32 val)
7909 {
7910 const struct rtw89_reg_def *regs;
7911 u32 reg;
7912 int i;
7913
7914 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
7915 regs = rtw89_tssi_fastmode_regs_flat;
7916 else
7917 regs = rtw89_tssi_fastmode_regs_level;
7918
7919 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
7920 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
7921 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
7922 }
7923 }
7924
7925 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
7926 {0xD91C, 0xff000000},
7927 {0xD920, 0xff},
7928 {0xD920, 0xff00},
7929 {0xD920, 0xff0000},
7930 {0xD920, 0xff000000},
7931 {0xD924, 0xff},
7932 {0xD924, 0xff00},
7933 {0xD914, 0xff000000},
7934 {0xD918, 0xff},
7935 {0xD918, 0xff00},
7936 {0xD918, 0xff0000},
7937 {0xD918, 0xff000000},
7938 {0xD91C, 0xff},
7939 {0xD91C, 0xff00},
7940 {0xD91C, 0xff0000},
7941 };
7942
7943 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
7944 {0xD910, 0xff},
7945 {0xD910, 0xff00},
7946 {0xD910, 0xff0000},
7947 {0xD910, 0xff000000},
7948 {0xD914, 0xff},
7949 {0xD914, 0xff00},
7950 {0xD914, 0xff0000},
7951 {0xD908, 0xff},
7952 {0xD908, 0xff00},
7953 {0xD908, 0xff0000},
7954 {0xD908, 0xff000000},
7955 {0xD90C, 0xff},
7956 {0xD90C, 0xff00},
7957 {0xD90C, 0xff0000},
7958 {0xD90C, 0xff000000},
7959 };
7960
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)7961 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
7962 enum rtw89_mac_idx mac_idx,
7963 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
7964 {
7965 const struct rtw89_chip_info *chip = rtwdev->chip;
7966 const struct rtw89_reg_def *regs;
7967 const u32 *data;
7968 u32 reg;
7969 int i;
7970
7971 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
7972 return;
7973
7974 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
7975 regs = rtw89_tssi_bandedge_regs_flat;
7976 else
7977 regs = rtw89_tssi_bandedge_regs_level;
7978
7979 data = chip->tssi_dbw_table->data[bandedge_cfg];
7980
7981 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
7982 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
7983 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
7984 }
7985
7986 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
7987 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
7988
7989 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
7990 data[RTW89_TSSI_SBW20]);
7991 }
7992 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
7993
7994 static
7995 const u8 rtw89_ch_base_table[16] = {1, 0xff,
7996 36, 100, 132, 149, 0xff,
7997 1, 33, 65, 97, 129, 161, 193, 225, 0xff};
7998 #define RTW89_CH_BASE_IDX_2G 0
7999 #define RTW89_CH_BASE_IDX_5G_FIRST 2
8000 #define RTW89_CH_BASE_IDX_5G_LAST 5
8001 #define RTW89_CH_BASE_IDX_6G_FIRST 7
8002 #define RTW89_CH_BASE_IDX_6G_LAST 14
8003
8004 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)
8005 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0)
8006
rtw89_encode_chan_idx(struct rtw89_dev * rtwdev,u8 central_ch,u8 band)8007 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
8008 {
8009 u8 chan_idx;
8010 u8 last, first;
8011 u8 idx;
8012
8013 switch (band) {
8014 case RTW89_BAND_2G:
8015 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) |
8016 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch);
8017 return chan_idx;
8018 case RTW89_BAND_5G:
8019 first = RTW89_CH_BASE_IDX_5G_FIRST;
8020 last = RTW89_CH_BASE_IDX_5G_LAST;
8021 break;
8022 case RTW89_BAND_6G:
8023 first = RTW89_CH_BASE_IDX_6G_FIRST;
8024 last = RTW89_CH_BASE_IDX_6G_LAST;
8025 break;
8026 default:
8027 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
8028 return 0;
8029 }
8030
8031 for (idx = last; idx >= first; idx--)
8032 if (central_ch >= rtw89_ch_base_table[idx])
8033 break;
8034
8035 if (idx < first) {
8036 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
8037 return 0;
8038 }
8039
8040 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) |
8041 FIELD_PREP(RTW89_CH_OFFSET_MASK,
8042 (central_ch - rtw89_ch_base_table[idx]) >> 1);
8043 return chan_idx;
8044 }
8045 EXPORT_SYMBOL(rtw89_encode_chan_idx);
8046
rtw89_decode_chan_idx(struct rtw89_dev * rtwdev,u8 chan_idx,u8 * ch,enum nl80211_band * band)8047 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
8048 u8 *ch, enum nl80211_band *band)
8049 {
8050 u8 idx, offset;
8051
8052 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx);
8053 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx);
8054
8055 if (idx == RTW89_CH_BASE_IDX_2G) {
8056 *band = NL80211_BAND_2GHZ;
8057 *ch = offset;
8058 return;
8059 }
8060
8061 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
8062 *ch = rtw89_ch_base_table[idx] + (offset << 1);
8063 }
8064 EXPORT_SYMBOL(rtw89_decode_chan_idx);
8065
rtw89_phy_config_edcca(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool scan)8066 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
8067 struct rtw89_bb_ctx *bb, bool scan)
8068 {
8069 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
8070 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
8071
8072 if (scan) {
8073 edcca_bak->a =
8074 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
8075 edcca_regs->edcca_mask, bb->phy_idx);
8076 edcca_bak->p =
8077 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
8078 edcca_regs->edcca_p_mask, bb->phy_idx);
8079 edcca_bak->ppdu =
8080 rtw89_phy_read32_idx(rtwdev, edcca_regs->ppdu_level,
8081 edcca_regs->ppdu_mask, bb->phy_idx);
8082
8083 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
8084 edcca_regs->edcca_mask, EDCCA_MAX, bb->phy_idx);
8085 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
8086 edcca_regs->edcca_p_mask, EDCCA_MAX, bb->phy_idx);
8087 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
8088 edcca_regs->ppdu_mask, EDCCA_MAX, bb->phy_idx);
8089 } else {
8090 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
8091 edcca_regs->edcca_mask,
8092 edcca_bak->a, bb->phy_idx);
8093 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
8094 edcca_regs->edcca_p_mask,
8095 edcca_bak->p, bb->phy_idx);
8096 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
8097 edcca_regs->ppdu_mask,
8098 edcca_bak->ppdu, bb->phy_idx);
8099 }
8100 }
8101
rtw89_phy_edcca_log(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)8102 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
8103 {
8104 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
8105 const struct rtw89_edcca_p_regs *edcca_p_regs;
8106 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
8107 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
8108 u8 path, per20_bitmap = 0;
8109 u8 pwdb_sel = 5;
8110 u8 pwdb[8];
8111 u32 tmp;
8112
8113 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
8114 return;
8115
8116 if (bb->phy_idx == RTW89_PHY_1)
8117 edcca_p_regs = &edcca_regs->p[RTW89_PHY_1];
8118 else
8119 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0];
8120
8121 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
8122 edcca_p_regs->rpt_sel_mask, 0);
8123 if (rtwdev->chip->chip_id == RTL8922A || rtwdev->chip->chip_id == RTL8922D) {
8124 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
8125 edcca_regs->rpt_sel_be_mask, 0);
8126 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a,
8127 MASKBYTE0);
8128 }
8129 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
8130 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
8131 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
8132 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
8133 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20);
8134 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20);
8135 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB);
8136 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1);
8137 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
8138 pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
8139
8140 if (rtwdev->chip->chip_id == RTL8922D)
8141 pwdb_sel = 2;
8142
8143 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
8144 edcca_p_regs->rpt_sel_mask, pwdb_sel);
8145 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
8146 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
8147 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
8148
8149 if (rtwdev->chip->chip_id == RTL8922A || rtwdev->chip->chip_id == RTL8922D) {
8150 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
8151 edcca_regs->rpt_sel_be_mask, 4);
8152 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
8153 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
8154 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
8155 pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
8156 pwdb[3] = u32_get_bits(tmp, MASKBYTE0);
8157
8158 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
8159 edcca_regs->rpt_sel_be_mask, 5);
8160 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
8161 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
8162 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
8163 pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
8164 pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
8165 } else {
8166 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
8167 edcca_p_regs->rpt_sel_mask, 0);
8168 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
8169 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
8170 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
8171
8172 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
8173 edcca_p_regs->rpt_sel_mask, 5);
8174 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
8175 pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
8176 pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
8177
8178 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
8179 edcca_p_regs->rpt_sel_mask, 2);
8180 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
8181 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
8182 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
8183
8184 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
8185 edcca_p_regs->rpt_sel_mask, 3);
8186 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
8187 pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
8188 pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
8189 }
8190
8191 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
8192 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap);
8193
8194 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
8195 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
8196 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5],
8197 pwdb[6], pwdb[7]);
8198
8199 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
8200 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n",
8201 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80);
8202
8203 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
8204 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n",
8205 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80);
8206 }
8207
rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)8208 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev,
8209 struct rtw89_bb_ctx *bb)
8210 {
8211 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
8212 bool is_linked = rtwdev->total_sta_assoc > 0;
8213 u8 rssi_min = ch_info->rssi_min >> 1;
8214 u8 edcca_thre;
8215
8216 if (!is_linked) {
8217 edcca_thre = EDCCA_MAX;
8218 } else {
8219 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
8220 EDCCA_TH_REF;
8221 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB);
8222 }
8223
8224 return edcca_thre;
8225 }
8226
rtw89_phy_edcca_thre_calc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)8227 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
8228 {
8229 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
8230 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
8231 u8 th;
8232
8233 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev, bb);
8234 if (th == edcca_bak->th_old)
8235 return;
8236
8237 edcca_bak->th_old = th;
8238
8239 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
8240 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th);
8241
8242 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
8243 edcca_regs->edcca_mask, th, bb->phy_idx);
8244 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
8245 edcca_regs->edcca_p_mask, th, bb->phy_idx);
8246 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
8247 edcca_regs->ppdu_mask, th, bb->phy_idx);
8248 }
8249
8250 static
__rtw89_phy_edcca_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)8251 void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
8252 {
8253 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca track\n", bb->phy_idx);
8254
8255 rtw89_phy_edcca_thre_calc(rtwdev, bb);
8256 rtw89_phy_edcca_log(rtwdev, bb);
8257 }
8258
rtw89_phy_edcca_track(struct rtw89_dev * rtwdev)8259 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
8260 {
8261 struct rtw89_hal *hal = &rtwdev->hal;
8262 struct rtw89_bb_ctx *bb;
8263
8264 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
8265 return;
8266
8267 rtw89_for_each_active_bb(rtwdev, bb)
8268 __rtw89_phy_edcca_track(rtwdev, bb);
8269 }
8270
rtw89_phy_get_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)8271 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
8272 enum rtw89_phy_idx phy_idx)
8273 {
8274 rtw89_debug(rtwdev, RTW89_DBG_RFK,
8275 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
8276 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
8277
8278 switch (rtwdev->mlo_dbcc_mode) {
8279 case MLO_1_PLUS_1_1RF:
8280 if (phy_idx == RTW89_PHY_0)
8281 return RF_A;
8282 else
8283 return RF_B;
8284 case MLO_1_PLUS_1_2RF:
8285 if (phy_idx == RTW89_PHY_0)
8286 return RF_A;
8287 else
8288 return RF_D;
8289 case MLO_0_PLUS_2_1RF:
8290 case MLO_2_PLUS_0_1RF:
8291 /* for both PHY 0/1 */
8292 return RF_AB;
8293 case MLO_0_PLUS_2_2RF:
8294 case MLO_2_PLUS_0_2RF:
8295 case MLO_2_PLUS_2_2RF:
8296 default:
8297 if (phy_idx == RTW89_PHY_0)
8298 return RF_AB;
8299 else
8300 return RF_CD;
8301 }
8302 }
8303 EXPORT_SYMBOL(rtw89_phy_get_kpath);
8304
rtw89_phy_get_syn_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)8305 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
8306 enum rtw89_phy_idx phy_idx)
8307 {
8308 rtw89_debug(rtwdev, RTW89_DBG_RFK,
8309 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
8310 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
8311
8312 switch (rtwdev->mlo_dbcc_mode) {
8313 case MLO_1_PLUS_1_1RF:
8314 if (phy_idx == RTW89_PHY_0)
8315 return RF_PATH_A;
8316 else
8317 return RF_PATH_B;
8318 case MLO_1_PLUS_1_2RF:
8319 if (phy_idx == RTW89_PHY_0)
8320 return RF_PATH_A;
8321 else
8322 return RF_PATH_D;
8323 case MLO_0_PLUS_2_1RF:
8324 case MLO_2_PLUS_0_1RF:
8325 if (phy_idx == RTW89_PHY_0)
8326 return RF_PATH_A;
8327 else
8328 return RF_PATH_B;
8329 case MLO_0_PLUS_2_2RF:
8330 case MLO_2_PLUS_0_2RF:
8331 case MLO_2_PLUS_2_2RF:
8332 default:
8333 if (phy_idx == RTW89_PHY_0)
8334 return RF_PATH_A;
8335 else
8336 return RF_PATH_C;
8337 }
8338 }
8339 EXPORT_SYMBOL(rtw89_phy_get_syn_sel);
8340
8341 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
8342 .setting_addr = R_CCX,
8343 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
8344 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
8345 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
8346 .en_mask = B_CCX_EN_MSK,
8347 .ifs_cnt_addr = R_IFS_COUNTER,
8348 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
8349 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
8350 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
8351 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
8352 .ifs_t1_addr = R_IFS_T1,
8353 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
8354 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
8355 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
8356 .ifs_t2_addr = R_IFS_T2,
8357 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
8358 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
8359 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
8360 .ifs_t3_addr = R_IFS_T3,
8361 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
8362 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
8363 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
8364 .ifs_t4_addr = R_IFS_T4,
8365 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
8366 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
8367 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
8368 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
8369 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
8370 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
8371 .ifs_clm_cca_addr = R_IFS_CLM_CCA,
8372 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
8373 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
8374 .ifs_clm_fa_addr = R_IFS_CLM_FA,
8375 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
8376 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
8377 .ifs_his_addr = R_IFS_HIS,
8378 .ifs_his_addr2 = R_IFS_HIS,
8379 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
8380 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
8381 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
8382 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
8383 .ifs_avg_l_addr = R_IFS_AVG_L,
8384 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
8385 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
8386 .ifs_avg_h_addr = R_IFS_AVG_H,
8387 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
8388 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
8389 .ifs_cca_l_addr = R_IFS_CCA_L,
8390 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
8391 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
8392 .ifs_cca_h_addr = R_IFS_CCA_H,
8393 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
8394 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
8395 .ifs_total_addr = R_IFSCNT,
8396 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
8397 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
8398 .nhm = R_NHM_AX,
8399 .nhm_ready = B_NHM_READY_MSK,
8400 .nhm_config = R_NHM_CFG,
8401 .nhm_period_mask = B_NHM_PERIOD_MSK,
8402 .nhm_unit_mask = B_NHM_COUNTER_MSK,
8403 .nhm_include_cca_mask = B_NHM_INCLUDE_CCA_MSK,
8404 .nhm_en_mask = B_NHM_EN_MSK,
8405 .nhm_method = R_NHM_TH9,
8406 .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK,
8407 };
8408
8409 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
8410 .setting_addr = R_PLCP_HISTOGRAM,
8411 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
8412 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
8413 };
8414
8415 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
8416 .comp = R_DCFO_WEIGHT,
8417 .weighting_mask = B_DCFO_WEIGHT_MSK,
8418 .comp_seg0 = R_DCFO_OPT,
8419 .valid_0_mask = B_DCFO_OPT_EN,
8420 };
8421
8422 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
8423 .cr_base = 0x10000,
8424 .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START,
8425 .physt_bmp_eht = 0xfc,
8426 .ccx = &rtw89_ccx_regs_ax,
8427 .physts = &rtw89_physts_regs_ax,
8428 .cfo = &rtw89_cfo_regs_ax,
8429 .bb_wrap = NULL,
8430 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
8431 .config_bb_gain = rtw89_phy_config_bb_gain_ax,
8432 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
8433 .bb_wrap_init = NULL,
8434 .ch_info_init = NULL,
8435
8436 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
8437 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
8438 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax,
8439 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax,
8440 };
8441 EXPORT_SYMBOL(rtw89_phy_gen_ax);
8442